tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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net: stmmac: visconti: convert to set_clk_tx_rate() method

Convert visconti to use the set_clk_tx_rate() method. By doing so,
the GMAC control register will already have been updated (unlike with
the fix_mac_speed() method) so this code can be removed while porting
to the set_clk_tx_rate() method.

There is also no need for the spinlock, and has never been - neither
fix_mac_speed() nor set_clk_tx_rate() can be called by more than one
thread at a time, so the lock does nothing useful.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
Acked-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1u5SiQ-001I0B-OQ@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Russell King (Oracle) and committed by
Jakub Kicinski 21b01cb8 f7ca6120

+6 -19
+6 -19
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
··· 51 51 u32 phy_intf_sel; 52 52 struct clk *phy_ref_clk; 53 53 struct device *dev; 54 - spinlock_t lock; /* lock to protect register update */ 55 54 }; 56 55 57 - static void visconti_eth_fix_mac_speed(void *priv, int speed, unsigned int mode) 56 + static int visconti_eth_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i, 57 + phy_interface_t interface, int speed) 58 58 { 59 - struct visconti_eth *dwmac = priv; 59 + struct visconti_eth *dwmac = bsp_priv; 60 60 struct net_device *netdev = dev_get_drvdata(dwmac->dev); 61 61 unsigned int val, clk_sel_val = 0; 62 - unsigned long flags; 63 - 64 - spin_lock_irqsave(&dwmac->lock, flags); 65 - 66 - /* adjust link */ 67 - val = readl(dwmac->reg + MAC_CTRL_REG); 68 - val &= ~(GMAC_CONFIG_PS | GMAC_CONFIG_FES); 69 62 70 63 switch (speed) { 71 64 case SPEED_1000: ··· 70 77 clk_sel_val = ETHER_CLK_SEL_FREQ_SEL_25M; 71 78 if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RMII) 72 79 clk_sel_val = ETHER_CLK_SEL_DIV_SEL_2; 73 - val |= GMAC_CONFIG_PS | GMAC_CONFIG_FES; 74 80 break; 75 81 case SPEED_10: 76 82 if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII) 77 83 clk_sel_val = ETHER_CLK_SEL_FREQ_SEL_2P5M; 78 84 if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RMII) 79 85 clk_sel_val = ETHER_CLK_SEL_DIV_SEL_20; 80 - val |= GMAC_CONFIG_PS; 81 86 break; 82 87 default: 83 88 /* No bit control */ 84 89 netdev_err(netdev, "Unsupported speed request (%d)", speed); 85 - spin_unlock_irqrestore(&dwmac->lock, flags); 86 - return; 90 + return -EINVAL; 87 91 } 88 - 89 - writel(val, dwmac->reg + MAC_CTRL_REG); 90 92 91 93 /* Stop internal clock */ 92 94 val = readl(dwmac->reg + REG_ETHER_CLOCK_SEL); ··· 124 136 break; 125 137 } 126 138 127 - spin_unlock_irqrestore(&dwmac->lock, flags); 139 + return 0; 128 140 } 129 141 130 142 static int visconti_eth_init_hw(struct platform_device *pdev, struct plat_stmmacenet_data *plat_dat) ··· 216 228 if (!dwmac) 217 229 return -ENOMEM; 218 230 219 - spin_lock_init(&dwmac->lock); 220 231 dwmac->reg = stmmac_res.addr; 221 232 dwmac->dev = &pdev->dev; 222 233 plat_dat->bsp_priv = dwmac; 223 - plat_dat->fix_mac_speed = visconti_eth_fix_mac_speed; 234 + plat_dat->set_clk_tx_rate = visconti_eth_set_clk_tx_rate; 224 235 225 236 ret = visconti_eth_clock_probe(pdev, plat_dat); 226 237 if (ret)