tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'gpio-fixes-v3.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull gpio fixes from Linus Walleij:
- Fix a resource leak in the SCH driver
- Fix the register address calculation in the MSIC driver
- Fix the PXA driver's devicetree functions
- Delete redundant shadow variable leftovers in the MXC driver
- Specify the GPIO base for the device tree probe in the MXC driver
- Add a modalias for the i.MX driver
- Fix off-by-one bug in the Samsung driver
- Fix erroneous errorpath in the Langwell driver

* tag 'gpio-fixes-v3.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio:
drivers/gpio/gpio-langwell.c: fix error return code
gpio: samsung: Fix off-by-one bug in gpio addresses
ARM: dts: imx: add alias for gpio
gpio/mxc: specify gpio base for device tree probe
gpio/mxc: remove redundant shadow variables initialization
GPIO: gpio-pxa: fix devicetree functions
gpio: msic: Fix calculating register address in msic_gpio_to_oreg()
gpio-sch: Fix leak of resource

Linus Torvalds 21d2f8dc c8dfbf48

+67 -14
+6
arch/arm/boot/dts/imx27.dtsi
··· 19 19 serial3 = &uart4; 20 20 serial4 = &uart5; 21 21 serial5 = &uart6; 22 + gpio0 = &gpio1; 23 + gpio1 = &gpio2; 24 + gpio2 = &gpio3; 25 + gpio3 = &gpio4; 26 + gpio4 = &gpio5; 27 + gpio5 = &gpio6; 22 28 }; 23 29 24 30 avic: avic-interrupt-controller@e0000000 {
+4
arch/arm/boot/dts/imx51.dtsi
··· 17 17 serial0 = &uart1; 18 18 serial1 = &uart2; 19 19 serial2 = &uart3; 20 + gpio0 = &gpio1; 21 + gpio1 = &gpio2; 22 + gpio2 = &gpio3; 23 + gpio3 = &gpio4; 20 24 }; 21 25 22 26 tzic: tz-interrupt-controller@e0000000 {
+7
arch/arm/boot/dts/imx53.dtsi
··· 19 19 serial2 = &uart3; 20 20 serial3 = &uart4; 21 21 serial4 = &uart5; 22 + gpio0 = &gpio1; 23 + gpio1 = &gpio2; 24 + gpio2 = &gpio3; 25 + gpio3 = &gpio4; 26 + gpio4 = &gpio5; 27 + gpio5 = &gpio6; 28 + gpio6 = &gpio7; 22 29 }; 23 30 24 31 tzic: tz-interrupt-controller@0fffc000 {
+7
arch/arm/boot/dts/imx6q.dtsi
··· 19 19 serial2 = &uart3; 20 20 serial3 = &uart4; 21 21 serial4 = &uart5; 22 + gpio0 = &gpio1; 23 + gpio1 = &gpio2; 24 + gpio2 = &gpio3; 25 + gpio3 = &gpio4; 26 + gpio4 = &gpio5; 27 + gpio5 = &gpio6; 28 + gpio6 = &gpio7; 22 29 }; 23 30 24 31 cpus {
+5 -2
drivers/gpio/gpio-langwell.c
··· 339 339 resource_size_t start, len; 340 340 struct lnw_gpio *lnw; 341 341 u32 gpio_base; 342 - int retval = 0; 342 + int retval; 343 343 int ngpio = id->driver_data; 344 344 345 345 retval = pci_enable_device(pdev); ··· 357 357 base = ioremap_nocache(start, len); 358 358 if (!base) { 359 359 dev_err(&pdev->dev, "error mapping bar1\n"); 360 + retval = -EFAULT; 360 361 goto err3; 361 362 } 362 363 gpio_base = *((u32 *)base + 1); ··· 382 381 383 382 lnw->domain = irq_domain_add_linear(pdev->dev.of_node, ngpio, 384 383 &lnw_gpio_irq_ops, lnw); 385 - if (!lnw->domain) 384 + if (!lnw->domain) { 385 + retval = -ENOMEM; 386 386 goto err3; 387 + } 387 388 388 389 lnw->reg_base = base; 389 390 lnw->chip.label = dev_name(&pdev->dev);
+1 -1
drivers/gpio/gpio-msic.c
··· 99 99 if (offset < 20) 100 100 return INTEL_MSIC_GPIO0HV0CTLO - offset + 16; 101 101 102 - return INTEL_MSIC_GPIO1HV0CTLO + offset + 20; 102 + return INTEL_MSIC_GPIO1HV0CTLO - offset + 20; 103 103 } 104 104 105 105 static int msic_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+2 -3
drivers/gpio/gpio-mxc.c
··· 465 465 goto out_iounmap; 466 466 467 467 port->bgc.gc.to_irq = mxc_gpio_to_irq; 468 - port->bgc.gc.base = pdev->id * 32; 469 - port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir); 470 - port->bgc.data = port->bgc.read_reg(port->bgc.reg_set); 468 + port->bgc.gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : 469 + pdev->id * 32; 471 470 472 471 err = gpiochip_add(&port->bgc.gc); 473 472 if (err)
+26
drivers/gpio/gpio-pxa.c
··· 62 62 63 63 #ifdef CONFIG_OF 64 64 static struct irq_domain *domain; 65 + static struct device_node *pxa_gpio_of_node; 65 66 #endif 66 67 67 68 struct pxa_gpio_chip { ··· 278 277 (value ? GPSR_OFFSET : GPCR_OFFSET)); 279 278 } 280 279 280 + #ifdef CONFIG_OF_GPIO 281 + static int pxa_gpio_of_xlate(struct gpio_chip *gc, 282 + const struct of_phandle_args *gpiospec, 283 + u32 *flags) 284 + { 285 + if (gpiospec->args[0] > pxa_last_gpio) 286 + return -EINVAL; 287 + 288 + if (gc != &pxa_gpio_chips[gpiospec->args[0] / 32].chip) 289 + return -EINVAL; 290 + 291 + if (flags) 292 + *flags = gpiospec->args[1]; 293 + 294 + return gpiospec->args[0] % 32; 295 + } 296 + #endif 297 + 281 298 static int __devinit pxa_init_gpio_chip(int gpio_end, 282 299 int (*set_wake)(unsigned int, unsigned int)) 283 300 { ··· 323 304 c->get = pxa_gpio_get; 324 305 c->set = pxa_gpio_set; 325 306 c->to_irq = pxa_gpio_to_irq; 307 + #ifdef CONFIG_OF_GPIO 308 + c->of_node = pxa_gpio_of_node; 309 + c->of_xlate = pxa_gpio_of_xlate; 310 + c->of_gpio_n_cells = 2; 311 + #endif 326 312 327 313 /* number of GPIOs on last bank may be less than 32 */ 328 314 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32; ··· 529 505 530 506 const struct irq_domain_ops pxa_irq_domain_ops = { 531 507 .map = pxa_irq_domain_map, 508 + .xlate = irq_domain_xlate_twocell, 532 509 }; 533 510 534 511 #ifdef CONFIG_OF ··· 570 545 } 571 546 domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0, 572 547 &pxa_irq_domain_ops, NULL); 548 + pxa_gpio_of_node = np; 573 549 return 0; 574 550 err: 575 551 iounmap(gpio_reg_base);
+7 -7
drivers/gpio/gpio-samsung.c
··· 2454 2454 }, 2455 2455 }, { 2456 2456 .chip = { 2457 - .base = EXYNOS5_GPC4(0), 2458 - .ngpio = EXYNOS5_GPIO_C4_NR, 2459 - .label = "GPC4", 2460 - }, 2461 - }, { 2462 - .chip = { 2463 2457 .base = EXYNOS5_GPD0(0), 2464 2458 .ngpio = EXYNOS5_GPIO_D0_NR, 2465 2459 .label = "GPD0", ··· 2505 2511 .base = EXYNOS5_GPY6(0), 2506 2512 .ngpio = EXYNOS5_GPIO_Y6_NR, 2507 2513 .label = "GPY6", 2514 + }, 2515 + }, { 2516 + .chip = { 2517 + .base = EXYNOS5_GPC4(0), 2518 + .ngpio = EXYNOS5_GPIO_C4_NR, 2519 + .label = "GPC4", 2508 2520 }, 2509 2521 }, { 2510 2522 .config = &samsung_gpio_cfgs[9], ··· 2836 2836 } 2837 2837 2838 2838 /* need to set base address for gpc4 */ 2839 - exynos5_gpios_1[11].base = gpio_base1 + 0x2E0; 2839 + exynos5_gpios_1[20].base = gpio_base1 + 0x2E0; 2840 2840 2841 2841 /* need to set base address for gpx */ 2842 2842 chip = &exynos5_gpios_1[21];
+2 -1
drivers/gpio/gpio-sch.c
··· 241 241 break; 242 242 243 243 default: 244 - return -ENODEV; 244 + err = -ENODEV; 245 + goto err_sch_gpio_core; 245 246 } 246 247 247 248 sch_gpio_core.dev = &pdev->dev;