Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux
Pull clock fixes from Mike Turquette:
"Late fixes for clock drivers. All of these fixes are for user-visible
regressions, typically boot failures or other unsafe system
configuration that causes badness"
* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
clk: clk-divider: fix divisor > 255 bug
clk: exynos: File scope reg_save array should depend on PM_SLEEP
clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock
ARM: dts: exynos5250: Fix MDMA0 clock number
clk: samsung: exynos5250: Add MDMA0 clocks
clk: samsung: exynos5250: Fix ACP gate register offset
clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks
clk: samsung: exynos4: Correct SRC_MFC register
+19
-13
+2
Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+2
Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+1
-1
arch/arm/boot/dts/exynos5250.dtsi
+1
-1
arch/arm/boot/dts/exynos5250.dtsi
+1
-1
drivers/clk/clk-divider.c
+1
-1
drivers/clk/clk-divider.c
+5
-5
drivers/clk/samsung/clk-exynos-audss.c
+5
-5
drivers/clk/samsung/clk-exynos-audss.c
···
26
26
#define ASS_CLK_DIV 0x4
27
27
#define ASS_CLK_GATE 0x8
28
28
29
+
/* list of all parent clock list */
30
+
static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
31
+
static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
32
+
33
+
#ifdef CONFIG_PM_SLEEP
29
34
static unsigned long reg_save[][2] = {
30
35
{ASS_CLK_SRC, 0},
31
36
{ASS_CLK_DIV, 0},
32
37
{ASS_CLK_GATE, 0},
33
38
};
34
39
35
-
/* list of all parent clock list */
36
-
static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
37
-
static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
38
-
39
-
#ifdef CONFIG_PM_SLEEP
40
40
static int exynos_audss_clk_suspend(void)
41
41
{
42
42
int i;
+1
-1
drivers/clk/samsung/clk-exynos4.c
+1
-1
drivers/clk/samsung/clk-exynos4.c
+9
-5
drivers/clk/samsung/clk-exynos5250.c
+9
-5
drivers/clk/samsung/clk-exynos5250.c
···
25
25
#define MPLL_LOCK 0x4000
26
26
#define MPLL_CON0 0x4100
27
27
#define SRC_CORE1 0x4204
28
+
#define GATE_IP_ACP 0x8800
28
29
#define CPLL_LOCK 0x10020
29
30
#define EPLL_LOCK 0x10030
30
31
#define VPLL_LOCK 0x10040
···
76
75
#define SRC_CDREX 0x20200
77
76
#define PLL_DIV2_SEL 0x20a24
78
77
#define GATE_IP_DISP1 0x10928
79
-
#define GATE_IP_ACP 0x10000
80
78
81
79
/* list of PLLs to be registered */
82
80
enum exynos5250_plls {
···
120
120
spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
121
121
hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
122
122
tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
123
-
wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
123
+
wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, mdma0,
124
+
smmu_mdma0,
124
125
125
126
/* mux clocks */
126
127
mout_hdmi = 1024,
···
355
354
GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0),
356
355
GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0),
357
356
GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
358
-
GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
359
-
GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
357
+
GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 2, 0, 0),
358
+
GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 1, 0, 0),
360
359
GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
361
360
GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0),
362
361
GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
···
407
406
GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
408
407
GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
409
408
GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
410
-
GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
409
+
GATE(sysreg, "sysreg", "aclk66",
410
+
GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
411
411
GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
412
412
GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
413
413
GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
···
494
492
GATE(mixer, "mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
495
493
GATE(hdmi, "hdmi", "mout_aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
496
494
GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0),
495
+
GATE(mdma0, "mdma0", "aclk266", GATE_IP_ACP, 1, 0, 0),
496
+
GATE(smmu_mdma0, "smmu_mdma0", "aclk266", GATE_IP_ACP, 5, 0, 0),
497
497
};
498
498
499
499
static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {