Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
serial: sh-sci: Introduced function pointers
The aim here is to prepare support for new sci controllers like
the T2H/RSCI whose registers are too much different for being
handled in common code.
This named serial controller also has 32 bits register,
so some return types had to be changed.
The needed generic functions are no longer static, with prototypes
defined in sh-sci-common.h so that they can be used from specific
implementation in a separate file, to keep this driver as little
changed as possible.
For doing so, a set of 'ops' is added to struct sci_port.
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Link: https://lore.kernel.org/r/20250403212919.1137670-9-thierry.bultel.yh@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Thierry Bultel
and committed by
Greg Kroah-Hartman
21fc3d6b
d004e359
+407
-238
+159
drivers/tty/serial/sh-sci-common.h
+159
drivers/tty/serial/sh-sci-common.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
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+
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#ifndef __SH_SCI_COMMON_H__
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#define __SH_SCI_COMMON_H__
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#include <linux/serial_core.h>
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+
8
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enum SCI_CLKS {
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SCI_FCK, /* Functional Clock */
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SCI_SCK, /* Optional External Clock */
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SCI_BRG_INT, /* Optional BRG Internal Clock Source */
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SCI_SCIF_CLK, /* Optional BRG External Clock Source */
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SCI_NUM_CLKS
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};
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+
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/* Offsets into the sci_port->irqs array */
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enum {
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SCIx_ERI_IRQ,
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SCIx_RXI_IRQ,
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SCIx_TXI_IRQ,
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SCIx_BRI_IRQ,
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SCIx_DRI_IRQ,
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SCIx_TEI_IRQ,
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SCIx_NR_IRQS,
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+
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SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
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};
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+
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/* Bit x set means sampling rate x + 1 is supported */
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#define SCI_SR(x) BIT((x) - 1)
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#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
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void sci_release_port(struct uart_port *port);
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int sci_request_port(struct uart_port *port);
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void sci_config_port(struct uart_port *port, int flags);
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int sci_verify_port(struct uart_port *port, struct serial_struct *ser);
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void sci_pm(struct uart_port *port, unsigned int state,
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unsigned int oldstate);
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struct plat_sci_reg {
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u8 offset;
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u8 size;
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};
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+
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struct sci_port_params_bits {
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unsigned int rxtx_enable;
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unsigned int te_clear;
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unsigned int poll_sent_bits;
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};
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+
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struct sci_common_regs {
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unsigned int status;
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unsigned int control;
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};
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/* The actual number of needed registers. This is used by sci only */
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#define SCI_NR_REGS 20
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struct sci_port_params {
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const struct plat_sci_reg regs[SCI_NR_REGS];
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const struct sci_common_regs *common_regs;
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const struct sci_port_params_bits *param_bits;
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unsigned int fifosize;
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unsigned int overrun_reg;
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unsigned int overrun_mask;
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unsigned int sampling_rate_mask;
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unsigned int error_mask;
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unsigned int error_clear;
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};
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struct sci_port_ops {
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u32 (*read_reg)(struct uart_port *port, int reg);
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void (*write_reg)(struct uart_port *port, int reg, int value);
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void (*clear_SCxSR)(struct uart_port *port, unsigned int mask);
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void (*transmit_chars)(struct uart_port *port);
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void (*receive_chars)(struct uart_port *port);
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void (*poll_put_char)(struct uart_port *port, unsigned char c);
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int (*set_rtrg)(struct uart_port *port, int rx_trig);
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int (*rtrg_enabled)(struct uart_port *port);
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void (*shutdown_complete)(struct uart_port *port);
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void (*prepare_console_write)(struct uart_port *port, u32 ctrl);
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void (*console_save)(struct uart_port *port);
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void (*console_restore)(struct uart_port *port);
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size_t (*suspend_regs_size)(void);
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};
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struct sci_port {
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struct uart_port port;
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/* Platform configuration */
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const struct sci_port_params *params;
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const struct plat_sci_port *cfg;
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unsigned int sampling_rate_mask;
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resource_size_t reg_size;
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struct mctrl_gpios *gpios;
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+
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/* Clocks */
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struct clk *clks[SCI_NUM_CLKS];
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unsigned long clk_rates[SCI_NUM_CLKS];
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+
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int irqs[SCIx_NR_IRQS];
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char *irqstr[SCIx_NR_IRQS];
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struct dma_chan *chan_tx;
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struct dma_chan *chan_rx;
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struct reset_control *rstc;
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struct sci_suspend_regs *suspend_regs;
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#ifdef CONFIG_SERIAL_SH_SCI_DMA
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struct dma_chan *chan_tx_saved;
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struct dma_chan *chan_rx_saved;
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dma_cookie_t cookie_tx;
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dma_cookie_t cookie_rx[2];
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dma_cookie_t active_rx;
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dma_addr_t tx_dma_addr;
123
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unsigned int tx_dma_len;
124
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struct scatterlist sg_rx[2];
125
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void *rx_buf[2];
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size_t buf_len_rx;
127
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struct work_struct work_tx;
128
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struct hrtimer rx_timer;
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unsigned int rx_timeout; /* microseconds */
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#endif
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unsigned int rx_frame;
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int rx_trigger;
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struct timer_list rx_fifo_timer;
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int rx_fifo_timeout;
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u16 hscif_tot;
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const struct sci_port_ops *ops;
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bool has_rtscts;
140
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bool autorts;
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bool tx_occurred;
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};
143
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#define to_sci_port(uart) container_of((uart), struct sci_port, port)
145
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void sci_port_disable(struct sci_port *sci_port);
147
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void sci_port_enable(struct sci_port *sci_port);
148
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149
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int sci_startup(struct uart_port *port);
150
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void sci_shutdown(struct uart_port *port);
151
+
152
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#define min_sr(_port) ffs((_port)->sampling_rate_mask)
153
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#define max_sr(_port) fls((_port)->sampling_rate_mask)
154
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155
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#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
156
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int __init scix_early_console_setup(struct earlycon_device *device, int);
157
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#endif
158
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#endif /* __SH_SCI_COMMON_H__ */
+248
-236
drivers/tty/serial/sh-sci.c
+248
-236
drivers/tty/serial/sh-sci.c
···
56
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57
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#include "serial_mctrl_gpio.h"
58
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#include "sh-sci.h"
59
-
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/* Offsets into the sci_port->irqs array */
61
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enum {
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SCIx_ERI_IRQ,
63
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SCIx_RXI_IRQ,
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SCIx_TXI_IRQ,
65
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SCIx_BRI_IRQ,
66
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SCIx_DRI_IRQ,
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SCIx_TEI_IRQ,
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SCIx_NR_IRQS,
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-
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SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71
-
};
59
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#include "sh-sci-common.h"
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#define SCIx_IRQ_IS_MUXED(port) \
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62
((port)->irqs[SCIx_ERI_IRQ] == \
···
64
76
((port)->irqs[SCIx_ERI_IRQ] && \
65
77
((port)->irqs[SCIx_RXI_IRQ] < 0))
66
78
67
-
enum SCI_CLKS {
68
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SCI_FCK, /* Functional Clock */
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SCI_SCK, /* Optional External Clock */
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SCI_BRG_INT, /* Optional BRG Internal Clock Source */
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SCI_SCIF_CLK, /* Optional BRG External Clock Source */
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SCI_NUM_CLKS
73
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};
74
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75
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/* Bit x set means sampling rate x + 1 is supported */
76
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#define SCI_SR(x) BIT((x) - 1)
77
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#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
78
-
79
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#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
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SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
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SCI_SR(19) | SCI_SR(27)
82
-
83
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#define min_sr(_port) ffs((_port)->sampling_rate_mask)
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#define max_sr(_port) fls((_port)->sampling_rate_mask)
85
82
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/* Iterate over all supported sampling rates, from high to low */
87
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#define for_each_sr(_sr, _port) \
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for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
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if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
90
87
91
-
struct plat_sci_reg {
92
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u8 offset, size;
88
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#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
89
+
90
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static struct sci_port sci_ports[SCI_NPORTS];
91
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static unsigned long sci_ports_in_use;
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static struct uart_driver sci_uart_driver;
93
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static bool sci_uart_earlycon;
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static bool sci_uart_earlycon_dev_probing;
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static const struct sci_port_params_bits sci_sci_port_params_bits = {
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.rxtx_enable = SCSCR_RE | SCSCR_TE,
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.te_clear = SCSCR_TE | SCSCR_TEIE,
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.poll_sent_bits = SCI_TDRE | SCI_TEND
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};
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static const struct sci_port_params_bits sci_scif_port_params_bits = {
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.rxtx_enable = SCSCR_RE | SCSCR_TE,
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.te_clear = SCSCR_TE | SCSCR_TEIE,
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.poll_sent_bits = SCIF_TDFE | SCIF_TEND
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};
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static const struct sci_common_regs sci_common_regs = {
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.status = SCxSR,
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.control = SCSCR,
93
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};
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struct sci_suspend_regs {
···
112
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u8 semr;
113
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};
114
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struct sci_port_params {
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const struct plat_sci_reg regs[SCIx_NR_REGS];
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unsigned int fifosize;
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unsigned int overrun_reg;
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unsigned int overrun_mask;
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unsigned int sampling_rate_mask;
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unsigned int error_mask;
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unsigned int error_clear;
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};
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struct sci_port {
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struct uart_port port;
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/* Platform configuration */
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const struct sci_port_params *params;
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const struct plat_sci_port *cfg;
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unsigned int sampling_rate_mask;
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resource_size_t reg_size;
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struct mctrl_gpios *gpios;
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-
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/* Clocks */
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struct clk *clks[SCI_NUM_CLKS];
137
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unsigned long clk_rates[SCI_NUM_CLKS];
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-
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int irqs[SCIx_NR_IRQS];
140
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char *irqstr[SCIx_NR_IRQS];
141
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struct dma_chan *chan_tx;
143
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struct dma_chan *chan_rx;
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struct reset_control *rstc;
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#ifdef CONFIG_SERIAL_SH_SCI_DMA
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struct dma_chan *chan_tx_saved;
149
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struct dma_chan *chan_rx_saved;
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dma_cookie_t cookie_tx;
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dma_cookie_t cookie_rx[2];
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dma_cookie_t active_rx;
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dma_addr_t tx_dma_addr;
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unsigned int tx_dma_len;
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struct scatterlist sg_rx[2];
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void *rx_buf[2];
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size_t buf_len_rx;
158
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struct work_struct work_tx;
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struct hrtimer rx_timer;
160
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unsigned int rx_timeout; /* microseconds */
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#endif
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unsigned int rx_frame;
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int rx_trigger;
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struct timer_list rx_fifo_timer;
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int rx_fifo_timeout;
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struct sci_suspend_regs suspend_regs;
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u16 hscif_tot;
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bool has_rtscts;
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bool autorts;
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bool tx_occurred;
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};
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#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
175
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176
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static struct sci_port sci_ports[SCI_NPORTS];
177
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static unsigned long sci_ports_in_use;
178
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static struct uart_driver sci_uart_driver;
179
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static bool sci_uart_earlycon;
180
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static bool sci_uart_earlycon_dev_probing;
181
-
182
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static inline struct sci_port *
183
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to_sci_port(struct uart_port *uart)
121
+
static size_t sci_suspend_regs_size(void)
184
122
{
185
-
return container_of(uart, struct sci_port, port);
123
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return sizeof(struct sci_suspend_regs);
186
124
}
187
125
188
126
static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
···
137
211
.sampling_rate_mask = SCI_SR(32),
138
212
.error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
139
213
.error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
214
+
.param_bits = &sci_sci_port_params_bits,
215
+
.common_regs = &sci_common_regs,
140
216
},
141
217
142
218
/*
···
161
233
.sampling_rate_mask = SCI_SR(32),
162
234
.error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
163
235
.error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
236
+
.param_bits = &sci_scif_port_params_bits,
237
+
.common_regs = &sci_common_regs,
164
238
},
165
239
166
240
/*
···
187
257
.sampling_rate_mask = SCI_SR_SCIFAB,
188
258
.error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
189
259
.error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
260
+
.param_bits = &sci_scif_port_params_bits,
261
+
.common_regs = &sci_common_regs,
190
262
},
191
263
192
264
/*
···
214
282
.sampling_rate_mask = SCI_SR_SCIFAB,
215
283
.error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
216
284
.error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
285
+
.param_bits = &sci_scif_port_params_bits,
286
+
.common_regs = &sci_common_regs,
217
287
},
218
288
219
289
/*
···
241
307
.sampling_rate_mask = SCI_SR(32),
242
308
.error_mask = SCIF_DEFAULT_ERROR_MASK,
243
309
.error_clear = SCIF_ERROR_CLEAR,
310
+
.param_bits = &sci_scif_port_params_bits,
311
+
.common_regs = &sci_common_regs,
244
312
},
245
313
246
314
/*
···
271
335
.sampling_rate_mask = SCI_SR(32),
272
336
.error_mask = SCIF_DEFAULT_ERROR_MASK,
273
337
.error_clear = SCIF_ERROR_CLEAR,
338
+
.param_bits = &sci_scif_port_params_bits,
339
+
.common_regs = &sci_common_regs,
274
340
},
275
341
276
342
/*
···
304
366
.sampling_rate_mask = SCI_SR(32),
305
367
.error_mask = SCIF_DEFAULT_ERROR_MASK,
306
368
.error_clear = SCIF_ERROR_CLEAR,
369
+
.param_bits = &sci_scif_port_params_bits,
370
+
.common_regs = &sci_common_regs,
307
371
},
308
372
309
373
/*
···
328
388
.sampling_rate_mask = SCI_SR(32),
329
389
.error_mask = SCIF_DEFAULT_ERROR_MASK,
330
390
.error_clear = SCIF_ERROR_CLEAR,
391
+
.param_bits = &sci_scif_port_params_bits,
392
+
.common_regs = &sci_common_regs,
331
393
},
332
394
333
395
/*
···
354
412
.sampling_rate_mask = SCI_SR(32),
355
413
.error_mask = SCIF_DEFAULT_ERROR_MASK,
356
414
.error_clear = SCIF_ERROR_CLEAR,
415
+
.param_bits = &sci_scif_port_params_bits,
416
+
.common_regs = &sci_common_regs,
357
417
},
358
418
359
419
/*
···
383
439
.sampling_rate_mask = SCI_SR(32),
384
440
.error_mask = SCIF_DEFAULT_ERROR_MASK,
385
441
.error_clear = SCIF_ERROR_CLEAR,
442
+
.param_bits = &sci_scif_port_params_bits,
443
+
.common_regs = &sci_common_regs,
386
444
},
387
445
388
446
/*
···
414
468
.sampling_rate_mask = SCI_SR_RANGE(8, 32),
415
469
.error_mask = SCIF_DEFAULT_ERROR_MASK,
416
470
.error_clear = SCIF_ERROR_CLEAR,
471
+
.param_bits = &sci_scif_port_params_bits,
472
+
.common_regs = &sci_common_regs,
417
473
},
418
474
419
475
/*
···
440
492
.sampling_rate_mask = SCI_SR(32),
441
493
.error_mask = SCIF_DEFAULT_ERROR_MASK,
442
494
.error_clear = SCIF_ERROR_CLEAR,
495
+
.param_bits = &sci_scif_port_params_bits,
496
+
.common_regs = &sci_common_regs,
443
497
},
444
498
445
499
/*
···
469
519
.sampling_rate_mask = SCI_SR(32),
470
520
.error_mask = SCIF_DEFAULT_ERROR_MASK,
471
521
.error_clear = SCIF_ERROR_CLEAR,
522
+
.param_bits = &sci_scif_port_params_bits,
523
+
.common_regs = &sci_common_regs,
472
524
},
473
525
474
526
/*
···
494
542
.sampling_rate_mask = SCI_SR(16),
495
543
.error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
496
544
.error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
545
+
.param_bits = &sci_scif_port_params_bits,
546
+
.common_regs = &sci_common_regs,
497
547
},
498
548
};
499
549
···
533
579
WARN(1, "Invalid register access\n");
534
580
}
535
581
536
-
static void sci_port_enable(struct sci_port *sci_port)
582
+
void sci_port_enable(struct sci_port *sci_port)
537
583
{
538
584
unsigned int i;
539
585
···
549
595
sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
550
596
}
551
597
552
-
static void sci_port_disable(struct sci_port *sci_port)
598
+
void sci_port_disable(struct sci_port *sci_port)
553
599
{
554
600
unsigned int i;
555
601
···
689
735
static int sci_poll_get_char(struct uart_port *port)
690
736
{
691
737
unsigned short status;
738
+
struct sci_port *s = to_sci_port(port);
692
739
int c;
693
740
694
741
do {
695
742
status = sci_serial_in(port, SCxSR);
696
743
if (status & SCxSR_ERRORS(port)) {
697
-
sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
744
+
s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
698
745
continue;
699
746
}
700
747
break;
···
708
753
709
754
/* Dummy read */
710
755
sci_serial_in(port, SCxSR);
711
-
sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
756
+
s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
712
757
713
758
return c;
714
759
}
···
716
761
717
762
static void sci_poll_put_char(struct uart_port *port, unsigned char c)
718
763
{
719
-
unsigned short status;
764
+
struct sci_port *s = to_sci_port(port);
765
+
const struct sci_common_regs *regs = s->params->common_regs;
766
+
unsigned int status;
720
767
721
768
do {
722
-
status = sci_serial_in(port, SCxSR);
769
+
status = s->ops->read_reg(port, regs->status);
723
770
} while (!(status & SCxSR_TDxE(port)));
724
771
725
772
sci_serial_out(port, SCxTDR, c);
726
-
sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
773
+
s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
727
774
}
728
775
#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
729
776
CONFIG_SERIAL_SH_SCI_EARLYCON */
···
868
911
port->icount.tx++;
869
912
} while (--count > 0);
870
913
871
-
sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
914
+
s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
872
915
873
916
if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
874
917
uart_write_wakeup(port);
···
887
930
static void sci_receive_chars(struct uart_port *port)
888
931
{
889
932
struct tty_port *tport = &port->state->port;
933
+
struct sci_port *s = to_sci_port(port);
890
934
int i, count, copied = 0;
891
935
unsigned short status;
892
936
unsigned char flag;
···
942
984
}
943
985
944
986
sci_serial_in(port, SCxSR); /* dummy read */
945
-
sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
987
+
s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
946
988
947
989
copied += count;
948
990
port->icount.rx += count;
···
955
997
/* TTY buffers full; read from RX reg to prevent lockup */
956
998
sci_serial_in(port, SCxRDR);
957
999
sci_serial_in(port, SCxSR); /* dummy read */
958
-
sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1000
+
s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
959
1001
}
960
1002
}
961
1003
962
1004
static int sci_handle_errors(struct uart_port *port)
963
1005
{
964
1006
int copied = 0;
965
-
unsigned short status = sci_serial_in(port, SCxSR);
966
-
struct tty_port *tport = &port->state->port;
967
1007
struct sci_port *s = to_sci_port(port);
1008
+
const struct sci_common_regs *regs = s->params->common_regs;
1009
+
unsigned int status = s->ops->read_reg(port, regs->status);
1010
+
struct tty_port *tport = &port->state->port;
968
1011
969
1012
/* Handle overruns */
970
1013
if (status & s->params->overrun_mask) {
···
1124
1165
struct uart_port *port = &s->port;
1125
1166
1126
1167
dev_dbg(port->dev, "Rx timed out\n");
1127
-
scif_set_rtrg(port, 1);
1168
+
s->ops->set_rtrg(port, 1);
1128
1169
}
1129
1170
1130
1171
static ssize_t rx_fifo_trigger_show(struct device *dev,
···
1149
1190
if (ret)
1150
1191
return ret;
1151
1192
1152
-
sci->rx_trigger = scif_set_rtrg(port, r);
1193
+
sci->rx_trigger = sci->ops->set_rtrg(port, r);
1153
1194
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1154
-
scif_set_rtrg(port, 1);
1195
+
sci->ops->set_rtrg(port, 1);
1155
1196
1156
1197
return count;
1157
1198
}
···
1194
1235
sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1195
1236
} else {
1196
1237
sci->rx_fifo_timeout = r;
1197
-
scif_set_rtrg(port, 1);
1238
+
sci->ops->set_rtrg(port, 1);
1198
1239
if (r > 0)
1199
1240
timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1200
1241
}
···
1319
1360
s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1320
1361
enable_irq(s->irqs[SCIx_RXI_IRQ]);
1321
1362
if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1322
-
scif_set_rtrg(port, s->rx_trigger);
1363
+
s->ops->set_rtrg(port, s->rx_trigger);
1323
1364
else
1324
1365
scr &= ~SCSCR_RDRQE;
1325
1366
}
···
1757
1798
s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1758
1799
disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
1759
1800
if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1760
-
scif_set_rtrg(port, 1);
1801
+
s->ops->set_rtrg(port, 1);
1761
1802
scr |= SCSCR_RIE;
1762
1803
} else {
1763
1804
scr |= SCSCR_RDRQE;
···
1783
1824
#endif
1784
1825
1785
1826
if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1786
-
if (!scif_rtrg_enabled(port))
1787
-
scif_set_rtrg(port, s->rx_trigger);
1827
+
if (!s->ops->rtrg_enabled(port))
1828
+
s->ops->set_rtrg(port, s->rx_trigger);
1788
1829
1789
1830
mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1790
1831
s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
···
1794
1835
* of whether the I_IXOFF is set, otherwise, how is the interrupt
1795
1836
* to be disabled?
1796
1837
*/
1797
-
sci_receive_chars(port);
1838
+
s->ops->receive_chars(port);
1798
1839
1799
1840
return IRQ_HANDLED;
1800
1841
}
···
1803
1844
{
1804
1845
struct uart_port *port = ptr;
1805
1846
unsigned long flags;
1847
+
struct sci_port *s = to_sci_port(port);
1806
1848
1807
1849
uart_port_lock_irqsave(port, &flags);
1808
-
sci_transmit_chars(port);
1850
+
s->ops->transmit_chars(port);
1809
1851
uart_port_unlock_irqrestore(port, flags);
1810
1852
1811
1853
return IRQ_HANDLED;
···
1815
1855
static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
1816
1856
{
1817
1857
struct uart_port *port = ptr;
1858
+
struct sci_port *s = to_sci_port(port);
1859
+
const struct sci_common_regs *regs = s->params->common_regs;
1818
1860
unsigned long flags;
1819
-
unsigned short ctrl;
1861
+
u32 ctrl;
1820
1862
1821
1863
if (port->type != PORT_SCI)
1822
1864
return sci_tx_interrupt(irq, ptr);
1823
1865
1824
1866
uart_port_lock_irqsave(port, &flags);
1825
-
ctrl = sci_serial_in(port, SCSCR);
1826
-
ctrl &= ~(SCSCR_TE | SCSCR_TEIE);
1827
-
sci_serial_out(port, SCSCR, ctrl);
1867
+
ctrl = s->ops->read_reg(port, regs->control) &
1868
+
~(s->params->param_bits->te_clear);
1869
+
s->ops->write_reg(port, regs->control, ctrl);
1828
1870
uart_port_unlock_irqrestore(port, flags);
1829
1871
1830
1872
return IRQ_HANDLED;
···
1835
1873
static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1836
1874
{
1837
1875
struct uart_port *port = ptr;
1876
+
struct sci_port *s = to_sci_port(port);
1838
1877
1839
1878
/* Handle BREAKs */
1840
1879
sci_handle_breaks(port);
···
1843
1880
/* drop invalid character received before break was detected */
1844
1881
sci_serial_in(port, SCxRDR);
1845
1882
1846
-
sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1883
+
s->ops->clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1847
1884
1848
1885
return IRQ_HANDLED;
1849
1886
}
···
1871
1908
if (sci_handle_errors(port)) {
1872
1909
/* discard character in rx buffer */
1873
1910
sci_serial_in(port, SCxSR);
1874
-
sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1911
+
s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1875
1912
}
1876
1913
} else {
1877
1914
sci_handle_fifo_overrun(port);
1878
1915
if (!s->chan_rx)
1879
-
sci_receive_chars(port);
1916
+
s->ops->receive_chars(port);
1880
1917
}
1881
1918
1882
-
sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1919
+
s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1883
1920
1884
1921
/* Kick the transmission */
1885
1922
if (!s->chan_tx)
···
2249
2286
uart_port_unlock_irqrestore(port, flags);
2250
2287
}
2251
2288
2252
-
static int sci_startup(struct uart_port *port)
2289
+
static void sci_shutdown_complete(struct uart_port *port)
2290
+
{
2291
+
struct sci_port *s = to_sci_port(port);
2292
+
u16 scr;
2293
+
2294
+
scr = sci_serial_in(port, SCSCR);
2295
+
sci_serial_out(port, SCSCR,
2296
+
scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2297
+
}
2298
+
2299
+
int sci_startup(struct uart_port *port)
2253
2300
{
2254
2301
struct sci_port *s = to_sci_port(port);
2255
2302
int ret;
···
2278
2305
return 0;
2279
2306
}
2280
2307
2281
-
static void sci_shutdown(struct uart_port *port)
2308
+
void sci_shutdown(struct uart_port *port)
2282
2309
{
2283
2310
struct sci_port *s = to_sci_port(port);
2284
2311
unsigned long flags;
2285
-
u16 scr;
2286
2312
2287
2313
dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2288
2314
···
2291
2319
uart_port_lock_irqsave(port, &flags);
2292
2320
sci_stop_rx(port);
2293
2321
sci_stop_tx(port);
2294
-
/*
2295
-
* Stop RX and TX, disable related interrupts, keep clock source
2296
-
* and HSCIF TOT bits
2297
-
*/
2298
-
scr = sci_serial_in(port, SCSCR);
2299
-
sci_serial_out(port, SCSCR,
2300
-
scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2322
+
s->ops->shutdown_complete(port);
2301
2323
uart_port_unlock_irqrestore(port, flags);
2302
2324
2303
2325
#ifdef CONFIG_SERIAL_SH_SCI_DMA
···
2368
2402
2369
2403
/* calculate sample rate, BRR, and clock select */
2370
2404
static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2371
-
unsigned int *brr, unsigned int *srr,
2372
-
unsigned int *cks)
2405
+
unsigned int *brr, unsigned int *srr,
2406
+
unsigned int *cks)
2373
2407
{
2374
2408
unsigned long freq = s->clk_rates[SCI_FCK];
2375
2409
unsigned int sr, br, prediv, scrate, c;
···
2446
2480
if (reg->size)
2447
2481
sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2448
2482
2449
-
sci_clear_SCxSR(port,
2450
-
SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2451
-
SCxSR_BREAK_CLEAR(port));
2483
+
s->ops->clear_SCxSR(port,
2484
+
SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2485
+
SCxSR_BREAK_CLEAR(port));
2452
2486
if (sci_getreg(port, SCLSR)->size) {
2453
2487
status = sci_serial_in(port, SCLSR);
2454
2488
status &= ~(SCLSR_TO | SCLSR_ORER);
···
2457
2491
2458
2492
if (s->rx_trigger > 1) {
2459
2493
if (s->rx_fifo_timeout) {
2460
-
scif_set_rtrg(port, 1);
2494
+
s->ops->set_rtrg(port, 1);
2461
2495
timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2462
2496
} else {
2463
2497
if (port->type == PORT_SCIFA ||
2464
2498
port->type == PORT_SCIFB)
2465
-
scif_set_rtrg(port, 1);
2499
+
s->ops->set_rtrg(port, 1);
2466
2500
else
2467
-
scif_set_rtrg(port, s->rx_trigger);
2501
+
s->ops->set_rtrg(port, s->rx_trigger);
2468
2502
}
2469
2503
}
2470
2504
}
···
2724
2758
sci_enable_ms(port);
2725
2759
}
2726
2760
2727
-
static void sci_pm(struct uart_port *port, unsigned int state,
2761
+
void sci_pm(struct uart_port *port, unsigned int state,
2728
2762
unsigned int oldstate)
2729
2763
{
2730
2764
struct sci_port *sci_port = to_sci_port(port);
···
2787
2821
return 0;
2788
2822
}
2789
2823
2790
-
static void sci_release_port(struct uart_port *port)
2824
+
void sci_release_port(struct uart_port *port)
2791
2825
{
2792
2826
struct sci_port *sport = to_sci_port(port);
2793
2827
···
2799
2833
release_mem_region(port->mapbase, sport->reg_size);
2800
2834
}
2801
2835
2802
-
static int sci_request_port(struct uart_port *port)
2836
+
int sci_request_port(struct uart_port *port)
2803
2837
{
2804
2838
struct resource *res;
2805
2839
struct sci_port *sport = to_sci_port(port);
···
2821
2855
return 0;
2822
2856
}
2823
2857
2824
-
static void sci_config_port(struct uart_port *port, int flags)
2858
+
void sci_config_port(struct uart_port *port, int flags)
2825
2859
{
2826
2860
if (flags & UART_CONFIG_TYPE) {
2827
2861
struct sci_port *sport = to_sci_port(port);
···
2831
2865
}
2832
2866
}
2833
2867
2834
-
static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2868
+
int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2835
2869
{
2836
2870
if (ser->baud_base < 2400)
2837
2871
/* No paper tape reader for Mitch.. */
2838
2872
return -EINVAL;
2839
2873
2840
2874
return 0;
2875
+
}
2876
+
2877
+
static void sci_prepare_console_write(struct uart_port *port, u32 ctrl)
2878
+
{
2879
+
struct sci_port *s = to_sci_port(port);
2880
+
u32 ctrl_temp =
2881
+
s->params->param_bits->rxtx_enable |
2882
+
(s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2883
+
(ctrl & (SCSCR_CKE1 | SCSCR_CKE0)) |
2884
+
s->hscif_tot;
2885
+
sci_serial_out(port, SCSCR, ctrl_temp);
2886
+
}
2887
+
2888
+
static void sci_console_save(struct uart_port *port)
2889
+
{
2890
+
struct sci_port *s = to_sci_port(port);
2891
+
struct sci_suspend_regs *regs = s->suspend_regs;
2892
+
2893
+
if (sci_getreg(port, SCDL)->size)
2894
+
regs->scdl = sci_serial_in(port, SCDL);
2895
+
if (sci_getreg(port, SCCKS)->size)
2896
+
regs->sccks = sci_serial_in(port, SCCKS);
2897
+
if (sci_getreg(port, SCSMR)->size)
2898
+
regs->scsmr = sci_serial_in(port, SCSMR);
2899
+
if (sci_getreg(port, SCSCR)->size)
2900
+
regs->scscr = sci_serial_in(port, SCSCR);
2901
+
if (sci_getreg(port, SCFCR)->size)
2902
+
regs->scfcr = sci_serial_in(port, SCFCR);
2903
+
if (sci_getreg(port, SCSPTR)->size)
2904
+
regs->scsptr = sci_serial_in(port, SCSPTR);
2905
+
if (sci_getreg(port, SCBRR)->size)
2906
+
regs->scbrr = sci_serial_in(port, SCBRR);
2907
+
if (sci_getreg(port, HSSRR)->size)
2908
+
regs->hssrr = sci_serial_in(port, HSSRR);
2909
+
if (sci_getreg(port, SCPCR)->size)
2910
+
regs->scpcr = sci_serial_in(port, SCPCR);
2911
+
if (sci_getreg(port, SCPDR)->size)
2912
+
regs->scpdr = sci_serial_in(port, SCPDR);
2913
+
if (sci_getreg(port, SEMR)->size)
2914
+
regs->semr = sci_serial_in(port, SEMR);
2915
+
}
2916
+
2917
+
static void sci_console_restore(struct uart_port *port)
2918
+
{
2919
+
struct sci_port *s = to_sci_port(port);
2920
+
struct sci_suspend_regs *regs = s->suspend_regs;
2921
+
2922
+
if (sci_getreg(port, SCDL)->size)
2923
+
sci_serial_out(port, SCDL, regs->scdl);
2924
+
if (sci_getreg(port, SCCKS)->size)
2925
+
sci_serial_out(port, SCCKS, regs->sccks);
2926
+
if (sci_getreg(port, SCSMR)->size)
2927
+
sci_serial_out(port, SCSMR, regs->scsmr);
2928
+
if (sci_getreg(port, SCSCR)->size)
2929
+
sci_serial_out(port, SCSCR, regs->scscr);
2930
+
if (sci_getreg(port, SCFCR)->size)
2931
+
sci_serial_out(port, SCFCR, regs->scfcr);
2932
+
if (sci_getreg(port, SCSPTR)->size)
2933
+
sci_serial_out(port, SCSPTR, regs->scsptr);
2934
+
if (sci_getreg(port, SCBRR)->size)
2935
+
sci_serial_out(port, SCBRR, regs->scbrr);
2936
+
if (sci_getreg(port, HSSRR)->size)
2937
+
sci_serial_out(port, HSSRR, regs->hssrr);
2938
+
if (sci_getreg(port, SCPCR)->size)
2939
+
sci_serial_out(port, SCPCR, regs->scpcr);
2940
+
if (sci_getreg(port, SCPDR)->size)
2941
+
sci_serial_out(port, SCPDR, regs->scpdr);
2942
+
if (sci_getreg(port, SEMR)->size)
2943
+
sci_serial_out(port, SEMR, regs->semr);
2841
2944
}
2842
2945
2843
2946
static const struct uart_ops sci_uart_ops = {
···
2932
2897
.poll_get_char = sci_poll_get_char,
2933
2898
.poll_put_char = sci_poll_put_char,
2934
2899
#endif
2900
+
};
2901
+
2902
+
static const struct sci_port_ops sci_port_ops = {
2903
+
.read_reg = sci_serial_in,
2904
+
.write_reg = sci_serial_out,
2905
+
.clear_SCxSR = sci_clear_SCxSR,
2906
+
.transmit_chars = sci_transmit_chars,
2907
+
.receive_chars = sci_receive_chars,
2908
+
#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2909
+
defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2910
+
.poll_put_char = sci_poll_put_char,
2911
+
#endif
2912
+
.set_rtrg = scif_set_rtrg,
2913
+
.rtrg_enabled = scif_rtrg_enabled,
2914
+
.shutdown_complete = sci_shutdown_complete,
2915
+
.prepare_console_write = sci_prepare_console_write,
2916
+
.console_save = sci_console_save,
2917
+
.console_restore = sci_console_restore,
2918
+
.suspend_regs_size = sci_suspend_regs_size,
2935
2919
};
2936
2920
2937
2921
static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
···
3046
2992
int ret;
3047
2993
3048
2994
sci_port->cfg = p;
2995
+
sci_port->ops = &sci_port_ops;
3049
2996
3050
2997
port->ops = &sci_uart_ops;
3051
2998
port->iotype = UPIO_MEM;
···
3159
3104
defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
3160
3105
static void serial_console_putchar(struct uart_port *port, unsigned char ch)
3161
3106
{
3162
-
sci_poll_put_char(port, ch);
3107
+
to_sci_port(port)->ops->poll_put_char(port, ch);
3163
3108
}
3164
3109
3165
3110
/*
···
3171
3116
{
3172
3117
struct sci_port *sci_port = &sci_ports[co->index];
3173
3118
struct uart_port *port = &sci_port->port;
3174
-
unsigned short bits, ctrl, ctrl_temp;
3119
+
const struct sci_common_regs *regs = sci_port->params->common_regs;
3120
+
unsigned int bits;
3121
+
u32 ctrl;
3175
3122
unsigned long flags;
3176
3123
int locked = 1;
3177
3124
···
3185
3128
uart_port_lock_irqsave(port, &flags);
3186
3129
3187
3130
/* first save SCSCR then disable interrupts, keep clock source */
3188
-
ctrl = sci_serial_in(port, SCSCR);
3189
-
ctrl_temp = SCSCR_RE | SCSCR_TE |
3190
-
(sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3191
-
(ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3192
-
sci_serial_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3131
+
3132
+
ctrl = sci_port->ops->read_reg(port, regs->control);
3133
+
sci_port->ops->prepare_console_write(port, ctrl);
3193
3134
3194
3135
uart_console_write(port, s, count, serial_console_putchar);
3195
3136
3196
3137
/* wait until fifo is empty and last bit has been transmitted */
3197
-
bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3198
-
while ((sci_serial_in(port, SCxSR) & bits) != bits)
3138
+
3139
+
bits = sci_port->params->param_bits->poll_sent_bits;
3140
+
3141
+
while ((sci_port->ops->read_reg(port, regs->status) & bits) != bits)
3199
3142
cpu_relax();
3200
3143
3201
3144
/* restore the SCSCR */
3202
-
sci_serial_out(port, SCSCR, ctrl);
3145
+
sci_port->ops->write_reg(port, regs->control, ctrl);
3203
3146
3204
3147
if (locked)
3205
3148
uart_port_unlock_irqrestore(port, flags);
···
3331
3274
if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3332
3275
device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3333
3276
}
3334
-
3335
3277
3336
3278
#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3337
3279
#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
···
3568
3512
}
3569
3513
3570
3514
sp = &sci_ports[dev_id];
3515
+
sp->suspend_regs = devm_kzalloc(&dev->dev,
3516
+
sp->ops->suspend_regs_size(),
3517
+
GFP_KERNEL);
3518
+
if (!sp->suspend_regs)
3519
+
return -ENOMEM;
3571
3520
3572
3521
/*
3573
3522
* In case:
···
3624
3563
return 0;
3625
3564
}
3626
3565
3627
-
static void sci_console_save(struct sci_port *s)
3628
-
{
3629
-
struct sci_suspend_regs *regs = &s->suspend_regs;
3630
-
struct uart_port *port = &s->port;
3631
-
3632
-
if (sci_getreg(port, SCDL)->size)
3633
-
regs->scdl = sci_serial_in(port, SCDL);
3634
-
if (sci_getreg(port, SCCKS)->size)
3635
-
regs->sccks = sci_serial_in(port, SCCKS);
3636
-
if (sci_getreg(port, SCSMR)->size)
3637
-
regs->scsmr = sci_serial_in(port, SCSMR);
3638
-
if (sci_getreg(port, SCSCR)->size)
3639
-
regs->scscr = sci_serial_in(port, SCSCR);
3640
-
if (sci_getreg(port, SCFCR)->size)
3641
-
regs->scfcr = sci_serial_in(port, SCFCR);
3642
-
if (sci_getreg(port, SCSPTR)->size)
3643
-
regs->scsptr = sci_serial_in(port, SCSPTR);
3644
-
if (sci_getreg(port, SCBRR)->size)
3645
-
regs->scbrr = sci_serial_in(port, SCBRR);
3646
-
if (sci_getreg(port, HSSRR)->size)
3647
-
regs->hssrr = sci_serial_in(port, HSSRR);
3648
-
if (sci_getreg(port, SCPCR)->size)
3649
-
regs->scpcr = sci_serial_in(port, SCPCR);
3650
-
if (sci_getreg(port, SCPDR)->size)
3651
-
regs->scpdr = sci_serial_in(port, SCPDR);
3652
-
if (sci_getreg(port, SEMR)->size)
3653
-
regs->semr = sci_serial_in(port, SEMR);
3654
-
}
3655
-
3656
-
static void sci_console_restore(struct sci_port *s)
3657
-
{
3658
-
struct sci_suspend_regs *regs = &s->suspend_regs;
3659
-
struct uart_port *port = &s->port;
3660
-
3661
-
if (sci_getreg(port, SCDL)->size)
3662
-
sci_serial_out(port, SCDL, regs->scdl);
3663
-
if (sci_getreg(port, SCCKS)->size)
3664
-
sci_serial_out(port, SCCKS, regs->sccks);
3665
-
if (sci_getreg(port, SCSMR)->size)
3666
-
sci_serial_out(port, SCSMR, regs->scsmr);
3667
-
if (sci_getreg(port, SCSCR)->size)
3668
-
sci_serial_out(port, SCSCR, regs->scscr);
3669
-
if (sci_getreg(port, SCFCR)->size)
3670
-
sci_serial_out(port, SCFCR, regs->scfcr);
3671
-
if (sci_getreg(port, SCSPTR)->size)
3672
-
sci_serial_out(port, SCSPTR, regs->scsptr);
3673
-
if (sci_getreg(port, SCBRR)->size)
3674
-
sci_serial_out(port, SCBRR, regs->scbrr);
3675
-
if (sci_getreg(port, HSSRR)->size)
3676
-
sci_serial_out(port, HSSRR, regs->hssrr);
3677
-
if (sci_getreg(port, SCPCR)->size)
3678
-
sci_serial_out(port, SCPCR, regs->scpcr);
3679
-
if (sci_getreg(port, SCPDR)->size)
3680
-
sci_serial_out(port, SCPDR, regs->scpdr);
3681
-
if (sci_getreg(port, SEMR)->size)
3682
-
sci_serial_out(port, SEMR, regs->semr);
3683
-
}
3684
-
3685
3566
static __maybe_unused int sci_suspend(struct device *dev)
3686
3567
{
3687
3568
struct sci_port *sport = dev_get_drvdata(dev);
···
3631
3628
if (sport) {
3632
3629
uart_suspend_port(&sci_uart_driver, &sport->port);
3633
3630
3634
-
if (!console_suspend_enabled && uart_console(&sport->port))
3635
-
sci_console_save(sport);
3631
+
if (!console_suspend_enabled && uart_console(&sport->port)) {
3632
+
if (sport->ops->console_save)
3633
+
sport->ops->console_save(&sport->port);
3634
+
}
3636
3635
else
3637
3636
return reset_control_assert(sport->rstc);
3638
3637
}
···
3648
3643
3649
3644
if (sport) {
3650
3645
if (!console_suspend_enabled && uart_console(&sport->port)) {
3651
-
sci_console_restore(sport);
3646
+
if (sport->ops->console_restore)
3647
+
sport->ops->console_restore(&sport->port);
3652
3648
} else {
3653
3649
int ret = reset_control_deassert(sport->rstc);
3654
3650
···
3713
3707
return 0;
3714
3708
}
3715
3709
3716
-
static int __init early_console_setup(struct earlycon_device *device,
3710
+
int __init scix_early_console_setup(struct earlycon_device *device,
3717
3711
int type)
3718
3712
{
3713
+
const struct sci_common_regs *regs;
3714
+
3719
3715
if (!device->port.membase)
3720
3716
return -ENODEV;
3721
3717
···
3725
3717
sci_ports[0].port = device->port;
3726
3718
port_cfg.type = type;
3727
3719
sci_ports[0].cfg = &port_cfg;
3720
+
sci_ports[0].ops = &sci_port_ops;
3728
3721
sci_ports[0].params = sci_probe_regmap(&port_cfg);
3729
3722
sci_uart_earlycon = true;
3730
-
port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3731
-
sci_serial_out(&sci_ports[0].port, SCSCR,
3732
-
SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3723
+
regs = sci_ports[0].params->common_regs;
3724
+
3725
+
port_cfg.scscr = sci_ports[0].ops->read_reg(&sci_ports[0].port, regs->control);
3726
+
sci_ports[0].ops->write_reg(&sci_ports[0].port,
3727
+
regs->control,
3728
+
sci_ports[0].params->param_bits->rxtx_enable | port_cfg.scscr);
3733
3729
3734
3730
device->con->write = serial_console_write;
3735
3731
device->con->exit = early_console_exit;
···
3743
3731
static int __init sci_early_console_setup(struct earlycon_device *device,
3744
3732
const char *opt)
3745
3733
{
3746
-
return early_console_setup(device, PORT_SCI);
3734
+
return scix_early_console_setup(device, PORT_SCI);
3747
3735
}
3748
3736
static int __init scif_early_console_setup(struct earlycon_device *device,
3749
3737
const char *opt)
3750
3738
{
3751
-
return early_console_setup(device, PORT_SCIF);
3739
+
return scix_early_console_setup(device, PORT_SCIF);
3752
3740
}
3753
3741
static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3754
3742
const char *opt)
3755
3743
{
3756
3744
port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3757
-
return early_console_setup(device, PORT_SCIF);
3745
+
return scix_early_console_setup(device, PORT_SCIF);
3758
3746
}
3759
3747
3760
3748
static int __init rzv2hscif_early_console_setup(struct earlycon_device *device,
3761
3749
const char *opt)
3762
3750
{
3763
3751
port_cfg.regtype = SCIx_RZV2H_SCIF_REGTYPE;
3764
-
return early_console_setup(device, PORT_SCIF);
3752
+
return scix_early_console_setup(device, PORT_SCIF);
3765
3753
}
3766
3754
3767
3755
static int __init scifa_early_console_setup(struct earlycon_device *device,
3768
3756
const char *opt)
3769
3757
{
3770
-
return early_console_setup(device, PORT_SCIFA);
3758
+
return scix_early_console_setup(device, PORT_SCIFA);
3771
3759
}
3772
3760
static int __init scifb_early_console_setup(struct earlycon_device *device,
3773
3761
const char *opt)
3774
3762
{
3775
-
return early_console_setup(device, PORT_SCIFB);
3763
+
return scix_early_console_setup(device, PORT_SCIFB);
3776
3764
}
3777
3765
static int __init hscif_early_console_setup(struct earlycon_device *device,
3778
3766
const char *opt)
3779
3767
{
3780
-
return early_console_setup(device, PORT_HSCIF);
3768
+
return scix_early_console_setup(device, PORT_HSCIF);
3781
3769
}
3782
3770
3783
3771
OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);