Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
perf vendor events: Add westmereep-dp counter information
Add counter information necessary for optimizing event grouping the
perf tool.
The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/
The information was added in:
https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4765e1
and later patches.
Co-authored-by: Weilin Wang <weilin.wang@intel.com>
Co-authored-by: Caleb Biggers <caleb.biggers@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-36-irogers@google.com
authored by
Ian Rogers
Weilin Wang
Caleb Biggers
and committed by
Namhyung Kim
22123c26
321e0ffa
+549
+282
tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json
+282
tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Cycles L1D locked",
4
+
"Counter": "0,1",
4
5
"EventCode": "0x63",
5
6
"EventName": "CACHE_LOCK_CYCLES.L1D",
6
7
"SampleAfterValue": "2000000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Cycles L1D and L2 locked",
11
+
"Counter": "0,1",
12
12
"EventCode": "0x63",
13
13
"EventName": "CACHE_LOCK_CYCLES.L1D_L2",
14
14
"SampleAfterValue": "2000000",
···
17
15
},
18
16
{
19
17
"BriefDescription": "L1D cache lines replaced in M state",
18
+
"Counter": "0,1",
20
19
"EventCode": "0x51",
21
20
"EventName": "L1D.M_EVICT",
22
21
"SampleAfterValue": "2000000",
···
25
22
},
26
23
{
27
24
"BriefDescription": "L1D cache lines allocated in the M state",
25
+
"Counter": "0,1",
28
26
"EventCode": "0x51",
29
27
"EventName": "L1D.M_REPL",
30
28
"SampleAfterValue": "2000000",
···
33
29
},
34
30
{
35
31
"BriefDescription": "L1D snoop eviction of cache lines in M state",
32
+
"Counter": "0,1",
36
33
"EventCode": "0x51",
37
34
"EventName": "L1D.M_SNOOP_EVICT",
38
35
"SampleAfterValue": "2000000",
···
41
36
},
42
37
{
43
38
"BriefDescription": "L1 data cache lines allocated",
39
+
"Counter": "0,1",
44
40
"EventCode": "0x51",
45
41
"EventName": "L1D.REPL",
46
42
"SampleAfterValue": "2000000",
···
49
43
},
50
44
{
51
45
"BriefDescription": "L1D prefetch load lock accepted in fill buffer",
46
+
"Counter": "0,1",
52
47
"EventCode": "0x52",
53
48
"EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
54
49
"SampleAfterValue": "2000000",
···
57
50
},
58
51
{
59
52
"BriefDescription": "L1D hardware prefetch misses",
53
+
"Counter": "0,1",
60
54
"EventCode": "0x4E",
61
55
"EventName": "L1D_PREFETCH.MISS",
62
56
"SampleAfterValue": "200000",
···
65
57
},
66
58
{
67
59
"BriefDescription": "L1D hardware prefetch requests",
60
+
"Counter": "0,1",
68
61
"EventCode": "0x4E",
69
62
"EventName": "L1D_PREFETCH.REQUESTS",
70
63
"SampleAfterValue": "200000",
···
73
64
},
74
65
{
75
66
"BriefDescription": "L1D hardware prefetch requests triggered",
67
+
"Counter": "0,1",
76
68
"EventCode": "0x4E",
77
69
"EventName": "L1D_PREFETCH.TRIGGERS",
78
70
"SampleAfterValue": "200000",
···
81
71
},
82
72
{
83
73
"BriefDescription": "L1 writebacks to L2 in E state",
74
+
"Counter": "0,1,2,3",
84
75
"EventCode": "0x28",
85
76
"EventName": "L1D_WB_L2.E_STATE",
86
77
"SampleAfterValue": "100000",
···
89
78
},
90
79
{
91
80
"BriefDescription": "L1 writebacks to L2 in I state (misses)",
81
+
"Counter": "0,1,2,3",
92
82
"EventCode": "0x28",
93
83
"EventName": "L1D_WB_L2.I_STATE",
94
84
"SampleAfterValue": "100000",
···
97
85
},
98
86
{
99
87
"BriefDescription": "All L1 writebacks to L2",
88
+
"Counter": "0,1,2,3",
100
89
"EventCode": "0x28",
101
90
"EventName": "L1D_WB_L2.MESI",
102
91
"SampleAfterValue": "100000",
···
105
92
},
106
93
{
107
94
"BriefDescription": "L1 writebacks to L2 in M state",
95
+
"Counter": "0,1,2,3",
108
96
"EventCode": "0x28",
109
97
"EventName": "L1D_WB_L2.M_STATE",
110
98
"SampleAfterValue": "100000",
···
113
99
},
114
100
{
115
101
"BriefDescription": "L1 writebacks to L2 in S state",
102
+
"Counter": "0,1,2,3",
116
103
"EventCode": "0x28",
117
104
"EventName": "L1D_WB_L2.S_STATE",
118
105
"SampleAfterValue": "100000",
···
121
106
},
122
107
{
123
108
"BriefDescription": "All L2 data requests",
109
+
"Counter": "0,1,2,3",
124
110
"EventCode": "0x26",
125
111
"EventName": "L2_DATA_RQSTS.ANY",
126
112
"SampleAfterValue": "200000",
···
129
113
},
130
114
{
131
115
"BriefDescription": "L2 data demand loads in E state",
116
+
"Counter": "0,1,2,3",
132
117
"EventCode": "0x26",
133
118
"EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
134
119
"SampleAfterValue": "200000",
···
137
120
},
138
121
{
139
122
"BriefDescription": "L2 data demand loads in I state (misses)",
123
+
"Counter": "0,1,2,3",
140
124
"EventCode": "0x26",
141
125
"EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
142
126
"SampleAfterValue": "200000",
···
145
127
},
146
128
{
147
129
"BriefDescription": "L2 data demand requests",
130
+
"Counter": "0,1,2,3",
148
131
"EventCode": "0x26",
149
132
"EventName": "L2_DATA_RQSTS.DEMAND.MESI",
150
133
"SampleAfterValue": "200000",
···
153
134
},
154
135
{
155
136
"BriefDescription": "L2 data demand loads in M state",
137
+
"Counter": "0,1,2,3",
156
138
"EventCode": "0x26",
157
139
"EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
158
140
"SampleAfterValue": "200000",
···
161
141
},
162
142
{
163
143
"BriefDescription": "L2 data demand loads in S state",
144
+
"Counter": "0,1,2,3",
164
145
"EventCode": "0x26",
165
146
"EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
166
147
"SampleAfterValue": "200000",
···
169
148
},
170
149
{
171
150
"BriefDescription": "L2 data prefetches in E state",
151
+
"Counter": "0,1,2,3",
172
152
"EventCode": "0x26",
173
153
"EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
174
154
"SampleAfterValue": "200000",
···
177
155
},
178
156
{
179
157
"BriefDescription": "L2 data prefetches in the I state (misses)",
158
+
"Counter": "0,1,2,3",
180
159
"EventCode": "0x26",
181
160
"EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
182
161
"SampleAfterValue": "200000",
···
185
162
},
186
163
{
187
164
"BriefDescription": "All L2 data prefetches",
165
+
"Counter": "0,1,2,3",
188
166
"EventCode": "0x26",
189
167
"EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
190
168
"SampleAfterValue": "200000",
···
193
169
},
194
170
{
195
171
"BriefDescription": "L2 data prefetches in M state",
172
+
"Counter": "0,1,2,3",
196
173
"EventCode": "0x26",
197
174
"EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
198
175
"SampleAfterValue": "200000",
···
201
176
},
202
177
{
203
178
"BriefDescription": "L2 data prefetches in the S state",
179
+
"Counter": "0,1,2,3",
204
180
"EventCode": "0x26",
205
181
"EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
206
182
"SampleAfterValue": "200000",
···
209
183
},
210
184
{
211
185
"BriefDescription": "L2 lines allocated",
186
+
"Counter": "0,1,2,3",
212
187
"EventCode": "0xF1",
213
188
"EventName": "L2_LINES_IN.ANY",
214
189
"SampleAfterValue": "100000",
···
217
190
},
218
191
{
219
192
"BriefDescription": "L2 lines allocated in the E state",
193
+
"Counter": "0,1,2,3",
220
194
"EventCode": "0xF1",
221
195
"EventName": "L2_LINES_IN.E_STATE",
222
196
"SampleAfterValue": "100000",
···
225
197
},
226
198
{
227
199
"BriefDescription": "L2 lines allocated in the S state",
200
+
"Counter": "0,1,2,3",
228
201
"EventCode": "0xF1",
229
202
"EventName": "L2_LINES_IN.S_STATE",
230
203
"SampleAfterValue": "100000",
···
233
204
},
234
205
{
235
206
"BriefDescription": "L2 lines evicted",
207
+
"Counter": "0,1,2,3",
236
208
"EventCode": "0xF2",
237
209
"EventName": "L2_LINES_OUT.ANY",
238
210
"SampleAfterValue": "100000",
···
241
211
},
242
212
{
243
213
"BriefDescription": "L2 lines evicted by a demand request",
214
+
"Counter": "0,1,2,3",
244
215
"EventCode": "0xF2",
245
216
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
246
217
"SampleAfterValue": "100000",
···
249
218
},
250
219
{
251
220
"BriefDescription": "L2 modified lines evicted by a demand request",
221
+
"Counter": "0,1,2,3",
252
222
"EventCode": "0xF2",
253
223
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
254
224
"SampleAfterValue": "100000",
···
257
225
},
258
226
{
259
227
"BriefDescription": "L2 lines evicted by a prefetch request",
228
+
"Counter": "0,1,2,3",
260
229
"EventCode": "0xF2",
261
230
"EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
262
231
"SampleAfterValue": "100000",
···
265
232
},
266
233
{
267
234
"BriefDescription": "L2 modified lines evicted by a prefetch request",
235
+
"Counter": "0,1,2,3",
268
236
"EventCode": "0xF2",
269
237
"EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
270
238
"SampleAfterValue": "100000",
···
273
239
},
274
240
{
275
241
"BriefDescription": "L2 instruction fetches",
242
+
"Counter": "0,1,2,3",
276
243
"EventCode": "0x24",
277
244
"EventName": "L2_RQSTS.IFETCHES",
278
245
"SampleAfterValue": "200000",
···
281
246
},
282
247
{
283
248
"BriefDescription": "L2 instruction fetch hits",
249
+
"Counter": "0,1,2,3",
284
250
"EventCode": "0x24",
285
251
"EventName": "L2_RQSTS.IFETCH_HIT",
286
252
"SampleAfterValue": "200000",
···
289
253
},
290
254
{
291
255
"BriefDescription": "L2 instruction fetch misses",
256
+
"Counter": "0,1,2,3",
292
257
"EventCode": "0x24",
293
258
"EventName": "L2_RQSTS.IFETCH_MISS",
294
259
"SampleAfterValue": "200000",
···
297
260
},
298
261
{
299
262
"BriefDescription": "L2 load hits",
263
+
"Counter": "0,1,2,3",
300
264
"EventCode": "0x24",
301
265
"EventName": "L2_RQSTS.LD_HIT",
302
266
"SampleAfterValue": "200000",
···
305
267
},
306
268
{
307
269
"BriefDescription": "L2 load misses",
270
+
"Counter": "0,1,2,3",
308
271
"EventCode": "0x24",
309
272
"EventName": "L2_RQSTS.LD_MISS",
310
273
"SampleAfterValue": "200000",
···
313
274
},
314
275
{
315
276
"BriefDescription": "L2 requests",
277
+
"Counter": "0,1,2,3",
316
278
"EventCode": "0x24",
317
279
"EventName": "L2_RQSTS.LOADS",
318
280
"SampleAfterValue": "200000",
···
321
281
},
322
282
{
323
283
"BriefDescription": "All L2 misses",
284
+
"Counter": "0,1,2,3",
324
285
"EventCode": "0x24",
325
286
"EventName": "L2_RQSTS.MISS",
326
287
"SampleAfterValue": "200000",
···
329
288
},
330
289
{
331
290
"BriefDescription": "All L2 prefetches",
291
+
"Counter": "0,1,2,3",
332
292
"EventCode": "0x24",
333
293
"EventName": "L2_RQSTS.PREFETCHES",
334
294
"SampleAfterValue": "200000",
···
337
295
},
338
296
{
339
297
"BriefDescription": "L2 prefetch hits",
298
+
"Counter": "0,1,2,3",
340
299
"EventCode": "0x24",
341
300
"EventName": "L2_RQSTS.PREFETCH_HIT",
342
301
"SampleAfterValue": "200000",
···
345
302
},
346
303
{
347
304
"BriefDescription": "L2 prefetch misses",
305
+
"Counter": "0,1,2,3",
348
306
"EventCode": "0x24",
349
307
"EventName": "L2_RQSTS.PREFETCH_MISS",
350
308
"SampleAfterValue": "200000",
···
353
309
},
354
310
{
355
311
"BriefDescription": "All L2 requests",
312
+
"Counter": "0,1,2,3",
356
313
"EventCode": "0x24",
357
314
"EventName": "L2_RQSTS.REFERENCES",
358
315
"SampleAfterValue": "200000",
···
361
316
},
362
317
{
363
318
"BriefDescription": "L2 RFO requests",
319
+
"Counter": "0,1,2,3",
364
320
"EventCode": "0x24",
365
321
"EventName": "L2_RQSTS.RFOS",
366
322
"SampleAfterValue": "200000",
···
369
323
},
370
324
{
371
325
"BriefDescription": "L2 RFO hits",
326
+
"Counter": "0,1,2,3",
372
327
"EventCode": "0x24",
373
328
"EventName": "L2_RQSTS.RFO_HIT",
374
329
"SampleAfterValue": "200000",
···
377
330
},
378
331
{
379
332
"BriefDescription": "L2 RFO misses",
333
+
"Counter": "0,1,2,3",
380
334
"EventCode": "0x24",
381
335
"EventName": "L2_RQSTS.RFO_MISS",
382
336
"SampleAfterValue": "200000",
···
385
337
},
386
338
{
387
339
"BriefDescription": "All L2 transactions",
340
+
"Counter": "0,1,2,3",
388
341
"EventCode": "0xF0",
389
342
"EventName": "L2_TRANSACTIONS.ANY",
390
343
"SampleAfterValue": "200000",
···
393
344
},
394
345
{
395
346
"BriefDescription": "L2 fill transactions",
347
+
"Counter": "0,1,2,3",
396
348
"EventCode": "0xF0",
397
349
"EventName": "L2_TRANSACTIONS.FILL",
398
350
"SampleAfterValue": "200000",
···
401
351
},
402
352
{
403
353
"BriefDescription": "L2 instruction fetch transactions",
354
+
"Counter": "0,1,2,3",
404
355
"EventCode": "0xF0",
405
356
"EventName": "L2_TRANSACTIONS.IFETCH",
406
357
"SampleAfterValue": "200000",
···
409
358
},
410
359
{
411
360
"BriefDescription": "L1D writeback to L2 transactions",
361
+
"Counter": "0,1,2,3",
412
362
"EventCode": "0xF0",
413
363
"EventName": "L2_TRANSACTIONS.L1D_WB",
414
364
"SampleAfterValue": "200000",
···
417
365
},
418
366
{
419
367
"BriefDescription": "L2 Load transactions",
368
+
"Counter": "0,1,2,3",
420
369
"EventCode": "0xF0",
421
370
"EventName": "L2_TRANSACTIONS.LOAD",
422
371
"SampleAfterValue": "200000",
···
425
372
},
426
373
{
427
374
"BriefDescription": "L2 prefetch transactions",
375
+
"Counter": "0,1,2,3",
428
376
"EventCode": "0xF0",
429
377
"EventName": "L2_TRANSACTIONS.PREFETCH",
430
378
"SampleAfterValue": "200000",
···
433
379
},
434
380
{
435
381
"BriefDescription": "L2 RFO transactions",
382
+
"Counter": "0,1,2,3",
436
383
"EventCode": "0xF0",
437
384
"EventName": "L2_TRANSACTIONS.RFO",
438
385
"SampleAfterValue": "200000",
···
441
386
},
442
387
{
443
388
"BriefDescription": "L2 writeback to LLC transactions",
389
+
"Counter": "0,1,2,3",
444
390
"EventCode": "0xF0",
445
391
"EventName": "L2_TRANSACTIONS.WB",
446
392
"SampleAfterValue": "200000",
···
449
393
},
450
394
{
451
395
"BriefDescription": "L2 demand lock RFOs in E state",
396
+
"Counter": "0,1,2,3",
452
397
"EventCode": "0x27",
453
398
"EventName": "L2_WRITE.LOCK.E_STATE",
454
399
"SampleAfterValue": "100000",
···
457
400
},
458
401
{
459
402
"BriefDescription": "All demand L2 lock RFOs that hit the cache",
403
+
"Counter": "0,1,2,3",
460
404
"EventCode": "0x27",
461
405
"EventName": "L2_WRITE.LOCK.HIT",
462
406
"SampleAfterValue": "100000",
···
465
407
},
466
408
{
467
409
"BriefDescription": "L2 demand lock RFOs in I state (misses)",
410
+
"Counter": "0,1,2,3",
468
411
"EventCode": "0x27",
469
412
"EventName": "L2_WRITE.LOCK.I_STATE",
470
413
"SampleAfterValue": "100000",
···
473
414
},
474
415
{
475
416
"BriefDescription": "All demand L2 lock RFOs",
417
+
"Counter": "0,1,2,3",
476
418
"EventCode": "0x27",
477
419
"EventName": "L2_WRITE.LOCK.MESI",
478
420
"SampleAfterValue": "100000",
···
481
421
},
482
422
{
483
423
"BriefDescription": "L2 demand lock RFOs in M state",
424
+
"Counter": "0,1,2,3",
484
425
"EventCode": "0x27",
485
426
"EventName": "L2_WRITE.LOCK.M_STATE",
486
427
"SampleAfterValue": "100000",
···
489
428
},
490
429
{
491
430
"BriefDescription": "L2 demand lock RFOs in S state",
431
+
"Counter": "0,1,2,3",
492
432
"EventCode": "0x27",
493
433
"EventName": "L2_WRITE.LOCK.S_STATE",
494
434
"SampleAfterValue": "100000",
···
497
435
},
498
436
{
499
437
"BriefDescription": "All L2 demand store RFOs that hit the cache",
438
+
"Counter": "0,1,2,3",
500
439
"EventCode": "0x27",
501
440
"EventName": "L2_WRITE.RFO.HIT",
502
441
"SampleAfterValue": "100000",
···
505
442
},
506
443
{
507
444
"BriefDescription": "L2 demand store RFOs in I state (misses)",
445
+
"Counter": "0,1,2,3",
508
446
"EventCode": "0x27",
509
447
"EventName": "L2_WRITE.RFO.I_STATE",
510
448
"SampleAfterValue": "100000",
···
513
449
},
514
450
{
515
451
"BriefDescription": "All L2 demand store RFOs",
452
+
"Counter": "0,1,2,3",
516
453
"EventCode": "0x27",
517
454
"EventName": "L2_WRITE.RFO.MESI",
518
455
"SampleAfterValue": "100000",
···
521
456
},
522
457
{
523
458
"BriefDescription": "L2 demand store RFOs in M state",
459
+
"Counter": "0,1,2,3",
524
460
"EventCode": "0x27",
525
461
"EventName": "L2_WRITE.RFO.M_STATE",
526
462
"SampleAfterValue": "100000",
···
529
463
},
530
464
{
531
465
"BriefDescription": "L2 demand store RFOs in S state",
466
+
"Counter": "0,1,2,3",
532
467
"EventCode": "0x27",
533
468
"EventName": "L2_WRITE.RFO.S_STATE",
534
469
"SampleAfterValue": "100000",
···
537
470
},
538
471
{
539
472
"BriefDescription": "Longest latency cache miss",
473
+
"Counter": "0,1,2,3",
540
474
"EventCode": "0x2E",
541
475
"EventName": "LONGEST_LAT_CACHE.MISS",
542
476
"SampleAfterValue": "100000",
···
545
477
},
546
478
{
547
479
"BriefDescription": "Longest latency cache reference",
480
+
"Counter": "0,1,2,3",
548
481
"EventCode": "0x2E",
549
482
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
550
483
"SampleAfterValue": "200000",
···
553
484
},
554
485
{
555
486
"BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
487
+
"Counter": "3",
556
488
"EventCode": "0xB",
557
489
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
558
490
"MSRIndex": "0x3F6",
···
563
493
},
564
494
{
565
495
"BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
496
+
"Counter": "3",
566
497
"EventCode": "0xB",
567
498
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
568
499
"MSRIndex": "0x3F6",
···
574
503
},
575
504
{
576
505
"BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
506
+
"Counter": "3",
577
507
"EventCode": "0xB",
578
508
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
579
509
"MSRIndex": "0x3F6",
···
585
513
},
586
514
{
587
515
"BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
516
+
"Counter": "3",
588
517
"EventCode": "0xB",
589
518
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
590
519
"MSRIndex": "0x3F6",
···
596
523
},
597
524
{
598
525
"BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
526
+
"Counter": "3",
599
527
"EventCode": "0xB",
600
528
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
601
529
"MSRIndex": "0x3F6",
···
607
533
},
608
534
{
609
535
"BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
536
+
"Counter": "3",
610
537
"EventCode": "0xB",
611
538
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
612
539
"MSRIndex": "0x3F6",
···
618
543
},
619
544
{
620
545
"BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
546
+
"Counter": "3",
621
547
"EventCode": "0xB",
622
548
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
623
549
"MSRIndex": "0x3F6",
···
629
553
},
630
554
{
631
555
"BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
556
+
"Counter": "3",
632
557
"EventCode": "0xB",
633
558
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
634
559
"MSRIndex": "0x3F6",
···
640
563
},
641
564
{
642
565
"BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
566
+
"Counter": "3",
643
567
"EventCode": "0xB",
644
568
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
645
569
"MSRIndex": "0x3F6",
···
651
573
},
652
574
{
653
575
"BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
576
+
"Counter": "3",
654
577
"EventCode": "0xB",
655
578
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
656
579
"MSRIndex": "0x3F6",
···
662
583
},
663
584
{
664
585
"BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
586
+
"Counter": "3",
665
587
"EventCode": "0xB",
666
588
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
667
589
"MSRIndex": "0x3F6",
···
673
593
},
674
594
{
675
595
"BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
596
+
"Counter": "3",
676
597
"EventCode": "0xB",
677
598
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
678
599
"MSRIndex": "0x3F6",
···
684
603
},
685
604
{
686
605
"BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
606
+
"Counter": "3",
687
607
"EventCode": "0xB",
688
608
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
689
609
"MSRIndex": "0x3F6",
···
695
613
},
696
614
{
697
615
"BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
616
+
"Counter": "3",
698
617
"EventCode": "0xB",
699
618
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
700
619
"MSRIndex": "0x3F6",
···
706
623
},
707
624
{
708
625
"BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
626
+
"Counter": "3",
709
627
"EventCode": "0xB",
710
628
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
711
629
"MSRIndex": "0x3F6",
···
717
633
},
718
634
{
719
635
"BriefDescription": "Instructions retired which contains a load (Precise Event)",
636
+
"Counter": "0,1,2,3",
720
637
"EventCode": "0xB",
721
638
"EventName": "MEM_INST_RETIRED.LOADS",
722
639
"PEBS": "1",
···
726
641
},
727
642
{
728
643
"BriefDescription": "Instructions retired which contains a store (Precise Event)",
644
+
"Counter": "0,1,2,3",
729
645
"EventCode": "0xB",
730
646
"EventName": "MEM_INST_RETIRED.STORES",
731
647
"PEBS": "1",
···
735
649
},
736
650
{
737
651
"BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
652
+
"Counter": "0,1,2,3",
738
653
"EventCode": "0xCB",
739
654
"EventName": "MEM_LOAD_RETIRED.HIT_LFB",
740
655
"PEBS": "1",
···
744
657
},
745
658
{
746
659
"BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
660
+
"Counter": "0,1,2,3",
747
661
"EventCode": "0xCB",
748
662
"EventName": "MEM_LOAD_RETIRED.L1D_HIT",
749
663
"PEBS": "1",
···
753
665
},
754
666
{
755
667
"BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
668
+
"Counter": "0,1,2,3",
756
669
"EventCode": "0xCB",
757
670
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
758
671
"PEBS": "1",
···
762
673
},
763
674
{
764
675
"BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
676
+
"Counter": "0,1,2,3",
765
677
"EventCode": "0xCB",
766
678
"EventName": "MEM_LOAD_RETIRED.LLC_MISS",
767
679
"PEBS": "1",
···
771
681
},
772
682
{
773
683
"BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
684
+
"Counter": "0,1,2,3",
774
685
"EventCode": "0xCB",
775
686
"EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
776
687
"PEBS": "1",
···
780
689
},
781
690
{
782
691
"BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
692
+
"Counter": "0,1,2,3",
783
693
"EventCode": "0xCB",
784
694
"EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
785
695
"PEBS": "1",
···
789
697
},
790
698
{
791
699
"BriefDescription": "All offcore requests",
700
+
"Counter": "0,1,2,3",
792
701
"EventCode": "0xB0",
793
702
"EventName": "OFFCORE_REQUESTS.ANY",
794
703
"SampleAfterValue": "100000",
···
797
704
},
798
705
{
799
706
"BriefDescription": "Offcore read requests",
707
+
"Counter": "0,1,2,3",
800
708
"EventCode": "0xB0",
801
709
"EventName": "OFFCORE_REQUESTS.ANY.READ",
802
710
"SampleAfterValue": "100000",
···
805
711
},
806
712
{
807
713
"BriefDescription": "Offcore RFO requests",
714
+
"Counter": "0,1,2,3",
808
715
"EventCode": "0xB0",
809
716
"EventName": "OFFCORE_REQUESTS.ANY.RFO",
810
717
"SampleAfterValue": "100000",
···
813
718
},
814
719
{
815
720
"BriefDescription": "Offcore demand code read requests",
721
+
"Counter": "0,1,2,3",
816
722
"EventCode": "0xB0",
817
723
"EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",
818
724
"SampleAfterValue": "100000",
···
821
725
},
822
726
{
823
727
"BriefDescription": "Offcore demand data read requests",
728
+
"Counter": "0,1,2,3",
824
729
"EventCode": "0xB0",
825
730
"EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",
826
731
"SampleAfterValue": "100000",
···
829
732
},
830
733
{
831
734
"BriefDescription": "Offcore demand RFO requests",
735
+
"Counter": "0,1,2,3",
832
736
"EventCode": "0xB0",
833
737
"EventName": "OFFCORE_REQUESTS.DEMAND.RFO",
834
738
"SampleAfterValue": "100000",
···
837
739
},
838
740
{
839
741
"BriefDescription": "Offcore L1 data cache writebacks",
742
+
"Counter": "0,1,2,3",
840
743
"EventCode": "0xB0",
841
744
"EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
842
745
"SampleAfterValue": "100000",
···
845
746
},
846
747
{
847
748
"BriefDescription": "Outstanding offcore reads",
749
+
"Counter": "0",
848
750
"EventCode": "0x60",
849
751
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ",
850
752
"SampleAfterValue": "2000000",
···
853
753
},
854
754
{
855
755
"BriefDescription": "Cycles offcore reads busy",
756
+
"Counter": "0",
856
757
"CounterMask": "1",
857
758
"EventCode": "0x60",
858
759
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY",
···
862
761
},
863
762
{
864
763
"BriefDescription": "Outstanding offcore demand code reads",
764
+
"Counter": "0",
865
765
"EventCode": "0x60",
866
766
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE",
867
767
"SampleAfterValue": "2000000",
···
870
768
},
871
769
{
872
770
"BriefDescription": "Cycles offcore demand code read busy",
771
+
"Counter": "0",
873
772
"CounterMask": "1",
874
773
"EventCode": "0x60",
875
774
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY",
···
879
776
},
880
777
{
881
778
"BriefDescription": "Outstanding offcore demand data reads",
779
+
"Counter": "0",
882
780
"EventCode": "0x60",
883
781
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA",
884
782
"SampleAfterValue": "2000000",
···
887
783
},
888
784
{
889
785
"BriefDescription": "Cycles offcore demand data read busy",
786
+
"Counter": "0",
890
787
"CounterMask": "1",
891
788
"EventCode": "0x60",
892
789
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY",
···
896
791
},
897
792
{
898
793
"BriefDescription": "Outstanding offcore demand RFOs",
794
+
"Counter": "0",
899
795
"EventCode": "0x60",
900
796
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO",
901
797
"SampleAfterValue": "2000000",
···
904
798
},
905
799
{
906
800
"BriefDescription": "Cycles offcore demand RFOs busy",
801
+
"Counter": "0",
907
802
"CounterMask": "1",
908
803
"EventCode": "0x60",
909
804
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY",
···
913
806
},
914
807
{
915
808
"BriefDescription": "Offcore requests blocked due to Super Queue full",
809
+
"Counter": "0,1,2,3",
916
810
"EventCode": "0xB2",
917
811
"EventName": "OFFCORE_REQUESTS_SQ_FULL",
918
812
"SampleAfterValue": "100000",
···
921
813
},
922
814
{
923
815
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
816
+
"Counter": "0,1,2,3",
924
817
"EventCode": "0xB7, 0xBB",
925
818
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
926
819
"MSRIndex": "0x1a6,0x1a7",
···
931
822
},
932
823
{
933
824
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM",
825
+
"Counter": "0,1,2,3",
934
826
"EventCode": "0xB7, 0xBB",
935
827
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
936
828
"MSRIndex": "0x1a6,0x1a7",
···
941
831
},
942
832
{
943
833
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION",
834
+
"Counter": "0,1,2,3",
944
835
"EventCode": "0xB7, 0xBB",
945
836
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
946
837
"MSRIndex": "0x1a6,0x1a7",
···
951
840
},
952
841
{
953
842
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO",
843
+
"Counter": "0,1,2,3",
954
844
"EventCode": "0xB7, 0xBB",
955
845
"EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
956
846
"MSRIndex": "0x1a6,0x1a7",
···
961
849
},
962
850
{
963
851
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE",
852
+
"Counter": "0,1,2,3",
964
853
"EventCode": "0xB7, 0xBB",
965
854
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
966
855
"MSRIndex": "0x1a6,0x1a7",
···
971
858
},
972
859
{
973
860
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
861
+
"Counter": "0,1,2,3",
974
862
"EventCode": "0xB7, 0xBB",
975
863
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
976
864
"MSRIndex": "0x1a6,0x1a7",
···
981
867
},
982
868
{
983
869
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
870
+
"Counter": "0,1,2,3",
984
871
"EventCode": "0xB7, 0xBB",
985
872
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
986
873
"MSRIndex": "0x1a6,0x1a7",
···
991
876
},
992
877
{
993
878
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE",
879
+
"Counter": "0,1,2,3",
994
880
"EventCode": "0xB7, 0xBB",
995
881
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
996
882
"MSRIndex": "0x1a6,0x1a7",
···
1001
885
},
1002
886
{
1003
887
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
888
+
"Counter": "0,1,2,3",
1004
889
"EventCode": "0xB7, 0xBB",
1005
890
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1006
891
"MSRIndex": "0x1a6,0x1a7",
···
1011
894
},
1012
895
{
1013
896
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM",
897
+
"Counter": "0,1,2,3",
1014
898
"EventCode": "0xB7, 0xBB",
1015
899
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
1016
900
"MSRIndex": "0x1a6,0x1a7",
···
1021
903
},
1022
904
{
1023
905
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
906
+
"Counter": "0,1,2,3",
1024
907
"EventCode": "0xB7, 0xBB",
1025
908
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1026
909
"MSRIndex": "0x1a6,0x1a7",
···
1031
912
},
1032
913
{
1033
914
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM",
915
+
"Counter": "0,1,2,3",
1034
916
"EventCode": "0xB7, 0xBB",
1035
917
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
1036
918
"MSRIndex": "0x1a6,0x1a7",
···
1041
921
},
1042
922
{
1043
923
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION",
924
+
"Counter": "0,1,2,3",
1044
925
"EventCode": "0xB7, 0xBB",
1045
926
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
1046
927
"MSRIndex": "0x1a6,0x1a7",
···
1051
930
},
1052
931
{
1053
932
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO",
933
+
"Counter": "0,1,2,3",
1054
934
"EventCode": "0xB7, 0xBB",
1055
935
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
1056
936
"MSRIndex": "0x1a6,0x1a7",
···
1061
939
},
1062
940
{
1063
941
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
942
+
"Counter": "0,1,2,3",
1064
943
"EventCode": "0xB7, 0xBB",
1065
944
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
1066
945
"MSRIndex": "0x1a6,0x1a7",
···
1071
948
},
1072
949
{
1073
950
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
951
+
"Counter": "0,1,2,3",
1074
952
"EventCode": "0xB7, 0xBB",
1075
953
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1076
954
"MSRIndex": "0x1a6,0x1a7",
···
1081
957
},
1082
958
{
1083
959
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
960
+
"Counter": "0,1,2,3",
1084
961
"EventCode": "0xB7, 0xBB",
1085
962
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1086
963
"MSRIndex": "0x1a6,0x1a7",
···
1091
966
},
1092
967
{
1093
968
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE",
969
+
"Counter": "0,1,2,3",
1094
970
"EventCode": "0xB7, 0xBB",
1095
971
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
1096
972
"MSRIndex": "0x1a6,0x1a7",
···
1101
975
},
1102
976
{
1103
977
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
978
+
"Counter": "0,1,2,3",
1104
979
"EventCode": "0xB7, 0xBB",
1105
980
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1106
981
"MSRIndex": "0x1a6,0x1a7",
···
1111
984
},
1112
985
{
1113
986
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM",
987
+
"Counter": "0,1,2,3",
1114
988
"EventCode": "0xB7, 0xBB",
1115
989
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
1116
990
"MSRIndex": "0x1a6,0x1a7",
···
1121
993
},
1122
994
{
1123
995
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
996
+
"Counter": "0,1,2,3",
1124
997
"EventCode": "0xB7, 0xBB",
1125
998
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1126
999
"MSRIndex": "0x1a6,0x1a7",
···
1131
1002
},
1132
1003
{
1133
1004
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM",
1005
+
"Counter": "0,1,2,3",
1134
1006
"EventCode": "0xB7, 0xBB",
1135
1007
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
1136
1008
"MSRIndex": "0x1a6,0x1a7",
···
1141
1011
},
1142
1012
{
1143
1013
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION",
1014
+
"Counter": "0,1,2,3",
1144
1015
"EventCode": "0xB7, 0xBB",
1145
1016
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
1146
1017
"MSRIndex": "0x1a6,0x1a7",
···
1151
1020
},
1152
1021
{
1153
1022
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO",
1023
+
"Counter": "0,1,2,3",
1154
1024
"EventCode": "0xB7, 0xBB",
1155
1025
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
1156
1026
"MSRIndex": "0x1a6,0x1a7",
···
1161
1029
},
1162
1030
{
1163
1031
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1032
+
"Counter": "0,1,2,3",
1164
1033
"EventCode": "0xB7, 0xBB",
1165
1034
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
1166
1035
"MSRIndex": "0x1a6,0x1a7",
···
1171
1038
},
1172
1039
{
1173
1040
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1041
+
"Counter": "0,1,2,3",
1174
1042
"EventCode": "0xB7, 0xBB",
1175
1043
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
1176
1044
"MSRIndex": "0x1a6,0x1a7",
···
1181
1047
},
1182
1048
{
1183
1049
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1050
+
"Counter": "0,1,2,3",
1184
1051
"EventCode": "0xB7, 0xBB",
1185
1052
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
1186
1053
"MSRIndex": "0x1a6,0x1a7",
···
1191
1056
},
1192
1057
{
1193
1058
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE",
1059
+
"Counter": "0,1,2,3",
1194
1060
"EventCode": "0xB7, 0xBB",
1195
1061
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
1196
1062
"MSRIndex": "0x1a6,0x1a7",
···
1201
1065
},
1202
1066
{
1203
1067
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1068
+
"Counter": "0,1,2,3",
1204
1069
"EventCode": "0xB7, 0xBB",
1205
1070
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1206
1071
"MSRIndex": "0x1a6,0x1a7",
···
1211
1074
},
1212
1075
{
1213
1076
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM",
1077
+
"Counter": "0,1,2,3",
1214
1078
"EventCode": "0xB7, 0xBB",
1215
1079
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
1216
1080
"MSRIndex": "0x1a6,0x1a7",
···
1221
1083
},
1222
1084
{
1223
1085
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1086
+
"Counter": "0,1,2,3",
1224
1087
"EventCode": "0xB7, 0xBB",
1225
1088
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1226
1089
"MSRIndex": "0x1a6,0x1a7",
···
1231
1092
},
1232
1093
{
1233
1094
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM",
1095
+
"Counter": "0,1,2,3",
1234
1096
"EventCode": "0xB7, 0xBB",
1235
1097
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
1236
1098
"MSRIndex": "0x1a6,0x1a7",
···
1241
1101
},
1242
1102
{
1243
1103
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LOCATION",
1104
+
"Counter": "0,1,2,3",
1244
1105
"EventCode": "0xB7, 0xBB",
1245
1106
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
1246
1107
"MSRIndex": "0x1a6,0x1a7",
···
1251
1110
},
1252
1111
{
1253
1112
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO",
1113
+
"Counter": "0,1,2,3",
1254
1114
"EventCode": "0xB7, 0xBB",
1255
1115
"EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
1256
1116
"MSRIndex": "0x1a6,0x1a7",
···
1261
1119
},
1262
1120
{
1263
1121
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1122
+
"Counter": "0,1,2,3",
1264
1123
"EventCode": "0xB7, 0xBB",
1265
1124
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
1266
1125
"MSRIndex": "0x1a6,0x1a7",
···
1271
1128
},
1272
1129
{
1273
1130
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1131
+
"Counter": "0,1,2,3",
1274
1132
"EventCode": "0xB7, 0xBB",
1275
1133
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
1276
1134
"MSRIndex": "0x1a6,0x1a7",
···
1281
1137
},
1282
1138
{
1283
1139
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1140
+
"Counter": "0,1,2,3",
1284
1141
"EventCode": "0xB7, 0xBB",
1285
1142
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
1286
1143
"MSRIndex": "0x1a6,0x1a7",
···
1291
1146
},
1292
1147
{
1293
1148
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE",
1149
+
"Counter": "0,1,2,3",
1294
1150
"EventCode": "0xB7, 0xBB",
1295
1151
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
1296
1152
"MSRIndex": "0x1a6,0x1a7",
···
1301
1155
},
1302
1156
{
1303
1157
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1158
+
"Counter": "0,1,2,3",
1304
1159
"EventCode": "0xB7, 0xBB",
1305
1160
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1306
1161
"MSRIndex": "0x1a6,0x1a7",
···
1311
1164
},
1312
1165
{
1313
1166
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM",
1167
+
"Counter": "0,1,2,3",
1314
1168
"EventCode": "0xB7, 0xBB",
1315
1169
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
1316
1170
"MSRIndex": "0x1a6,0x1a7",
···
1321
1173
},
1322
1174
{
1323
1175
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1176
+
"Counter": "0,1,2,3",
1324
1177
"EventCode": "0xB7, 0xBB",
1325
1178
"EventName": "OFFCORE_RESPONSE.COREWB.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1326
1179
"MSRIndex": "0x1a6,0x1a7",
···
1331
1182
},
1332
1183
{
1333
1184
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM",
1185
+
"Counter": "0,1,2,3",
1334
1186
"EventCode": "0xB7, 0xBB",
1335
1187
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
1336
1188
"MSRIndex": "0x1a6,0x1a7",
···
1341
1191
},
1342
1192
{
1343
1193
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LOCATION",
1194
+
"Counter": "0,1,2,3",
1344
1195
"EventCode": "0xB7, 0xBB",
1345
1196
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
1346
1197
"MSRIndex": "0x1a6,0x1a7",
···
1351
1200
},
1352
1201
{
1353
1202
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO",
1203
+
"Counter": "0,1,2,3",
1354
1204
"EventCode": "0xB7, 0xBB",
1355
1205
"EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
1356
1206
"MSRIndex": "0x1a6,0x1a7",
···
1361
1209
},
1362
1210
{
1363
1211
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1212
+
"Counter": "0,1,2,3",
1364
1213
"EventCode": "0xB7, 0xBB",
1365
1214
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
1366
1215
"MSRIndex": "0x1a6,0x1a7",
···
1371
1218
},
1372
1219
{
1373
1220
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1221
+
"Counter": "0,1,2,3",
1374
1222
"EventCode": "0xB7, 0xBB",
1375
1223
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HIT",
1376
1224
"MSRIndex": "0x1a6,0x1a7",
···
1381
1227
},
1382
1228
{
1383
1229
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1230
+
"Counter": "0,1,2,3",
1384
1231
"EventCode": "0xB7, 0xBB",
1385
1232
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
1386
1233
"MSRIndex": "0x1a6,0x1a7",
···
1391
1236
},
1392
1237
{
1393
1238
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE",
1239
+
"Counter": "0,1,2,3",
1394
1240
"EventCode": "0xB7, 0xBB",
1395
1241
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
1396
1242
"MSRIndex": "0x1a6,0x1a7",
···
1401
1245
},
1402
1246
{
1403
1247
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1248
+
"Counter": "0,1,2,3",
1404
1249
"EventCode": "0xB7, 0xBB",
1405
1250
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1406
1251
"MSRIndex": "0x1a6,0x1a7",
···
1411
1254
},
1412
1255
{
1413
1256
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM",
1257
+
"Counter": "0,1,2,3",
1414
1258
"EventCode": "0xB7, 0xBB",
1415
1259
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
1416
1260
"MSRIndex": "0x1a6,0x1a7",
···
1421
1263
},
1422
1264
{
1423
1265
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1266
+
"Counter": "0,1,2,3",
1424
1267
"EventCode": "0xB7, 0xBB",
1425
1268
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1426
1269
"MSRIndex": "0x1a6,0x1a7",
···
1431
1272
},
1432
1273
{
1433
1274
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM",
1275
+
"Counter": "0,1,2,3",
1434
1276
"EventCode": "0xB7, 0xBB",
1435
1277
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
1436
1278
"MSRIndex": "0x1a6,0x1a7",
···
1441
1281
},
1442
1282
{
1443
1283
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION",
1284
+
"Counter": "0,1,2,3",
1444
1285
"EventCode": "0xB7, 0xBB",
1445
1286
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
1446
1287
"MSRIndex": "0x1a6,0x1a7",
···
1451
1290
},
1452
1291
{
1453
1292
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO",
1293
+
"Counter": "0,1,2,3",
1454
1294
"EventCode": "0xB7, 0xBB",
1455
1295
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
1456
1296
"MSRIndex": "0x1a6,0x1a7",
···
1461
1299
},
1462
1300
{
1463
1301
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1302
+
"Counter": "0,1,2,3",
1464
1303
"EventCode": "0xB7, 0xBB",
1465
1304
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
1466
1305
"MSRIndex": "0x1a6,0x1a7",
···
1471
1308
},
1472
1309
{
1473
1310
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1311
+
"Counter": "0,1,2,3",
1474
1312
"EventCode": "0xB7, 0xBB",
1475
1313
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1476
1314
"MSRIndex": "0x1a6,0x1a7",
···
1481
1317
},
1482
1318
{
1483
1319
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1320
+
"Counter": "0,1,2,3",
1484
1321
"EventCode": "0xB7, 0xBB",
1485
1322
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1486
1323
"MSRIndex": "0x1a6,0x1a7",
···
1491
1326
},
1492
1327
{
1493
1328
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE",
1329
+
"Counter": "0,1,2,3",
1494
1330
"EventCode": "0xB7, 0xBB",
1495
1331
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
1496
1332
"MSRIndex": "0x1a6,0x1a7",
···
1501
1335
},
1502
1336
{
1503
1337
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1338
+
"Counter": "0,1,2,3",
1504
1339
"EventCode": "0xB7, 0xBB",
1505
1340
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1506
1341
"MSRIndex": "0x1a6,0x1a7",
···
1511
1344
},
1512
1345
{
1513
1346
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
1347
+
"Counter": "0,1,2,3",
1514
1348
"EventCode": "0xB7, 0xBB",
1515
1349
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
1516
1350
"MSRIndex": "0x1a6,0x1a7",
···
1521
1353
},
1522
1354
{
1523
1355
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1356
+
"Counter": "0,1,2,3",
1524
1357
"EventCode": "0xB7, 0xBB",
1525
1358
"EventName": "OFFCORE_RESPONSE.DATA_IN.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1526
1359
"MSRIndex": "0x1a6,0x1a7",
···
1531
1362
},
1532
1363
{
1533
1364
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM",
1365
+
"Counter": "0,1,2,3",
1534
1366
"EventCode": "0xB7, 0xBB",
1535
1367
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
1536
1368
"MSRIndex": "0x1a6,0x1a7",
···
1541
1371
},
1542
1372
{
1543
1373
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LOCATION",
1374
+
"Counter": "0,1,2,3",
1544
1375
"EventCode": "0xB7, 0xBB",
1545
1376
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
1546
1377
"MSRIndex": "0x1a6,0x1a7",
···
1551
1380
},
1552
1381
{
1553
1382
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO",
1383
+
"Counter": "0,1,2,3",
1554
1384
"EventCode": "0xB7, 0xBB",
1555
1385
"EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
1556
1386
"MSRIndex": "0x1a6,0x1a7",
···
1561
1389
},
1562
1390
{
1563
1391
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1392
+
"Counter": "0,1,2,3",
1564
1393
"EventCode": "0xB7, 0xBB",
1565
1394
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
1566
1395
"MSRIndex": "0x1a6,0x1a7",
···
1571
1398
},
1572
1399
{
1573
1400
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1401
+
"Counter": "0,1,2,3",
1574
1402
"EventCode": "0xB7, 0xBB",
1575
1403
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
1576
1404
"MSRIndex": "0x1a6,0x1a7",
···
1581
1407
},
1582
1408
{
1583
1409
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1410
+
"Counter": "0,1,2,3",
1584
1411
"EventCode": "0xB7, 0xBB",
1585
1412
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
1586
1413
"MSRIndex": "0x1a6,0x1a7",
···
1591
1416
},
1592
1417
{
1593
1418
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE",
1419
+
"Counter": "0,1,2,3",
1594
1420
"EventCode": "0xB7, 0xBB",
1595
1421
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
1596
1422
"MSRIndex": "0x1a6,0x1a7",
···
1601
1425
},
1602
1426
{
1603
1427
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1428
+
"Counter": "0,1,2,3",
1604
1429
"EventCode": "0xB7, 0xBB",
1605
1430
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1606
1431
"MSRIndex": "0x1a6,0x1a7",
···
1611
1434
},
1612
1435
{
1613
1436
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM",
1437
+
"Counter": "0,1,2,3",
1614
1438
"EventCode": "0xB7, 0xBB",
1615
1439
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
1616
1440
"MSRIndex": "0x1a6,0x1a7",
···
1621
1443
},
1622
1444
{
1623
1445
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1446
+
"Counter": "0,1,2,3",
1624
1447
"EventCode": "0xB7, 0xBB",
1625
1448
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1626
1449
"MSRIndex": "0x1a6,0x1a7",
···
1631
1452
},
1632
1453
{
1633
1454
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM",
1455
+
"Counter": "0,1,2,3",
1634
1456
"EventCode": "0xB7, 0xBB",
1635
1457
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
1636
1458
"MSRIndex": "0x1a6,0x1a7",
···
1641
1461
},
1642
1462
{
1643
1463
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION",
1464
+
"Counter": "0,1,2,3",
1644
1465
"EventCode": "0xB7, 0xBB",
1645
1466
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
1646
1467
"MSRIndex": "0x1a6,0x1a7",
···
1651
1470
},
1652
1471
{
1653
1472
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO",
1473
+
"Counter": "0,1,2,3",
1654
1474
"EventCode": "0xB7, 0xBB",
1655
1475
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
1656
1476
"MSRIndex": "0x1a6,0x1a7",
···
1661
1479
},
1662
1480
{
1663
1481
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1482
+
"Counter": "0,1,2,3",
1664
1483
"EventCode": "0xB7, 0xBB",
1665
1484
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
1666
1485
"MSRIndex": "0x1a6,0x1a7",
···
1671
1488
},
1672
1489
{
1673
1490
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1491
+
"Counter": "0,1,2,3",
1674
1492
"EventCode": "0xB7, 0xBB",
1675
1493
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
1676
1494
"MSRIndex": "0x1a6,0x1a7",
···
1681
1497
},
1682
1498
{
1683
1499
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1500
+
"Counter": "0,1,2,3",
1684
1501
"EventCode": "0xB7, 0xBB",
1685
1502
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
1686
1503
"MSRIndex": "0x1a6,0x1a7",
···
1691
1506
},
1692
1507
{
1693
1508
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE",
1509
+
"Counter": "0,1,2,3",
1694
1510
"EventCode": "0xB7, 0xBB",
1695
1511
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
1696
1512
"MSRIndex": "0x1a6,0x1a7",
···
1701
1515
},
1702
1516
{
1703
1517
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1518
+
"Counter": "0,1,2,3",
1704
1519
"EventCode": "0xB7, 0xBB",
1705
1520
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1706
1521
"MSRIndex": "0x1a6,0x1a7",
···
1711
1524
},
1712
1525
{
1713
1526
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM",
1527
+
"Counter": "0,1,2,3",
1714
1528
"EventCode": "0xB7, 0xBB",
1715
1529
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
1716
1530
"MSRIndex": "0x1a6,0x1a7",
···
1721
1533
},
1722
1534
{
1723
1535
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1536
+
"Counter": "0,1,2,3",
1724
1537
"EventCode": "0xB7, 0xBB",
1725
1538
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1726
1539
"MSRIndex": "0x1a6,0x1a7",
···
1731
1542
},
1732
1543
{
1733
1544
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM",
1545
+
"Counter": "0,1,2,3",
1734
1546
"EventCode": "0xB7, 0xBB",
1735
1547
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
1736
1548
"MSRIndex": "0x1a6,0x1a7",
···
1741
1551
},
1742
1552
{
1743
1553
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION",
1554
+
"Counter": "0,1,2,3",
1744
1555
"EventCode": "0xB7, 0xBB",
1745
1556
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
1746
1557
"MSRIndex": "0x1a6,0x1a7",
···
1751
1560
},
1752
1561
{
1753
1562
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO",
1563
+
"Counter": "0,1,2,3",
1754
1564
"EventCode": "0xB7, 0xBB",
1755
1565
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
1756
1566
"MSRIndex": "0x1a6,0x1a7",
···
1761
1569
},
1762
1570
{
1763
1571
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1572
+
"Counter": "0,1,2,3",
1764
1573
"EventCode": "0xB7, 0xBB",
1765
1574
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
1766
1575
"MSRIndex": "0x1a6,0x1a7",
···
1771
1578
},
1772
1579
{
1773
1580
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1581
+
"Counter": "0,1,2,3",
1774
1582
"EventCode": "0xB7, 0xBB",
1775
1583
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
1776
1584
"MSRIndex": "0x1a6,0x1a7",
···
1781
1587
},
1782
1588
{
1783
1589
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1590
+
"Counter": "0,1,2,3",
1784
1591
"EventCode": "0xB7, 0xBB",
1785
1592
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
1786
1593
"MSRIndex": "0x1a6,0x1a7",
···
1791
1596
},
1792
1597
{
1793
1598
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE",
1599
+
"Counter": "0,1,2,3",
1794
1600
"EventCode": "0xB7, 0xBB",
1795
1601
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
1796
1602
"MSRIndex": "0x1a6,0x1a7",
···
1801
1605
},
1802
1606
{
1803
1607
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1608
+
"Counter": "0,1,2,3",
1804
1609
"EventCode": "0xB7, 0xBB",
1805
1610
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1806
1611
"MSRIndex": "0x1a6,0x1a7",
···
1811
1614
},
1812
1615
{
1813
1616
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM",
1617
+
"Counter": "0,1,2,3",
1814
1618
"EventCode": "0xB7, 0xBB",
1815
1619
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
1816
1620
"MSRIndex": "0x1a6,0x1a7",
···
1821
1623
},
1822
1624
{
1823
1625
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1626
+
"Counter": "0,1,2,3",
1824
1627
"EventCode": "0xB7, 0xBB",
1825
1628
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1826
1629
"MSRIndex": "0x1a6,0x1a7",
···
1831
1632
},
1832
1633
{
1833
1634
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM",
1635
+
"Counter": "0,1,2,3",
1834
1636
"EventCode": "0xB7, 0xBB",
1835
1637
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
1836
1638
"MSRIndex": "0x1a6,0x1a7",
···
1841
1641
},
1842
1642
{
1843
1643
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION",
1644
+
"Counter": "0,1,2,3",
1844
1645
"EventCode": "0xB7, 0xBB",
1845
1646
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
1846
1647
"MSRIndex": "0x1a6,0x1a7",
···
1851
1650
},
1852
1651
{
1853
1652
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO",
1653
+
"Counter": "0,1,2,3",
1854
1654
"EventCode": "0xB7, 0xBB",
1855
1655
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
1856
1656
"MSRIndex": "0x1a6,0x1a7",
···
1861
1659
},
1862
1660
{
1863
1661
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1662
+
"Counter": "0,1,2,3",
1864
1663
"EventCode": "0xB7, 0xBB",
1865
1664
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
1866
1665
"MSRIndex": "0x1a6,0x1a7",
···
1871
1668
},
1872
1669
{
1873
1670
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1671
+
"Counter": "0,1,2,3",
1874
1672
"EventCode": "0xB7, 0xBB",
1875
1673
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1876
1674
"MSRIndex": "0x1a6,0x1a7",
···
1881
1677
},
1882
1678
{
1883
1679
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1680
+
"Counter": "0,1,2,3",
1884
1681
"EventCode": "0xB7, 0xBB",
1885
1682
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1886
1683
"MSRIndex": "0x1a6,0x1a7",
···
1891
1686
},
1892
1687
{
1893
1688
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE",
1689
+
"Counter": "0,1,2,3",
1894
1690
"EventCode": "0xB7, 0xBB",
1895
1691
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
1896
1692
"MSRIndex": "0x1a6,0x1a7",
···
1901
1695
},
1902
1696
{
1903
1697
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1698
+
"Counter": "0,1,2,3",
1904
1699
"EventCode": "0xB7, 0xBB",
1905
1700
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1906
1701
"MSRIndex": "0x1a6,0x1a7",
···
1911
1704
},
1912
1705
{
1913
1706
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
1707
+
"Counter": "0,1,2,3",
1914
1708
"EventCode": "0xB7, 0xBB",
1915
1709
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
1916
1710
"MSRIndex": "0x1a6,0x1a7",
···
1921
1713
},
1922
1714
{
1923
1715
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1716
+
"Counter": "0,1,2,3",
1924
1717
"EventCode": "0xB7, 0xBB",
1925
1718
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1926
1719
"MSRIndex": "0x1a6,0x1a7",
···
1931
1722
},
1932
1723
{
1933
1724
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM",
1725
+
"Counter": "0,1,2,3",
1934
1726
"EventCode": "0xB7, 0xBB",
1935
1727
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
1936
1728
"MSRIndex": "0x1a6,0x1a7",
···
1941
1731
},
1942
1732
{
1943
1733
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION",
1734
+
"Counter": "0,1,2,3",
1944
1735
"EventCode": "0xB7, 0xBB",
1945
1736
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
1946
1737
"MSRIndex": "0x1a6,0x1a7",
···
1951
1740
},
1952
1741
{
1953
1742
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO",
1743
+
"Counter": "0,1,2,3",
1954
1744
"EventCode": "0xB7, 0xBB",
1955
1745
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
1956
1746
"MSRIndex": "0x1a6,0x1a7",
···
1961
1749
},
1962
1750
{
1963
1751
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1752
+
"Counter": "0,1,2,3",
1964
1753
"EventCode": "0xB7, 0xBB",
1965
1754
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
1966
1755
"MSRIndex": "0x1a6,0x1a7",
···
1971
1758
},
1972
1759
{
1973
1760
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1761
+
"Counter": "0,1,2,3",
1974
1762
"EventCode": "0xB7, 0xBB",
1975
1763
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
1976
1764
"MSRIndex": "0x1a6,0x1a7",
···
1981
1767
},
1982
1768
{
1983
1769
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1770
+
"Counter": "0,1,2,3",
1984
1771
"EventCode": "0xB7, 0xBB",
1985
1772
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
1986
1773
"MSRIndex": "0x1a6,0x1a7",
···
1991
1776
},
1992
1777
{
1993
1778
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE",
1779
+
"Counter": "0,1,2,3",
1994
1780
"EventCode": "0xB7, 0xBB",
1995
1781
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
1996
1782
"MSRIndex": "0x1a6,0x1a7",
···
2001
1785
},
2002
1786
{
2003
1787
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1788
+
"Counter": "0,1,2,3",
2004
1789
"EventCode": "0xB7, 0xBB",
2005
1790
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2006
1791
"MSRIndex": "0x1a6,0x1a7",
···
2011
1794
},
2012
1795
{
2013
1796
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM",
1797
+
"Counter": "0,1,2,3",
2014
1798
"EventCode": "0xB7, 0xBB",
2015
1799
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
2016
1800
"MSRIndex": "0x1a6,0x1a7",
···
2021
1803
},
2022
1804
{
2023
1805
"BriefDescription": "REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1806
+
"Counter": "0,1,2,3",
2024
1807
"EventCode": "0xB7, 0xBB",
2025
1808
"EventName": "OFFCORE_RESPONSE.OTHER.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2026
1809
"MSRIndex": "0x1a6,0x1a7",
···
2031
1812
},
2032
1813
{
2033
1814
"BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM",
1815
+
"Counter": "0,1,2,3",
2034
1816
"EventCode": "0xB7, 0xBB",
2035
1817
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
2036
1818
"MSRIndex": "0x1a6,0x1a7",
···
2041
1821
},
2042
1822
{
2043
1823
"BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LOCATION",
1824
+
"Counter": "0,1,2,3",
2044
1825
"EventCode": "0xB7, 0xBB",
2045
1826
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
2046
1827
"MSRIndex": "0x1a6,0x1a7",
···
2051
1830
},
2052
1831
{
2053
1832
"BriefDescription": "REQUEST = OTHER and RESPONSE = IO_CSR_MMIO",
1833
+
"Counter": "0,1,2,3",
2054
1834
"EventCode": "0xB7, 0xBB",
2055
1835
"EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
2056
1836
"MSRIndex": "0x1a6,0x1a7",
···
2061
1839
},
2062
1840
{
2063
1841
"BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1842
+
"Counter": "0,1,2,3",
2064
1843
"EventCode": "0xB7, 0xBB",
2065
1844
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
2066
1845
"MSRIndex": "0x1a6,0x1a7",
···
2071
1848
},
2072
1849
{
2073
1850
"BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1851
+
"Counter": "0,1,2,3",
2074
1852
"EventCode": "0xB7, 0xBB",
2075
1853
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
2076
1854
"MSRIndex": "0x1a6,0x1a7",
···
2081
1857
},
2082
1858
{
2083
1859
"BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1860
+
"Counter": "0,1,2,3",
2084
1861
"EventCode": "0xB7, 0xBB",
2085
1862
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
2086
1863
"MSRIndex": "0x1a6,0x1a7",
···
2091
1866
},
2092
1867
{
2093
1868
"BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_CACHE",
1869
+
"Counter": "0,1,2,3",
2094
1870
"EventCode": "0xB7, 0xBB",
2095
1871
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
2096
1872
"MSRIndex": "0x1a6,0x1a7",
···
2101
1875
},
2102
1876
{
2103
1877
"BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1878
+
"Counter": "0,1,2,3",
2104
1879
"EventCode": "0xB7, 0xBB",
2105
1880
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2106
1881
"MSRIndex": "0x1a6,0x1a7",
···
2111
1884
},
2112
1885
{
2113
1886
"BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM",
1887
+
"Counter": "0,1,2,3",
2114
1888
"EventCode": "0xB7, 0xBB",
2115
1889
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
2116
1890
"MSRIndex": "0x1a6,0x1a7",
···
2121
1893
},
2122
1894
{
2123
1895
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1896
+
"Counter": "0,1,2,3",
2124
1897
"EventCode": "0xB7, 0xBB",
2125
1898
"EventName": "OFFCORE_RESPONSE.PF_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2126
1899
"MSRIndex": "0x1a6,0x1a7",
···
2131
1902
},
2132
1903
{
2133
1904
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM",
1905
+
"Counter": "0,1,2,3",
2134
1906
"EventCode": "0xB7, 0xBB",
2135
1907
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
2136
1908
"MSRIndex": "0x1a6,0x1a7",
···
2141
1911
},
2142
1912
{
2143
1913
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LOCATION",
1914
+
"Counter": "0,1,2,3",
2144
1915
"EventCode": "0xB7, 0xBB",
2145
1916
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
2146
1917
"MSRIndex": "0x1a6,0x1a7",
···
2151
1920
},
2152
1921
{
2153
1922
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO",
1923
+
"Counter": "0,1,2,3",
2154
1924
"EventCode": "0xB7, 0xBB",
2155
1925
"EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
2156
1926
"MSRIndex": "0x1a6,0x1a7",
···
2161
1929
},
2162
1930
{
2163
1931
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1932
+
"Counter": "0,1,2,3",
2164
1933
"EventCode": "0xB7, 0xBB",
2165
1934
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
2166
1935
"MSRIndex": "0x1a6,0x1a7",
···
2171
1938
},
2172
1939
{
2173
1940
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1941
+
"Counter": "0,1,2,3",
2174
1942
"EventCode": "0xB7, 0xBB",
2175
1943
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
2176
1944
"MSRIndex": "0x1a6,0x1a7",
···
2181
1947
},
2182
1948
{
2183
1949
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1950
+
"Counter": "0,1,2,3",
2184
1951
"EventCode": "0xB7, 0xBB",
2185
1952
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
2186
1953
"MSRIndex": "0x1a6,0x1a7",
···
2191
1956
},
2192
1957
{
2193
1958
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE",
1959
+
"Counter": "0,1,2,3",
2194
1960
"EventCode": "0xB7, 0xBB",
2195
1961
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
2196
1962
"MSRIndex": "0x1a6,0x1a7",
···
2201
1965
},
2202
1966
{
2203
1967
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1968
+
"Counter": "0,1,2,3",
2204
1969
"EventCode": "0xB7, 0xBB",
2205
1970
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2206
1971
"MSRIndex": "0x1a6,0x1a7",
···
2211
1974
},
2212
1975
{
2213
1976
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM",
1977
+
"Counter": "0,1,2,3",
2214
1978
"EventCode": "0xB7, 0xBB",
2215
1979
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
2216
1980
"MSRIndex": "0x1a6,0x1a7",
···
2221
1983
},
2222
1984
{
2223
1985
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1986
+
"Counter": "0,1,2,3",
2224
1987
"EventCode": "0xB7, 0xBB",
2225
1988
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2226
1989
"MSRIndex": "0x1a6,0x1a7",
···
2231
1992
},
2232
1993
{
2233
1994
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM",
1995
+
"Counter": "0,1,2,3",
2234
1996
"EventCode": "0xB7, 0xBB",
2235
1997
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
2236
1998
"MSRIndex": "0x1a6,0x1a7",
···
2241
2001
},
2242
2002
{
2243
2003
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION",
2004
+
"Counter": "0,1,2,3",
2244
2005
"EventCode": "0xB7, 0xBB",
2245
2006
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
2246
2007
"MSRIndex": "0x1a6,0x1a7",
···
2251
2010
},
2252
2011
{
2253
2012
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO",
2013
+
"Counter": "0,1,2,3",
2254
2014
"EventCode": "0xB7, 0xBB",
2255
2015
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
2256
2016
"MSRIndex": "0x1a6,0x1a7",
···
2261
2019
},
2262
2020
{
2263
2021
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2022
+
"Counter": "0,1,2,3",
2264
2023
"EventCode": "0xB7, 0xBB",
2265
2024
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
2266
2025
"MSRIndex": "0x1a6,0x1a7",
···
2271
2028
},
2272
2029
{
2273
2030
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2031
+
"Counter": "0,1,2,3",
2274
2032
"EventCode": "0xB7, 0xBB",
2275
2033
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
2276
2034
"MSRIndex": "0x1a6,0x1a7",
···
2281
2037
},
2282
2038
{
2283
2039
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2040
+
"Counter": "0,1,2,3",
2284
2041
"EventCode": "0xB7, 0xBB",
2285
2042
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
2286
2043
"MSRIndex": "0x1a6,0x1a7",
···
2291
2046
},
2292
2047
{
2293
2048
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE",
2049
+
"Counter": "0,1,2,3",
2294
2050
"EventCode": "0xB7, 0xBB",
2295
2051
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
2296
2052
"MSRIndex": "0x1a6,0x1a7",
···
2301
2055
},
2302
2056
{
2303
2057
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2058
+
"Counter": "0,1,2,3",
2304
2059
"EventCode": "0xB7, 0xBB",
2305
2060
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2306
2061
"MSRIndex": "0x1a6,0x1a7",
···
2311
2064
},
2312
2065
{
2313
2066
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM",
2067
+
"Counter": "0,1,2,3",
2314
2068
"EventCode": "0xB7, 0xBB",
2315
2069
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
2316
2070
"MSRIndex": "0x1a6,0x1a7",
···
2321
2073
},
2322
2074
{
2323
2075
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2076
+
"Counter": "0,1,2,3",
2324
2077
"EventCode": "0xB7, 0xBB",
2325
2078
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2326
2079
"MSRIndex": "0x1a6,0x1a7",
···
2331
2082
},
2332
2083
{
2333
2084
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM",
2085
+
"Counter": "0,1,2,3",
2334
2086
"EventCode": "0xB7, 0xBB",
2335
2087
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
2336
2088
"MSRIndex": "0x1a6,0x1a7",
···
2341
2091
},
2342
2092
{
2343
2093
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LOCATION",
2094
+
"Counter": "0,1,2,3",
2344
2095
"EventCode": "0xB7, 0xBB",
2345
2096
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
2346
2097
"MSRIndex": "0x1a6,0x1a7",
···
2351
2100
},
2352
2101
{
2353
2102
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO",
2103
+
"Counter": "0,1,2,3",
2354
2104
"EventCode": "0xB7, 0xBB",
2355
2105
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
2356
2106
"MSRIndex": "0x1a6,0x1a7",
···
2361
2109
},
2362
2110
{
2363
2111
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2112
+
"Counter": "0,1,2,3",
2364
2113
"EventCode": "0xB7, 0xBB",
2365
2114
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
2366
2115
"MSRIndex": "0x1a6,0x1a7",
···
2371
2118
},
2372
2119
{
2373
2120
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2121
+
"Counter": "0,1,2,3",
2374
2122
"EventCode": "0xB7, 0xBB",
2375
2123
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2376
2124
"MSRIndex": "0x1a6,0x1a7",
···
2381
2127
},
2382
2128
{
2383
2129
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2130
+
"Counter": "0,1,2,3",
2384
2131
"EventCode": "0xB7, 0xBB",
2385
2132
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2386
2133
"MSRIndex": "0x1a6,0x1a7",
···
2391
2136
},
2392
2137
{
2393
2138
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE",
2139
+
"Counter": "0,1,2,3",
2394
2140
"EventCode": "0xB7, 0xBB",
2395
2141
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
2396
2142
"MSRIndex": "0x1a6,0x1a7",
···
2401
2145
},
2402
2146
{
2403
2147
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2148
+
"Counter": "0,1,2,3",
2404
2149
"EventCode": "0xB7, 0xBB",
2405
2150
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2406
2151
"MSRIndex": "0x1a6,0x1a7",
···
2411
2154
},
2412
2155
{
2413
2156
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM",
2157
+
"Counter": "0,1,2,3",
2414
2158
"EventCode": "0xB7, 0xBB",
2415
2159
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
2416
2160
"MSRIndex": "0x1a6,0x1a7",
···
2421
2163
},
2422
2164
{
2423
2165
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2166
+
"Counter": "0,1,2,3",
2424
2167
"EventCode": "0xB7, 0xBB",
2425
2168
"EventName": "OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2426
2169
"MSRIndex": "0x1a6,0x1a7",
···
2431
2172
},
2432
2173
{
2433
2174
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM",
2175
+
"Counter": "0,1,2,3",
2434
2176
"EventCode": "0xB7, 0xBB",
2435
2177
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
2436
2178
"MSRIndex": "0x1a6,0x1a7",
···
2441
2181
},
2442
2182
{
2443
2183
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION",
2184
+
"Counter": "0,1,2,3",
2444
2185
"EventCode": "0xB7, 0xBB",
2445
2186
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
2446
2187
"MSRIndex": "0x1a6,0x1a7",
···
2451
2190
},
2452
2191
{
2453
2192
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO",
2193
+
"Counter": "0,1,2,3",
2454
2194
"EventCode": "0xB7, 0xBB",
2455
2195
"EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
2456
2196
"MSRIndex": "0x1a6,0x1a7",
···
2461
2199
},
2462
2200
{
2463
2201
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2202
+
"Counter": "0,1,2,3",
2464
2203
"EventCode": "0xB7, 0xBB",
2465
2204
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
2466
2205
"MSRIndex": "0x1a6,0x1a7",
···
2471
2208
},
2472
2209
{
2473
2210
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2211
+
"Counter": "0,1,2,3",
2474
2212
"EventCode": "0xB7, 0xBB",
2475
2213
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
2476
2214
"MSRIndex": "0x1a6,0x1a7",
···
2481
2217
},
2482
2218
{
2483
2219
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2220
+
"Counter": "0,1,2,3",
2484
2221
"EventCode": "0xB7, 0xBB",
2485
2222
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
2486
2223
"MSRIndex": "0x1a6,0x1a7",
···
2491
2226
},
2492
2227
{
2493
2228
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE",
2229
+
"Counter": "0,1,2,3",
2494
2230
"EventCode": "0xB7, 0xBB",
2495
2231
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
2496
2232
"MSRIndex": "0x1a6,0x1a7",
···
2501
2235
},
2502
2236
{
2503
2237
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2238
+
"Counter": "0,1,2,3",
2504
2239
"EventCode": "0xB7, 0xBB",
2505
2240
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2506
2241
"MSRIndex": "0x1a6,0x1a7",
···
2511
2244
},
2512
2245
{
2513
2246
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
2247
+
"Counter": "0,1,2,3",
2514
2248
"EventCode": "0xB7, 0xBB",
2515
2249
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
2516
2250
"MSRIndex": "0x1a6,0x1a7",
···
2521
2253
},
2522
2254
{
2523
2255
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2256
+
"Counter": "0,1,2,3",
2524
2257
"EventCode": "0xB7, 0xBB",
2525
2258
"EventName": "OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2526
2259
"MSRIndex": "0x1a6,0x1a7",
···
2531
2262
},
2532
2263
{
2533
2264
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM",
2265
+
"Counter": "0,1,2,3",
2534
2266
"EventCode": "0xB7, 0xBB",
2535
2267
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
2536
2268
"MSRIndex": "0x1a6,0x1a7",
···
2541
2271
},
2542
2272
{
2543
2273
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LOCATION",
2274
+
"Counter": "0,1,2,3",
2544
2275
"EventCode": "0xB7, 0xBB",
2545
2276
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
2546
2277
"MSRIndex": "0x1a6,0x1a7",
···
2551
2280
},
2552
2281
{
2553
2282
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO",
2283
+
"Counter": "0,1,2,3",
2554
2284
"EventCode": "0xB7, 0xBB",
2555
2285
"EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
2556
2286
"MSRIndex": "0x1a6,0x1a7",
···
2561
2289
},
2562
2290
{
2563
2291
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2292
+
"Counter": "0,1,2,3",
2564
2293
"EventCode": "0xB7, 0xBB",
2565
2294
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
2566
2295
"MSRIndex": "0x1a6,0x1a7",
···
2571
2298
},
2572
2299
{
2573
2300
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2301
+
"Counter": "0,1,2,3",
2574
2302
"EventCode": "0xB7, 0xBB",
2575
2303
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
2576
2304
"MSRIndex": "0x1a6,0x1a7",
···
2581
2307
},
2582
2308
{
2583
2309
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2310
+
"Counter": "0,1,2,3",
2584
2311
"EventCode": "0xB7, 0xBB",
2585
2312
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
2586
2313
"MSRIndex": "0x1a6,0x1a7",
···
2591
2316
},
2592
2317
{
2593
2318
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE",
2319
+
"Counter": "0,1,2,3",
2594
2320
"EventCode": "0xB7, 0xBB",
2595
2321
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
2596
2322
"MSRIndex": "0x1a6,0x1a7",
···
2601
2325
},
2602
2326
{
2603
2327
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2328
+
"Counter": "0,1,2,3",
2604
2329
"EventCode": "0xB7, 0xBB",
2605
2330
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2606
2331
"MSRIndex": "0x1a6,0x1a7",
···
2611
2334
},
2612
2335
{
2613
2336
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM",
2337
+
"Counter": "0,1,2,3",
2614
2338
"EventCode": "0xB7, 0xBB",
2615
2339
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
2616
2340
"MSRIndex": "0x1a6,0x1a7",
···
2621
2343
},
2622
2344
{
2623
2345
"BriefDescription": "Super Queue LRU hints sent to LLC",
2346
+
"Counter": "0,1,2,3",
2624
2347
"EventCode": "0xF4",
2625
2348
"EventName": "SQ_MISC.LRU_HINTS",
2626
2349
"SampleAfterValue": "2000000",
···
2629
2350
},
2630
2351
{
2631
2352
"BriefDescription": "Super Queue lock splits across a cache line",
2353
+
"Counter": "0,1,2,3",
2632
2354
"EventCode": "0xF4",
2633
2355
"EventName": "SQ_MISC.SPLIT_LOCK",
2634
2356
"SampleAfterValue": "2000000",
···
2637
2357
},
2638
2358
{
2639
2359
"BriefDescription": "Loads delayed with at-Retirement block code",
2360
+
"Counter": "0,1,2,3",
2640
2361
"EventCode": "0x6",
2641
2362
"EventName": "STORE_BLOCKS.AT_RET",
2642
2363
"SampleAfterValue": "200000",
···
2645
2364
},
2646
2365
{
2647
2366
"BriefDescription": "Cacheable loads delayed with L1D block code",
2367
+
"Counter": "0,1,2,3",
2648
2368
"EventCode": "0x6",
2649
2369
"EventName": "STORE_BLOCKS.L1D_BLOCK",
2650
2370
"SampleAfterValue": "200000",
+7
tools/perf/pmu-events/arch/x86/westmereep-dp/counter.json
+7
tools/perf/pmu-events/arch/x86/westmereep-dp/counter.json
+28
tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json
+28
tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "X87 Floating point assists (Precise Event)",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xF7",
5
6
"EventName": "FP_ASSIST.ALL",
6
7
"PEBS": "1",
···
10
9
},
11
10
{
12
11
"BriefDescription": "X87 Floating point assists for invalid input value (Precise Event)",
12
+
"Counter": "0,1,2,3",
13
13
"EventCode": "0xF7",
14
14
"EventName": "FP_ASSIST.INPUT",
15
15
"PEBS": "1",
···
19
17
},
20
18
{
21
19
"BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
20
+
"Counter": "0,1,2,3",
22
21
"EventCode": "0xF7",
23
22
"EventName": "FP_ASSIST.OUTPUT",
24
23
"PEBS": "1",
···
28
25
},
29
26
{
30
27
"BriefDescription": "MMX Uops",
28
+
"Counter": "0,1,2,3",
31
29
"EventCode": "0x10",
32
30
"EventName": "FP_COMP_OPS_EXE.MMX",
33
31
"SampleAfterValue": "2000000",
···
36
32
},
37
33
{
38
34
"BriefDescription": "SSE2 integer Uops",
35
+
"Counter": "0,1,2,3",
39
36
"EventCode": "0x10",
40
37
"EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
41
38
"SampleAfterValue": "2000000",
···
44
39
},
45
40
{
46
41
"BriefDescription": "SSE* FP double precision Uops",
42
+
"Counter": "0,1,2,3",
47
43
"EventCode": "0x10",
48
44
"EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
49
45
"SampleAfterValue": "2000000",
···
52
46
},
53
47
{
54
48
"BriefDescription": "SSE and SSE2 FP Uops",
49
+
"Counter": "0,1,2,3",
55
50
"EventCode": "0x10",
56
51
"EventName": "FP_COMP_OPS_EXE.SSE_FP",
57
52
"SampleAfterValue": "2000000",
···
60
53
},
61
54
{
62
55
"BriefDescription": "SSE FP packed Uops",
56
+
"Counter": "0,1,2,3",
63
57
"EventCode": "0x10",
64
58
"EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
65
59
"SampleAfterValue": "2000000",
···
68
60
},
69
61
{
70
62
"BriefDescription": "SSE FP scalar Uops",
63
+
"Counter": "0,1,2,3",
71
64
"EventCode": "0x10",
72
65
"EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
73
66
"SampleAfterValue": "2000000",
···
76
67
},
77
68
{
78
69
"BriefDescription": "SSE* FP single precision Uops",
70
+
"Counter": "0,1,2,3",
79
71
"EventCode": "0x10",
80
72
"EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
81
73
"SampleAfterValue": "2000000",
···
84
74
},
85
75
{
86
76
"BriefDescription": "Computational floating-point operations executed",
77
+
"Counter": "0,1,2,3",
87
78
"EventCode": "0x10",
88
79
"EventName": "FP_COMP_OPS_EXE.X87",
89
80
"SampleAfterValue": "2000000",
···
92
81
},
93
82
{
94
83
"BriefDescription": "All Floating Point to and from MMX transitions",
84
+
"Counter": "0,1,2,3",
95
85
"EventCode": "0xCC",
96
86
"EventName": "FP_MMX_TRANS.ANY",
97
87
"SampleAfterValue": "2000000",
···
100
88
},
101
89
{
102
90
"BriefDescription": "Transitions from MMX to Floating Point instructions",
91
+
"Counter": "0,1,2,3",
103
92
"EventCode": "0xCC",
104
93
"EventName": "FP_MMX_TRANS.TO_FP",
105
94
"SampleAfterValue": "2000000",
···
108
95
},
109
96
{
110
97
"BriefDescription": "Transitions from Floating Point to MMX instructions",
98
+
"Counter": "0,1,2,3",
111
99
"EventCode": "0xCC",
112
100
"EventName": "FP_MMX_TRANS.TO_MMX",
113
101
"SampleAfterValue": "2000000",
···
116
102
},
117
103
{
118
104
"BriefDescription": "128 bit SIMD integer pack operations",
105
+
"Counter": "0,1,2,3",
119
106
"EventCode": "0x12",
120
107
"EventName": "SIMD_INT_128.PACK",
121
108
"SampleAfterValue": "200000",
···
124
109
},
125
110
{
126
111
"BriefDescription": "128 bit SIMD integer arithmetic operations",
112
+
"Counter": "0,1,2,3",
127
113
"EventCode": "0x12",
128
114
"EventName": "SIMD_INT_128.PACKED_ARITH",
129
115
"SampleAfterValue": "200000",
···
132
116
},
133
117
{
134
118
"BriefDescription": "128 bit SIMD integer logical operations",
119
+
"Counter": "0,1,2,3",
135
120
"EventCode": "0x12",
136
121
"EventName": "SIMD_INT_128.PACKED_LOGICAL",
137
122
"SampleAfterValue": "200000",
···
140
123
},
141
124
{
142
125
"BriefDescription": "128 bit SIMD integer multiply operations",
126
+
"Counter": "0,1,2,3",
143
127
"EventCode": "0x12",
144
128
"EventName": "SIMD_INT_128.PACKED_MPY",
145
129
"SampleAfterValue": "200000",
···
148
130
},
149
131
{
150
132
"BriefDescription": "128 bit SIMD integer shift operations",
133
+
"Counter": "0,1,2,3",
151
134
"EventCode": "0x12",
152
135
"EventName": "SIMD_INT_128.PACKED_SHIFT",
153
136
"SampleAfterValue": "200000",
···
156
137
},
157
138
{
158
139
"BriefDescription": "128 bit SIMD integer shuffle/move operations",
140
+
"Counter": "0,1,2,3",
159
141
"EventCode": "0x12",
160
142
"EventName": "SIMD_INT_128.SHUFFLE_MOVE",
161
143
"SampleAfterValue": "200000",
···
164
144
},
165
145
{
166
146
"BriefDescription": "128 bit SIMD integer unpack operations",
147
+
"Counter": "0,1,2,3",
167
148
"EventCode": "0x12",
168
149
"EventName": "SIMD_INT_128.UNPACK",
169
150
"SampleAfterValue": "200000",
···
172
151
},
173
152
{
174
153
"BriefDescription": "SIMD integer 64 bit pack operations",
154
+
"Counter": "0,1,2,3",
175
155
"EventCode": "0xFD",
176
156
"EventName": "SIMD_INT_64.PACK",
177
157
"SampleAfterValue": "200000",
···
180
158
},
181
159
{
182
160
"BriefDescription": "SIMD integer 64 bit arithmetic operations",
161
+
"Counter": "0,1,2,3",
183
162
"EventCode": "0xFD",
184
163
"EventName": "SIMD_INT_64.PACKED_ARITH",
185
164
"SampleAfterValue": "200000",
···
188
165
},
189
166
{
190
167
"BriefDescription": "SIMD integer 64 bit logical operations",
168
+
"Counter": "0,1,2,3",
191
169
"EventCode": "0xFD",
192
170
"EventName": "SIMD_INT_64.PACKED_LOGICAL",
193
171
"SampleAfterValue": "200000",
···
196
172
},
197
173
{
198
174
"BriefDescription": "SIMD integer 64 bit packed multiply operations",
175
+
"Counter": "0,1,2,3",
199
176
"EventCode": "0xFD",
200
177
"EventName": "SIMD_INT_64.PACKED_MPY",
201
178
"SampleAfterValue": "200000",
···
204
179
},
205
180
{
206
181
"BriefDescription": "SIMD integer 64 bit shift operations",
182
+
"Counter": "0,1,2,3",
207
183
"EventCode": "0xFD",
208
184
"EventName": "SIMD_INT_64.PACKED_SHIFT",
209
185
"SampleAfterValue": "200000",
···
212
186
},
213
187
{
214
188
"BriefDescription": "SIMD integer 64 bit shuffle/move operations",
189
+
"Counter": "0,1,2,3",
215
190
"EventCode": "0xFD",
216
191
"EventName": "SIMD_INT_64.SHUFFLE_MOVE",
217
192
"SampleAfterValue": "200000",
···
220
193
},
221
194
{
222
195
"BriefDescription": "SIMD integer 64 bit unpack operations",
196
+
"Counter": "0,1,2,3",
223
197
"EventCode": "0xFD",
224
198
"EventName": "SIMD_INT_64.UNPACK",
225
199
"SampleAfterValue": "200000",
+3
tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json
+3
tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Instructions decoded",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xD0",
5
6
"EventName": "MACRO_INSTS.DECODED",
6
7
"SampleAfterValue": "2000000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Macro-fused instructions decoded",
11
+
"Counter": "0,1,2,3",
12
12
"EventCode": "0xA6",
13
13
"EventName": "MACRO_INSTS.FUSIONS_DECODED",
14
14
"SampleAfterValue": "2000000",
···
17
15
},
18
16
{
19
17
"BriefDescription": "Two Uop instructions decoded",
18
+
"Counter": "0,1,2,3",
20
19
"EventCode": "0x19",
21
20
"EventName": "TWO_UOP_INSTS_DECODED",
22
21
"SampleAfterValue": "2000000",
+69
tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json
+69
tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Misaligned store references",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x5",
5
6
"EventName": "MISALIGN_MEM_REF.STORE",
6
7
"SampleAfterValue": "200000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWD",
11
+
"Counter": "0,1,2,3",
12
12
"EventCode": "0xB7, 0xBB",
13
13
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM_AND_REMOTE_FWD",
14
14
"MSRIndex": "0x1a6,0x1a7",
···
19
17
},
20
18
{
21
19
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISS",
20
+
"Counter": "0,1,2,3",
22
21
"EventCode": "0xB7, 0xBB",
23
22
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
24
23
"MSRIndex": "0x1a6,0x1a7",
···
29
26
},
30
27
{
31
28
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAM",
29
+
"Counter": "0,1,2,3",
32
30
"EventCode": "0xB7, 0xBB",
33
31
"EventName": "OFFCORE_RESPONSE.ANY_DATA.OTHER_LOCAL_DRAM",
34
32
"MSRIndex": "0x1a6,0x1a7",
···
39
35
},
40
36
{
41
37
"BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAM",
38
+
"Counter": "0,1,2,3",
42
39
"EventCode": "0xB7, 0xBB",
43
40
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
44
41
"MSRIndex": "0x1a6,0x1a7",
···
49
44
},
50
45
{
51
46
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",
47
+
"Counter": "0,1,2,3",
52
48
"EventCode": "0xB7, 0xBB",
53
49
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM_AND_REMOTE_FWD",
54
50
"MSRIndex": "0x1a6,0x1a7",
···
59
53
},
60
54
{
61
55
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISS",
56
+
"Counter": "0,1,2,3",
62
57
"EventCode": "0xB7, 0xBB",
63
58
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
64
59
"MSRIndex": "0x1a6,0x1a7",
···
69
62
},
70
63
{
71
64
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAM",
65
+
"Counter": "0,1,2,3",
72
66
"EventCode": "0xB7, 0xBB",
73
67
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.OTHER_LOCAL_DRAM",
74
68
"MSRIndex": "0x1a6,0x1a7",
···
79
71
},
80
72
{
81
73
"BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAM",
74
+
"Counter": "0,1,2,3",
82
75
"EventCode": "0xB7, 0xBB",
83
76
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
84
77
"MSRIndex": "0x1a6,0x1a7",
···
89
80
},
90
81
{
91
82
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWD",
83
+
"Counter": "0,1,2,3",
92
84
"EventCode": "0xB7, 0xBB",
93
85
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM_AND_REMOTE_FWD",
94
86
"MSRIndex": "0x1a6,0x1a7",
···
99
89
},
100
90
{
101
91
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISS",
92
+
"Counter": "0,1,2,3",
102
93
"EventCode": "0xB7, 0xBB",
103
94
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
104
95
"MSRIndex": "0x1a6,0x1a7",
···
109
98
},
110
99
{
111
100
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAM",
101
+
"Counter": "0,1,2,3",
112
102
"EventCode": "0xB7, 0xBB",
113
103
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OTHER_LOCAL_DRAM",
114
104
"MSRIndex": "0x1a6,0x1a7",
···
119
107
},
120
108
{
121
109
"BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAM",
110
+
"Counter": "0,1,2,3",
122
111
"EventCode": "0xB7, 0xBB",
123
112
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
124
113
"MSRIndex": "0x1a6,0x1a7",
···
129
116
},
130
117
{
131
118
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD",
119
+
"Counter": "0,1,2,3",
132
120
"EventCode": "0xB7, 0xBB",
133
121
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM_AND_REMOTE_FWD",
134
122
"MSRIndex": "0x1a6,0x1a7",
···
139
125
},
140
126
{
141
127
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISS",
128
+
"Counter": "0,1,2,3",
142
129
"EventCode": "0xB7, 0xBB",
143
130
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
144
131
"MSRIndex": "0x1a6,0x1a7",
···
149
134
},
150
135
{
151
136
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAM",
137
+
"Counter": "0,1,2,3",
152
138
"EventCode": "0xB7, 0xBB",
153
139
"EventName": "OFFCORE_RESPONSE.ANY_RFO.OTHER_LOCAL_DRAM",
154
140
"MSRIndex": "0x1a6,0x1a7",
···
159
143
},
160
144
{
161
145
"BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_DRAM",
146
+
"Counter": "0,1,2,3",
162
147
"EventCode": "0xB7, 0xBB",
163
148
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
164
149
"MSRIndex": "0x1a6,0x1a7",
···
169
152
},
170
153
{
171
154
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWD",
155
+
"Counter": "0,1,2,3",
172
156
"EventCode": "0xB7, 0xBB",
173
157
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM_AND_REMOTE_FWD",
174
158
"MSRIndex": "0x1a6,0x1a7",
···
179
161
},
180
162
{
181
163
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISS",
164
+
"Counter": "0,1,2,3",
182
165
"EventCode": "0xB7, 0xBB",
183
166
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
184
167
"MSRIndex": "0x1a6,0x1a7",
···
189
170
},
190
171
{
191
172
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAM",
173
+
"Counter": "0,1,2,3",
192
174
"EventCode": "0xB7, 0xBB",
193
175
"EventName": "OFFCORE_RESPONSE.COREWB.OTHER_LOCAL_DRAM",
194
176
"MSRIndex": "0x1a6,0x1a7",
···
199
179
},
200
180
{
201
181
"BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_DRAM",
182
+
"Counter": "0,1,2,3",
202
183
"EventCode": "0xB7, 0xBB",
203
184
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
204
185
"MSRIndex": "0x1a6,0x1a7",
···
209
188
},
210
189
{
211
190
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",
191
+
"Counter": "0,1,2,3",
212
192
"EventCode": "0xB7, 0xBB",
213
193
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM_AND_REMOTE_FWD",
214
194
"MSRIndex": "0x1a6,0x1a7",
···
219
197
},
220
198
{
221
199
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISS",
200
+
"Counter": "0,1,2,3",
222
201
"EventCode": "0xB7, 0xBB",
223
202
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
224
203
"MSRIndex": "0x1a6,0x1a7",
···
229
206
},
230
207
{
231
208
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAM",
209
+
"Counter": "0,1,2,3",
232
210
"EventCode": "0xB7, 0xBB",
233
211
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.OTHER_LOCAL_DRAM",
234
212
"MSRIndex": "0x1a6,0x1a7",
···
239
215
},
240
216
{
241
217
"BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAM",
218
+
"Counter": "0,1,2,3",
242
219
"EventCode": "0xB7, 0xBB",
243
220
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
244
221
"MSRIndex": "0x1a6,0x1a7",
···
249
224
},
250
225
{
251
226
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWD",
227
+
"Counter": "0,1,2,3",
252
228
"EventCode": "0xB7, 0xBB",
253
229
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM_AND_REMOTE_FWD",
254
230
"MSRIndex": "0x1a6,0x1a7",
···
259
233
},
260
234
{
261
235
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISS",
236
+
"Counter": "0,1,2,3",
262
237
"EventCode": "0xB7, 0xBB",
263
238
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
264
239
"MSRIndex": "0x1a6,0x1a7",
···
269
242
},
270
243
{
271
244
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAM",
245
+
"Counter": "0,1,2,3",
272
246
"EventCode": "0xB7, 0xBB",
273
247
"EventName": "OFFCORE_RESPONSE.DATA_IN.OTHER_LOCAL_DRAM",
274
248
"MSRIndex": "0x1a6,0x1a7",
···
279
251
},
280
252
{
281
253
"BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_DRAM",
254
+
"Counter": "0,1,2,3",
282
255
"EventCode": "0xB7, 0xBB",
283
256
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
284
257
"MSRIndex": "0x1a6,0x1a7",
···
289
260
},
290
261
{
291
262
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD",
263
+
"Counter": "0,1,2,3",
292
264
"EventCode": "0xB7, 0xBB",
293
265
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM_AND_REMOTE_FWD",
294
266
"MSRIndex": "0x1a6,0x1a7",
···
299
269
},
300
270
{
301
271
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISS",
272
+
"Counter": "0,1,2,3",
302
273
"EventCode": "0xB7, 0xBB",
303
274
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
304
275
"MSRIndex": "0x1a6,0x1a7",
···
309
278
},
310
279
{
311
280
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAM",
281
+
"Counter": "0,1,2,3",
312
282
"EventCode": "0xB7, 0xBB",
313
283
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.OTHER_LOCAL_DRAM",
314
284
"MSRIndex": "0x1a6,0x1a7",
···
319
287
},
320
288
{
321
289
"BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAM",
290
+
"Counter": "0,1,2,3",
322
291
"EventCode": "0xB7, 0xBB",
323
292
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
324
293
"MSRIndex": "0x1a6,0x1a7",
···
329
296
},
330
297
{
331
298
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD",
299
+
"Counter": "0,1,2,3",
332
300
"EventCode": "0xB7, 0xBB",
333
301
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM_AND_REMOTE_FWD",
334
302
"MSRIndex": "0x1a6,0x1a7",
···
339
305
},
340
306
{
341
307
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISS",
308
+
"Counter": "0,1,2,3",
342
309
"EventCode": "0xB7, 0xBB",
343
310
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
344
311
"MSRIndex": "0x1a6,0x1a7",
···
349
314
},
350
315
{
351
316
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM",
317
+
"Counter": "0,1,2,3",
352
318
"EventCode": "0xB7, 0xBB",
353
319
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OTHER_LOCAL_DRAM",
354
320
"MSRIndex": "0x1a6,0x1a7",
···
359
323
},
360
324
{
361
325
"BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAM",
326
+
"Counter": "0,1,2,3",
362
327
"EventCode": "0xB7, 0xBB",
363
328
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
364
329
"MSRIndex": "0x1a6,0x1a7",
···
369
332
},
370
333
{
371
334
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",
335
+
"Counter": "0,1,2,3",
372
336
"EventCode": "0xB7, 0xBB",
373
337
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM_AND_REMOTE_FWD",
374
338
"MSRIndex": "0x1a6,0x1a7",
···
379
341
},
380
342
{
381
343
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISS",
344
+
"Counter": "0,1,2,3",
382
345
"EventCode": "0xB7, 0xBB",
383
346
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
384
347
"MSRIndex": "0x1a6,0x1a7",
···
389
350
},
390
351
{
391
352
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAM",
353
+
"Counter": "0,1,2,3",
392
354
"EventCode": "0xB7, 0xBB",
393
355
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.OTHER_LOCAL_DRAM",
394
356
"MSRIndex": "0x1a6,0x1a7",
···
399
359
},
400
360
{
401
361
"BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAM",
362
+
"Counter": "0,1,2,3",
402
363
"EventCode": "0xB7, 0xBB",
403
364
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
404
365
"MSRIndex": "0x1a6,0x1a7",
···
409
368
},
410
369
{
411
370
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD",
371
+
"Counter": "0,1,2,3",
412
372
"EventCode": "0xB7, 0xBB",
413
373
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM_AND_REMOTE_FWD",
414
374
"MSRIndex": "0x1a6,0x1a7",
···
419
377
},
420
378
{
421
379
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISS",
380
+
"Counter": "0,1,2,3",
422
381
"EventCode": "0xB7, 0xBB",
423
382
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
424
383
"MSRIndex": "0x1a6,0x1a7",
···
429
386
},
430
387
{
431
388
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAM",
389
+
"Counter": "0,1,2,3",
432
390
"EventCode": "0xB7, 0xBB",
433
391
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OTHER_LOCAL_DRAM",
434
392
"MSRIndex": "0x1a6,0x1a7",
···
439
395
},
440
396
{
441
397
"BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAM",
398
+
"Counter": "0,1,2,3",
442
399
"EventCode": "0xB7, 0xBB",
443
400
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
444
401
"MSRIndex": "0x1a6,0x1a7",
···
449
404
},
450
405
{
451
406
"BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWD",
407
+
"Counter": "0,1,2,3",
452
408
"EventCode": "0xB7, 0xBB",
453
409
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM_AND_REMOTE_FWD",
454
410
"MSRIndex": "0x1a6,0x1a7",
···
459
413
},
460
414
{
461
415
"BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LLC_MISS",
416
+
"Counter": "0,1,2,3",
462
417
"EventCode": "0xB7, 0xBB",
463
418
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
464
419
"MSRIndex": "0x1a6,0x1a7",
···
469
422
},
470
423
{
471
424
"BriefDescription": "REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAM",
425
+
"Counter": "0,1,2,3",
472
426
"EventCode": "0xB7, 0xBB",
473
427
"EventName": "OFFCORE_RESPONSE.OTHER.OTHER_LOCAL_DRAM",
474
428
"MSRIndex": "0x1a6,0x1a7",
···
479
431
},
480
432
{
481
433
"BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_DRAM",
434
+
"Counter": "0,1,2,3",
482
435
"EventCode": "0xB7, 0xBB",
483
436
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
484
437
"MSRIndex": "0x1a6,0x1a7",
···
489
440
},
490
441
{
491
442
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD",
443
+
"Counter": "0,1,2,3",
492
444
"EventCode": "0xB7, 0xBB",
493
445
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM_AND_REMOTE_FWD",
494
446
"MSRIndex": "0x1a6,0x1a7",
···
499
449
},
500
450
{
501
451
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISS",
452
+
"Counter": "0,1,2,3",
502
453
"EventCode": "0xB7, 0xBB",
503
454
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
504
455
"MSRIndex": "0x1a6,0x1a7",
···
509
458
},
510
459
{
511
460
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAM",
461
+
"Counter": "0,1,2,3",
512
462
"EventCode": "0xB7, 0xBB",
513
463
"EventName": "OFFCORE_RESPONSE.PF_DATA.OTHER_LOCAL_DRAM",
514
464
"MSRIndex": "0x1a6,0x1a7",
···
519
467
},
520
468
{
521
469
"BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_DRAM",
470
+
"Counter": "0,1,2,3",
522
471
"EventCode": "0xB7, 0xBB",
523
472
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
524
473
"MSRIndex": "0x1a6,0x1a7",
···
529
476
},
530
477
{
531
478
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD",
479
+
"Counter": "0,1,2,3",
532
480
"EventCode": "0xB7, 0xBB",
533
481
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM_AND_REMOTE_FWD",
534
482
"MSRIndex": "0x1a6,0x1a7",
···
539
485
},
540
486
{
541
487
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISS",
488
+
"Counter": "0,1,2,3",
542
489
"EventCode": "0xB7, 0xBB",
543
490
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
544
491
"MSRIndex": "0x1a6,0x1a7",
···
549
494
},
550
495
{
551
496
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM",
497
+
"Counter": "0,1,2,3",
552
498
"EventCode": "0xB7, 0xBB",
553
499
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.OTHER_LOCAL_DRAM",
554
500
"MSRIndex": "0x1a6,0x1a7",
···
559
503
},
560
504
{
561
505
"BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAM",
506
+
"Counter": "0,1,2,3",
562
507
"EventCode": "0xB7, 0xBB",
563
508
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
564
509
"MSRIndex": "0x1a6,0x1a7",
···
569
512
},
570
513
{
571
514
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD",
515
+
"Counter": "0,1,2,3",
572
516
"EventCode": "0xB7, 0xBB",
573
517
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM_AND_REMOTE_FWD",
574
518
"MSRIndex": "0x1a6,0x1a7",
···
579
521
},
580
522
{
581
523
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISS",
524
+
"Counter": "0,1,2,3",
582
525
"EventCode": "0xB7, 0xBB",
583
526
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
584
527
"MSRIndex": "0x1a6,0x1a7",
···
589
530
},
590
531
{
591
532
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAM",
533
+
"Counter": "0,1,2,3",
592
534
"EventCode": "0xB7, 0xBB",
593
535
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.OTHER_LOCAL_DRAM",
594
536
"MSRIndex": "0x1a6,0x1a7",
···
599
539
},
600
540
{
601
541
"BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_DRAM",
542
+
"Counter": "0,1,2,3",
602
543
"EventCode": "0xB7, 0xBB",
603
544
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
604
545
"MSRIndex": "0x1a6,0x1a7",
···
609
548
},
610
549
{
611
550
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",
551
+
"Counter": "0,1,2,3",
612
552
"EventCode": "0xB7, 0xBB",
613
553
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM_AND_REMOTE_FWD",
614
554
"MSRIndex": "0x1a6,0x1a7",
···
619
557
},
620
558
{
621
559
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISS",
560
+
"Counter": "0,1,2,3",
622
561
"EventCode": "0xB7, 0xBB",
623
562
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
624
563
"MSRIndex": "0x1a6,0x1a7",
···
629
566
},
630
567
{
631
568
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAM",
569
+
"Counter": "0,1,2,3",
632
570
"EventCode": "0xB7, 0xBB",
633
571
"EventName": "OFFCORE_RESPONSE.PF_RFO.OTHER_LOCAL_DRAM",
634
572
"MSRIndex": "0x1a6,0x1a7",
···
639
575
},
640
576
{
641
577
"BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAM",
578
+
"Counter": "0,1,2,3",
642
579
"EventCode": "0xB7, 0xBB",
643
580
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
644
581
"MSRIndex": "0x1a6,0x1a7",
···
649
584
},
650
585
{
651
586
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",
587
+
"Counter": "0,1,2,3",
652
588
"EventCode": "0xB7, 0xBB",
653
589
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM_AND_REMOTE_FWD",
654
590
"MSRIndex": "0x1a6,0x1a7",
···
659
593
},
660
594
{
661
595
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISS",
596
+
"Counter": "0,1,2,3",
662
597
"EventCode": "0xB7, 0xBB",
663
598
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
664
599
"MSRIndex": "0x1a6,0x1a7",
···
669
602
},
670
603
{
671
604
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAM",
605
+
"Counter": "0,1,2,3",
672
606
"EventCode": "0xB7, 0xBB",
673
607
"EventName": "OFFCORE_RESPONSE.PREFETCH.OTHER_LOCAL_DRAM",
674
608
"MSRIndex": "0x1a6,0x1a7",
···
679
611
},
680
612
{
681
613
"BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_DRAM",
614
+
"Counter": "0,1,2,3",
682
615
"EventCode": "0xB7, 0xBB",
683
616
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
684
617
"MSRIndex": "0x1a6,0x1a7",
+28
tools/perf/pmu-events/arch/x86/westmereep-dp/other.json
+28
tools/perf/pmu-events/arch/x86/westmereep-dp/other.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "ES segment renames",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xD5",
5
6
"EventName": "ES_REG_RENAMES",
6
7
"SampleAfterValue": "2000000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "I/O transactions",
11
+
"Counter": "0,1,2,3",
12
12
"EventCode": "0x6C",
13
13
"EventName": "IO_TRANSACTIONS",
14
14
"SampleAfterValue": "2000000",
···
17
15
},
18
16
{
19
17
"BriefDescription": "L1I instruction fetch stall cycles",
18
+
"Counter": "0,1,2,3",
20
19
"EventCode": "0x80",
21
20
"EventName": "L1I.CYCLES_STALLED",
22
21
"SampleAfterValue": "2000000",
···
25
22
},
26
23
{
27
24
"BriefDescription": "L1I instruction fetch hits",
25
+
"Counter": "0,1,2,3",
28
26
"EventCode": "0x80",
29
27
"EventName": "L1I.HITS",
30
28
"SampleAfterValue": "2000000",
···
33
29
},
34
30
{
35
31
"BriefDescription": "L1I instruction fetch misses",
32
+
"Counter": "0,1,2,3",
36
33
"EventCode": "0x80",
37
34
"EventName": "L1I.MISSES",
38
35
"SampleAfterValue": "2000000",
···
41
36
},
42
37
{
43
38
"BriefDescription": "L1I Instruction fetches",
39
+
"Counter": "0,1,2,3",
44
40
"EventCode": "0x80",
45
41
"EventName": "L1I.READS",
46
42
"SampleAfterValue": "2000000",
···
49
43
},
50
44
{
51
45
"BriefDescription": "Large ITLB hit",
46
+
"Counter": "0,1,2,3",
52
47
"EventCode": "0x82",
53
48
"EventName": "LARGE_ITLB.HIT",
54
49
"SampleAfterValue": "200000",
···
57
50
},
58
51
{
59
52
"BriefDescription": "Loads that partially overlap an earlier store",
53
+
"Counter": "0,1,2,3",
60
54
"EventCode": "0x3",
61
55
"EventName": "LOAD_BLOCK.OVERLAP_STORE",
62
56
"SampleAfterValue": "200000",
···
65
57
},
66
58
{
67
59
"BriefDescription": "All loads dispatched",
60
+
"Counter": "0,1,2,3",
68
61
"EventCode": "0x13",
69
62
"EventName": "LOAD_DISPATCH.ANY",
70
63
"SampleAfterValue": "2000000",
···
73
64
},
74
65
{
75
66
"BriefDescription": "Loads dispatched from the MOB",
67
+
"Counter": "0,1,2,3",
76
68
"EventCode": "0x13",
77
69
"EventName": "LOAD_DISPATCH.MOB",
78
70
"SampleAfterValue": "2000000",
···
81
71
},
82
72
{
83
73
"BriefDescription": "Loads dispatched that bypass the MOB",
74
+
"Counter": "0,1,2,3",
84
75
"EventCode": "0x13",
85
76
"EventName": "LOAD_DISPATCH.RS",
86
77
"SampleAfterValue": "2000000",
···
89
78
},
90
79
{
91
80
"BriefDescription": "Loads dispatched from stage 305",
81
+
"Counter": "0,1,2,3",
92
82
"EventCode": "0x13",
93
83
"EventName": "LOAD_DISPATCH.RS_DELAYED",
94
84
"SampleAfterValue": "2000000",
···
97
85
},
98
86
{
99
87
"BriefDescription": "False dependencies due to partial address aliasing",
88
+
"Counter": "0,1,2,3",
100
89
"EventCode": "0x7",
101
90
"EventName": "PARTIAL_ADDRESS_ALIAS",
102
91
"SampleAfterValue": "200000",
···
105
92
},
106
93
{
107
94
"BriefDescription": "All Store buffer stall cycles",
95
+
"Counter": "0,1,2,3",
108
96
"EventCode": "0x4",
109
97
"EventName": "SB_DRAIN.ANY",
110
98
"SampleAfterValue": "200000",
···
113
99
},
114
100
{
115
101
"BriefDescription": "Segment rename stall cycles",
102
+
"Counter": "0,1,2,3",
116
103
"EventCode": "0xD4",
117
104
"EventName": "SEG_RENAME_STALLS",
118
105
"SampleAfterValue": "2000000",
···
121
106
},
122
107
{
123
108
"BriefDescription": "Snoop code requests",
109
+
"Counter": "0,1,2,3",
124
110
"EventCode": "0xB4",
125
111
"EventName": "SNOOPQ_REQUESTS.CODE",
126
112
"SampleAfterValue": "100000",
···
129
113
},
130
114
{
131
115
"BriefDescription": "Snoop data requests",
116
+
"Counter": "0,1,2,3",
132
117
"EventCode": "0xB4",
133
118
"EventName": "SNOOPQ_REQUESTS.DATA",
134
119
"SampleAfterValue": "100000",
···
137
120
},
138
121
{
139
122
"BriefDescription": "Snoop invalidate requests",
123
+
"Counter": "0,1,2,3",
140
124
"EventCode": "0xB4",
141
125
"EventName": "SNOOPQ_REQUESTS.INVALIDATE",
142
126
"SampleAfterValue": "100000",
···
145
127
},
146
128
{
147
129
"BriefDescription": "Outstanding snoop code requests",
130
+
"Counter": "0",
148
131
"EventCode": "0xB3",
149
132
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE",
150
133
"SampleAfterValue": "2000000",
···
153
134
},
154
135
{
155
136
"BriefDescription": "Cycles snoop code requests queued",
137
+
"Counter": "0",
156
138
"CounterMask": "1",
157
139
"EventCode": "0xB3",
158
140
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY",
···
162
142
},
163
143
{
164
144
"BriefDescription": "Outstanding snoop data requests",
145
+
"Counter": "0",
165
146
"EventCode": "0xB3",
166
147
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA",
167
148
"SampleAfterValue": "2000000",
···
170
149
},
171
150
{
172
151
"BriefDescription": "Cycles snoop data requests queued",
152
+
"Counter": "0",
173
153
"CounterMask": "1",
174
154
"EventCode": "0xB3",
175
155
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY",
···
179
157
},
180
158
{
181
159
"BriefDescription": "Outstanding snoop invalidate requests",
160
+
"Counter": "0",
182
161
"EventCode": "0xB3",
183
162
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",
184
163
"SampleAfterValue": "2000000",
···
187
164
},
188
165
{
189
166
"BriefDescription": "Cycles snoop invalidate requests queued",
167
+
"Counter": "0",
190
168
"CounterMask": "1",
191
169
"EventCode": "0xB3",
192
170
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY",
···
196
172
},
197
173
{
198
174
"BriefDescription": "Thread responded HIT to snoop",
175
+
"Counter": "0,1,2,3",
199
176
"EventCode": "0xB8",
200
177
"EventName": "SNOOP_RESPONSE.HIT",
201
178
"SampleAfterValue": "100000",
···
204
179
},
205
180
{
206
181
"BriefDescription": "Thread responded HITE to snoop",
182
+
"Counter": "0,1,2,3",
207
183
"EventCode": "0xB8",
208
184
"EventName": "SNOOP_RESPONSE.HITE",
209
185
"SampleAfterValue": "100000",
···
212
186
},
213
187
{
214
188
"BriefDescription": "Thread responded HITM to snoop",
189
+
"Counter": "0,1,2,3",
215
190
"EventCode": "0xB8",
216
191
"EventName": "SNOOP_RESPONSE.HITM",
217
192
"SampleAfterValue": "100000",
···
220
193
},
221
194
{
222
195
"BriefDescription": "Super Queue full stall cycles",
196
+
"Counter": "0,1,2,3",
223
197
"EventCode": "0xF6",
224
198
"EventName": "SQ_FULL_STALL_CYCLES",
225
199
"SampleAfterValue": "2000000",
+111
tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json
+111
tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Cycles the divider is busy",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x14",
5
6
"EventName": "ARITH.CYCLES_DIV_BUSY",
6
7
"SampleAfterValue": "2000000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Divide Operations executed",
11
+
"Counter": "0,1,2,3",
12
12
"CounterMask": "1",
13
13
"EdgeDetect": "1",
14
14
"EventCode": "0x14",
···
20
18
},
21
19
{
22
20
"BriefDescription": "Multiply operations executed",
21
+
"Counter": "0,1,2,3",
23
22
"EventCode": "0x14",
24
23
"EventName": "ARITH.MUL",
25
24
"SampleAfterValue": "2000000",
···
28
25
},
29
26
{
30
27
"BriefDescription": "BACLEAR asserted with bad target address",
28
+
"Counter": "0,1,2,3",
31
29
"EventCode": "0xE6",
32
30
"EventName": "BACLEAR.BAD_TARGET",
33
31
"SampleAfterValue": "2000000",
···
36
32
},
37
33
{
38
34
"BriefDescription": "BACLEAR asserted, regardless of cause",
35
+
"Counter": "0,1,2,3",
39
36
"EventCode": "0xE6",
40
37
"EventName": "BACLEAR.CLEAR",
41
38
"SampleAfterValue": "2000000",
···
44
39
},
45
40
{
46
41
"BriefDescription": "Instruction queue forced BACLEAR",
42
+
"Counter": "0,1,2,3",
47
43
"EventCode": "0xA7",
48
44
"EventName": "BACLEAR_FORCE_IQ",
49
45
"SampleAfterValue": "2000000",
···
52
46
},
53
47
{
54
48
"BriefDescription": "Early Branch Prediciton Unit clears",
49
+
"Counter": "0,1,2,3",
55
50
"EventCode": "0xE8",
56
51
"EventName": "BPU_CLEARS.EARLY",
57
52
"SampleAfterValue": "2000000",
···
60
53
},
61
54
{
62
55
"BriefDescription": "Late Branch Prediction Unit clears",
56
+
"Counter": "0,1,2,3",
63
57
"EventCode": "0xE8",
64
58
"EventName": "BPU_CLEARS.LATE",
65
59
"SampleAfterValue": "2000000",
···
68
60
},
69
61
{
70
62
"BriefDescription": "Branch prediction unit missed call or return",
63
+
"Counter": "0,1,2,3",
71
64
"EventCode": "0xE5",
72
65
"EventName": "BPU_MISSED_CALL_RET",
73
66
"SampleAfterValue": "2000000",
···
76
67
},
77
68
{
78
69
"BriefDescription": "Branch instructions decoded",
70
+
"Counter": "0,1,2,3",
79
71
"EventCode": "0xE0",
80
72
"EventName": "BR_INST_DECODED",
81
73
"SampleAfterValue": "2000000",
···
84
74
},
85
75
{
86
76
"BriefDescription": "Branch instructions executed",
77
+
"Counter": "0,1,2,3",
87
78
"EventCode": "0x88",
88
79
"EventName": "BR_INST_EXEC.ANY",
89
80
"SampleAfterValue": "200000",
···
92
81
},
93
82
{
94
83
"BriefDescription": "Conditional branch instructions executed",
84
+
"Counter": "0,1,2,3",
95
85
"EventCode": "0x88",
96
86
"EventName": "BR_INST_EXEC.COND",
97
87
"SampleAfterValue": "200000",
···
100
88
},
101
89
{
102
90
"BriefDescription": "Unconditional branches executed",
91
+
"Counter": "0,1,2,3",
103
92
"EventCode": "0x88",
104
93
"EventName": "BR_INST_EXEC.DIRECT",
105
94
"SampleAfterValue": "200000",
···
108
95
},
109
96
{
110
97
"BriefDescription": "Unconditional call branches executed",
98
+
"Counter": "0,1,2,3",
111
99
"EventCode": "0x88",
112
100
"EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
113
101
"SampleAfterValue": "20000",
···
116
102
},
117
103
{
118
104
"BriefDescription": "Indirect call branches executed",
105
+
"Counter": "0,1,2,3",
119
106
"EventCode": "0x88",
120
107
"EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
121
108
"SampleAfterValue": "20000",
···
124
109
},
125
110
{
126
111
"BriefDescription": "Indirect non call branches executed",
112
+
"Counter": "0,1,2,3",
127
113
"EventCode": "0x88",
128
114
"EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
129
115
"SampleAfterValue": "20000",
···
132
116
},
133
117
{
134
118
"BriefDescription": "Call branches executed",
119
+
"Counter": "0,1,2,3",
135
120
"EventCode": "0x88",
136
121
"EventName": "BR_INST_EXEC.NEAR_CALLS",
137
122
"SampleAfterValue": "20000",
···
140
123
},
141
124
{
142
125
"BriefDescription": "All non call branches executed",
126
+
"Counter": "0,1,2,3",
143
127
"EventCode": "0x88",
144
128
"EventName": "BR_INST_EXEC.NON_CALLS",
145
129
"SampleAfterValue": "200000",
···
148
130
},
149
131
{
150
132
"BriefDescription": "Indirect return branches executed",
133
+
"Counter": "0,1,2,3",
151
134
"EventCode": "0x88",
152
135
"EventName": "BR_INST_EXEC.RETURN_NEAR",
153
136
"SampleAfterValue": "20000",
···
156
137
},
157
138
{
158
139
"BriefDescription": "Taken branches executed",
140
+
"Counter": "0,1,2,3",
159
141
"EventCode": "0x88",
160
142
"EventName": "BR_INST_EXEC.TAKEN",
161
143
"SampleAfterValue": "200000",
···
164
144
},
165
145
{
166
146
"BriefDescription": "Retired branch instructions (Precise Event)",
147
+
"Counter": "0,1,2,3",
167
148
"EventCode": "0xC4",
168
149
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
169
150
"PEBS": "1",
···
173
152
},
174
153
{
175
154
"BriefDescription": "Retired conditional branch instructions (Precise Event)",
155
+
"Counter": "0,1,2,3",
176
156
"EventCode": "0xC4",
177
157
"EventName": "BR_INST_RETIRED.CONDITIONAL",
178
158
"PEBS": "1",
···
182
160
},
183
161
{
184
162
"BriefDescription": "Retired near call instructions (Precise Event)",
163
+
"Counter": "0,1,2,3",
185
164
"EventCode": "0xC4",
186
165
"EventName": "BR_INST_RETIRED.NEAR_CALL",
187
166
"PEBS": "1",
···
191
168
},
192
169
{
193
170
"BriefDescription": "Mispredicted branches executed",
171
+
"Counter": "0,1,2,3",
194
172
"EventCode": "0x89",
195
173
"EventName": "BR_MISP_EXEC.ANY",
196
174
"SampleAfterValue": "20000",
···
199
175
},
200
176
{
201
177
"BriefDescription": "Mispredicted conditional branches executed",
178
+
"Counter": "0,1,2,3",
202
179
"EventCode": "0x89",
203
180
"EventName": "BR_MISP_EXEC.COND",
204
181
"SampleAfterValue": "20000",
···
207
182
},
208
183
{
209
184
"BriefDescription": "Mispredicted unconditional branches executed",
185
+
"Counter": "0,1,2,3",
210
186
"EventCode": "0x89",
211
187
"EventName": "BR_MISP_EXEC.DIRECT",
212
188
"SampleAfterValue": "20000",
···
215
189
},
216
190
{
217
191
"BriefDescription": "Mispredicted non call branches executed",
192
+
"Counter": "0,1,2,3",
218
193
"EventCode": "0x89",
219
194
"EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
220
195
"SampleAfterValue": "2000",
···
223
196
},
224
197
{
225
198
"BriefDescription": "Mispredicted indirect call branches executed",
199
+
"Counter": "0,1,2,3",
226
200
"EventCode": "0x89",
227
201
"EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
228
202
"SampleAfterValue": "2000",
···
231
203
},
232
204
{
233
205
"BriefDescription": "Mispredicted indirect non call branches executed",
206
+
"Counter": "0,1,2,3",
234
207
"EventCode": "0x89",
235
208
"EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
236
209
"SampleAfterValue": "2000",
···
239
210
},
240
211
{
241
212
"BriefDescription": "Mispredicted call branches executed",
213
+
"Counter": "0,1,2,3",
242
214
"EventCode": "0x89",
243
215
"EventName": "BR_MISP_EXEC.NEAR_CALLS",
244
216
"SampleAfterValue": "2000",
···
247
217
},
248
218
{
249
219
"BriefDescription": "Mispredicted non call branches executed",
220
+
"Counter": "0,1,2,3",
250
221
"EventCode": "0x89",
251
222
"EventName": "BR_MISP_EXEC.NON_CALLS",
252
223
"SampleAfterValue": "20000",
···
255
224
},
256
225
{
257
226
"BriefDescription": "Mispredicted return branches executed",
227
+
"Counter": "0,1,2,3",
258
228
"EventCode": "0x89",
259
229
"EventName": "BR_MISP_EXEC.RETURN_NEAR",
260
230
"SampleAfterValue": "2000",
···
263
231
},
264
232
{
265
233
"BriefDescription": "Mispredicted taken branches executed",
234
+
"Counter": "0,1,2,3",
266
235
"EventCode": "0x89",
267
236
"EventName": "BR_MISP_EXEC.TAKEN",
268
237
"SampleAfterValue": "20000",
···
271
238
},
272
239
{
273
240
"BriefDescription": "Mispredicted retired branch instructions (Precise Event)",
241
+
"Counter": "0,1,2,3",
274
242
"EventCode": "0xC5",
275
243
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
276
244
"PEBS": "1",
···
280
246
},
281
247
{
282
248
"BriefDescription": "Mispredicted conditional retired branches (Precise Event)",
249
+
"Counter": "0,1,2,3",
283
250
"EventCode": "0xC5",
284
251
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
285
252
"PEBS": "1",
···
289
254
},
290
255
{
291
256
"BriefDescription": "Mispredicted near retired calls (Precise Event)",
257
+
"Counter": "0,1,2,3",
292
258
"EventCode": "0xC5",
293
259
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
294
260
"PEBS": "1",
···
298
262
},
299
263
{
300
264
"BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
265
+
"Counter": "Fixed counter 3",
301
266
"EventName": "CPU_CLK_UNHALTED.REF",
302
267
"SampleAfterValue": "2000000"
303
268
},
304
269
{
305
270
"BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
271
+
"Counter": "0,1,2,3",
306
272
"EventCode": "0x3C",
307
273
"EventName": "CPU_CLK_UNHALTED.REF_P",
308
274
"SampleAfterValue": "100000",
···
312
274
},
313
275
{
314
276
"BriefDescription": "Cycles when thread is not halted (fixed counter)",
277
+
"Counter": "Fixed counter 2",
315
278
"EventName": "CPU_CLK_UNHALTED.THREAD",
316
279
"SampleAfterValue": "2000000"
317
280
},
318
281
{
319
282
"BriefDescription": "Cycles when thread is not halted (programmable counter)",
283
+
"Counter": "0,1,2,3",
320
284
"EventCode": "0x3C",
321
285
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
322
286
"SampleAfterValue": "2000000"
323
287
},
324
288
{
325
289
"BriefDescription": "Total CPU cycles",
290
+
"Counter": "0,1,2,3",
326
291
"CounterMask": "2",
327
292
"EventCode": "0x3C",
328
293
"EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
···
334
293
},
335
294
{
336
295
"BriefDescription": "Any Instruction Length Decoder stall cycles",
296
+
"Counter": "0,1,2,3",
337
297
"EventCode": "0x87",
338
298
"EventName": "ILD_STALL.ANY",
339
299
"SampleAfterValue": "2000000",
···
342
300
},
343
301
{
344
302
"BriefDescription": "Instruction Queue full stall cycles",
303
+
"Counter": "0,1,2,3",
345
304
"EventCode": "0x87",
346
305
"EventName": "ILD_STALL.IQ_FULL",
347
306
"SampleAfterValue": "2000000",
···
350
307
},
351
308
{
352
309
"BriefDescription": "Length Change Prefix stall cycles",
310
+
"Counter": "0,1,2,3",
353
311
"EventCode": "0x87",
354
312
"EventName": "ILD_STALL.LCP",
355
313
"SampleAfterValue": "2000000",
···
358
314
},
359
315
{
360
316
"BriefDescription": "Stall cycles due to BPU MRU bypass",
317
+
"Counter": "0,1,2,3",
361
318
"EventCode": "0x87",
362
319
"EventName": "ILD_STALL.MRU",
363
320
"SampleAfterValue": "2000000",
···
366
321
},
367
322
{
368
323
"BriefDescription": "Regen stall cycles",
324
+
"Counter": "0,1,2,3",
369
325
"EventCode": "0x87",
370
326
"EventName": "ILD_STALL.REGEN",
371
327
"SampleAfterValue": "2000000",
···
374
328
},
375
329
{
376
330
"BriefDescription": "Instructions that must be decoded by decoder 0",
331
+
"Counter": "0,1,2,3",
377
332
"EventCode": "0x18",
378
333
"EventName": "INST_DECODED.DEC0",
379
334
"SampleAfterValue": "2000000",
···
382
335
},
383
336
{
384
337
"BriefDescription": "Instructions written to instruction queue.",
338
+
"Counter": "0,1,2,3",
385
339
"EventCode": "0x17",
386
340
"EventName": "INST_QUEUE_WRITES",
387
341
"SampleAfterValue": "2000000",
···
390
342
},
391
343
{
392
344
"BriefDescription": "Cycles instructions are written to the instruction queue",
345
+
"Counter": "0,1,2,3",
393
346
"EventCode": "0x1E",
394
347
"EventName": "INST_QUEUE_WRITE_CYCLES",
395
348
"SampleAfterValue": "2000000",
···
398
349
},
399
350
{
400
351
"BriefDescription": "Instructions retired (fixed counter)",
352
+
"Counter": "Fixed counter 1",
401
353
"EventName": "INST_RETIRED.ANY",
402
354
"SampleAfterValue": "2000000"
403
355
},
404
356
{
405
357
"BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
358
+
"Counter": "0,1,2,3",
406
359
"EventCode": "0xC0",
407
360
"EventName": "INST_RETIRED.ANY_P",
408
361
"PEBS": "1",
···
413
362
},
414
363
{
415
364
"BriefDescription": "Retired MMX instructions (Precise Event)",
365
+
"Counter": "0,1,2,3",
416
366
"EventCode": "0xC0",
417
367
"EventName": "INST_RETIRED.MMX",
418
368
"PEBS": "1",
···
422
370
},
423
371
{
424
372
"BriefDescription": "Total cycles (Precise Event)",
373
+
"Counter": "0,1,2,3",
425
374
"CounterMask": "16",
426
375
"EventCode": "0xC0",
427
376
"EventName": "INST_RETIRED.TOTAL_CYCLES",
···
433
380
},
434
381
{
435
382
"BriefDescription": "Total cycles (Precise Event)",
383
+
"Counter": "0,1,2,3",
436
384
"CounterMask": "16",
437
385
"EventCode": "0xC0",
438
386
"EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
···
444
390
},
445
391
{
446
392
"BriefDescription": "Retired floating-point operations (Precise Event)",
393
+
"Counter": "0,1,2,3",
447
394
"EventCode": "0xC0",
448
395
"EventName": "INST_RETIRED.X87",
449
396
"PEBS": "1",
···
453
398
},
454
399
{
455
400
"BriefDescription": "Load operations conflicting with software prefetches",
401
+
"Counter": "0,1",
456
402
"EventCode": "0x4C",
457
403
"EventName": "LOAD_HIT_PRE",
458
404
"SampleAfterValue": "200000",
···
461
405
},
462
406
{
463
407
"BriefDescription": "Cycles when uops were delivered by the LSD",
408
+
"Counter": "0,1,2,3",
464
409
"CounterMask": "1",
465
410
"EventCode": "0xA8",
466
411
"EventName": "LSD.ACTIVE",
···
470
413
},
471
414
{
472
415
"BriefDescription": "Cycles no uops were delivered by the LSD",
416
+
"Counter": "0,1,2,3",
473
417
"CounterMask": "1",
474
418
"EventCode": "0xA8",
475
419
"EventName": "LSD.INACTIVE",
···
480
422
},
481
423
{
482
424
"BriefDescription": "Loops that can't stream from the instruction queue",
425
+
"Counter": "0,1,2,3",
483
426
"EventCode": "0x20",
484
427
"EventName": "LSD_OVERFLOW",
485
428
"SampleAfterValue": "2000000",
···
488
429
},
489
430
{
490
431
"BriefDescription": "Cycles machine clear asserted",
432
+
"Counter": "0,1,2,3",
491
433
"EventCode": "0xC3",
492
434
"EventName": "MACHINE_CLEARS.CYCLES",
493
435
"SampleAfterValue": "20000",
···
496
436
},
497
437
{
498
438
"BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
439
+
"Counter": "0,1,2,3",
499
440
"EventCode": "0xC3",
500
441
"EventName": "MACHINE_CLEARS.MEM_ORDER",
501
442
"SampleAfterValue": "20000",
···
504
443
},
505
444
{
506
445
"BriefDescription": "Self-Modifying Code detected",
446
+
"Counter": "0,1,2,3",
507
447
"EventCode": "0xC3",
508
448
"EventName": "MACHINE_CLEARS.SMC",
509
449
"SampleAfterValue": "20000",
···
512
450
},
513
451
{
514
452
"BriefDescription": "All RAT stall cycles",
453
+
"Counter": "0,1,2,3",
515
454
"EventCode": "0xD2",
516
455
"EventName": "RAT_STALLS.ANY",
517
456
"SampleAfterValue": "2000000",
···
520
457
},
521
458
{
522
459
"BriefDescription": "Flag stall cycles",
460
+
"Counter": "0,1,2,3",
523
461
"EventCode": "0xD2",
524
462
"EventName": "RAT_STALLS.FLAGS",
525
463
"SampleAfterValue": "2000000",
···
528
464
},
529
465
{
530
466
"BriefDescription": "Partial register stall cycles",
467
+
"Counter": "0,1,2,3",
531
468
"EventCode": "0xD2",
532
469
"EventName": "RAT_STALLS.REGISTERS",
533
470
"SampleAfterValue": "2000000",
···
536
471
},
537
472
{
538
473
"BriefDescription": "ROB read port stalls cycles",
474
+
"Counter": "0,1,2,3",
539
475
"EventCode": "0xD2",
540
476
"EventName": "RAT_STALLS.ROB_READ_PORT",
541
477
"SampleAfterValue": "2000000",
···
544
478
},
545
479
{
546
480
"BriefDescription": "Scoreboard stall cycles",
481
+
"Counter": "0,1,2,3",
547
482
"EventCode": "0xD2",
548
483
"EventName": "RAT_STALLS.SCOREBOARD",
549
484
"SampleAfterValue": "2000000",
···
552
485
},
553
486
{
554
487
"BriefDescription": "Resource related stall cycles",
488
+
"Counter": "0,1,2,3",
555
489
"EventCode": "0xA2",
556
490
"EventName": "RESOURCE_STALLS.ANY",
557
491
"SampleAfterValue": "2000000",
···
560
492
},
561
493
{
562
494
"BriefDescription": "FPU control word write stall cycles",
495
+
"Counter": "0,1,2,3",
563
496
"EventCode": "0xA2",
564
497
"EventName": "RESOURCE_STALLS.FPCW",
565
498
"SampleAfterValue": "2000000",
···
568
499
},
569
500
{
570
501
"BriefDescription": "Load buffer stall cycles",
502
+
"Counter": "0,1,2,3",
571
503
"EventCode": "0xA2",
572
504
"EventName": "RESOURCE_STALLS.LOAD",
573
505
"SampleAfterValue": "2000000",
···
576
506
},
577
507
{
578
508
"BriefDescription": "MXCSR rename stall cycles",
509
+
"Counter": "0,1,2,3",
579
510
"EventCode": "0xA2",
580
511
"EventName": "RESOURCE_STALLS.MXCSR",
581
512
"SampleAfterValue": "2000000",
···
584
513
},
585
514
{
586
515
"BriefDescription": "Other Resource related stall cycles",
516
+
"Counter": "0,1,2,3",
587
517
"EventCode": "0xA2",
588
518
"EventName": "RESOURCE_STALLS.OTHER",
589
519
"SampleAfterValue": "2000000",
···
592
520
},
593
521
{
594
522
"BriefDescription": "ROB full stall cycles",
523
+
"Counter": "0,1,2,3",
595
524
"EventCode": "0xA2",
596
525
"EventName": "RESOURCE_STALLS.ROB_FULL",
597
526
"SampleAfterValue": "2000000",
···
600
527
},
601
528
{
602
529
"BriefDescription": "Reservation Station full stall cycles",
530
+
"Counter": "0,1,2,3",
603
531
"EventCode": "0xA2",
604
532
"EventName": "RESOURCE_STALLS.RS_FULL",
605
533
"SampleAfterValue": "2000000",
···
608
534
},
609
535
{
610
536
"BriefDescription": "Store buffer stall cycles",
537
+
"Counter": "0,1,2,3",
611
538
"EventCode": "0xA2",
612
539
"EventName": "RESOURCE_STALLS.STORE",
613
540
"SampleAfterValue": "2000000",
···
616
541
},
617
542
{
618
543
"BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
544
+
"Counter": "0,1,2,3",
619
545
"EventCode": "0xC7",
620
546
"EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
621
547
"PEBS": "1",
···
625
549
},
626
550
{
627
551
"BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
552
+
"Counter": "0,1,2,3",
628
553
"EventCode": "0xC7",
629
554
"EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
630
555
"PEBS": "1",
···
634
557
},
635
558
{
636
559
"BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
560
+
"Counter": "0,1,2,3",
637
561
"EventCode": "0xC7",
638
562
"EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
639
563
"PEBS": "1",
···
643
565
},
644
566
{
645
567
"BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
568
+
"Counter": "0,1,2,3",
646
569
"EventCode": "0xC7",
647
570
"EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
648
571
"PEBS": "1",
···
652
573
},
653
574
{
654
575
"BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
576
+
"Counter": "0,1,2,3",
655
577
"EventCode": "0xC7",
656
578
"EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
657
579
"PEBS": "1",
···
661
581
},
662
582
{
663
583
"BriefDescription": "Stack pointer instructions decoded",
584
+
"Counter": "0,1,2,3",
664
585
"EventCode": "0xD1",
665
586
"EventName": "UOPS_DECODED.ESP_FOLDING",
666
587
"SampleAfterValue": "2000000",
···
669
588
},
670
589
{
671
590
"BriefDescription": "Stack pointer sync operations",
591
+
"Counter": "0,1,2,3",
672
592
"EventCode": "0xD1",
673
593
"EventName": "UOPS_DECODED.ESP_SYNC",
674
594
"SampleAfterValue": "2000000",
···
677
595
},
678
596
{
679
597
"BriefDescription": "Uops decoded by Microcode Sequencer",
598
+
"Counter": "0,1,2,3",
680
599
"CounterMask": "1",
681
600
"EventCode": "0xD1",
682
601
"EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
···
686
603
},
687
604
{
688
605
"BriefDescription": "Cycles no Uops are decoded",
606
+
"Counter": "0,1,2,3",
689
607
"CounterMask": "1",
690
608
"EventCode": "0xD1",
691
609
"EventName": "UOPS_DECODED.STALL_CYCLES",
···
697
613
{
698
614
"AnyThread": "1",
699
615
"BriefDescription": "Cycles Uops executed on any port (core count)",
616
+
"Counter": "0,1,2,3",
700
617
"CounterMask": "1",
701
618
"EventCode": "0xB1",
702
619
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
···
707
622
{
708
623
"AnyThread": "1",
709
624
"BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
625
+
"Counter": "0,1,2,3",
710
626
"CounterMask": "1",
711
627
"EventCode": "0xB1",
712
628
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
···
717
631
{
718
632
"AnyThread": "1",
719
633
"BriefDescription": "Uops executed on any port (core count)",
634
+
"Counter": "0,1,2,3",
720
635
"CounterMask": "1",
721
636
"EdgeDetect": "1",
722
637
"EventCode": "0xB1",
···
729
642
{
730
643
"AnyThread": "1",
731
644
"BriefDescription": "Uops executed on ports 0-4 (core count)",
645
+
"Counter": "0,1,2,3",
732
646
"CounterMask": "1",
733
647
"EdgeDetect": "1",
734
648
"EventCode": "0xB1",
···
741
653
{
742
654
"AnyThread": "1",
743
655
"BriefDescription": "Cycles no Uops issued on any port (core count)",
656
+
"Counter": "0,1,2,3",
744
657
"CounterMask": "1",
745
658
"EventCode": "0xB1",
746
659
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
···
752
663
{
753
664
"AnyThread": "1",
754
665
"BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
666
+
"Counter": "0,1,2,3",
755
667
"CounterMask": "1",
756
668
"EventCode": "0xB1",
757
669
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
···
762
672
},
763
673
{
764
674
"BriefDescription": "Uops executed on port 0",
675
+
"Counter": "0,1,2,3",
765
676
"EventCode": "0xB1",
766
677
"EventName": "UOPS_EXECUTED.PORT0",
767
678
"SampleAfterValue": "2000000",
···
770
679
},
771
680
{
772
681
"BriefDescription": "Uops issued on ports 0, 1 or 5",
682
+
"Counter": "0,1,2,3",
773
683
"EventCode": "0xB1",
774
684
"EventName": "UOPS_EXECUTED.PORT015",
775
685
"SampleAfterValue": "2000000",
···
778
686
},
779
687
{
780
688
"BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
689
+
"Counter": "0,1,2,3",
781
690
"CounterMask": "1",
782
691
"EventCode": "0xB1",
783
692
"EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
···
788
695
},
789
696
{
790
697
"BriefDescription": "Uops executed on port 1",
698
+
"Counter": "0,1,2,3",
791
699
"EventCode": "0xB1",
792
700
"EventName": "UOPS_EXECUTED.PORT1",
793
701
"SampleAfterValue": "2000000",
···
797
703
{
798
704
"AnyThread": "1",
799
705
"BriefDescription": "Uops issued on ports 2, 3 or 4",
706
+
"Counter": "0,1,2,3",
800
707
"EventCode": "0xB1",
801
708
"EventName": "UOPS_EXECUTED.PORT234_CORE",
802
709
"SampleAfterValue": "2000000",
···
806
711
{
807
712
"AnyThread": "1",
808
713
"BriefDescription": "Uops executed on port 2 (core count)",
714
+
"Counter": "0,1,2,3",
809
715
"EventCode": "0xB1",
810
716
"EventName": "UOPS_EXECUTED.PORT2_CORE",
811
717
"SampleAfterValue": "2000000",
···
815
719
{
816
720
"AnyThread": "1",
817
721
"BriefDescription": "Uops executed on port 3 (core count)",
722
+
"Counter": "0,1,2,3",
818
723
"EventCode": "0xB1",
819
724
"EventName": "UOPS_EXECUTED.PORT3_CORE",
820
725
"SampleAfterValue": "2000000",
···
824
727
{
825
728
"AnyThread": "1",
826
729
"BriefDescription": "Uops executed on port 4 (core count)",
730
+
"Counter": "0,1,2,3",
827
731
"EventCode": "0xB1",
828
732
"EventName": "UOPS_EXECUTED.PORT4_CORE",
829
733
"SampleAfterValue": "2000000",
···
832
734
},
833
735
{
834
736
"BriefDescription": "Uops executed on port 5",
737
+
"Counter": "0,1,2,3",
835
738
"EventCode": "0xB1",
836
739
"EventName": "UOPS_EXECUTED.PORT5",
837
740
"SampleAfterValue": "2000000",
···
840
741
},
841
742
{
842
743
"BriefDescription": "Uops issued",
744
+
"Counter": "0,1,2,3",
843
745
"EventCode": "0xE",
844
746
"EventName": "UOPS_ISSUED.ANY",
845
747
"SampleAfterValue": "2000000",
···
849
749
{
850
750
"AnyThread": "1",
851
751
"BriefDescription": "Cycles no Uops were issued on any thread",
752
+
"Counter": "0,1,2,3",
852
753
"CounterMask": "1",
853
754
"EventCode": "0xE",
854
755
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
···
860
759
{
861
760
"AnyThread": "1",
862
761
"BriefDescription": "Cycles Uops were issued on either thread",
762
+
"Counter": "0,1,2,3",
863
763
"CounterMask": "1",
864
764
"EventCode": "0xE",
865
765
"EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
···
869
767
},
870
768
{
871
769
"BriefDescription": "Fused Uops issued",
770
+
"Counter": "0,1,2,3",
872
771
"EventCode": "0xE",
873
772
"EventName": "UOPS_ISSUED.FUSED",
874
773
"SampleAfterValue": "2000000",
···
877
774
},
878
775
{
879
776
"BriefDescription": "Cycles no Uops were issued",
777
+
"Counter": "0,1,2,3",
880
778
"CounterMask": "1",
881
779
"EventCode": "0xE",
882
780
"EventName": "UOPS_ISSUED.STALL_CYCLES",
···
887
783
},
888
784
{
889
785
"BriefDescription": "Cycles Uops are being retired",
786
+
"Counter": "0,1,2,3",
890
787
"CounterMask": "1",
891
788
"EventCode": "0xC2",
892
789
"EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
···
897
792
},
898
793
{
899
794
"BriefDescription": "Uops retired (Precise Event)",
795
+
"Counter": "0,1,2,3",
900
796
"EventCode": "0xC2",
901
797
"EventName": "UOPS_RETIRED.ANY",
902
798
"PEBS": "1",
···
906
800
},
907
801
{
908
802
"BriefDescription": "Macro-fused Uops retired (Precise Event)",
803
+
"Counter": "0,1,2,3",
909
804
"EventCode": "0xC2",
910
805
"EventName": "UOPS_RETIRED.MACRO_FUSED",
911
806
"PEBS": "1",
···
915
808
},
916
809
{
917
810
"BriefDescription": "Retirement slots used (Precise Event)",
811
+
"Counter": "0,1,2,3",
918
812
"EventCode": "0xC2",
919
813
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
920
814
"PEBS": "1",
···
924
816
},
925
817
{
926
818
"BriefDescription": "Cycles Uops are not retiring (Precise Event)",
819
+
"Counter": "0,1,2,3",
927
820
"CounterMask": "1",
928
821
"EventCode": "0xC2",
929
822
"EventName": "UOPS_RETIRED.STALL_CYCLES",
···
935
826
},
936
827
{
937
828
"BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
829
+
"Counter": "0,1,2,3",
938
830
"CounterMask": "16",
939
831
"EventCode": "0xC2",
940
832
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
···
946
836
},
947
837
{
948
838
"BriefDescription": "Uop unfusions due to FP exceptions",
839
+
"Counter": "0,1,2,3",
949
840
"EventCode": "0xDB",
950
841
"EventName": "UOP_UNFUSION",
951
842
"SampleAfterValue": "2000000",
+21
tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json
+21
tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "DTLB load misses",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x8",
5
6
"EventName": "DTLB_LOAD_MISSES.ANY",
6
7
"SampleAfterValue": "200000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "DTLB load miss large page walks",
11
+
"Counter": "0,1,2,3",
12
12
"EventCode": "0x8",
13
13
"EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",
14
14
"SampleAfterValue": "200000",
···
17
15
},
18
16
{
19
17
"BriefDescription": "DTLB load miss caused by low part of address",
18
+
"Counter": "0,1,2,3",
20
19
"EventCode": "0x8",
21
20
"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
22
21
"SampleAfterValue": "200000",
···
25
22
},
26
23
{
27
24
"BriefDescription": "DTLB second level hit",
25
+
"Counter": "0,1,2,3",
28
26
"EventCode": "0x8",
29
27
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
30
28
"SampleAfterValue": "2000000",
···
33
29
},
34
30
{
35
31
"BriefDescription": "DTLB load miss page walks complete",
32
+
"Counter": "0,1,2,3",
36
33
"EventCode": "0x8",
37
34
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
38
35
"SampleAfterValue": "200000",
···
41
36
},
42
37
{
43
38
"BriefDescription": "DTLB load miss page walk cycles",
39
+
"Counter": "0,1,2,3",
44
40
"EventCode": "0x8",
45
41
"EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
46
42
"SampleAfterValue": "200000",
···
49
43
},
50
44
{
51
45
"BriefDescription": "DTLB misses",
46
+
"Counter": "0,1,2,3",
52
47
"EventCode": "0x49",
53
48
"EventName": "DTLB_MISSES.ANY",
54
49
"SampleAfterValue": "200000",
···
57
50
},
58
51
{
59
52
"BriefDescription": "DTLB miss large page walks",
53
+
"Counter": "0,1,2,3",
60
54
"EventCode": "0x49",
61
55
"EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
62
56
"SampleAfterValue": "200000",
···
65
57
},
66
58
{
67
59
"BriefDescription": "DTLB misses caused by low part of address",
60
+
"Counter": "0,1,2,3",
68
61
"EventCode": "0x49",
69
62
"EventName": "DTLB_MISSES.PDE_MISS",
70
63
"SampleAfterValue": "200000",
···
73
64
},
74
65
{
75
66
"BriefDescription": "DTLB first level misses but second level hit",
67
+
"Counter": "0,1,2,3",
76
68
"EventCode": "0x49",
77
69
"EventName": "DTLB_MISSES.STLB_HIT",
78
70
"SampleAfterValue": "200000",
···
81
71
},
82
72
{
83
73
"BriefDescription": "DTLB miss page walks",
74
+
"Counter": "0,1,2,3",
84
75
"EventCode": "0x49",
85
76
"EventName": "DTLB_MISSES.WALK_COMPLETED",
86
77
"SampleAfterValue": "200000",
···
89
78
},
90
79
{
91
80
"BriefDescription": "DTLB miss page walk cycles",
81
+
"Counter": "0,1,2,3",
92
82
"EventCode": "0x49",
93
83
"EventName": "DTLB_MISSES.WALK_CYCLES",
94
84
"SampleAfterValue": "2000000",
···
97
85
},
98
86
{
99
87
"BriefDescription": "Extended Page Table walk cycles",
88
+
"Counter": "0,1,2,3",
100
89
"EventCode": "0x4F",
101
90
"EventName": "EPT.WALK_CYCLES",
102
91
"SampleAfterValue": "2000000",
···
105
92
},
106
93
{
107
94
"BriefDescription": "ITLB flushes",
95
+
"Counter": "0,1,2,3",
108
96
"EventCode": "0xAE",
109
97
"EventName": "ITLB_FLUSH",
110
98
"SampleAfterValue": "2000000",
···
113
99
},
114
100
{
115
101
"BriefDescription": "ITLB miss",
102
+
"Counter": "0,1,2,3",
116
103
"EventCode": "0x85",
117
104
"EventName": "ITLB_MISSES.ANY",
118
105
"SampleAfterValue": "200000",
···
121
106
},
122
107
{
123
108
"BriefDescription": "ITLB miss large page walks",
109
+
"Counter": "0,1,2,3",
124
110
"EventCode": "0x85",
125
111
"EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED",
126
112
"SampleAfterValue": "200000",
···
129
113
},
130
114
{
131
115
"BriefDescription": "ITLB miss page walks",
116
+
"Counter": "0,1,2,3",
132
117
"EventCode": "0x85",
133
118
"EventName": "ITLB_MISSES.WALK_COMPLETED",
134
119
"SampleAfterValue": "200000",
···
137
120
},
138
121
{
139
122
"BriefDescription": "ITLB miss page walk cycles",
123
+
"Counter": "0,1,2,3",
140
124
"EventCode": "0x85",
141
125
"EventName": "ITLB_MISSES.WALK_CYCLES",
142
126
"SampleAfterValue": "2000000",
···
145
127
},
146
128
{
147
129
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
130
+
"Counter": "0,1,2,3",
148
131
"EventCode": "0xC8",
149
132
"EventName": "ITLB_MISS_RETIRED",
150
133
"PEBS": "1",
···
154
135
},
155
136
{
156
137
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
138
+
"Counter": "0,1,2,3",
157
139
"EventCode": "0xCB",
158
140
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
159
141
"PEBS": "1",
···
163
143
},
164
144
{
165
145
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
146
+
"Counter": "0,1,2,3",
166
147
"EventCode": "0xC",
167
148
"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
168
149
"PEBS": "1",