Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: add vcn_v2_0 ip dump support
Add support of vcn ip dump in the devcoredump
for vcn_v2_0.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Sunil Khatri
and committed by
Alex Deucher
2239aaa2
ef9f3b5f
+78
-1
+78
-1
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+78
-1
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
···
53
53
#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7
54
54
#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2
55
55
56
+
static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_0[] = {
57
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
58
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
59
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
60
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),
61
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
62
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
63
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),
64
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),
65
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
66
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
67
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),
68
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),
69
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),
70
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),
71
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),
72
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),
73
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
74
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
75
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
76
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),
77
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),
78
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),
79
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
80
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
81
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),
82
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),
83
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),
84
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),
85
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),
86
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),
87
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),
88
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),
89
+
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)
90
+
};
91
+
56
92
static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
57
93
static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
58
94
static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
···
132
96
{
133
97
struct amdgpu_ring *ring;
134
98
int i, r;
99
+
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
100
+
uint32_t *ptr;
135
101
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
136
102
volatile struct amdgpu_fw_shared *fw_shared;
137
103
···
222
184
if (amdgpu_vcnfw_log)
223
185
amdgpu_vcn_fwlog_init(adev->vcn.inst);
224
186
187
+
/* Allocate memory for VCN IP Dump buffer */
188
+
ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
189
+
if (!ptr) {
190
+
DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
191
+
adev->vcn.ip_dump = NULL;
192
+
} else {
193
+
adev->vcn.ip_dump = ptr;
194
+
}
195
+
225
196
return 0;
226
197
}
227
198
···
259
212
return r;
260
213
261
214
r = amdgpu_vcn_sw_fini(adev);
215
+
216
+
kfree(adev->vcn.ip_dump);
262
217
263
218
return r;
264
219
}
···
2034
1985
return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table);
2035
1986
}
2036
1987
1988
+
static void vcn_v2_0_dump_ip_state(void *handle)
1989
+
{
1990
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1991
+
int i, j;
1992
+
bool is_powered;
1993
+
uint32_t inst_off;
1994
+
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
1995
+
1996
+
if (!adev->vcn.ip_dump)
1997
+
return;
1998
+
1999
+
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2000
+
if (adev->vcn.harvest_config & (1 << i))
2001
+
continue;
2002
+
2003
+
inst_off = i * reg_count;
2004
+
/* mmUVD_POWER_STATUS is always readable and is first element of the array */
2005
+
adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
2006
+
is_powered = (adev->vcn.ip_dump[inst_off] &
2007
+
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
2008
+
2009
+
if (is_powered)
2010
+
for (j = 1; j < reg_count; j++)
2011
+
adev->vcn.ip_dump[inst_off + j] =
2012
+
RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], i));
2013
+
}
2014
+
}
2015
+
2037
2016
static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
2038
2017
.name = "vcn_v2_0",
2039
2018
.early_init = vcn_v2_0_early_init,
···
2080
2003
.post_soft_reset = NULL,
2081
2004
.set_clockgating_state = vcn_v2_0_set_clockgating_state,
2082
2005
.set_powergating_state = vcn_v2_0_set_powergating_state,
2083
-
.dump_ip_state = NULL,
2006
+
.dump_ip_state = vcn_v2_0_dump_ip_state,
2084
2007
.print_ip_state = NULL,
2085
2008
};
2086
2009