tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/msm/dsi/phy: Add support for Kaanapali

Add DSI PHY support for the Kaanapali platform, Kaanapali introduce
addition of DSI2/DSI2_phy compared to SM8650. However, based on the
HPG diagram, only DSI0_phy and DSI1_phy works.

Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/698705/
Link: https://lore.kernel.org/r/20260115092749.533-7-yuanjie.yang@oss.qualcomm.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

authored by

Yuanjie Yang and committed by
Dmitry Baryshkov 223bff62 3d2d7a33

+26
+2
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
··· 577 577 .data = &dsi_phy_4nm_8650_cfgs }, 578 578 { .compatible = "qcom,sm8750-dsi-phy-3nm", 579 579 .data = &dsi_phy_3nm_8750_cfgs }, 580 + { .compatible = "qcom,kaanapali-dsi-phy-3nm", 581 + .data = &dsi_phy_3nm_kaanapali_cfgs }, 580 582 #endif 581 583 {} 582 584 };
+1
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
··· 64 64 extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; 65 65 extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; 66 66 extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs; 67 + extern const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs; 67 68 68 69 struct msm_dsi_dphy_timing { 69 70 u32 clk_zero;
+23
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
··· 1504 1504 .num_dsi_phy = 2, 1505 1505 .quirks = DSI_PHY_7NM_QUIRK_V7_0, 1506 1506 }; 1507 + 1508 + const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs = { 1509 + .has_phy_lane = true, 1510 + .regulator_data = dsi_phy_7nm_98000uA_regulators, 1511 + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), 1512 + .ops = { 1513 + .enable = dsi_7nm_phy_enable, 1514 + .disable = dsi_7nm_phy_disable, 1515 + .pll_init = dsi_pll_7nm_init, 1516 + .save_pll_state = dsi_7nm_pll_save_state, 1517 + .restore_pll_state = dsi_7nm_pll_restore_state, 1518 + .set_continuous_clock = dsi_7nm_set_continuous_clock, 1519 + }, 1520 + .min_pll_rate = 600000000UL, 1521 + #ifdef CONFIG_64BIT 1522 + .max_pll_rate = 5000000000UL, 1523 + #else 1524 + .max_pll_rate = ULONG_MAX, 1525 + #endif 1526 + .io_start = { 0x9ac1000, 0x9ac4000 }, 1527 + .num_dsi_phy = 2, 1528 + .quirks = DSI_PHY_7NM_QUIRK_V7_0, 1529 + };