Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpu: nova-core: remove `io::` qualifier to register macro invocations
The kernel's `register` macro would clash with nova-core's own version
if it was imported directly, so it was accessed through its `io` module
during the conversion phase.
Now that nova-core's `register` macro doesn't exist anymore, we can
import and use it directly without risk of name collision.
Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
Reviewed-by: Gary Guo <gary@garyguo.net>
Acked-by: Danilo Krummrich <dakr@kernel.org>
Link: https://patch.msgid.link/20260325-b4-nova-register-v4-9-bdf172f0f6ca@nvidia.com
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
+15
-15
+15
-15
drivers/gpu/nova-core/regs.rs
+15
-15
drivers/gpu/nova-core/regs.rs
···
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2
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3
use kernel::{
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4
io::{
5
-
self,
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+
register,
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register::WithBase,
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7
Io, //
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8
},
···
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// PMC
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-
io::register! {
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+
register! {
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/// Basic revision information about the GPU.
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pub(crate) NV_PMC_BOOT_0(u32) @ 0x00000000 {
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/// Lower bits of the architecture.
···
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// PBUS
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-
io::register! {
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+
register! {
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pub(crate) NV_PBUS_SW_SCRATCH(u32)[64] @ 0x00001400 {}
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/// Scratch register 0xe used as FRTS firmware error code.
···
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// PFB
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-
io::register! {
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+
register! {
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/// Low bits of the physical system memory address used by the GPU to perform sysmembar
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/// operations (see [`crate::fb::SysmemFlush`]).
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pub(crate) NV_PFB_NISO_FLUSH_SYSMEM_ADDR(u32) @ 0x00100c10 {
···
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// PGSP
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-
io::register! {
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+
register! {
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pub(crate) NV_PGSP_QUEUE_HEAD(u32) @ 0x00110c00 {
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31:0 address;
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}
···
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// These scratch registers remain powered on even in a low-power state and have a designated group
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// number.
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-
io::register! {
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+
register! {
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/// Boot Sequence Interface (BSI) register used to determine
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/// if GSP reload/resume has completed during the boot process.
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pub(crate) NV_PGC6_BSI_SECURE_SCRATCH_14(u32) @ 0x001180f8 {
···
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// PDISP
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-
io::register! {
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+
register! {
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pub(crate) NV_PDISP_VGA_WORKSPACE_BASE(u32) @ 0x00625f04 {
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/// VGA workspace base address divided by 0x10000.
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31:8 addr;
···
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pub(crate) const NV_FUSE_OPT_FPF_SIZE: usize = 16;
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-
io::register! {
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+
register! {
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pub(crate) NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION(u32)[NV_FUSE_OPT_FPF_SIZE] @ 0x00824100 {
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15:0 data => u16;
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}
···
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// PFALCON
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-
io::register! {
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+
register! {
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pub(crate) NV_PFALCON_FALCON_IRQSCLR(u32) @ PFalconBase + 0x00000004 {
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6:6 swgen0 => bool;
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4:4 halt => bool;
···
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/* PFALCON2 */
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-
io::register! {
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+
register! {
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pub(crate) NV_PFALCON2_FALCON_MOD_SEL(u32) @ PFalcon2Base + 0x00000180 {
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7:0 algo ?=> FalconModSelAlgo;
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}
···
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// PRISCV
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-
io::register! {
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+
register! {
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/// RISC-V status register for debug (Turing and GA100 only).
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/// Reflects current RISC-V core status.
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pub(crate) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ PFalcon2Base + 0x00000240 {
···
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// only be used in HAL modules.
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pub(crate) mod gm107 {
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-
use kernel::io;
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+
use kernel::io::register;
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// FUSE
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-
io::register! {
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+
register! {
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pub(crate) NV_FUSE_STATUS_OPT_DISPLAY(u32) @ 0x00021c04 {
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0:0 display_disabled => bool;
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}
···
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}
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pub(crate) mod ga100 {
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-
use kernel::io;
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+
use kernel::io::register;
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// FUSE
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-
io::register! {
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+
register! {
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pub(crate) NV_FUSE_STATUS_OPT_DISPLAY(u32) @ 0x00820c04 {
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0:0 display_disabled => bool;
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}