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reset: npcm: register npcm8xx clock auxiliary bus device

Add NPCM8xx clock controller auxiliary bus device registration.

The NPCM8xx clock controller is registered as an aux device because the
reset and the clock controller share the same register region.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Tested-by: Benjamin Fair <benjaminfair@google.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20240912191038.981105-3-tmaimon77@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Tomer Maimon and committed by
Stephen Boyd
22823157 d62f45b5

+95 -2
+1
drivers/reset/Kconfig
··· 170 170 config RESET_NPCM 171 171 bool "NPCM BMC Reset Driver" if COMPILE_TEST 172 172 default ARCH_NPCM 173 + select AUXILIARY_BUS 173 174 help 174 175 This enables the reset controller driver for Nuvoton NPCM 175 176 BMC SoCs.
+76 -2
drivers/reset/reset-npcm.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 // Copyright (c) 2019 Nuvoton Technology corporation. 3 3 4 + #include <linux/auxiliary_bus.h> 4 5 #include <linux/delay.h> 5 6 #include <linux/err.h> 6 7 #include <linux/io.h> ··· 11 10 #include <linux/property.h> 12 11 #include <linux/reboot.h> 13 12 #include <linux/reset-controller.h> 13 + #include <linux/slab.h> 14 14 #include <linux/spinlock.h> 15 15 #include <linux/mfd/syscon.h> 16 16 #include <linux/regmap.h> 17 17 #include <linux/of_address.h> 18 + 19 + #include <soc/nuvoton/clock-npcm8xx.h> 18 20 19 21 /* NPCM7xx GCR registers */ 20 22 #define NPCM_MDLR_OFFSET 0x7C ··· 93 89 const struct npcm_reset_info *info; 94 90 struct regmap *gcr_regmap; 95 91 u32 sw_reset_number; 92 + struct device *dev; 96 93 void __iomem *base; 97 94 spinlock_t lock; 98 95 }; ··· 377 372 .status = npcm_rc_status, 378 373 }; 379 374 375 + static void npcm_clock_unregister_adev(void *_adev) 376 + { 377 + struct auxiliary_device *adev = _adev; 378 + 379 + auxiliary_device_delete(adev); 380 + auxiliary_device_uninit(adev); 381 + } 382 + 383 + static void npcm_clock_adev_release(struct device *dev) 384 + { 385 + struct auxiliary_device *adev = to_auxiliary_dev(dev); 386 + struct npcm_clock_adev *rdev = to_npcm_clock_adev(adev); 387 + 388 + kfree(rdev); 389 + } 390 + 391 + static struct auxiliary_device *npcm_clock_adev_alloc(struct npcm_rc_data *rst_data, char *clk_name) 392 + { 393 + struct npcm_clock_adev *rdev; 394 + struct auxiliary_device *adev; 395 + int ret; 396 + 397 + rdev = kzalloc(sizeof(*rdev), GFP_KERNEL); 398 + if (!rdev) 399 + return ERR_PTR(-ENOMEM); 400 + 401 + rdev->base = rst_data->base; 402 + 403 + adev = &rdev->adev; 404 + adev->name = clk_name; 405 + adev->dev.parent = rst_data->dev; 406 + adev->dev.release = npcm_clock_adev_release; 407 + adev->id = 555u; 408 + 409 + ret = auxiliary_device_init(adev); 410 + if (ret) { 411 + kfree(rdev); 412 + return ERR_PTR(ret); 413 + } 414 + 415 + return adev; 416 + } 417 + 418 + static int npcm8xx_clock_controller_register(struct npcm_rc_data *rst_data, char *clk_name) 419 + { 420 + struct auxiliary_device *adev; 421 + int ret; 422 + 423 + adev = npcm_clock_adev_alloc(rst_data, clk_name); 424 + if (IS_ERR(adev)) 425 + return PTR_ERR(adev); 426 + 427 + ret = auxiliary_device_add(adev); 428 + if (ret) { 429 + auxiliary_device_uninit(adev); 430 + return ret; 431 + } 432 + 433 + return devm_add_action_or_reset(rst_data->dev, npcm_clock_unregister_adev, adev); 434 + } 435 + 380 436 static int npcm_rc_probe(struct platform_device *pdev) 381 437 { 382 438 struct npcm_rc_data *rc; ··· 458 392 rc->rcdev.of_node = pdev->dev.of_node; 459 393 rc->rcdev.of_reset_n_cells = 2; 460 394 rc->rcdev.of_xlate = npcm_reset_xlate; 395 + rc->dev = &pdev->dev; 461 396 462 397 ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev); 463 398 if (ret) { ··· 475 408 rc->restart_nb.priority = 192, 476 409 rc->restart_nb.notifier_call = npcm_rc_restart, 477 410 ret = register_restart_handler(&rc->restart_nb); 478 - if (ret) 411 + if (ret) { 479 412 dev_warn(&pdev->dev, "failed to register restart handler\n"); 413 + return ret; 414 + } 480 415 } 481 416 } 482 417 483 - return ret; 418 + switch (rc->info->bmc_id) { 419 + case BMC_NPCM8XX: 420 + return npcm8xx_clock_controller_register(rc, "clk-npcm8xx"); 421 + default: 422 + return 0; 423 + } 484 424 } 485 425 486 426 static struct platform_driver npcm_rc_driver = {
+18
include/soc/nuvoton/clock-npcm8xx.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + #ifndef __SOC_NPCM8XX_CLOCK_H 3 + #define __SOC_NPCM8XX_CLOCK_H 4 + 5 + #include <linux/auxiliary_bus.h> 6 + #include <linux/container_of.h> 7 + 8 + struct npcm_clock_adev { 9 + void __iomem *base; 10 + struct auxiliary_device adev; 11 + }; 12 + 13 + static inline struct npcm_clock_adev *to_npcm_clock_adev(struct auxiliary_device *_adev) 14 + { 15 + return container_of(_adev, struct npcm_clock_adev, adev); 16 + } 17 + 18 + #endif