Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'riscv-for-linus-6.0-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Palmer Dabbelt:
- A pair of device tree fixes for the Polarfire SOC
- A fix to avoid overflowing the PMU counter array when firmware
incorrectly reports the number of supported counters, which manifests
on OpenSBI versions prior to 1.1
* tag 'riscv-for-linus-6.0-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
perf: RISC-V: fix access beyond allocated array
riscv: dts: microchip: use an mpfs specific l2 compatible
dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible
+50
-31
+48
-29
Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
+48
-29
Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
···
17
17
acts as directory-based coherency manager.
18
18
All the properties in ePAPR/DeviceTree specification applies for this platform.
19
19
20
-
allOf:
21
-
- $ref: /schemas/cache-controller.yaml#
22
-
23
20
select:
24
21
properties:
25
22
compatible:
···
30
33
31
34
properties:
32
35
compatible:
33
-
items:
34
-
- enum:
35
-
- sifive,fu540-c000-ccache
36
-
- sifive,fu740-c000-ccache
37
-
- const: cache
36
+
oneOf:
37
+
- items:
38
+
- enum:
39
+
- sifive,fu540-c000-ccache
40
+
- sifive,fu740-c000-ccache
41
+
- const: cache
42
+
- items:
43
+
- const: microchip,mpfs-ccache
44
+
- const: sifive,fu540-c000-ccache
45
+
- const: cache
38
46
39
47
cache-block-size:
40
48
const: 64
···
74
72
The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
75
73
The reserved memory node should be defined as per the bindings in reserved-memory.txt.
76
74
77
-
if:
78
-
properties:
79
-
compatible:
80
-
contains:
81
-
const: sifive,fu540-c000-ccache
75
+
allOf:
76
+
- $ref: /schemas/cache-controller.yaml#
82
77
83
-
then:
84
-
properties:
85
-
interrupts:
86
-
description: |
87
-
Must contain entries for DirError, DataError and DataFail signals.
88
-
maxItems: 3
89
-
cache-sets:
90
-
const: 1024
78
+
- if:
79
+
properties:
80
+
compatible:
81
+
contains:
82
+
enum:
83
+
- sifive,fu740-c000-ccache
84
+
- microchip,mpfs-ccache
91
85
92
-
else:
93
-
properties:
94
-
interrupts:
95
-
description: |
96
-
Must contain entries for DirError, DataError, DataFail, DirFail signals.
97
-
minItems: 4
98
-
cache-sets:
99
-
const: 2048
86
+
then:
87
+
properties:
88
+
interrupts:
89
+
description: |
90
+
Must contain entries for DirError, DataError, DataFail, DirFail signals.
91
+
minItems: 4
92
+
93
+
else:
94
+
properties:
95
+
interrupts:
96
+
description: |
97
+
Must contain entries for DirError, DataError and DataFail signals.
98
+
maxItems: 3
99
+
100
+
- if:
101
+
properties:
102
+
compatible:
103
+
contains:
104
+
const: sifive,fu740-c000-ccache
105
+
106
+
then:
107
+
properties:
108
+
cache-sets:
109
+
const: 2048
110
+
111
+
else:
112
+
properties:
113
+
cache-sets:
114
+
const: 1024
100
115
101
116
additionalProperties: false
102
117
+1
-1
arch/riscv/boot/dts/microchip/mpfs.dtsi
+1
-1
arch/riscv/boot/dts/microchip/mpfs.dtsi
···
185
185
ranges;
186
186
187
187
cctrllr: cache-controller@2010000 {
188
-
compatible = "sifive,fu540-c000-ccache", "cache";
188
+
compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
189
189
reg = <0x0 0x2010000 0x0 0x1000>;
190
190
cache-block-size = <64>;
191
191
cache-level = <2>;
+1
-1
drivers/perf/riscv_pmu_sbi.c
+1
-1
drivers/perf/riscv_pmu_sbi.c
···
473
473
if (!pmu_ctr_list)
474
474
return -ENOMEM;
475
475
476
-
for (i = 0; i <= nctr; i++) {
476
+
for (i = 0; i < nctr; i++) {
477
477
ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, 0, 0, 0, 0, 0);
478
478
if (ret.error)
479
479
/* The logical counter ids are not expected to be contiguous */