Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'net-stmmac-simplify-axi_blen-handling'
Russell King says:
====================
net: stmmac: simplify axi_blen handling
stmmac's axi_blen (burst length) handling is very verbose and
unnecessary.
Firstly, the burst length register bitfield is the same across all
dwmac cores, so we can use common definitions for these bits which
platform glue can use.
We end up with platform glue:
- filling in the axi_blen[] array with the decimal burst lengths, e.g.
dwmac-intel.c, etc
- decoding a bitmap into burst lengths for this array, e.g.
dwmac-dwc-qos-eth.c
Other cases read the array from DT, placing it into the axi_blen
array, and converting later to the register bitfield.
This series removes all this complexity, ultimately ending up with
platform glue providing the register value containing the burst
length bitfield directly. Where necessary, platform glue calls
stmmac_axi_blen_to_mask() to convert a decimal array (e.g. from
DT) to the register value.
This also means that stmmac_axi_blen_to_mask() can issue a
diagnostic message at probe time if the burst length is incorrect.
====================
Link: https://patch.msgid.link/aR2aaDs6rqfu32B-@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+78
-146
+13
drivers/net/ethernet/stmicro/stmmac/common.h
+13
drivers/net/ethernet/stmicro/stmmac/common.h
···
548
548
#define LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */
549
549
#define LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */
550
550
551
+
/* Common definitions for AXI Master Bus Mode */
552
+
#define DMA_AXI_AAL BIT(12)
553
+
#define DMA_AXI_BLEN256 BIT(7)
554
+
#define DMA_AXI_BLEN128 BIT(6)
555
+
#define DMA_AXI_BLEN64 BIT(5)
556
+
#define DMA_AXI_BLEN32 BIT(4)
557
+
#define DMA_AXI_BLEN16 BIT(3)
558
+
#define DMA_AXI_BLEN8 BIT(2)
559
+
#define DMA_AXI_BLEN4 BIT(1)
560
+
#define DMA_AXI_BLEN_MASK GENMASK(7, 1)
561
+
562
+
void stmmac_axi_blen_to_mask(u32 *regval, const u32 *blen, size_t len);
563
+
551
564
#define STMMAC_CHAIN_MODE 0x1
552
565
#define STMMAC_RING_MODE 0x2
553
566
+2
-26
drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
+2
-26
drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
···
38
38
{
39
39
struct device *dev = &pdev->dev;
40
40
u32 burst_map = 0;
41
-
u32 bit_index = 0;
42
-
u32 a_index = 0;
43
41
44
42
if (!plat_dat->axi) {
45
43
plat_dat->axi = devm_kzalloc(&pdev->dev,
···
81
83
}
82
84
device_property_read_u32(dev, "snps,burst-map", &burst_map);
83
85
84
-
/* converts burst-map bitmask to burst array */
85
-
for (bit_index = 0; bit_index < 7; bit_index++) {
86
-
if (burst_map & (1 << bit_index)) {
87
-
switch (bit_index) {
88
-
case 0:
89
-
plat_dat->axi->axi_blen[a_index] = 4; break;
90
-
case 1:
91
-
plat_dat->axi->axi_blen[a_index] = 8; break;
92
-
case 2:
93
-
plat_dat->axi->axi_blen[a_index] = 16; break;
94
-
case 3:
95
-
plat_dat->axi->axi_blen[a_index] = 32; break;
96
-
case 4:
97
-
plat_dat->axi->axi_blen[a_index] = 64; break;
98
-
case 5:
99
-
plat_dat->axi->axi_blen[a_index] = 128; break;
100
-
case 6:
101
-
plat_dat->axi->axi_blen[a_index] = 256; break;
102
-
default:
103
-
break;
104
-
}
105
-
a_index++;
106
-
}
107
-
}
86
+
plat_dat->axi->axi_blen_regval = FIELD_PREP(DMA_AXI_BLEN_MASK,
87
+
burst_map);
108
88
109
89
/* dwc-qos needs GMAC4, AAL, TSO and PMT */
110
90
plat_dat->core_type = DWMAC_CORE_GMAC4;
+2
-3
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+2
-3
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
···
650
650
plat->axi->axi_xit_frm = 0;
651
651
plat->axi->axi_wr_osr_lmt = 1;
652
652
plat->axi->axi_rd_osr_lmt = 1;
653
-
plat->axi->axi_blen[0] = 4;
654
-
plat->axi->axi_blen[1] = 8;
655
-
plat->axi->axi_blen[2] = 16;
653
+
plat->axi->axi_blen_regval = DMA_AXI_BLEN4 | DMA_AXI_BLEN8 |
654
+
DMA_AXI_BLEN16;
656
655
657
656
plat->ptp_max_adj = plat->clk_ptp_rate;
658
657
+3
-27
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
+3
-27
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
···
19
19
static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
20
20
{
21
21
u32 value = readl(ioaddr + DMA_AXI_BUS_MODE);
22
-
int i;
23
22
24
23
pr_info("dwmac1000: Master AXI performs %s burst length\n",
25
24
!(value & DMA_AXI_UNDEF) ? "fixed" : "any");
···
38
39
39
40
/* Depending on the UNDEF bit the Master AXI will perform any burst
40
41
* length according to the BLEN programmed (by default all BLEN are
41
-
* set).
42
+
* set). Note that the UNDEF bit is readonly, and is the inverse of
43
+
* Bus Mode bit 16.
42
44
*/
43
-
for (i = 0; i < AXI_BLEN; i++) {
44
-
switch (axi->axi_blen[i]) {
45
-
case 256:
46
-
value |= DMA_AXI_BLEN256;
47
-
break;
48
-
case 128:
49
-
value |= DMA_AXI_BLEN128;
50
-
break;
51
-
case 64:
52
-
value |= DMA_AXI_BLEN64;
53
-
break;
54
-
case 32:
55
-
value |= DMA_AXI_BLEN32;
56
-
break;
57
-
case 16:
58
-
value |= DMA_AXI_BLEN16;
59
-
break;
60
-
case 8:
61
-
value |= DMA_AXI_BLEN8;
62
-
break;
63
-
case 4:
64
-
value |= DMA_AXI_BLEN4;
65
-
break;
66
-
}
67
-
}
45
+
value = (value & ~DMA_AXI_BLEN_MASK) | axi->axi_blen_regval;
68
46
69
47
writel(value, ioaddr + DMA_AXI_BUS_MODE);
70
48
}
+3
-27
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
+3
-27
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
···
18
18
static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
19
19
{
20
20
u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
21
-
int i;
22
21
23
22
pr_info("dwmac4: Master AXI performs %s burst length\n",
24
23
(value & DMA_SYS_BUS_FB) ? "fixed" : "any");
···
37
38
38
39
/* Depending on the UNDEF bit the Master AXI will perform any burst
39
40
* length according to the BLEN programmed (by default all BLEN are
40
-
* set).
41
+
* set). Note that the UNDEF bit is readonly, and is the inverse of
42
+
* Bus Mode bit 16.
41
43
*/
42
-
for (i = 0; i < AXI_BLEN; i++) {
43
-
switch (axi->axi_blen[i]) {
44
-
case 256:
45
-
value |= DMA_AXI_BLEN256;
46
-
break;
47
-
case 128:
48
-
value |= DMA_AXI_BLEN128;
49
-
break;
50
-
case 64:
51
-
value |= DMA_AXI_BLEN64;
52
-
break;
53
-
case 32:
54
-
value |= DMA_AXI_BLEN32;
55
-
break;
56
-
case 16:
57
-
value |= DMA_AXI_BLEN16;
58
-
break;
59
-
case 8:
60
-
value |= DMA_AXI_BLEN8;
61
-
break;
62
-
case 4:
63
-
value |= DMA_AXI_BLEN4;
64
-
break;
65
-
}
66
-
}
44
+
value = (value & ~DMA_AXI_BLEN_MASK) | axi->axi_blen_regval;
67
45
68
46
writel(value, ioaddr + DMA_SYS_BUS_MODE);
69
47
}
+1
-10
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
+1
-10
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
···
69
69
70
70
#define DMA_SYS_BUS_MB BIT(14)
71
71
#define DMA_AXI_1KBBE BIT(13)
72
-
#define DMA_SYS_BUS_AAL BIT(12)
72
+
#define DMA_SYS_BUS_AAL DMA_AXI_AAL
73
73
#define DMA_SYS_BUS_EAME BIT(11)
74
-
#define DMA_AXI_BLEN256 BIT(7)
75
-
#define DMA_AXI_BLEN128 BIT(6)
76
-
#define DMA_AXI_BLEN64 BIT(5)
77
-
#define DMA_AXI_BLEN32 BIT(4)
78
-
#define DMA_AXI_BLEN16 BIT(3)
79
-
#define DMA_AXI_BLEN8 BIT(2)
80
-
#define DMA_AXI_BLEN4 BIT(1)
81
74
#define DMA_SYS_BUS_FB BIT(0)
82
75
83
76
#define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
84
77
DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
85
78
DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
86
79
DMA_AXI_BLEN4)
87
-
88
-
#define DMA_AXI_BURST_LEN_MASK 0x000000FE
89
80
90
81
/* DMA TBS Control */
91
82
#define DMA_TBS_FTOS GENMASK(31, 8)
+2
-11
drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
+2
-11
drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
···
68
68
#define DMA_AXI_OSR_MAX 0xf
69
69
#define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
70
70
(DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
71
-
#define DMA_AXI_1KBBE BIT(13)
72
-
#define DMA_AXI_AAL BIT(12)
73
-
#define DMA_AXI_BLEN256 BIT(7)
74
-
#define DMA_AXI_BLEN128 BIT(6)
75
-
#define DMA_AXI_BLEN64 BIT(5)
76
-
#define DMA_AXI_BLEN32 BIT(4)
77
-
#define DMA_AXI_BLEN16 BIT(3)
78
-
#define DMA_AXI_BLEN8 BIT(2)
79
-
#define DMA_AXI_BLEN4 BIT(1)
80
71
#define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
81
72
DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
82
73
DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
83
74
DMA_AXI_BLEN4)
84
75
85
-
#define DMA_AXI_UNDEF BIT(0)
76
+
#define DMA_AXI_1KBBE BIT(13)
86
77
87
-
#define DMA_AXI_BURST_LEN_MASK 0x000000FE
78
+
#define DMA_AXI_UNDEF BIT(0)
88
79
89
80
#define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */
90
81
#define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */
+2
-9
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+2
-9
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
···
338
338
#define XGMAC_RD_OSR_LMT_SHIFT 16
339
339
#define XGMAC_EN_LPI BIT(15)
340
340
#define XGMAC_LPI_XIT_PKT BIT(14)
341
-
#define XGMAC_AAL BIT(12)
341
+
#define XGMAC_AAL DMA_AXI_AAL
342
342
#define XGMAC_EAME BIT(11)
343
-
#define XGMAC_BLEN GENMASK(7, 1)
344
-
#define XGMAC_BLEN256 BIT(7)
345
-
#define XGMAC_BLEN128 BIT(6)
346
-
#define XGMAC_BLEN64 BIT(5)
347
-
#define XGMAC_BLEN32 BIT(4)
348
-
#define XGMAC_BLEN16 BIT(3)
349
-
#define XGMAC_BLEN8 BIT(2)
350
-
#define XGMAC_BLEN4 BIT(1)
343
+
/* XGMAC_BLEN* are now defined as DMA_AXI_BLEN* in common.h */
351
344
#define XGMAC_UNDEF BIT(0)
352
345
#define XGMAC_TX_EDMA_CTRL 0x00003040
353
346
#define XGMAC_TDPS GENMASK(29, 0)
+6
-27
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
+6
-27
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
···
84
84
static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
85
85
{
86
86
u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
87
-
int i;
88
87
89
88
if (axi->axi_lpi_en)
90
89
value |= XGMAC_EN_LPI;
···
101
102
if (!axi->axi_fb)
102
103
value |= XGMAC_UNDEF;
103
104
104
-
value &= ~XGMAC_BLEN;
105
-
for (i = 0; i < AXI_BLEN; i++) {
106
-
switch (axi->axi_blen[i]) {
107
-
case 256:
108
-
value |= XGMAC_BLEN256;
109
-
break;
110
-
case 128:
111
-
value |= XGMAC_BLEN128;
112
-
break;
113
-
case 64:
114
-
value |= XGMAC_BLEN64;
115
-
break;
116
-
case 32:
117
-
value |= XGMAC_BLEN32;
118
-
break;
119
-
case 16:
120
-
value |= XGMAC_BLEN16;
121
-
break;
122
-
case 8:
123
-
value |= XGMAC_BLEN8;
124
-
break;
125
-
case 4:
126
-
value |= XGMAC_BLEN4;
127
-
break;
128
-
}
129
-
}
105
+
/* Depending on the UNDEF bit the Master AXI will perform any burst
106
+
* length according to the BLEN programmed (by default all BLEN are
107
+
* set). Note that the UNDEF bit is readonly, and is the inverse of
108
+
* Bus Mode bit 16.
109
+
*/
110
+
value = (value & ~DMA_AXI_BLEN_MASK) | axi->axi_blen_regval;
130
111
131
112
writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
132
113
writel(XGMAC_TDPS, ioaddr + XGMAC_TX_EDMA_CTRL);
+38
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+38
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
···
190
190
EXPORT_SYMBOL_GPL(stmmac_set_clk_tx_rate);
191
191
192
192
/**
193
+
* stmmac_axi_blen_to_mask() - convert a burst length array to reg value
194
+
* @regval: pointer to a u32 for the resulting register value
195
+
* @blen: pointer to an array of u32 containing the burst length values in bytes
196
+
* @len: the number of entries in the @blen array
197
+
*/
198
+
void stmmac_axi_blen_to_mask(u32 *regval, const u32 *blen, size_t len)
199
+
{
200
+
size_t i;
201
+
u32 val;
202
+
203
+
for (val = i = 0; i < len; i++) {
204
+
u32 burst = blen[i];
205
+
206
+
/* Burst values of zero must be skipped. */
207
+
if (!burst)
208
+
continue;
209
+
210
+
/* The valid range for the burst length is 4 to 256 inclusive,
211
+
* and it must be a power of two.
212
+
*/
213
+
if (burst < 4 || burst > 256 || !is_power_of_2(burst)) {
214
+
pr_err("stmmac: invalid burst length %u at index %zu\n",
215
+
burst, i);
216
+
continue;
217
+
}
218
+
219
+
/* Since burst is a power of two, and the register field starts
220
+
* with burst = 4, shift right by two bits so bit 0 of the field
221
+
* corresponds with the minimum value.
222
+
*/
223
+
val |= burst >> 2;
224
+
}
225
+
226
+
*regval = FIELD_PREP(DMA_AXI_BLEN_MASK, val);
227
+
}
228
+
EXPORT_SYMBOL_GPL(stmmac_axi_blen_to_mask);
229
+
230
+
/**
193
231
* stmmac_verify_args - verify the driver parameters.
194
232
* Description: it checks the driver parameters and set a default in case of
195
233
* errors.
+2
-4
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
+2
-4
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
···
92
92
plat->axi->axi_rd_osr_lmt = 31;
93
93
94
94
plat->axi->axi_fb = false;
95
-
plat->axi->axi_blen[0] = 4;
96
-
plat->axi->axi_blen[1] = 8;
97
-
plat->axi->axi_blen[2] = 16;
98
-
plat->axi->axi_blen[3] = 32;
95
+
plat->axi->axi_blen_regval = DMA_AXI_BLEN4 | DMA_AXI_BLEN8 |
96
+
DMA_AXI_BLEN16 | DMA_AXI_BLEN32;
99
97
100
98
return 0;
101
99
}
+3
-1
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+3
-1
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
···
95
95
{
96
96
struct device_node *np;
97
97
struct stmmac_axi *axi;
98
+
u32 axi_blen[AXI_BLEN];
98
99
99
100
np = of_parse_phandle(pdev->dev.of_node, "snps,axi-config", 0);
100
101
if (!np)
···
118
117
axi->axi_wr_osr_lmt = 1;
119
118
if (of_property_read_u32(np, "snps,rd_osr_lmt", &axi->axi_rd_osr_lmt))
120
119
axi->axi_rd_osr_lmt = 1;
121
-
of_property_read_u32_array(np, "snps,blen", axi->axi_blen, AXI_BLEN);
120
+
of_property_read_u32_array(np, "snps,blen", axi_blen, AXI_BLEN);
121
+
stmmac_axi_blen_to_mask(&axi->axi_blen_regval, axi_blen, AXI_BLEN);
122
122
of_node_put(np);
123
123
124
124
return axi;