tjh.dev / kernel
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drm/amdgpu: Add mp v15_0_8 ip headers v4

Add header files for mp v15_0_8 register offsets
and shift masks
v2: Update mp v15_0_8 ip headers
v3: Update mp v15_0_8 ip headers
v4: Clean up registers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Hawking Zhang and committed by
Alex Deucher 22ef3af5 0b8c6bcd

+1484
+868
drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_8_offset.h
··· 1 + /* 2 + * Copyright 2025 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + */ 23 + #ifndef _mp_15_0_8_OFFSET_HEADER 24 + #define _mp_15_0_8_OFFSET_HEADER 25 + 26 + 27 + 28 + // addressBlock: mp_SmuMp1_SmnDec 29 + // base address: 0x0 30 + #define regMP1_SMN_C2PMSG_0 0x0040 31 + #define regMP1_SMN_C2PMSG_0_BASE_IDX 2 32 + #define regMP1_SMN_C2PMSG_1 0x0041 33 + #define regMP1_SMN_C2PMSG_1_BASE_IDX 2 34 + #define regMP1_SMN_C2PMSG_2 0x0042 35 + #define regMP1_SMN_C2PMSG_2_BASE_IDX 2 36 + #define regMP1_SMN_C2PMSG_3 0x0043 37 + #define regMP1_SMN_C2PMSG_3_BASE_IDX 2 38 + #define regMP1_SMN_C2PMSG_4 0x0044 39 + #define regMP1_SMN_C2PMSG_4_BASE_IDX 2 40 + #define regMP1_SMN_C2PMSG_5 0x0045 41 + #define regMP1_SMN_C2PMSG_5_BASE_IDX 2 42 + #define regMP1_SMN_C2PMSG_6 0x0046 43 + #define regMP1_SMN_C2PMSG_6_BASE_IDX 2 44 + #define regMP1_SMN_C2PMSG_7 0x0047 45 + #define regMP1_SMN_C2PMSG_7_BASE_IDX 2 46 + #define regMP1_SMN_C2PMSG_8 0x0048 47 + #define regMP1_SMN_C2PMSG_8_BASE_IDX 2 48 + #define regMP1_SMN_C2PMSG_9 0x0049 49 + #define regMP1_SMN_C2PMSG_9_BASE_IDX 2 50 + #define regMP1_SMN_C2PMSG_10 0x004a 51 + #define regMP1_SMN_C2PMSG_10_BASE_IDX 2 52 + #define regMP1_SMN_C2PMSG_11 0x004b 53 + #define regMP1_SMN_C2PMSG_11_BASE_IDX 2 54 + #define regMP1_SMN_C2PMSG_12 0x004c 55 + #define regMP1_SMN_C2PMSG_12_BASE_IDX 2 56 + #define regMP1_SMN_C2PMSG_13 0x004d 57 + #define regMP1_SMN_C2PMSG_13_BASE_IDX 2 58 + #define regMP1_SMN_C2PMSG_14 0x004e 59 + #define regMP1_SMN_C2PMSG_14_BASE_IDX 2 60 + #define regMP1_SMN_C2PMSG_15 0x004f 61 + #define regMP1_SMN_C2PMSG_15_BASE_IDX 2 62 + #define regMP1_SMN_C2PMSG_16 0x0050 63 + #define regMP1_SMN_C2PMSG_16_BASE_IDX 2 64 + #define regMP1_SMN_C2PMSG_17 0x0051 65 + #define regMP1_SMN_C2PMSG_17_BASE_IDX 2 66 + #define regMP1_SMN_C2PMSG_18 0x0052 67 + #define regMP1_SMN_C2PMSG_18_BASE_IDX 2 68 + #define regMP1_SMN_C2PMSG_19 0x0053 69 + #define regMP1_SMN_C2PMSG_19_BASE_IDX 2 70 + #define regMP1_SMN_C2PMSG_20 0x0054 71 + #define regMP1_SMN_C2PMSG_20_BASE_IDX 2 72 + #define regMP1_SMN_C2PMSG_21 0x0055 73 + #define regMP1_SMN_C2PMSG_21_BASE_IDX 2 74 + #define regMP1_SMN_C2PMSG_22 0x0056 75 + #define regMP1_SMN_C2PMSG_22_BASE_IDX 2 76 + #define regMP1_SMN_C2PMSG_23 0x0057 77 + #define regMP1_SMN_C2PMSG_23_BASE_IDX 2 78 + #define regMP1_SMN_C2PMSG_24 0x0058 79 + #define regMP1_SMN_C2PMSG_24_BASE_IDX 2 80 + #define regMP1_SMN_C2PMSG_25 0x0059 81 + #define regMP1_SMN_C2PMSG_25_BASE_IDX 2 82 + #define regMP1_SMN_C2PMSG_26 0x005a 83 + #define regMP1_SMN_C2PMSG_26_BASE_IDX 2 84 + #define regMP1_SMN_C2PMSG_27 0x005b 85 + #define regMP1_SMN_C2PMSG_27_BASE_IDX 2 86 + #define regMP1_SMN_C2PMSG_28 0x005c 87 + #define regMP1_SMN_C2PMSG_28_BASE_IDX 2 88 + #define regMP1_SMN_C2PMSG_29 0x005d 89 + #define regMP1_SMN_C2PMSG_29_BASE_IDX 2 90 + #define regMP1_SMN_C2PMSG_30 0x005e 91 + #define regMP1_SMN_C2PMSG_30_BASE_IDX 2 92 + #define regMP1_SMN_C2PMSG_31 0x005f 93 + #define regMP1_SMN_C2PMSG_31_BASE_IDX 2 94 + #define regMP1_SMN_C2PMSG_32 0x0060 95 + #define regMP1_SMN_C2PMSG_32_BASE_IDX 2 96 + #define regMP1_SMN_C2PMSG_33 0x0061 97 + #define regMP1_SMN_C2PMSG_33_BASE_IDX 2 98 + #define regMP1_SMN_C2PMSG_34 0x0062 99 + #define regMP1_SMN_C2PMSG_34_BASE_IDX 2 100 + #define regMP1_SMN_C2PMSG_35 0x0063 101 + #define regMP1_SMN_C2PMSG_35_BASE_IDX 2 102 + #define regMP1_SMN_C2PMSG_36 0x0064 103 + #define regMP1_SMN_C2PMSG_36_BASE_IDX 2 104 + #define regMP1_SMN_C2PMSG_37 0x0065 105 + #define regMP1_SMN_C2PMSG_37_BASE_IDX 2 106 + #define regMP1_SMN_C2PMSG_38 0x0066 107 + #define regMP1_SMN_C2PMSG_38_BASE_IDX 2 108 + #define regMP1_SMN_C2PMSG_39 0x0067 109 + #define regMP1_SMN_C2PMSG_39_BASE_IDX 2 110 + #define regMP1_SMN_C2PMSG_40 0x0068 111 + #define regMP1_SMN_C2PMSG_40_BASE_IDX 2 112 + #define regMP1_SMN_C2PMSG_41 0x0069 113 + #define regMP1_SMN_C2PMSG_41_BASE_IDX 2 114 + #define regMP1_SMN_C2PMSG_42 0x006a 115 + #define regMP1_SMN_C2PMSG_42_BASE_IDX 2 116 + #define regMP1_SMN_C2PMSG_43 0x006b 117 + #define regMP1_SMN_C2PMSG_43_BASE_IDX 2 118 + #define regMP1_SMN_C2PMSG_44 0x006c 119 + #define regMP1_SMN_C2PMSG_44_BASE_IDX 2 120 + #define regMP1_SMN_C2PMSG_45 0x006d 121 + #define regMP1_SMN_C2PMSG_45_BASE_IDX 2 122 + #define regMP1_SMN_C2PMSG_46 0x006e 123 + #define regMP1_SMN_C2PMSG_46_BASE_IDX 2 124 + #define regMP1_SMN_C2PMSG_47 0x006f 125 + #define regMP1_SMN_C2PMSG_47_BASE_IDX 2 126 + #define regMP1_SMN_C2PMSG_48 0x0070 127 + #define regMP1_SMN_C2PMSG_48_BASE_IDX 2 128 + #define regMP1_SMN_C2PMSG_49 0x0071 129 + #define regMP1_SMN_C2PMSG_49_BASE_IDX 2 130 + #define regMP1_SMN_C2PMSG_50 0x0072 131 + #define regMP1_SMN_C2PMSG_50_BASE_IDX 2 132 + #define regMP1_SMN_C2PMSG_51 0x0073 133 + #define regMP1_SMN_C2PMSG_51_BASE_IDX 2 134 + #define regMP1_SMN_C2PMSG_52 0x0074 135 + #define regMP1_SMN_C2PMSG_52_BASE_IDX 2 136 + #define regMP1_SMN_C2PMSG_53 0x0075 137 + #define regMP1_SMN_C2PMSG_53_BASE_IDX 2 138 + #define regMP1_SMN_C2PMSG_54 0x0076 139 + #define regMP1_SMN_C2PMSG_54_BASE_IDX 2 140 + #define regMP1_SMN_C2PMSG_55 0x0077 141 + #define regMP1_SMN_C2PMSG_55_BASE_IDX 2 142 + #define regMP1_SMN_C2PMSG_56 0x0078 143 + #define regMP1_SMN_C2PMSG_56_BASE_IDX 2 144 + #define regMP1_SMN_C2PMSG_57 0x0079 145 + #define regMP1_SMN_C2PMSG_57_BASE_IDX 2 146 + #define regMP1_SMN_C2PMSG_58 0x007a 147 + #define regMP1_SMN_C2PMSG_58_BASE_IDX 2 148 + #define regMP1_SMN_C2PMSG_59 0x007b 149 + #define regMP1_SMN_C2PMSG_59_BASE_IDX 2 150 + #define regMP1_SMN_C2PMSG_60 0x007c 151 + #define regMP1_SMN_C2PMSG_60_BASE_IDX 2 152 + #define regMP1_SMN_C2PMSG_61 0x007d 153 + #define regMP1_SMN_C2PMSG_61_BASE_IDX 2 154 + #define regMP1_SMN_C2PMSG_62 0x007e 155 + #define regMP1_SMN_C2PMSG_62_BASE_IDX 2 156 + #define regMP1_SMN_C2PMSG_63 0x007f 157 + #define regMP1_SMN_C2PMSG_63_BASE_IDX 2 158 + #define regMP1_SMN_C2PMSG_64 0x0080 159 + #define regMP1_SMN_C2PMSG_64_BASE_IDX 2 160 + #define regMP1_SMN_C2PMSG_65 0x0081 161 + #define regMP1_SMN_C2PMSG_65_BASE_IDX 2 162 + #define regMP1_SMN_C2PMSG_66 0x0082 163 + #define regMP1_SMN_C2PMSG_66_BASE_IDX 2 164 + #define regMP1_SMN_C2PMSG_67 0x0083 165 + #define regMP1_SMN_C2PMSG_67_BASE_IDX 2 166 + #define regMP1_SMN_C2PMSG_68 0x0084 167 + #define regMP1_SMN_C2PMSG_68_BASE_IDX 2 168 + #define regMP1_SMN_C2PMSG_69 0x0085 169 + #define regMP1_SMN_C2PMSG_69_BASE_IDX 2 170 + #define regMP1_SMN_C2PMSG_70 0x0086 171 + #define regMP1_SMN_C2PMSG_70_BASE_IDX 2 172 + #define regMP1_SMN_C2PMSG_71 0x0087 173 + #define regMP1_SMN_C2PMSG_71_BASE_IDX 2 174 + #define regMP1_SMN_C2PMSG_72 0x0088 175 + #define regMP1_SMN_C2PMSG_72_BASE_IDX 2 176 + #define regMP1_SMN_C2PMSG_73 0x0089 177 + #define regMP1_SMN_C2PMSG_73_BASE_IDX 2 178 + #define regMP1_SMN_C2PMSG_74 0x008a 179 + #define regMP1_SMN_C2PMSG_74_BASE_IDX 2 180 + #define regMP1_SMN_C2PMSG_75 0x008b 181 + #define regMP1_SMN_C2PMSG_75_BASE_IDX 2 182 + #define regMP1_SMN_C2PMSG_76 0x008c 183 + #define regMP1_SMN_C2PMSG_76_BASE_IDX 2 184 + #define regMP1_SMN_C2PMSG_77 0x008d 185 + #define regMP1_SMN_C2PMSG_77_BASE_IDX 2 186 + #define regMP1_SMN_C2PMSG_78 0x008e 187 + #define regMP1_SMN_C2PMSG_78_BASE_IDX 2 188 + #define regMP1_SMN_C2PMSG_79 0x008f 189 + #define regMP1_SMN_C2PMSG_79_BASE_IDX 2 190 + #define regMP1_SMN_C2PMSG_80 0x0090 191 + #define regMP1_SMN_C2PMSG_80_BASE_IDX 2 192 + #define regMP1_SMN_C2PMSG_81 0x0091 193 + #define regMP1_SMN_C2PMSG_81_BASE_IDX 2 194 + #define regMP1_SMN_C2PMSG_82 0x0092 195 + #define regMP1_SMN_C2PMSG_82_BASE_IDX 2 196 + #define regMP1_SMN_C2PMSG_83 0x0093 197 + #define regMP1_SMN_C2PMSG_83_BASE_IDX 2 198 + #define regMP1_SMN_C2PMSG_84 0x0094 199 + #define regMP1_SMN_C2PMSG_84_BASE_IDX 2 200 + #define regMP1_SMN_C2PMSG_85 0x0095 201 + #define regMP1_SMN_C2PMSG_85_BASE_IDX 2 202 + #define regMP1_SMN_C2PMSG_86 0x0096 203 + #define regMP1_SMN_C2PMSG_86_BASE_IDX 2 204 + #define regMP1_SMN_C2PMSG_87 0x0097 205 + #define regMP1_SMN_C2PMSG_87_BASE_IDX 2 206 + #define regMP1_SMN_C2PMSG_88 0x0098 207 + #define regMP1_SMN_C2PMSG_88_BASE_IDX 2 208 + #define regMP1_SMN_C2PMSG_89 0x0099 209 + #define regMP1_SMN_C2PMSG_89_BASE_IDX 2 210 + #define regMP1_SMN_C2PMSG_90 0x009a 211 + #define regMP1_SMN_C2PMSG_90_BASE_IDX 2 212 + #define regMP1_SMN_C2PMSG_91 0x009b 213 + #define regMP1_SMN_C2PMSG_91_BASE_IDX 2 214 + #define regMP1_SMN_C2PMSG_92 0x009c 215 + #define regMP1_SMN_C2PMSG_92_BASE_IDX 2 216 + #define regMP1_SMN_C2PMSG_93 0x009d 217 + #define regMP1_SMN_C2PMSG_93_BASE_IDX 2 218 + #define regMP1_SMN_C2PMSG_94 0x009e 219 + #define regMP1_SMN_C2PMSG_94_BASE_IDX 2 220 + #define regMP1_SMN_C2PMSG_95 0x009f 221 + #define regMP1_SMN_C2PMSG_95_BASE_IDX 2 222 + #define regMP1_SMN_C2PMSG_96 0x00a0 223 + #define regMP1_SMN_C2PMSG_96_BASE_IDX 2 224 + #define regMP1_SMN_C2PMSG_97 0x00a1 225 + #define regMP1_SMN_C2PMSG_97_BASE_IDX 2 226 + #define regMP1_SMN_C2PMSG_98 0x00a2 227 + #define regMP1_SMN_C2PMSG_98_BASE_IDX 2 228 + #define regMP1_SMN_C2PMSG_99 0x00a3 229 + #define regMP1_SMN_C2PMSG_99_BASE_IDX 2 230 + #define regMP1_SMN_C2PMSG_100 0x00a4 231 + #define regMP1_SMN_C2PMSG_100_BASE_IDX 2 232 + #define regMP1_SMN_C2PMSG_101 0x00a5 233 + #define regMP1_SMN_C2PMSG_101_BASE_IDX 2 234 + #define regMP1_SMN_C2PMSG_102 0x00a6 235 + #define regMP1_SMN_C2PMSG_102_BASE_IDX 2 236 + #define regMP1_SMN_C2PMSG_103 0x00a7 237 + #define regMP1_SMN_C2PMSG_103_BASE_IDX 2 238 + #define regMP1_SMN_C2PMSG_104 0x00a8 239 + #define regMP1_SMN_C2PMSG_104_BASE_IDX 2 240 + #define regMP1_SMN_C2PMSG_105 0x00a9 241 + #define regMP1_SMN_C2PMSG_105_BASE_IDX 2 242 + #define regMP1_SMN_C2PMSG_106 0x00aa 243 + #define regMP1_SMN_C2PMSG_106_BASE_IDX 2 244 + #define regMP1_SMN_C2PMSG_107 0x00ab 245 + #define regMP1_SMN_C2PMSG_107_BASE_IDX 2 246 + #define regMP1_SMN_C2PMSG_108 0x00ac 247 + #define regMP1_SMN_C2PMSG_108_BASE_IDX 2 248 + #define regMP1_SMN_C2PMSG_109 0x00ad 249 + #define regMP1_SMN_C2PMSG_109_BASE_IDX 2 250 + #define regMP1_SMN_C2PMSG_110 0x00ae 251 + #define regMP1_SMN_C2PMSG_110_BASE_IDX 2 252 + #define regMP1_SMN_C2PMSG_111 0x00af 253 + #define regMP1_SMN_C2PMSG_111_BASE_IDX 2 254 + #define regMP1_SMN_C2PMSG_112 0x00b0 255 + #define regMP1_SMN_C2PMSG_112_BASE_IDX 2 256 + #define regMP1_SMN_C2PMSG_113 0x00b1 257 + #define regMP1_SMN_C2PMSG_113_BASE_IDX 2 258 + #define regMP1_SMN_C2PMSG_114 0x00b2 259 + #define regMP1_SMN_C2PMSG_114_BASE_IDX 2 260 + #define regMP1_SMN_C2PMSG_115 0x00b3 261 + #define regMP1_SMN_C2PMSG_115_BASE_IDX 2 262 + #define regMP1_SMN_C2PMSG_116 0x00b4 263 + #define regMP1_SMN_C2PMSG_116_BASE_IDX 2 264 + #define regMP1_SMN_C2PMSG_117 0x00b5 265 + #define regMP1_SMN_C2PMSG_117_BASE_IDX 2 266 + #define regMP1_SMN_C2PMSG_118 0x00b6 267 + #define regMP1_SMN_C2PMSG_118_BASE_IDX 2 268 + #define regMP1_SMN_C2PMSG_119 0x00b7 269 + #define regMP1_SMN_C2PMSG_119_BASE_IDX 2 270 + #define regMP1_SMN_C2PMSG_120 0x00b8 271 + #define regMP1_SMN_C2PMSG_120_BASE_IDX 2 272 + #define regMP1_SMN_C2PMSG_121 0x00b9 273 + #define regMP1_SMN_C2PMSG_121_BASE_IDX 2 274 + #define regMP1_SMN_C2PMSG_122 0x00ba 275 + #define regMP1_SMN_C2PMSG_122_BASE_IDX 2 276 + #define regMP1_SMN_C2PMSG_123 0x00bb 277 + #define regMP1_SMN_C2PMSG_123_BASE_IDX 2 278 + #define regMP1_SMN_C2PMSG_124 0x00bc 279 + #define regMP1_SMN_C2PMSG_124_BASE_IDX 2 280 + #define regMP1_SMN_C2PMSG_125 0x00bd 281 + #define regMP1_SMN_C2PMSG_125_BASE_IDX 2 282 + #define regMP1_SMN_C2PMSG_126 0x00be 283 + #define regMP1_SMN_C2PMSG_126_BASE_IDX 2 284 + #define regMP1_SMN_C2PMSG_127 0x00bf 285 + #define regMP1_SMN_C2PMSG_127_BASE_IDX 2 286 + #define regMP1_SMN_C2PMSG_128 0x00c0 287 + #define regMP1_SMN_C2PMSG_128_BASE_IDX 2 288 + #define regMP1_SMN_C2PMSG_129 0x00c1 289 + #define regMP1_SMN_C2PMSG_129_BASE_IDX 2 290 + #define regMP1_SMN_C2PMSG_130 0x00c2 291 + #define regMP1_SMN_C2PMSG_130_BASE_IDX 2 292 + #define regMP1_SMN_C2PMSG_131 0x00c3 293 + #define regMP1_SMN_C2PMSG_131_BASE_IDX 2 294 + #define regMP1_SMN_C2PMSG_132 0x00c4 295 + #define regMP1_SMN_C2PMSG_132_BASE_IDX 2 296 + #define regMP1_SMN_C2PMSG_133 0x00c5 297 + #define regMP1_SMN_C2PMSG_133_BASE_IDX 2 298 + #define regMP1_SMN_C2PMSG_134 0x00c6 299 + #define regMP1_SMN_C2PMSG_134_BASE_IDX 2 300 + #define regMP1_SMN_C2PMSG_135 0x00c7 301 + #define regMP1_SMN_C2PMSG_135_BASE_IDX 2 302 + #define regMP1_SMN_C2PMSG_136 0x00c8 303 + #define regMP1_SMN_C2PMSG_136_BASE_IDX 2 304 + #define regMP1_SMN_C2PMSG_137 0x00c9 305 + #define regMP1_SMN_C2PMSG_137_BASE_IDX 2 306 + #define regMP1_SMN_C2PMSG_138 0x00ca 307 + #define regMP1_SMN_C2PMSG_138_BASE_IDX 2 308 + #define regMP1_SMN_C2PMSG_139 0x00cb 309 + #define regMP1_SMN_C2PMSG_139_BASE_IDX 2 310 + #define regMP1_SMN_C2PMSG_140 0x00cc 311 + #define regMP1_SMN_C2PMSG_140_BASE_IDX 2 312 + #define regMP1_SMN_C2PMSG_141 0x00cd 313 + #define regMP1_SMN_C2PMSG_141_BASE_IDX 2 314 + #define regMP1_SMN_C2PMSG_142 0x00ce 315 + #define regMP1_SMN_C2PMSG_142_BASE_IDX 2 316 + #define regMP1_SMN_C2PMSG_143 0x00cf 317 + #define regMP1_SMN_C2PMSG_143_BASE_IDX 2 318 + #define regMP1_SMN_C2PMSG_144 0x00d0 319 + #define regMP1_SMN_C2PMSG_144_BASE_IDX 2 320 + #define regMP1_SMN_C2PMSG_145 0x00d1 321 + #define regMP1_SMN_C2PMSG_145_BASE_IDX 2 322 + #define regMP1_SMN_C2PMSG_146 0x00d2 323 + #define regMP1_SMN_C2PMSG_146_BASE_IDX 2 324 + #define regMP1_SMN_C2PMSG_147 0x00d3 325 + #define regMP1_SMN_C2PMSG_147_BASE_IDX 2 326 + #define regMP1_SMN_C2PMSG_148 0x00d4 327 + #define regMP1_SMN_C2PMSG_148_BASE_IDX 2 328 + #define regMP1_SMN_C2PMSG_149 0x00d5 329 + #define regMP1_SMN_C2PMSG_149_BASE_IDX 2 330 + #define regMP1_SMN_C2PMSG_150 0x00d6 331 + #define regMP1_SMN_C2PMSG_150_BASE_IDX 2 332 + #define regMP1_SMN_C2PMSG_151 0x00d7 333 + #define regMP1_SMN_C2PMSG_151_BASE_IDX 2 334 + #define regMP1_SMN_C2PMSG_152 0x00d8 335 + #define regMP1_SMN_C2PMSG_152_BASE_IDX 2 336 + #define regMP1_SMN_C2PMSG_153 0x00d9 337 + #define regMP1_SMN_C2PMSG_153_BASE_IDX 2 338 + #define regMP1_SMN_C2PMSG_154 0x00da 339 + #define regMP1_SMN_C2PMSG_154_BASE_IDX 2 340 + #define regMP1_SMN_C2PMSG_155 0x00db 341 + #define regMP1_SMN_C2PMSG_155_BASE_IDX 2 342 + #define regMP1_SMN_C2PMSG_156 0x00dc 343 + #define regMP1_SMN_C2PMSG_156_BASE_IDX 2 344 + #define regMP1_SMN_C2PMSG_157 0x00dd 345 + #define regMP1_SMN_C2PMSG_157_BASE_IDX 2 346 + #define regMP1_SMN_C2PMSG_158 0x00de 347 + #define regMP1_SMN_C2PMSG_158_BASE_IDX 2 348 + #define regMP1_SMN_C2PMSG_159 0x00df 349 + #define regMP1_SMN_C2PMSG_159_BASE_IDX 2 350 + #define regMP1_SMN_C2PMSG_160 0x00e0 351 + #define regMP1_SMN_C2PMSG_160_BASE_IDX 2 352 + #define regMP1_SMN_C2PMSG_161 0x00e1 353 + #define regMP1_SMN_C2PMSG_161_BASE_IDX 2 354 + #define regMP1_SMN_C2PMSG_162 0x00e2 355 + #define regMP1_SMN_C2PMSG_162_BASE_IDX 2 356 + #define regMP1_SMN_C2PMSG_163 0x00e3 357 + #define regMP1_SMN_C2PMSG_163_BASE_IDX 2 358 + #define regMP1_SMN_C2PMSG_164 0x00e4 359 + #define regMP1_SMN_C2PMSG_164_BASE_IDX 2 360 + #define regMP1_SMN_C2PMSG_165 0x00e5 361 + #define regMP1_SMN_C2PMSG_165_BASE_IDX 2 362 + #define regMP1_SMN_C2PMSG_166 0x00e6 363 + #define regMP1_SMN_C2PMSG_166_BASE_IDX 2 364 + #define regMP1_SMN_C2PMSG_167 0x00e7 365 + #define regMP1_SMN_C2PMSG_167_BASE_IDX 2 366 + #define regMP1_SMN_C2PMSG_168 0x00e8 367 + #define regMP1_SMN_C2PMSG_168_BASE_IDX 2 368 + #define regMP1_SMN_C2PMSG_169 0x00e9 369 + #define regMP1_SMN_C2PMSG_169_BASE_IDX 2 370 + #define regMP1_SMN_C2PMSG_170 0x00ea 371 + #define regMP1_SMN_C2PMSG_170_BASE_IDX 2 372 + #define regMP1_SMN_C2PMSG_171 0x00eb 373 + #define regMP1_SMN_C2PMSG_171_BASE_IDX 2 374 + #define regMP1_SMN_C2PMSG_172 0x00ec 375 + #define regMP1_SMN_C2PMSG_172_BASE_IDX 2 376 + #define regMP1_SMN_C2PMSG_173 0x00ed 377 + #define regMP1_SMN_C2PMSG_173_BASE_IDX 2 378 + #define regMP1_SMN_C2PMSG_174 0x00ee 379 + #define regMP1_SMN_C2PMSG_174_BASE_IDX 2 380 + #define regMP1_SMN_C2PMSG_175 0x00ef 381 + #define regMP1_SMN_C2PMSG_175_BASE_IDX 2 382 + #define regMP1_SMN_IH_CREDIT 0x0140 383 + #define regMP1_SMN_IH_CREDIT_BASE_IDX 2 384 + #define regMP1_SMN_IH_SW_INT 0x0141 385 + #define regMP1_SMN_IH_SW_INT_BASE_IDX 2 386 + #define regMP1_SMN_IH_SW_INT_CTRL 0x0142 387 + #define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 2 388 + #define regMP1_SMN_FPS_CNT 0x0143 389 + #define regMP1_SMN_FPS_CNT_BASE_IDX 2 390 + #define regMP1_SMN_PUB_CTRL 0x0144 391 + #define regMP1_SMN_PUB_CTRL_BASE_IDX 2 392 + #define regMP1_SMN_EXT_SCRATCH0 0x01c0 393 + #define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 2 394 + #define regMP1_SMN_EXT_SCRATCH1 0x01c1 395 + #define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 2 396 + #define regMP1_SMN_EXT_SCRATCH2 0x01c2 397 + #define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 2 398 + #define regMP1_SMN_EXT_SCRATCH3 0x01c3 399 + #define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 2 400 + #define regMP1_SMN_EXT_SCRATCH4 0x01c4 401 + #define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 2 402 + #define regMP1_SMN_EXT_SCRATCH5 0x01c5 403 + #define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 2 404 + #define regMP1_SMN_EXT_SCRATCH6 0x01c6 405 + #define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 2 406 + #define regMP1_SMN_EXT_SCRATCH7 0x01c7 407 + #define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 2 408 + #define regMP1_SMN_EXT_SCRATCH8 0x01c8 409 + #define regMP1_SMN_EXT_SCRATCH8_BASE_IDX 2 410 + #define regMP1_SMN_EXT_SCRATCH9 0x01c9 411 + #define regMP1_SMN_EXT_SCRATCH9_BASE_IDX 2 412 + #define regMP1_SMN_EXT_SCRATCH10 0x01ca 413 + #define regMP1_SMN_EXT_SCRATCH10_BASE_IDX 2 414 + #define regMP1_SMN_EXT_SCRATCH11 0x01cb 415 + #define regMP1_SMN_EXT_SCRATCH11_BASE_IDX 2 416 + #define regMP1_SMN_EXT_SCRATCH12 0x01cc 417 + #define regMP1_SMN_EXT_SCRATCH12_BASE_IDX 2 418 + #define regMP1_SMN_EXT_SCRATCH13 0x01cd 419 + #define regMP1_SMN_EXT_SCRATCH13_BASE_IDX 2 420 + #define regMP1_SMN_EXT_SCRATCH14 0x01ce 421 + #define regMP1_SMN_EXT_SCRATCH14_BASE_IDX 2 422 + #define regMP1_SMN_EXT_SCRATCH15 0x01cf 423 + #define regMP1_SMN_EXT_SCRATCH15_BASE_IDX 2 424 + #define regMP1_SMN_EXT_SCRATCH16 0x01d0 425 + #define regMP1_SMN_EXT_SCRATCH16_BASE_IDX 2 426 + #define regMP1_SMN_EXT_SCRATCH17 0x01d1 427 + #define regMP1_SMN_EXT_SCRATCH17_BASE_IDX 2 428 + #define regMP1_SMN_EXT_SCRATCH18 0x01d2 429 + #define regMP1_SMN_EXT_SCRATCH18_BASE_IDX 2 430 + #define regMP1_SMN_EXT_SCRATCH19 0x01d3 431 + #define regMP1_SMN_EXT_SCRATCH19_BASE_IDX 2 432 + #define regMP1_SMN_EXT_SCRATCH20 0x01d4 433 + #define regMP1_SMN_EXT_SCRATCH20_BASE_IDX 2 434 + #define regMP1_SMN_EXT_SCRATCH21 0x01d5 435 + #define regMP1_SMN_EXT_SCRATCH21_BASE_IDX 2 436 + #define regMP1_SMN_EXT_SCRATCH22 0x01d6 437 + #define regMP1_SMN_EXT_SCRATCH22_BASE_IDX 2 438 + #define regMP1_SMN_EXT_SCRATCH23 0x01d7 439 + #define regMP1_SMN_EXT_SCRATCH23_BASE_IDX 2 440 + #define regMP1_SMN_EXT_SCRATCH24 0x01d8 441 + #define regMP1_SMN_EXT_SCRATCH24_BASE_IDX 2 442 + #define regMP1_SMN_EXT_SCRATCH25 0x01d9 443 + #define regMP1_SMN_EXT_SCRATCH25_BASE_IDX 2 444 + #define regMP1_SMN_EXT_SCRATCH26 0x01da 445 + #define regMP1_SMN_EXT_SCRATCH26_BASE_IDX 2 446 + #define regMP1_SMN_EXT_SCRATCH27 0x01db 447 + #define regMP1_SMN_EXT_SCRATCH27_BASE_IDX 2 448 + #define regMP1_SMN_EXT_SCRATCH28 0x01dc 449 + #define regMP1_SMN_EXT_SCRATCH28_BASE_IDX 2 450 + #define regMP1_SMN_EXT_SCRATCH29 0x01dd 451 + #define regMP1_SMN_EXT_SCRATCH29_BASE_IDX 2 452 + #define regMP1_SMN_EXT_SCRATCH30 0x01de 453 + #define regMP1_SMN_EXT_SCRATCH30_BASE_IDX 2 454 + #define regMP1_SMN_EXT_SCRATCH31 0x01df 455 + #define regMP1_SMN_EXT_SCRATCH31_BASE_IDX 2 456 + 457 + 458 + // addressBlock: mp_SmuMpASP_SmnDec 459 + // base address: 0x0 460 + #define regMPASP_SMN_C2PMSG_0 0x0040 461 + #define regMPASP_SMN_C2PMSG_0_BASE_IDX 1 462 + #define regMPASP_SMN_C2PMSG_1 0x0041 463 + #define regMPASP_SMN_C2PMSG_1_BASE_IDX 1 464 + #define regMPASP_SMN_C2PMSG_2 0x0042 465 + #define regMPASP_SMN_C2PMSG_2_BASE_IDX 1 466 + #define regMPASP_SMN_C2PMSG_3 0x0043 467 + #define regMPASP_SMN_C2PMSG_3_BASE_IDX 1 468 + #define regMPASP_SMN_C2PMSG_4 0x0044 469 + #define regMPASP_SMN_C2PMSG_4_BASE_IDX 1 470 + #define regMPASP_SMN_C2PMSG_5 0x0045 471 + #define regMPASP_SMN_C2PMSG_5_BASE_IDX 1 472 + #define regMPASP_SMN_C2PMSG_6 0x0046 473 + #define regMPASP_SMN_C2PMSG_6_BASE_IDX 1 474 + #define regMPASP_SMN_C2PMSG_7 0x0047 475 + #define regMPASP_SMN_C2PMSG_7_BASE_IDX 1 476 + #define regMPASP_SMN_C2PMSG_8 0x0048 477 + #define regMPASP_SMN_C2PMSG_8_BASE_IDX 1 478 + #define regMPASP_SMN_C2PMSG_9 0x0049 479 + #define regMPASP_SMN_C2PMSG_9_BASE_IDX 1 480 + #define regMPASP_SMN_C2PMSG_10 0x004a 481 + #define regMPASP_SMN_C2PMSG_10_BASE_IDX 1 482 + #define regMPASP_SMN_C2PMSG_11 0x004b 483 + #define regMPASP_SMN_C2PMSG_11_BASE_IDX 1 484 + #define regMPASP_SMN_C2PMSG_12 0x004c 485 + #define regMPASP_SMN_C2PMSG_12_BASE_IDX 1 486 + #define regMPASP_SMN_C2PMSG_13 0x004d 487 + #define regMPASP_SMN_C2PMSG_13_BASE_IDX 1 488 + #define regMPASP_SMN_C2PMSG_14 0x004e 489 + #define regMPASP_SMN_C2PMSG_14_BASE_IDX 1 490 + #define regMPASP_SMN_C2PMSG_15 0x004f 491 + #define regMPASP_SMN_C2PMSG_15_BASE_IDX 1 492 + #define regMPASP_SMN_C2PMSG_16 0x0050 493 + #define regMPASP_SMN_C2PMSG_16_BASE_IDX 1 494 + #define regMPASP_SMN_C2PMSG_17 0x0051 495 + #define regMPASP_SMN_C2PMSG_17_BASE_IDX 1 496 + #define regMPASP_SMN_C2PMSG_18 0x0052 497 + #define regMPASP_SMN_C2PMSG_18_BASE_IDX 1 498 + #define regMPASP_SMN_C2PMSG_19 0x0053 499 + #define regMPASP_SMN_C2PMSG_19_BASE_IDX 1 500 + #define regMPASP_SMN_C2PMSG_20 0x0054 501 + #define regMPASP_SMN_C2PMSG_20_BASE_IDX 1 502 + #define regMPASP_SMN_C2PMSG_21 0x0055 503 + #define regMPASP_SMN_C2PMSG_21_BASE_IDX 1 504 + #define regMPASP_SMN_C2PMSG_22 0x0056 505 + #define regMPASP_SMN_C2PMSG_22_BASE_IDX 1 506 + #define regMPASP_SMN_C2PMSG_23 0x0057 507 + #define regMPASP_SMN_C2PMSG_23_BASE_IDX 1 508 + #define regMPASP_SMN_C2PMSG_24 0x0058 509 + #define regMPASP_SMN_C2PMSG_24_BASE_IDX 1 510 + #define regMPASP_SMN_C2PMSG_25 0x0059 511 + #define regMPASP_SMN_C2PMSG_25_BASE_IDX 1 512 + #define regMPASP_SMN_C2PMSG_26 0x005a 513 + #define regMPASP_SMN_C2PMSG_26_BASE_IDX 1 514 + #define regMPASP_SMN_C2PMSG_27 0x005b 515 + #define regMPASP_SMN_C2PMSG_27_BASE_IDX 1 516 + #define regMPASP_SMN_C2PMSG_28 0x005c 517 + #define regMPASP_SMN_C2PMSG_28_BASE_IDX 1 518 + #define regMPASP_SMN_C2PMSG_29 0x005d 519 + #define regMPASP_SMN_C2PMSG_29_BASE_IDX 1 520 + #define regMPASP_SMN_C2PMSG_30 0x005e 521 + #define regMPASP_SMN_C2PMSG_30_BASE_IDX 1 522 + #define regMPASP_SMN_C2PMSG_31 0x005f 523 + #define regMPASP_SMN_C2PMSG_31_BASE_IDX 1 524 + #define regMPASP_SMN_C2PMSG_32 0x0060 525 + #define regMPASP_SMN_C2PMSG_32_BASE_IDX 1 526 + #define regMPASP_SMN_C2PMSG_33 0x0061 527 + #define regMPASP_SMN_C2PMSG_33_BASE_IDX 1 528 + #define regMPASP_SMN_C2PMSG_34 0x0062 529 + #define regMPASP_SMN_C2PMSG_34_BASE_IDX 1 530 + #define regMPASP_SMN_C2PMSG_35 0x0063 531 + #define regMPASP_SMN_C2PMSG_35_BASE_IDX 1 532 + #define regMPASP_SMN_C2PMSG_36 0x0064 533 + #define regMPASP_SMN_C2PMSG_36_BASE_IDX 1 534 + #define regMPASP_SMN_C2PMSG_37 0x0065 535 + #define regMPASP_SMN_C2PMSG_37_BASE_IDX 1 536 + #define regMPASP_SMN_C2PMSG_38 0x0066 537 + #define regMPASP_SMN_C2PMSG_38_BASE_IDX 1 538 + #define regMPASP_SMN_C2PMSG_39 0x0067 539 + #define regMPASP_SMN_C2PMSG_39_BASE_IDX 1 540 + #define regMPASP_SMN_C2PMSG_40 0x0068 541 + #define regMPASP_SMN_C2PMSG_40_BASE_IDX 1 542 + #define regMPASP_SMN_C2PMSG_41 0x0069 543 + #define regMPASP_SMN_C2PMSG_41_BASE_IDX 1 544 + #define regMPASP_SMN_C2PMSG_42 0x006a 545 + #define regMPASP_SMN_C2PMSG_42_BASE_IDX 1 546 + #define regMPASP_SMN_C2PMSG_43 0x006b 547 + #define regMPASP_SMN_C2PMSG_43_BASE_IDX 1 548 + #define regMPASP_SMN_C2PMSG_44 0x006c 549 + #define regMPASP_SMN_C2PMSG_44_BASE_IDX 1 550 + #define regMPASP_SMN_C2PMSG_45 0x006d 551 + #define regMPASP_SMN_C2PMSG_45_BASE_IDX 1 552 + #define regMPASP_SMN_C2PMSG_46 0x006e 553 + #define regMPASP_SMN_C2PMSG_46_BASE_IDX 1 554 + #define regMPASP_SMN_C2PMSG_47 0x006f 555 + #define regMPASP_SMN_C2PMSG_47_BASE_IDX 1 556 + #define regMPASP_SMN_C2PMSG_48 0x0070 557 + #define regMPASP_SMN_C2PMSG_48_BASE_IDX 1 558 + #define regMPASP_SMN_C2PMSG_49 0x0071 559 + #define regMPASP_SMN_C2PMSG_49_BASE_IDX 1 560 + #define regMPASP_SMN_C2PMSG_50 0x0072 561 + #define regMPASP_SMN_C2PMSG_50_BASE_IDX 1 562 + #define regMPASP_SMN_C2PMSG_51 0x0073 563 + #define regMPASP_SMN_C2PMSG_51_BASE_IDX 1 564 + #define regMPASP_SMN_C2PMSG_52 0x0074 565 + #define regMPASP_SMN_C2PMSG_52_BASE_IDX 1 566 + #define regMPASP_SMN_C2PMSG_53 0x0075 567 + #define regMPASP_SMN_C2PMSG_53_BASE_IDX 1 568 + #define regMPASP_SMN_C2PMSG_54 0x0076 569 + #define regMPASP_SMN_C2PMSG_54_BASE_IDX 1 570 + #define regMPASP_SMN_C2PMSG_55 0x0077 571 + #define regMPASP_SMN_C2PMSG_55_BASE_IDX 1 572 + #define regMPASP_SMN_C2PMSG_56 0x0078 573 + #define regMPASP_SMN_C2PMSG_56_BASE_IDX 1 574 + #define regMPASP_SMN_C2PMSG_57 0x0079 575 + #define regMPASP_SMN_C2PMSG_57_BASE_IDX 1 576 + #define regMPASP_SMN_C2PMSG_58 0x007a 577 + #define regMPASP_SMN_C2PMSG_58_BASE_IDX 1 578 + #define regMPASP_SMN_C2PMSG_59 0x007b 579 + #define regMPASP_SMN_C2PMSG_59_BASE_IDX 1 580 + #define regMPASP_SMN_C2PMSG_60 0x007c 581 + #define regMPASP_SMN_C2PMSG_60_BASE_IDX 1 582 + #define regMPASP_SMN_C2PMSG_61 0x007d 583 + #define regMPASP_SMN_C2PMSG_61_BASE_IDX 1 584 + #define regMPASP_SMN_C2PMSG_62 0x007e 585 + #define regMPASP_SMN_C2PMSG_62_BASE_IDX 1 586 + #define regMPASP_SMN_C2PMSG_63 0x007f 587 + #define regMPASP_SMN_C2PMSG_63_BASE_IDX 1 588 + #define regMPASP_SMN_C2PMSG_64 0x0080 589 + #define regMPASP_SMN_C2PMSG_64_BASE_IDX 1 590 + #define regMPASP_SMN_C2PMSG_65 0x0081 591 + #define regMPASP_SMN_C2PMSG_65_BASE_IDX 1 592 + #define regMPASP_SMN_C2PMSG_66 0x0082 593 + #define regMPASP_SMN_C2PMSG_66_BASE_IDX 1 594 + #define regMPASP_SMN_C2PMSG_67 0x0083 595 + #define regMPASP_SMN_C2PMSG_67_BASE_IDX 1 596 + #define regMPASP_SMN_C2PMSG_68 0x0084 597 + #define regMPASP_SMN_C2PMSG_68_BASE_IDX 1 598 + #define regMPASP_SMN_C2PMSG_69 0x0085 599 + #define regMPASP_SMN_C2PMSG_69_BASE_IDX 1 600 + #define regMPASP_SMN_C2PMSG_70 0x0086 601 + #define regMPASP_SMN_C2PMSG_70_BASE_IDX 1 602 + #define regMPASP_SMN_C2PMSG_71 0x0087 603 + #define regMPASP_SMN_C2PMSG_71_BASE_IDX 1 604 + #define regMPASP_SMN_C2PMSG_72 0x0088 605 + #define regMPASP_SMN_C2PMSG_72_BASE_IDX 1 606 + #define regMPASP_SMN_C2PMSG_73 0x0089 607 + #define regMPASP_SMN_C2PMSG_73_BASE_IDX 1 608 + #define regMPASP_SMN_C2PMSG_74 0x008a 609 + #define regMPASP_SMN_C2PMSG_74_BASE_IDX 1 610 + #define regMPASP_SMN_C2PMSG_75 0x008b 611 + #define regMPASP_SMN_C2PMSG_75_BASE_IDX 1 612 + #define regMPASP_SMN_C2PMSG_76 0x008c 613 + #define regMPASP_SMN_C2PMSG_76_BASE_IDX 1 614 + #define regMPASP_SMN_C2PMSG_77 0x008d 615 + #define regMPASP_SMN_C2PMSG_77_BASE_IDX 1 616 + #define regMPASP_SMN_C2PMSG_78 0x008e 617 + #define regMPASP_SMN_C2PMSG_78_BASE_IDX 1 618 + #define regMPASP_SMN_C2PMSG_79 0x008f 619 + #define regMPASP_SMN_C2PMSG_79_BASE_IDX 1 620 + #define regMPASP_SMN_C2PMSG_80 0x0090 621 + #define regMPASP_SMN_C2PMSG_80_BASE_IDX 1 622 + #define regMPASP_SMN_C2PMSG_81 0x0091 623 + #define regMPASP_SMN_C2PMSG_81_BASE_IDX 1 624 + #define regMPASP_SMN_C2PMSG_82 0x0092 625 + #define regMPASP_SMN_C2PMSG_82_BASE_IDX 1 626 + #define regMPASP_SMN_C2PMSG_83 0x0093 627 + #define regMPASP_SMN_C2PMSG_83_BASE_IDX 1 628 + #define regMPASP_SMN_C2PMSG_84 0x0094 629 + #define regMPASP_SMN_C2PMSG_84_BASE_IDX 1 630 + #define regMPASP_SMN_C2PMSG_85 0x0095 631 + #define regMPASP_SMN_C2PMSG_85_BASE_IDX 1 632 + #define regMPASP_SMN_C2PMSG_86 0x0096 633 + #define regMPASP_SMN_C2PMSG_86_BASE_IDX 1 634 + #define regMPASP_SMN_C2PMSG_87 0x0097 635 + #define regMPASP_SMN_C2PMSG_87_BASE_IDX 1 636 + #define regMPASP_SMN_C2PMSG_88 0x0098 637 + #define regMPASP_SMN_C2PMSG_88_BASE_IDX 1 638 + #define regMPASP_SMN_C2PMSG_89 0x0099 639 + #define regMPASP_SMN_C2PMSG_89_BASE_IDX 1 640 + #define regMPASP_SMN_C2PMSG_90 0x009a 641 + #define regMPASP_SMN_C2PMSG_90_BASE_IDX 1 642 + #define regMPASP_SMN_C2PMSG_91 0x009b 643 + #define regMPASP_SMN_C2PMSG_91_BASE_IDX 1 644 + #define regMPASP_SMN_C2PMSG_92 0x009c 645 + #define regMPASP_SMN_C2PMSG_92_BASE_IDX 1 646 + #define regMPASP_SMN_C2PMSG_93 0x009d 647 + #define regMPASP_SMN_C2PMSG_93_BASE_IDX 1 648 + #define regMPASP_SMN_C2PMSG_94 0x009e 649 + #define regMPASP_SMN_C2PMSG_94_BASE_IDX 1 650 + #define regMPASP_SMN_C2PMSG_95 0x009f 651 + #define regMPASP_SMN_C2PMSG_95_BASE_IDX 1 652 + #define regMPASP_SMN_C2PMSG_96 0x00a0 653 + #define regMPASP_SMN_C2PMSG_96_BASE_IDX 1 654 + #define regMPASP_SMN_C2PMSG_97 0x00a1 655 + #define regMPASP_SMN_C2PMSG_97_BASE_IDX 1 656 + #define regMPASP_SMN_C2PMSG_98 0x00a2 657 + #define regMPASP_SMN_C2PMSG_98_BASE_IDX 1 658 + #define regMPASP_SMN_C2PMSG_99 0x00a3 659 + #define regMPASP_SMN_C2PMSG_99_BASE_IDX 1 660 + #define regMPASP_SMN_C2PMSG_100 0x00a4 661 + #define regMPASP_SMN_C2PMSG_100_BASE_IDX 1 662 + #define regMPASP_SMN_C2PMSG_101 0x00a5 663 + #define regMPASP_SMN_C2PMSG_101_BASE_IDX 1 664 + #define regMPASP_SMN_C2PMSG_102 0x00a6 665 + #define regMPASP_SMN_C2PMSG_102_BASE_IDX 1 666 + #define regMPASP_SMN_C2PMSG_103 0x00a7 667 + #define regMPASP_SMN_C2PMSG_103_BASE_IDX 1 668 + #define regMPASP_SMN_C2PMSG_104 0x00a8 669 + #define regMPASP_SMN_C2PMSG_104_BASE_IDX 1 670 + #define regMPASP_SMN_C2PMSG_105 0x00a9 671 + #define regMPASP_SMN_C2PMSG_105_BASE_IDX 1 672 + #define regMPASP_SMN_C2PMSG_106 0x00aa 673 + #define regMPASP_SMN_C2PMSG_106_BASE_IDX 1 674 + #define regMPASP_SMN_C2PMSG_107 0x00ab 675 + #define regMPASP_SMN_C2PMSG_107_BASE_IDX 1 676 + #define regMPASP_SMN_C2PMSG_108 0x00ac 677 + #define regMPASP_SMN_C2PMSG_108_BASE_IDX 1 678 + #define regMPASP_SMN_C2PMSG_109 0x00ad 679 + #define regMPASP_SMN_C2PMSG_109_BASE_IDX 1 680 + #define regMPASP_SMN_C2PMSG_110 0x00ae 681 + #define regMPASP_SMN_C2PMSG_110_BASE_IDX 1 682 + #define regMPASP_SMN_C2PMSG_111 0x00af 683 + #define regMPASP_SMN_C2PMSG_111_BASE_IDX 1 684 + #define regMPASP_SMN_C2PMSG_112 0x00b0 685 + #define regMPASP_SMN_C2PMSG_112_BASE_IDX 1 686 + #define regMPASP_SMN_C2PMSG_113 0x00b1 687 + #define regMPASP_SMN_C2PMSG_113_BASE_IDX 1 688 + #define regMPASP_SMN_C2PMSG_114 0x00b2 689 + #define regMPASP_SMN_C2PMSG_114_BASE_IDX 1 690 + #define regMPASP_SMN_C2PMSG_115 0x00b3 691 + #define regMPASP_SMN_C2PMSG_115_BASE_IDX 1 692 + #define regMPASP_SMN_C2PMSG_116 0x00b4 693 + #define regMPASP_SMN_C2PMSG_116_BASE_IDX 1 694 + #define regMPASP_SMN_C2PMSG_117 0x00b5 695 + #define regMPASP_SMN_C2PMSG_117_BASE_IDX 1 696 + #define regMPASP_SMN_C2PMSG_118 0x00b6 697 + #define regMPASP_SMN_C2PMSG_118_BASE_IDX 1 698 + #define regMPASP_SMN_C2PMSG_119 0x00b7 699 + #define regMPASP_SMN_C2PMSG_119_BASE_IDX 1 700 + #define regMPASP_SMN_C2PMSG_120 0x00b8 701 + #define regMPASP_SMN_C2PMSG_120_BASE_IDX 1 702 + #define regMPASP_SMN_C2PMSG_121 0x00b9 703 + #define regMPASP_SMN_C2PMSG_121_BASE_IDX 1 704 + #define regMPASP_SMN_C2PMSG_122 0x00ba 705 + #define regMPASP_SMN_C2PMSG_122_BASE_IDX 1 706 + #define regMPASP_SMN_C2PMSG_123 0x00bb 707 + #define regMPASP_SMN_C2PMSG_123_BASE_IDX 1 708 + #define regMPASP_SMN_C2PMSG_124 0x00bc 709 + #define regMPASP_SMN_C2PMSG_124_BASE_IDX 1 710 + #define regMPASP_SMN_C2PMSG_125 0x00bd 711 + #define regMPASP_SMN_C2PMSG_125_BASE_IDX 1 712 + #define regMPASP_SMN_C2PMSG_126 0x00be 713 + #define regMPASP_SMN_C2PMSG_126_BASE_IDX 1 714 + #define regMPASP_SMN_C2PMSG_127 0x00bf 715 + #define regMPASP_SMN_C2PMSG_127_BASE_IDX 1 716 + #define regMPASP_SMN_C2PMSG_128 0x00c0 717 + #define regMPASP_SMN_C2PMSG_128_BASE_IDX 1 718 + #define regMPASP_SMN_C2PMSG_129 0x00c1 719 + #define regMPASP_SMN_C2PMSG_129_BASE_IDX 1 720 + #define regMPASP_SMN_C2PMSG_130 0x00c2 721 + #define regMPASP_SMN_C2PMSG_130_BASE_IDX 1 722 + #define regMPASP_SMN_C2PMSG_131 0x00c3 723 + #define regMPASP_SMN_C2PMSG_131_BASE_IDX 1 724 + #define regMPASP_SMN_C2PMSG_132 0x00c4 725 + #define regMPASP_SMN_C2PMSG_132_BASE_IDX 1 726 + #define regMPASP_SMN_C2PMSG_133 0x00c5 727 + #define regMPASP_SMN_C2PMSG_133_BASE_IDX 1 728 + #define regMPASP_SMN_C2PMSG_134 0x00c6 729 + #define regMPASP_SMN_C2PMSG_134_BASE_IDX 1 730 + #define regMPASP_SMN_C2PMSG_135 0x00c7 731 + #define regMPASP_SMN_C2PMSG_135_BASE_IDX 1 732 + #define regMPASP_SMN_C2PMSG_136 0x00c8 733 + #define regMPASP_SMN_C2PMSG_136_BASE_IDX 1 734 + #define regMPASP_SMN_C2PMSG_137 0x00c9 735 + #define regMPASP_SMN_C2PMSG_137_BASE_IDX 1 736 + #define regMPASP_SMN_C2PMSG_138 0x00ca 737 + #define regMPASP_SMN_C2PMSG_138_BASE_IDX 1 738 + #define regMPASP_SMN_C2PMSG_139 0x00cb 739 + #define regMPASP_SMN_C2PMSG_139_BASE_IDX 1 740 + #define regMPASP_SMN_C2PMSG_140 0x00cc 741 + #define regMPASP_SMN_C2PMSG_140_BASE_IDX 1 742 + #define regMPASP_SMN_C2PMSG_141 0x00cd 743 + #define regMPASP_SMN_C2PMSG_141_BASE_IDX 1 744 + #define regMPASP_SMN_C2PMSG_142 0x00ce 745 + #define regMPASP_SMN_C2PMSG_142_BASE_IDX 1 746 + #define regMPASP_SMN_C2PMSG_143 0x00cf 747 + #define regMPASP_SMN_C2PMSG_143_BASE_IDX 1 748 + #define regMPASP_SMN_C2PMSG_144 0x00d0 749 + #define regMPASP_SMN_C2PMSG_144_BASE_IDX 1 750 + #define regMPASP_SMN_C2PMSG_145 0x00d1 751 + #define regMPASP_SMN_C2PMSG_145_BASE_IDX 1 752 + #define regMPASP_SMN_C2PMSG_146 0x00d2 753 + #define regMPASP_SMN_C2PMSG_146_BASE_IDX 1 754 + #define regMPASP_SMN_C2PMSG_147 0x00d3 755 + #define regMPASP_SMN_C2PMSG_147_BASE_IDX 1 756 + #define regMPASP_SMN_C2PMSG_148 0x00d4 757 + #define regMPASP_SMN_C2PMSG_148_BASE_IDX 1 758 + #define regMPASP_SMN_C2PMSG_149 0x00d5 759 + #define regMPASP_SMN_C2PMSG_149_BASE_IDX 1 760 + #define regMPASP_SMN_C2PMSG_150 0x00d6 761 + #define regMPASP_SMN_C2PMSG_150_BASE_IDX 1 762 + #define regMPASP_SMN_C2PMSG_151 0x00d7 763 + #define regMPASP_SMN_C2PMSG_151_BASE_IDX 1 764 + #define regMPASP_SMN_C2PMSG_152 0x00d8 765 + #define regMPASP_SMN_C2PMSG_152_BASE_IDX 1 766 + #define regMPASP_SMN_C2PMSG_153 0x00d9 767 + #define regMPASP_SMN_C2PMSG_153_BASE_IDX 1 768 + #define regMPASP_SMN_C2PMSG_154 0x00da 769 + #define regMPASP_SMN_C2PMSG_154_BASE_IDX 1 770 + #define regMPASP_SMN_C2PMSG_155 0x00db 771 + #define regMPASP_SMN_C2PMSG_155_BASE_IDX 1 772 + #define regMPASP_SMN_C2PMSG_156 0x00dc 773 + #define regMPASP_SMN_C2PMSG_156_BASE_IDX 1 774 + #define regMPASP_SMN_C2PMSG_157 0x00dd 775 + #define regMPASP_SMN_C2PMSG_157_BASE_IDX 1 776 + #define regMPASP_SMN_C2PMSG_158 0x00de 777 + #define regMPASP_SMN_C2PMSG_158_BASE_IDX 1 778 + #define regMPASP_SMN_C2PMSG_159 0x00df 779 + #define regMPASP_SMN_C2PMSG_159_BASE_IDX 1 780 + #define regMPASP_SMN_C2PMSG_160 0x00e0 781 + #define regMPASP_SMN_C2PMSG_160_BASE_IDX 1 782 + #define regMPASP_SMN_C2PMSG_161 0x00e1 783 + #define regMPASP_SMN_C2PMSG_161_BASE_IDX 1 784 + #define regMPASP_SMN_C2PMSG_162 0x00e2 785 + #define regMPASP_SMN_C2PMSG_162_BASE_IDX 1 786 + #define regMPASP_SMN_C2PMSG_163 0x00e3 787 + #define regMPASP_SMN_C2PMSG_163_BASE_IDX 1 788 + #define regMPASP_SMN_C2PMSG_164 0x00e4 789 + #define regMPASP_SMN_C2PMSG_164_BASE_IDX 1 790 + #define regMPASP_SMN_C2PMSG_165 0x00e5 791 + #define regMPASP_SMN_C2PMSG_165_BASE_IDX 1 792 + #define regMPASP_SMN_C2PMSG_166 0x00e6 793 + #define regMPASP_SMN_C2PMSG_166_BASE_IDX 1 794 + #define regMPASP_SMN_C2PMSG_167 0x00e7 795 + #define regMPASP_SMN_C2PMSG_167_BASE_IDX 1 796 + #define regMPASP_SMN_C2PMSG_168 0x00e8 797 + #define regMPASP_SMN_C2PMSG_168_BASE_IDX 1 798 + #define regMPASP_SMN_C2PMSG_169 0x00e9 799 + #define regMPASP_SMN_C2PMSG_169_BASE_IDX 1 800 + #define regMPASP_SMN_C2PMSG_170 0x00ea 801 + #define regMPASP_SMN_C2PMSG_170_BASE_IDX 1 802 + #define regMPASP_SMN_C2PMSG_171 0x00eb 803 + #define regMPASP_SMN_C2PMSG_171_BASE_IDX 1 804 + #define regMPASP_SMN_C2PMSG_172 0x00ec 805 + #define regMPASP_SMN_C2PMSG_172_BASE_IDX 1 806 + #define regMPASP_SMN_C2PMSG_173 0x00ed 807 + #define regMPASP_SMN_C2PMSG_173_BASE_IDX 1 808 + #define regMPASP_SMN_C2PMSG_174 0x00ee 809 + #define regMPASP_SMN_C2PMSG_174_BASE_IDX 1 810 + #define regMPASP_SMN_C2PMSG_175 0x00ef 811 + #define regMPASP_SMN_C2PMSG_175_BASE_IDX 1 812 + #define regMPASP_SMN_IH_CREDIT 0x0140 813 + #define regMPASP_SMN_IH_CREDIT_BASE_IDX 1 814 + #define regMPASP_SMN_IH_SW_INT 0x0141 815 + #define regMPASP_SMN_IH_SW_INT_BASE_IDX 1 816 + #define regMPASP_SMN_IH_SW_INT_CTRL 0x0142 817 + #define regMPASP_SMN_IH_SW_INT_CTRL_BASE_IDX 1 818 + 819 + 820 + // addressBlock: mp_SmuMpRASPub_CruDec 821 + // base address: 0x0 822 + #define regMPRAS_CRU0_MPRAS_FIRMWARE_FLAGS 0xbeb009 823 + #define regMPRAS_CRU0_MPRAS_FIRMWARE_FLAGS_BASE_IDX 3 824 + 825 + 826 + // addressBlock: mp_SmuMpIFOEPub_CruDec 827 + // base address: 0x0 828 + #define regMPIFOE_CRU0_MPIFOE_FIRMWARE_FLAGS 0xbeb009 829 + #define regMPIFOE_CRU0_MPIFOE_FIRMWARE_FLAGS_BASE_IDX 3 830 + 831 + 832 + // addressBlock: mp_SmuMp1Pub_CruDec 833 + // base address: 0x0 834 + #define regMP1_CRU0_MP1_FIRMWARE_FLAGS 0xbeb009 835 + #define regMP1_CRU0_MP1_FIRMWARE_FLAGS_BASE_IDX 3 836 + 837 + 838 + // addressBlock: mp_SmuMpIOPub_CruDec 839 + // base address: 0x0 840 + #define regMPIO_CRU0_MPIO_FIRMWARE_FLAGS 0xbeb009 841 + #define regMPIO_CRU0_MPIO_FIRMWARE_FLAGS_BASE_IDX 3 842 + 843 + 844 + // addressBlock: MpRASMmioPublic_SmuMpRASPub_CruDec 845 + // base address: 0x3e00000 846 + #define regMPRAS_CRU1_MPRAS_FIRMWARE_FLAGS 0x4009 847 + #define regMPRAS_CRU1_MPRAS_FIRMWARE_FLAGS_BASE_IDX 9 848 + 849 + 850 + // addressBlock: MpIFoEMmioPublic_SmuMpIFOEPub_CruDec 851 + // base address: 0x49d00000 852 + #define regMPIFOE_CRU1_MPIFOE_FIRMWARE_FLAGS 0x4009 853 + #define regMPIFOE_CRU1_MPIFOE_FIRMWARE_FLAGS_BASE_IDX 26 854 + 855 + 856 + // addressBlock: Mp1MmioPublic_SmuMp1Pub_CruDec 857 + // base address: 0x3b00000 858 + #define regMP1_CRU1_MP1_FIRMWARE_FLAGS 0x4009 859 + #define regMP1_CRU1_MP1_FIRMWARE_FLAGS_BASE_IDX 6 860 + 861 + 862 + // addressBlock: MpIOMmioPublic_SmuMpIOPub_CruDec 863 + // base address: 0xc900000 864 + #define regMPIO_CRU1_MPIO_FIRMWARE_FLAGS 0x4009 865 + #define regMPIO_CRU1_MPIO_FIRMWARE_FLAGS_BASE_IDX 23 866 + 867 + 868 + #endif
+616
drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_8_sh_mask.h
··· 1 + /* 2 + * Copyright 2025 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + */ 23 + #ifndef _mp_15_0_8_SH_MASK_HEADER 24 + #define _mp_15_0_8_SH_MASK_HEADER 25 + 26 + 27 + // addressBlock: mp_SmuMp1_SmnDec 28 + //MP1_SMN_C2PMSG_0 29 + #define MP1_SMN_C2PMSG_0__CONTENT__SHIFT 0x0 30 + #define MP1_SMN_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL 31 + //MP1_SMN_C2PMSG_1 32 + #define MP1_SMN_C2PMSG_1__CONTENT__SHIFT 0x0 33 + #define MP1_SMN_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL 34 + //MP1_SMN_C2PMSG_2 35 + #define MP1_SMN_C2PMSG_2__CONTENT__SHIFT 0x0 36 + #define MP1_SMN_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL 37 + //MP1_SMN_C2PMSG_3 38 + #define MP1_SMN_C2PMSG_3__CONTENT__SHIFT 0x0 39 + #define MP1_SMN_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL 40 + //MP1_SMN_C2PMSG_4 41 + #define MP1_SMN_C2PMSG_4__CONTENT__SHIFT 0x0 42 + #define MP1_SMN_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL 43 + //MP1_SMN_C2PMSG_5 44 + #define MP1_SMN_C2PMSG_5__CONTENT__SHIFT 0x0 45 + #define MP1_SMN_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL 46 + //MP1_SMN_C2PMSG_6 47 + #define MP1_SMN_C2PMSG_6__CONTENT__SHIFT 0x0 48 + #define MP1_SMN_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL 49 + //MP1_SMN_C2PMSG_7 50 + #define MP1_SMN_C2PMSG_7__CONTENT__SHIFT 0x0 51 + #define MP1_SMN_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL 52 + //MP1_SMN_C2PMSG_8 53 + #define MP1_SMN_C2PMSG_8__CONTENT__SHIFT 0x0 54 + #define MP1_SMN_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL 55 + //MP1_SMN_C2PMSG_9 56 + #define MP1_SMN_C2PMSG_9__CONTENT__SHIFT 0x0 57 + #define MP1_SMN_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL 58 + //MP1_SMN_C2PMSG_10 59 + #define MP1_SMN_C2PMSG_10__CONTENT__SHIFT 0x0 60 + #define MP1_SMN_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL 61 + //MP1_SMN_C2PMSG_11 62 + #define MP1_SMN_C2PMSG_11__CONTENT__SHIFT 0x0 63 + #define MP1_SMN_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL 64 + //MP1_SMN_C2PMSG_12 65 + #define MP1_SMN_C2PMSG_12__CONTENT__SHIFT 0x0 66 + #define MP1_SMN_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL 67 + //MP1_SMN_C2PMSG_13 68 + #define MP1_SMN_C2PMSG_13__CONTENT__SHIFT 0x0 69 + #define MP1_SMN_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL 70 + //MP1_SMN_C2PMSG_14 71 + #define MP1_SMN_C2PMSG_14__CONTENT__SHIFT 0x0 72 + #define MP1_SMN_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL 73 + //MP1_SMN_C2PMSG_15 74 + #define MP1_SMN_C2PMSG_15__CONTENT__SHIFT 0x0 75 + #define MP1_SMN_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL 76 + //MP1_SMN_C2PMSG_16 77 + #define MP1_SMN_C2PMSG_16__CONTENT__SHIFT 0x0 78 + #define MP1_SMN_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL 79 + //MP1_SMN_C2PMSG_17 80 + #define MP1_SMN_C2PMSG_17__CONTENT__SHIFT 0x0 81 + #define MP1_SMN_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL 82 + //MP1_SMN_C2PMSG_18 83 + #define MP1_SMN_C2PMSG_18__CONTENT__SHIFT 0x0 84 + #define MP1_SMN_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL 85 + //MP1_SMN_C2PMSG_19 86 + #define MP1_SMN_C2PMSG_19__CONTENT__SHIFT 0x0 87 + #define MP1_SMN_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL 88 + //MP1_SMN_C2PMSG_20 89 + #define MP1_SMN_C2PMSG_20__CONTENT__SHIFT 0x0 90 + #define MP1_SMN_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL 91 + //MP1_SMN_C2PMSG_21 92 + #define MP1_SMN_C2PMSG_21__CONTENT__SHIFT 0x0 93 + #define MP1_SMN_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL 94 + //MP1_SMN_C2PMSG_22 95 + #define MP1_SMN_C2PMSG_22__CONTENT__SHIFT 0x0 96 + #define MP1_SMN_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL 97 + //MP1_SMN_C2PMSG_23 98 + #define MP1_SMN_C2PMSG_23__CONTENT__SHIFT 0x0 99 + #define MP1_SMN_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL 100 + //MP1_SMN_C2PMSG_24 101 + #define MP1_SMN_C2PMSG_24__CONTENT__SHIFT 0x0 102 + #define MP1_SMN_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL 103 + //MP1_SMN_C2PMSG_25 104 + #define MP1_SMN_C2PMSG_25__CONTENT__SHIFT 0x0 105 + #define MP1_SMN_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL 106 + //MP1_SMN_C2PMSG_26 107 + #define MP1_SMN_C2PMSG_26__CONTENT__SHIFT 0x0 108 + #define MP1_SMN_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL 109 + //MP1_SMN_C2PMSG_27 110 + #define MP1_SMN_C2PMSG_27__CONTENT__SHIFT 0x0 111 + #define MP1_SMN_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL 112 + //MP1_SMN_C2PMSG_28 113 + #define MP1_SMN_C2PMSG_28__CONTENT__SHIFT 0x0 114 + #define MP1_SMN_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL 115 + //MP1_SMN_C2PMSG_29 116 + #define MP1_SMN_C2PMSG_29__CONTENT__SHIFT 0x0 117 + #define MP1_SMN_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL 118 + //MP1_SMN_C2PMSG_30 119 + #define MP1_SMN_C2PMSG_30__CONTENT__SHIFT 0x0 120 + #define MP1_SMN_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL 121 + //MP1_SMN_C2PMSG_31 122 + #define MP1_SMN_C2PMSG_31__CONTENT__SHIFT 0x0 123 + #define MP1_SMN_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL 124 + //MP1_SMN_C2PMSG_32 125 + #define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 126 + #define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 127 + //MP1_SMN_C2PMSG_33 128 + #define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 129 + #define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 130 + //MP1_SMN_C2PMSG_34 131 + #define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 132 + #define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 133 + //MP1_SMN_C2PMSG_35 134 + #define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 135 + #define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 136 + //MP1_SMN_C2PMSG_36 137 + #define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 138 + #define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 139 + //MP1_SMN_C2PMSG_37 140 + #define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 141 + #define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 142 + //MP1_SMN_C2PMSG_38 143 + #define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 144 + #define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 145 + //MP1_SMN_C2PMSG_39 146 + #define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 147 + #define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 148 + //MP1_SMN_C2PMSG_40 149 + #define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 150 + #define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 151 + //MP1_SMN_C2PMSG_41 152 + #define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 153 + #define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 154 + //MP1_SMN_C2PMSG_42 155 + #define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 156 + #define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 157 + //MP1_SMN_C2PMSG_43 158 + #define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 159 + #define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 160 + //MP1_SMN_C2PMSG_44 161 + #define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 162 + #define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 163 + //MP1_SMN_C2PMSG_45 164 + #define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 165 + #define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 166 + //MP1_SMN_C2PMSG_46 167 + #define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 168 + #define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 169 + //MP1_SMN_C2PMSG_47 170 + #define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 171 + #define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 172 + //MP1_SMN_C2PMSG_48 173 + #define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 174 + #define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 175 + //MP1_SMN_C2PMSG_49 176 + #define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 177 + #define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 178 + //MP1_SMN_C2PMSG_50 179 + #define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 180 + #define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 181 + //MP1_SMN_C2PMSG_51 182 + #define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 183 + #define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 184 + //MP1_SMN_C2PMSG_52 185 + #define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 186 + #define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 187 + //MP1_SMN_C2PMSG_53 188 + #define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 189 + #define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 190 + //MP1_SMN_C2PMSG_54 191 + #define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 192 + #define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 193 + //MP1_SMN_C2PMSG_55 194 + #define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 195 + #define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 196 + //MP1_SMN_C2PMSG_56 197 + #define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 198 + #define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 199 + //MP1_SMN_C2PMSG_57 200 + #define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 201 + #define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 202 + //MP1_SMN_C2PMSG_58 203 + #define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 204 + #define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 205 + //MP1_SMN_C2PMSG_59 206 + #define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 207 + #define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 208 + //MP1_SMN_C2PMSG_60 209 + #define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 210 + #define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 211 + //MP1_SMN_C2PMSG_61 212 + #define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 213 + #define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 214 + //MP1_SMN_C2PMSG_62 215 + #define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 216 + #define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 217 + //MP1_SMN_C2PMSG_63 218 + #define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 219 + #define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 220 + //MP1_SMN_C2PMSG_64 221 + #define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 222 + #define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 223 + //MP1_SMN_C2PMSG_65 224 + #define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 225 + #define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 226 + //MP1_SMN_C2PMSG_66 227 + #define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 228 + #define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 229 + //MP1_SMN_C2PMSG_67 230 + #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 231 + #define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 232 + //MP1_SMN_C2PMSG_68 233 + #define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 234 + #define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 235 + //MP1_SMN_C2PMSG_69 236 + #define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 237 + #define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 238 + //MP1_SMN_C2PMSG_70 239 + #define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 240 + #define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 241 + //MP1_SMN_C2PMSG_71 242 + #define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 243 + #define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 244 + //MP1_SMN_C2PMSG_72 245 + #define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 246 + #define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 247 + //MP1_SMN_C2PMSG_73 248 + #define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 249 + #define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 250 + //MP1_SMN_C2PMSG_74 251 + #define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 252 + #define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 253 + //MP1_SMN_C2PMSG_75 254 + #define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 255 + #define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 256 + //MP1_SMN_C2PMSG_76 257 + #define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 258 + #define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 259 + //MP1_SMN_C2PMSG_77 260 + #define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 261 + #define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 262 + //MP1_SMN_C2PMSG_78 263 + #define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 264 + #define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 265 + //MP1_SMN_C2PMSG_79 266 + #define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 267 + #define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 268 + //MP1_SMN_C2PMSG_80 269 + #define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 270 + #define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 271 + //MP1_SMN_C2PMSG_81 272 + #define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 273 + #define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 274 + //MP1_SMN_C2PMSG_82 275 + #define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 276 + #define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 277 + //MP1_SMN_C2PMSG_83 278 + #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 279 + #define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 280 + //MP1_SMN_C2PMSG_84 281 + #define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 282 + #define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 283 + //MP1_SMN_C2PMSG_85 284 + #define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 285 + #define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 286 + //MP1_SMN_C2PMSG_86 287 + #define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 288 + #define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 289 + //MP1_SMN_C2PMSG_87 290 + #define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 291 + #define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 292 + //MP1_SMN_C2PMSG_88 293 + #define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 294 + #define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 295 + //MP1_SMN_C2PMSG_89 296 + #define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 297 + #define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 298 + //MP1_SMN_C2PMSG_90 299 + #define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 300 + #define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 301 + //MP1_SMN_C2PMSG_91 302 + #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 303 + #define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 304 + //MP1_SMN_C2PMSG_92 305 + #define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 306 + #define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 307 + //MP1_SMN_C2PMSG_93 308 + #define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 309 + #define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 310 + //MP1_SMN_C2PMSG_94 311 + #define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 312 + #define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 313 + //MP1_SMN_C2PMSG_95 314 + #define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 315 + #define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 316 + //MP1_SMN_C2PMSG_96 317 + #define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 318 + #define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 319 + //MP1_SMN_C2PMSG_97 320 + #define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 321 + #define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 322 + //MP1_SMN_C2PMSG_98 323 + #define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 324 + #define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 325 + //MP1_SMN_C2PMSG_99 326 + #define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 327 + #define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 328 + //MP1_SMN_C2PMSG_100 329 + #define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 330 + #define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 331 + //MP1_SMN_C2PMSG_101 332 + #define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 333 + #define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 334 + //MP1_SMN_C2PMSG_102 335 + #define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 336 + #define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 337 + //MP1_SMN_C2PMSG_103 338 + #define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 339 + #define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 340 + //MP1_SMN_C2PMSG_104 341 + #define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0 342 + #define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL 343 + //MP1_SMN_C2PMSG_105 344 + #define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0 345 + #define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL 346 + //MP1_SMN_C2PMSG_106 347 + #define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0 348 + #define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL 349 + //MP1_SMN_C2PMSG_107 350 + #define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0 351 + #define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL 352 + //MP1_SMN_C2PMSG_108 353 + #define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0 354 + #define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL 355 + //MP1_SMN_C2PMSG_109 356 + #define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0 357 + #define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL 358 + //MP1_SMN_C2PMSG_110 359 + #define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0 360 + #define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL 361 + //MP1_SMN_C2PMSG_111 362 + #define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0 363 + #define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL 364 + //MP1_SMN_C2PMSG_112 365 + #define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0 366 + #define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL 367 + //MP1_SMN_C2PMSG_113 368 + #define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0 369 + #define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL 370 + //MP1_SMN_C2PMSG_114 371 + #define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0 372 + #define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL 373 + //MP1_SMN_C2PMSG_115 374 + #define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0 375 + #define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL 376 + //MP1_SMN_C2PMSG_116 377 + #define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0 378 + #define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL 379 + //MP1_SMN_C2PMSG_117 380 + #define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0 381 + #define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL 382 + //MP1_SMN_C2PMSG_118 383 + #define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0 384 + #define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL 385 + //MP1_SMN_C2PMSG_119 386 + #define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0 387 + #define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL 388 + //MP1_SMN_C2PMSG_120 389 + #define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0 390 + #define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL 391 + //MP1_SMN_C2PMSG_121 392 + #define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0 393 + #define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL 394 + //MP1_SMN_C2PMSG_122 395 + #define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0 396 + #define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL 397 + //MP1_SMN_C2PMSG_123 398 + #define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0 399 + #define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL 400 + //MP1_SMN_C2PMSG_124 401 + #define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0 402 + #define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL 403 + //MP1_SMN_C2PMSG_125 404 + #define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0 405 + #define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL 406 + //MP1_SMN_C2PMSG_126 407 + #define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0 408 + #define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL 409 + //MP1_SMN_C2PMSG_127 410 + #define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0 411 + #define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL 412 + //MP1_SMN_IH_CREDIT 413 + #define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 414 + #define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 415 + #define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 416 + #define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 417 + //MP1_SMN_IH_SW_INT 418 + #define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 419 + #define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 420 + #define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL 421 + #define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L 422 + //MP1_SMN_IH_SW_INT_CTRL 423 + #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 424 + #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 425 + #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 426 + #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 427 + //MP1_SMN_FPS_CNT 428 + #define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 429 + #define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL 430 + //MP1_SMN_PUB_CTRL 431 + #define MP1_SMN_PUB_CTRL__LX3_RESET__SHIFT 0x0 432 + #define MP1_SMN_PUB_CTRL__LX3_RESET_MASK 0x00000001L 433 + //MP1_SMN_EXT_SCRATCH0 434 + #define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 435 + #define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL 436 + //MP1_SMN_EXT_SCRATCH1 437 + #define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 438 + #define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL 439 + //MP1_SMN_EXT_SCRATCH2 440 + #define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 441 + #define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL 442 + //MP1_SMN_EXT_SCRATCH3 443 + #define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 444 + #define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL 445 + //MP1_SMN_EXT_SCRATCH4 446 + #define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 447 + #define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL 448 + //MP1_SMN_EXT_SCRATCH5 449 + #define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 450 + #define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL 451 + //MP1_SMN_EXT_SCRATCH6 452 + #define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 453 + #define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL 454 + //MP1_SMN_EXT_SCRATCH7 455 + #define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 456 + #define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL 457 + //MP1_SMN_EXT_SCRATCH8 458 + #define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0 459 + #define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL 460 + //MP1_SMN_EXT_SCRATCH9 461 + #define MP1_SMN_EXT_SCRATCH9__DATA__SHIFT 0x0 462 + #define MP1_SMN_EXT_SCRATCH9__DATA_MASK 0xFFFFFFFFL 463 + //MP1_SMN_EXT_SCRATCH10 464 + #define MP1_SMN_EXT_SCRATCH10__DATA__SHIFT 0x0 465 + #define MP1_SMN_EXT_SCRATCH10__DATA_MASK 0xFFFFFFFFL 466 + //MP1_SMN_EXT_SCRATCH11 467 + #define MP1_SMN_EXT_SCRATCH11__DATA__SHIFT 0x0 468 + #define MP1_SMN_EXT_SCRATCH11__DATA_MASK 0xFFFFFFFFL 469 + //MP1_SMN_EXT_SCRATCH12 470 + #define MP1_SMN_EXT_SCRATCH12__DATA__SHIFT 0x0 471 + #define MP1_SMN_EXT_SCRATCH12__DATA_MASK 0xFFFFFFFFL 472 + //MP1_SMN_EXT_SCRATCH13 473 + #define MP1_SMN_EXT_SCRATCH13__DATA__SHIFT 0x0 474 + #define MP1_SMN_EXT_SCRATCH13__DATA_MASK 0xFFFFFFFFL 475 + //MP1_SMN_EXT_SCRATCH14 476 + #define MP1_SMN_EXT_SCRATCH14__DATA__SHIFT 0x0 477 + #define MP1_SMN_EXT_SCRATCH14__DATA_MASK 0xFFFFFFFFL 478 + //MP1_SMN_EXT_SCRATCH15 479 + #define MP1_SMN_EXT_SCRATCH15__DATA__SHIFT 0x0 480 + #define MP1_SMN_EXT_SCRATCH15__DATA_MASK 0xFFFFFFFFL 481 + //MP1_SMN_EXT_SCRATCH16 482 + #define MP1_SMN_EXT_SCRATCH16__DATA__SHIFT 0x0 483 + #define MP1_SMN_EXT_SCRATCH16__DATA_MASK 0xFFFFFFFFL 484 + //MP1_SMN_EXT_SCRATCH17 485 + #define MP1_SMN_EXT_SCRATCH17__DATA__SHIFT 0x0 486 + #define MP1_SMN_EXT_SCRATCH17__DATA_MASK 0xFFFFFFFFL 487 + //MP1_SMN_EXT_SCRATCH18 488 + #define MP1_SMN_EXT_SCRATCH18__DATA__SHIFT 0x0 489 + #define MP1_SMN_EXT_SCRATCH18__DATA_MASK 0xFFFFFFFFL 490 + //MP1_SMN_EXT_SCRATCH19 491 + #define MP1_SMN_EXT_SCRATCH19__DATA__SHIFT 0x0 492 + #define MP1_SMN_EXT_SCRATCH19__DATA_MASK 0xFFFFFFFFL 493 + //MP1_SMN_EXT_SCRATCH20 494 + #define MP1_SMN_EXT_SCRATCH20__DATA__SHIFT 0x0 495 + #define MP1_SMN_EXT_SCRATCH20__DATA_MASK 0xFFFFFFFFL 496 + //MP1_SMN_EXT_SCRATCH21 497 + #define MP1_SMN_EXT_SCRATCH21__DATA__SHIFT 0x0 498 + #define MP1_SMN_EXT_SCRATCH21__DATA_MASK 0xFFFFFFFFL 499 + //MP1_SMN_EXT_SCRATCH22 500 + #define MP1_SMN_EXT_SCRATCH22__DATA__SHIFT 0x0 501 + #define MP1_SMN_EXT_SCRATCH22__DATA_MASK 0xFFFFFFFFL 502 + //MP1_SMN_EXT_SCRATCH23 503 + #define MP1_SMN_EXT_SCRATCH23__DATA__SHIFT 0x0 504 + #define MP1_SMN_EXT_SCRATCH23__DATA_MASK 0xFFFFFFFFL 505 + //MP1_SMN_EXT_SCRATCH24 506 + #define MP1_SMN_EXT_SCRATCH24__DATA__SHIFT 0x0 507 + #define MP1_SMN_EXT_SCRATCH24__DATA_MASK 0xFFFFFFFFL 508 + //MP1_SMN_EXT_SCRATCH25 509 + #define MP1_SMN_EXT_SCRATCH25__DATA__SHIFT 0x0 510 + #define MP1_SMN_EXT_SCRATCH25__DATA_MASK 0xFFFFFFFFL 511 + //MP1_SMN_EXT_SCRATCH26 512 + #define MP1_SMN_EXT_SCRATCH26__DATA__SHIFT 0x0 513 + #define MP1_SMN_EXT_SCRATCH26__DATA_MASK 0xFFFFFFFFL 514 + //MP1_SMN_EXT_SCRATCH27 515 + #define MP1_SMN_EXT_SCRATCH27__DATA__SHIFT 0x0 516 + #define MP1_SMN_EXT_SCRATCH27__DATA_MASK 0xFFFFFFFFL 517 + //MP1_SMN_EXT_SCRATCH28 518 + #define MP1_SMN_EXT_SCRATCH28__DATA__SHIFT 0x0 519 + #define MP1_SMN_EXT_SCRATCH28__DATA_MASK 0xFFFFFFFFL 520 + //MP1_SMN_EXT_SCRATCH29 521 + #define MP1_SMN_EXT_SCRATCH29__DATA__SHIFT 0x0 522 + #define MP1_SMN_EXT_SCRATCH29__DATA_MASK 0xFFFFFFFFL 523 + //MP1_SMN_EXT_SCRATCH30 524 + #define MP1_SMN_EXT_SCRATCH30__DATA__SHIFT 0x0 525 + #define MP1_SMN_EXT_SCRATCH30__DATA_MASK 0xFFFFFFFFL 526 + //MP1_SMN_EXT_SCRATCH31 527 + #define MP1_SMN_EXT_SCRATCH31__DATA__SHIFT 0x0 528 + #define MP1_SMN_EXT_SCRATCH31__DATA_MASK 0xFFFFFFFFL 529 + 530 + 531 + // addressBlock: mp_SmuMpASP_SmnDec 532 + //MPASP_SMN_C2PMSG_81 533 + #define MPASP_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 534 + #define MPASP_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 535 + //MPASP_SMN_IH_CREDIT 536 + #define MPASP_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 537 + #define MPASP_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 538 + #define MPASP_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 539 + #define MPASP_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 540 + //MPASP_SMN_IH_SW_INT 541 + #define MPASP_SMN_IH_SW_INT__ID__SHIFT 0x0 542 + #define MPASP_SMN_IH_SW_INT__VALID__SHIFT 0x8 543 + #define MPASP_SMN_IH_SW_INT__ID_MASK 0x000000FFL 544 + #define MPASP_SMN_IH_SW_INT__VALID_MASK 0x00000100L 545 + //MPASP_SMN_IH_SW_INT_CTRL 546 + #define MPASP_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 547 + #define MPASP_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 548 + #define MPASP_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 549 + #define MPASP_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 550 + 551 + 552 + // addressBlock: mp_SmuMpRASPub_CruDec 553 + //MPRAS_CRU0_MPRAS_FIRMWARE_FLAGS 554 + #define MPRAS_CRU0_MPRAS_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 555 + #define MPRAS_CRU0_MPRAS_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 556 + #define MPRAS_CRU0_MPRAS_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L 557 + #define MPRAS_CRU0_MPRAS_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL 558 + 559 + 560 + // addressBlock: mp_SmuMpIFOEPub_CruDec 561 + //MPIFOE_CRU0_MPIFOE_FIRMWARE_FLAGS 562 + #define MPIFOE_CRU0_MPIFOE_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 563 + #define MPIFOE_CRU0_MPIFOE_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 564 + #define MPIFOE_CRU0_MPIFOE_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L 565 + #define MPIFOE_CRU0_MPIFOE_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL 566 + 567 + 568 + // addressBlock: mp_SmuMp1Pub_CruDec 569 + //MP1_CRU0_MP1_FIRMWARE_FLAGS 570 + #define MP1_CRU0_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 571 + #define MP1_CRU0_MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 572 + #define MP1_CRU0_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L 573 + #define MP1_CRU0_MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL 574 + 575 + 576 + // addressBlock: mp_SmuMpIOPub_CruDec 577 + //MPIO_CRU0_MPIO_FIRMWARE_FLAGS 578 + #define MPIO_CRU0_MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 579 + #define MPIO_CRU0_MPIO_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 580 + #define MPIO_CRU0_MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L 581 + #define MPIO_CRU0_MPIO_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL 582 + 583 + 584 + // addressBlock: MpRASMmioPublic_SmuMpRASPub_CruDec 585 + //MPRAS_CRU1_MPRAS_FIRMWARE_FLAGS 586 + #define MPRAS_CRU1_MPRAS_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 587 + #define MPRAS_CRU1_MPRAS_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 588 + #define MPRAS_CRU1_MPRAS_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L 589 + #define MPRAS_CRU1_MPRAS_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL 590 + 591 + 592 + // addressBlock: MpIFoEMmioPublic_SmuMpIFOEPub_CruDec 593 + //MPIFOE_CRU1_MPIFOE_FIRMWARE_FLAGS 594 + #define MPIFOE_CRU1_MPIFOE_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 595 + #define MPIFOE_CRU1_MPIFOE_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 596 + #define MPIFOE_CRU1_MPIFOE_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L 597 + #define MPIFOE_CRU1_MPIFOE_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL 598 + 599 + 600 + // addressBlock: Mp1MmioPublic_SmuMp1Pub_CruDec 601 + //MP1_CRU1_MP1_FIRMWARE_FLAGS 602 + #define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 603 + #define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 604 + #define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L 605 + #define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL 606 + 607 + 608 + // addressBlock: MpIOMmioPublic_SmuMpIOPub_CruDec 609 + //MPIO_CRU1_MPIO_FIRMWARE_FLAGS 610 + #define MPIO_CRU1_MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 611 + #define MPIO_CRU1_MPIO_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 612 + #define MPIO_CRU1_MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L 613 + #define MPIO_CRU1_MPIO_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL 614 + 615 + 616 + #endif