Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'pci/enumeration'
- Skip enabling ExtTag on VFs since that bit is Reserved and causes
misleading log messages (Håkon Bugge)
- Mark 3ware-9650SA Root Port Extended Tags as broken since 9650SA can't
handle 8-bit tags (Jörg Wedekind)
- Release domain number from the correct IDA when a PCI host bridge has no
parent device (Sergey Shtylyov)
- Initialize endpoint Read Completion Boundary to match Root Port,
regardless of ACPI _HPX (Håkon Bugge)
- Apply _HPX PCIe Setting Record only to AER configuration, and only when
OS owns PCIe hotplug but not AER, to avoid clobbering Extended Tag and
Relaxed Ordering settings (Håkon Bugge)
- Clear PCIe Root Status register with a write, not a read/modify/write
(Lukas Wunner)
* pci/enumeration:
PCI/PME: Replace RMW of Root Status register with direct write
PCI/ACPI: Restrict program_hpx_type2() to AER bits
PCI: Initialize RCB from pci_configure_device()
PCI: Check parent for NULL in of_pci_bus_release_domain_nr()
PCI: Mark 3ware-9650SA Root Port Extended Tags as broken
PCI: Do not attempt to set ExtTag for VFs
+64
-41
+24
-35
drivers/pci/pci-acpi.c
+24
-35
drivers/pci/pci-acpi.c
···
271
271
return AE_OK;
272
272
}
273
273
274
-
static bool pcie_root_rcb_set(struct pci_dev *dev)
275
-
{
276
-
struct pci_dev *rp = pcie_find_root_port(dev);
277
-
u16 lnkctl;
278
-
279
-
if (!rp)
280
-
return false;
281
-
282
-
pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
283
-
if (lnkctl & PCI_EXP_LNKCTL_RCB)
284
-
return true;
285
-
286
-
return false;
287
-
}
288
-
289
274
/* _HPX PCI Express Setting Record (Type 2) */
290
275
struct hpx_type2 {
291
276
u32 revision;
···
296
311
{
297
312
int pos;
298
313
u32 reg32;
314
+
const struct pci_host_bridge *host;
299
315
300
316
if (!hpx)
301
317
return;
302
318
303
319
if (!pci_is_pcie(dev))
320
+
return;
321
+
322
+
host = pci_find_host_bridge(dev->bus);
323
+
324
+
/*
325
+
* Only do the _HPX Type 2 programming if OS owns PCIe native
326
+
* hotplug but not AER.
327
+
*/
328
+
if (!host->native_pcie_hotplug || host->native_aer)
304
329
return;
305
330
306
331
if (hpx->revision > 1) {
···
320
325
}
321
326
322
327
/*
323
-
* Don't allow _HPX to change MPS or MRRS settings. We manage
324
-
* those to make sure they're consistent with the rest of the
325
-
* platform.
328
+
* We only allow _HPX to program DEVCTL bits related to AER, namely
329
+
* PCI_EXP_DEVCTL_CERE, PCI_EXP_DEVCTL_NFERE, PCI_EXP_DEVCTL_FERE,
330
+
* and PCI_EXP_DEVCTL_URRE.
331
+
*
332
+
* The rest of DEVCTL is managed by the OS to make sure it's
333
+
* consistent with the rest of the platform.
326
334
*/
327
-
hpx->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
328
-
PCI_EXP_DEVCTL_READRQ;
329
-
hpx->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
330
-
PCI_EXP_DEVCTL_READRQ);
335
+
hpx->pci_exp_devctl_and |= ~PCI_EXP_AER_FLAGS;
336
+
hpx->pci_exp_devctl_or &= PCI_EXP_AER_FLAGS;
331
337
332
338
/* Initialize Device Control Register */
333
339
pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
334
340
~hpx->pci_exp_devctl_and, hpx->pci_exp_devctl_or);
335
341
336
-
/* Initialize Link Control Register */
342
+
/* Log if _HPX attempts to modify Link Control Register */
337
343
if (pcie_cap_has_lnkctl(dev)) {
338
-
339
-
/*
340
-
* If the Root Port supports Read Completion Boundary of
341
-
* 128, set RCB to 128. Otherwise, clear it.
342
-
*/
343
-
hpx->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
344
-
hpx->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
345
-
if (pcie_root_rcb_set(dev))
346
-
hpx->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
347
-
348
-
pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
349
-
~hpx->pci_exp_lnkctl_and, hpx->pci_exp_lnkctl_or);
344
+
if (hpx->pci_exp_lnkctl_and != 0xffff ||
345
+
hpx->pci_exp_lnkctl_or != 0)
346
+
pci_info(dev, "_HPX attempts Link Control setting (AND %#06x OR %#06x)\n",
347
+
hpx->pci_exp_lnkctl_and,
348
+
hpx->pci_exp_lnkctl_or);
350
349
}
351
350
352
351
/* Find Advanced Error Reporting Enhanced Capability */
+2
-2
drivers/pci/pci.c
+2
-2
drivers/pci/pci.c
···
2256
2256
*/
2257
2257
void pcie_clear_root_pme_status(struct pci_dev *dev)
2258
2258
{
2259
-
pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2259
+
pcie_capability_write_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2260
2260
}
2261
2261
2262
2262
/**
···
6591
6591
return;
6592
6592
6593
6593
/* Release domain from IDA where it was allocated. */
6594
-
if (of_get_pci_domain_nr(parent->of_node) == domain_nr)
6594
+
if (parent && of_get_pci_domain_nr(parent->of_node) == domain_nr)
6595
6595
ida_free(&pci_domain_nr_static_ida, domain_nr);
6596
6596
else
6597
6597
ida_free(&pci_domain_nr_dynamic_ida, domain_nr);
+3
drivers/pci/pci.h
+3
drivers/pci/pci.h
···
88
88
#define PCI_BUS_BRIDGE_MEM_WINDOW 1
89
89
#define PCI_BUS_BRIDGE_PREF_MEM_WINDOW 2
90
90
91
+
#define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
92
+
PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
93
+
91
94
extern const unsigned char pcie_link_speed[];
92
95
extern bool pci_early_dump;
93
96
-3
drivers/pci/pcie/aer.c
-3
drivers/pci/pcie/aer.c
···
239
239
}
240
240
#endif /* CONFIG_PCIE_ECRC */
241
241
242
-
#define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
243
-
PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
244
-
245
242
int pcie_aer_is_native(struct pci_dev *dev)
246
243
{
247
244
struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
+34
-1
drivers/pci/probe.c
+34
-1
drivers/pci/probe.c
···
2270
2270
u16 ctl;
2271
2271
int ret;
2272
2272
2273
-
if (!pci_is_pcie(dev))
2273
+
/* PCI_EXP_DEVCTL_EXT_TAG is RsvdP in VFs */
2274
+
if (!pci_is_pcie(dev) || dev->is_virtfn)
2274
2275
return 0;
2275
2276
2276
2277
ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
···
2411
2410
}
2412
2411
}
2413
2412
2413
+
static void pci_configure_rcb(struct pci_dev *dev)
2414
+
{
2415
+
struct pci_dev *rp;
2416
+
u16 rp_lnkctl;
2417
+
2418
+
/*
2419
+
* Per PCIe r7.0, sec 7.5.3.7, RCB is only meaningful in Root Ports
2420
+
* (where it is read-only), Endpoints, and Bridges. It may only be
2421
+
* set for Endpoints and Bridges if it is set in the Root Port. For
2422
+
* Endpoints, it is 'RsvdP' for Virtual Functions.
2423
+
*/
2424
+
if (!pci_is_pcie(dev) ||
2425
+
pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
2426
+
pci_pcie_type(dev) == PCI_EXP_TYPE_UPSTREAM ||
2427
+
pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM ||
2428
+
pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC ||
2429
+
dev->is_virtfn)
2430
+
return;
2431
+
2432
+
/* Root Port often not visible to virtualized guests */
2433
+
rp = pcie_find_root_port(dev);
2434
+
if (!rp)
2435
+
return;
2436
+
2437
+
pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &rp_lnkctl);
2438
+
pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
2439
+
PCI_EXP_LNKCTL_RCB,
2440
+
(rp_lnkctl & PCI_EXP_LNKCTL_RCB) ?
2441
+
PCI_EXP_LNKCTL_RCB : 0);
2442
+
}
2443
+
2414
2444
static void pci_configure_device(struct pci_dev *dev)
2415
2445
{
2416
2446
pci_configure_mps(dev);
···
2451
2419
pci_configure_aspm_l1ss(dev);
2452
2420
pci_configure_eetlp_prefix(dev);
2453
2421
pci_configure_serr(dev);
2422
+
pci_configure_rcb(dev);
2454
2423
2455
2424
pci_acpi_program_hp_params(dev);
2456
2425
}
+1
drivers/pci/quirks.c
+1
drivers/pci/quirks.c
···
5591
5591
pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5592
5592
}
5593
5593
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1004, quirk_no_ext_tags);
5594
+
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1005, quirk_no_ext_tags);
5594
5595
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5595
5596
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5596
5597
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);