Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
net/mlx5: mlx5_ifc, Add hardware definitions needed for adjacent vports
Next patches will implement the discovery and creation of adjacent
functions vports, this patch introduces the hardware structures
definitions needed for the driver implementation.
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Reviewed-by: Parav Pandit <parav@nvidia.com>
Reviewed-by: Jack Morgenstein <jackm@nvidia.com>
Signed-off-by: Alexei Lazar <alazar@nvidia.com>
+129
-4
+129
-4
include/linux/mlx5/mlx5_ifc.h
+129
-4
include/linux/mlx5/mlx5_ifc.h
···
189
189
MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
190
190
MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
191
191
MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
192
+
MLX5_CMD_OPCODE_QUERY_DELEGATED_VHCA = 0x732,
193
+
MLX5_CMD_OPCODE_CREATE_ESW_VPORT = 0x733,
194
+
MLX5_CMD_OPCODE_DESTROY_ESW_VPORT = 0x734,
192
195
MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
193
196
MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
194
197
MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
···
2210
2207
2211
2208
u8 reserved_at_440[0x8];
2212
2209
u8 max_num_eqs_24b[0x18];
2213
-
u8 reserved_at_460[0x3a0];
2210
+
2211
+
u8 reserved_at_460[0x160];
2212
+
2213
+
u8 query_adjacent_functions_id[0x1];
2214
+
u8 ingress_egress_esw_vport_connect[0x1];
2215
+
u8 function_id_type_vhca_id[0x1];
2216
+
u8 reserved_at_5c3[0xd];
2217
+
u8 delegate_vhca_management_profiles[0x10];
2218
+
2219
+
u8 delegated_vhca_max[0x10];
2220
+
u8 delegate_vhca_max[0x10];
2221
+
2222
+
u8 reserved_at_600[0x200];
2214
2223
};
2215
2224
2216
2225
enum mlx5_ifc_flow_destination_type {
···
5174
5159
5175
5160
u8 other_function[0x1];
5176
5161
u8 ec_vf_function[0x1];
5177
-
u8 reserved_at_42[0xe];
5162
+
u8 reserved_at_42[0x1];
5163
+
u8 function_id_type[0x1];
5164
+
u8 reserved_at_44[0xc];
5178
5165
u8 function_id[0x10];
5179
5166
5180
5167
u8 reserved_at_60[0x20];
···
6374
6357
6375
6358
u8 other_function[0x1];
6376
6359
u8 ec_vf_function[0x1];
6377
-
u8 reserved_at_42[0xe];
6360
+
u8 reserved_at_42[0x1];
6361
+
u8 function_id_type[0x1];
6362
+
u8 reserved_at_44[0xc];
6378
6363
u8 function_id[0x10];
6379
6364
6380
6365
u8 reserved_at_60[0x20];
···
7002
6983
u8 reserved_at_60[0x20];
7003
6984
};
7004
6985
6986
+
struct mlx5_ifc_destroy_esw_vport_out_bits {
6987
+
u8 status[0x8];
6988
+
u8 reserved_at_8[0x18];
6989
+
6990
+
u8 syndrome[0x20];
6991
+
6992
+
u8 reserved_at_40[0x20];
6993
+
};
6994
+
6995
+
struct mlx5_ifc_destroy_esw_vport_in_bits {
6996
+
u8 opcode[0x10];
6997
+
u8 uid[0x10];
6998
+
6999
+
u8 reserved_at_20[0x10];
7000
+
u8 op_mod[0x10];
7001
+
7002
+
u8 reserved_at_40[0x10];
7003
+
u8 vport_num[0x10];
7004
+
7005
+
u8 reserved_at_60[0x20];
7006
+
};
7007
+
7005
7008
struct mlx5_ifc_modify_esw_vport_context_out_bits {
7006
7009
u8 status[0x8];
7007
7010
u8 reserved_at_8[0x18];
···
7525
7484
u8 reserved_at_40[0x40];
7526
7485
};
7527
7486
7487
+
struct mlx5_ifc_function_vhca_rid_info_reg_bits {
7488
+
u8 host_number[0x8];
7489
+
u8 host_pci_device_function[0x8];
7490
+
u8 host_pci_bus[0x8];
7491
+
u8 reserved_at_18[0x3];
7492
+
u8 pci_bus_assigned[0x1];
7493
+
u8 function_type[0x4];
7494
+
7495
+
u8 parent_pci_device_function[0x8];
7496
+
u8 parent_pci_bus[0x8];
7497
+
u8 vhca_id[0x10];
7498
+
7499
+
u8 reserved_at_40[0x10];
7500
+
u8 function_id[0x10];
7501
+
7502
+
u8 reserved_at_60[0x20];
7503
+
};
7504
+
7505
+
struct mlx5_ifc_delegated_function_vhca_rid_info_bits {
7506
+
struct mlx5_ifc_function_vhca_rid_info_reg_bits function_vhca_rid_info;
7507
+
7508
+
u8 reserved_at_80[0x18];
7509
+
u8 manage_profile[0x8];
7510
+
7511
+
u8 reserved_at_a0[0x60];
7512
+
};
7513
+
7514
+
struct mlx5_ifc_query_delegated_vhca_out_bits {
7515
+
u8 status[0x8];
7516
+
u8 reserved_at_8[0x18];
7517
+
7518
+
u8 syndrome[0x20];
7519
+
7520
+
u8 reserved_at_40[0x20];
7521
+
7522
+
u8 reserved_at_60[0x10];
7523
+
u8 functions_count[0x10];
7524
+
7525
+
u8 reserved_at_80[0x80];
7526
+
7527
+
struct mlx5_ifc_delegated_function_vhca_rid_info_bits
7528
+
delegated_function_vhca_rid_info[];
7529
+
};
7530
+
7531
+
struct mlx5_ifc_query_delegated_vhca_in_bits {
7532
+
u8 opcode[0x10];
7533
+
u8 uid[0x10];
7534
+
7535
+
u8 reserved_at_20[0x10];
7536
+
u8 op_mod[0x10];
7537
+
7538
+
u8 reserved_at_40[0x40];
7539
+
};
7540
+
7541
+
struct mlx5_ifc_create_esw_vport_out_bits {
7542
+
u8 status[0x8];
7543
+
u8 reserved_at_8[0x18];
7544
+
7545
+
u8 syndrome[0x20];
7546
+
7547
+
u8 reserved_at_40[0x20];
7548
+
7549
+
u8 reserved_at_60[0x10];
7550
+
u8 vport_num[0x10];
7551
+
};
7552
+
7553
+
struct mlx5_ifc_create_esw_vport_in_bits {
7554
+
u8 opcode[0x10];
7555
+
u8 reserved_at_10[0x10];
7556
+
7557
+
u8 reserved_at_20[0x10];
7558
+
u8 op_mod[0x10];
7559
+
7560
+
u8 reserved_at_40[0x10];
7561
+
u8 managed_vhca_id[0x10];
7562
+
7563
+
u8 reserved_at_60[0x20];
7564
+
};
7565
+
7528
7566
struct mlx5_ifc_qp_2rst_out_bits {
7529
7567
u8 status[0x8];
7530
7568
u8 reserved_at_8[0x18];
···
7731
7611
u8 reserved_at_41[0xf];
7732
7612
u8 vport_number[0x10];
7733
7613
7734
-
u8 reserved_at_60[0x18];
7614
+
u8 reserved_at_60[0x10];
7615
+
u8 ingress_connect[0x1];
7616
+
u8 egress_connect[0x1];
7617
+
u8 ingress_connect_valid[0x1];
7618
+
u8 egress_connect_valid[0x1];
7619
+
u8 reserved_at_74[0x4];
7735
7620
u8 admin_state[0x4];
7736
7621
u8 reserved_at_7c[0x4];
7737
7622
};