+1

drivers/net/ethernet/sfc/ef10.c

reviewed

··· 4419 4419 .can_rx_scatter = true, 4420 4420 .always_rx_scatter = true, 4421 4421 .option_descriptors = true, 4422 4422 + .flash_auto_partition = true, 4422 4423 .min_interrupt_mode = EFX_INT_MODE_MSIX, 4423 4424 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4424 4425 .offload_features = EF10_OFFLOAD_FEATURES,

-1

drivers/net/ethernet/sfc/ef100_netdev.c

reviewed

··· 452 452 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO; 453 453 netif_set_tso_max_segs(net_dev, 454 454 ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT); 455 455 - efx->mdio.dev = net_dev; 456 455 457 456 rc = efx_ef100_init_datapath_caps(efx); 458 457 if (rc < 0)

-24

drivers/net/ethernet/sfc/efx.c

reviewed

··· 476 476 477 477 /************************************************************************** 478 478 * 479 479 - * ioctls 480 480 - * 481 481 - *************************************************************************/ 482 482 - 483 483 - /* Net device ioctl 484 484 - * Context: process, rtnl_lock() held. 485 485 - */ 486 486 - static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 487 487 - { 488 488 - struct efx_nic *efx = efx_netdev_priv(net_dev); 489 489 - struct mii_ioctl_data *data = if_mii(ifr); 490 490 - 491 491 - /* Convert phy_id from older PRTAD/DEVAD format */ 492 492 - if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && 493 493 - (data->phy_id & 0xfc00) == 0x0400) 494 494 - data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; 495 495 - 496 496 - return mdio_mii_ioctl(&efx->mdio, data, cmd); 497 497 - } 498 498 - 499 499 - /************************************************************************** 500 500 - * 501 479 * Kernel net device interface 502 480 * 503 481 *************************************************************************/ ··· 571 593 .ndo_tx_timeout = efx_watchdog, 572 594 .ndo_start_xmit = efx_hard_start_xmit, 573 595 .ndo_validate_addr = eth_validate_addr, 574 574 - .ndo_eth_ioctl = efx_ioctl, 575 596 .ndo_change_mtu = efx_change_mtu, 576 597 .ndo_set_mac_address = efx_set_mac_address, 577 598 .ndo_set_rx_mode = efx_set_rx_mode, ··· 1178 1201 rc = efx_init_struct(efx, pci_dev); 1179 1202 if (rc) 1180 1203 goto fail1; 1181 1181 - efx->mdio.dev = net_dev; 1182 1204 1183 1205 pci_info(pci_dev, "Solarflare NIC detected\n"); 1184 1206

+31 -23

drivers/net/ethernet/sfc/efx_reflash.c

reviewed

··· 407 407 return -EOPNOTSUPP; 408 408 } 409 409 410 410 - devlink_flash_update_status_notify(devlink, "Checking update", NULL, 0, 0); 411 411 - 412 412 - rc = efx_reflash_parse_firmware_data(fw, &type, &data_subtype, &data, 413 413 - &data_size); 414 414 - if (rc) { 415 415 - NL_SET_ERR_MSG_MOD(extack, 416 416 - "Firmware image validation check failed"); 417 417 - goto out; 418 418 - } 419 419 - 420 410 mutex_lock(&efx->reflash_mutex); 421 411 422 422 - rc = efx_mcdi_nvram_metadata(efx, type, &subtype, NULL, NULL, 0); 423 423 - if (rc) { 424 424 - NL_SET_ERR_MSG_FMT_MOD(extack, 425 425 - "Metadata query for NVRAM partition %#x failed", 426 426 - type); 427 427 - goto out_unlock; 428 428 - } 412 412 + devlink_flash_update_status_notify(devlink, "Checking update", NULL, 0, 0); 429 413 430 430 - if (subtype != data_subtype) { 431 431 - NL_SET_ERR_MSG_MOD(extack, 432 432 - "Firmware image is not appropriate for this adapter"); 433 433 - rc = -EINVAL; 434 434 - goto out_unlock; 414 414 + if (efx->type->flash_auto_partition) { 415 415 + /* NIC wants entire FW file including headers; 416 416 + * FW will validate 'subtype' if there is one 417 417 + */ 418 418 + type = NVRAM_PARTITION_TYPE_AUTO; 419 419 + data = fw->data; 420 420 + data_size = fw->size; 421 421 + } else { 422 422 + rc = efx_reflash_parse_firmware_data(fw, &type, &data_subtype, &data, 423 423 + &data_size); 424 424 + if (rc) { 425 425 + NL_SET_ERR_MSG_MOD(extack, 426 426 + "Firmware image validation check failed"); 427 427 + goto out_unlock; 428 428 + } 429 429 + 430 430 + rc = efx_mcdi_nvram_metadata(efx, type, &subtype, NULL, NULL, 0); 431 431 + if (rc) { 432 432 + NL_SET_ERR_MSG_FMT_MOD(extack, 433 433 + "Metadata query for NVRAM partition %#x failed", 434 434 + type); 435 435 + goto out_unlock; 436 436 + } 437 437 + 438 438 + if (subtype != data_subtype) { 439 439 + NL_SET_ERR_MSG_MOD(extack, 440 440 + "Firmware image is not appropriate for this adapter"); 441 441 + rc = -EINVAL; 442 442 + goto out_unlock; 443 443 + } 435 444 } 436 445 437 446 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_align, &write_align, ··· 515 506 rc = efx_mcdi_nvram_update_finish_polled(efx, type); 516 507 out_unlock: 517 508 mutex_unlock(&efx->reflash_mutex); 518 518 - out: 519 509 devlink_flash_update_status_notify(devlink, rc ? "Update failed" : 520 510 "Update complete", 521 511 NULL, 0, 0);

+5018 -8804

drivers/net/ethernet/sfc/mcdi_pcol.h

reviewed

··· 72 72 * | \------- Error 73 73 * \------------------------------ Resync (always set) 74 74 * 75 75 - * The client writes it's request into MC shared memory, and rings the 76 76 - * doorbell. Each request is completed by either by the MC writing 75 75 + * The client writes its request into MC shared memory, and rings the 76 76 + * doorbell. Each request is completed either by the MC writing 77 77 * back into shared memory, or by writing out an event. 78 78 * 79 79 * All MCDI commands support completion by shared memory response. Each 80 80 * request may also contain additional data (accounted for by HEADER.LEN), 81 81 - * and some response's may also contain additional data (again, accounted 81 81 + * and some responses may also contain additional data (again, accounted 82 82 * for by HEADER.LEN). 83 83 * 84 84 * Some MCDI commands support completion by event, in which any associated 85 85 * response data is included in the event. 86 86 * 87 87 - * The protocol requires one response to be delivered for every request, a 87 87 + * The protocol requires one response to be delivered for every request; a 88 88 * request should not be sent unless the response for the previous request 89 89 * has been received (either by polling shared memory, or by receiving 90 90 * an event). ··· 163 163 * generated events. 164 164 */ 165 165 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 166 166 + 166 167 167 168 168 169 #define MC_CMD_ERR_CODE_OFST 0 ··· 322 321 /* enum: The requesting client is not a function */ 323 322 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c 324 323 /* enum: The requested operation might require the command to be passed between 325 325 - * MCs, and thetransport doesn't support that. Should only ever been seen over 324 324 + * MCs, and the transport doesn't support that. Should only ever been seen over 326 325 * the UART. 327 326 */ 328 327 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d ··· 359 358 * sub-variant switching. 360 359 */ 361 360 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 362 362 - /* enum: The clock whose frequency you've attempted to set set doesn't exist on 361 361 + /* enum: The clock whose frequency you've attempted to set doesn't exist on 363 362 * this NIC 364 363 */ 365 364 #define MC_CMD_ERR_NO_CLOCK 0x1015 ··· 388 387 */ 389 388 #define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b 390 389 391 391 - /* MC_CMD_RESOURCE_SPECIFIER enum */ 392 392 - /* enum: Any */ 393 393 - #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff 394 394 - #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */ 395 395 - 396 396 - /* MC_CMD_FPGA_FLASH_INDEX enum */ 397 397 - #define MC_CMD_FPGA_FLASH_PRIMARY 0x0 /* enum */ 398 398 - #define MC_CMD_FPGA_FLASH_SECONDARY 0x1 /* enum */ 399 399 - 400 400 - /* MC_CMD_EXTERNAL_MAE_LINK_MODE enum */ 401 401 - /* enum: Legacy mode as described in XN-200039-TC. */ 402 402 - #define MC_CMD_EXTERNAL_MAE_LINK_MODE_LEGACY 0x0 403 403 - /* enum: Switchdev mode as described in XN-200039-TC. */ 404 404 - #define MC_CMD_EXTERNAL_MAE_LINK_MODE_SWITCHDEV 0x1 405 405 - /* enum: Bootstrap mode as described in XN-200039-TC. */ 406 406 - #define MC_CMD_EXTERNAL_MAE_LINK_MODE_BOOTSTRAP 0x2 407 407 - /* enum: Link-mode change is in-progress as described in XN-200039-TC. */ 408 408 - #define MC_CMD_EXTERNAL_MAE_LINK_MODE_PENDING 0xf 409 409 - 410 390 /* PCIE_INTERFACE enum: From EF100 onwards, SFC products can have multiple PCIe 411 391 * interfaces. There is a need to refer to interfaces explicitly from drivers 412 392 * (for example, a management driver on one interface administering a function ··· 406 424 * an on-NIC ARM module is expected to be connected. 407 425 */ 408 426 #define PCIE_INTERFACE_NIC_EMBEDDED 0x1 427 427 + /* enum: The PCIe logical interface 0. It is an alias for HOST_PRIMARY. */ 428 428 + #define PCIE_INTERFACE_PCIE_HOST_INTF_0 0x0 429 429 + /* enum: The PCIe logical interface 1. */ 430 430 + #define PCIE_INTERFACE_PCIE_HOST_INTF_1 0x2 431 431 + /* enum: The PCIe logical interface 2. */ 432 432 + #define PCIE_INTERFACE_PCIE_HOST_INTF_2 0x3 433 433 + /* enum: The PCIe logical interface 3. */ 434 434 + #define PCIE_INTERFACE_PCIE_HOST_INTF_3 0x4 409 435 /* enum: For MCDI commands issued over a PCIe interface, this value is 410 436 * translated into the interface over which the command was issued. Not 411 437 * meaningful for other MCDI transports. ··· 630 640 * be allocated by different counter blocks, so e.g. AR counter 42 is different 631 641 * from CT counter 42. Generation counts are also type-specific. This value is 632 642 * also present in the header of streaming counter packets, in the IDENTIFIER 633 633 - * field (see packetiser packet format definitions). 643 643 + * field (see packetiser packet format definitions). Also note that LACP 644 644 + * counter IDs are not allocated individually, instead the counter IDs are 645 645 + * directly tied to the LACP balance table indices. These in turn are allocated 646 646 + * in large contiguous blocks as a LAG config. Calling MAE_COUNTER_ALLOC/FREE 647 647 + * with an LACP counter type will return EPERM. 634 648 */ 635 649 /* enum: Action Rule counters - can be referenced in AR response. */ 636 650 #define MAE_COUNTER_TYPE_AR 0x0 ··· 642 648 #define MAE_COUNTER_TYPE_CT 0x1 643 649 /* enum: Outer Rule counters - can be referenced in OR response. */ 644 650 #define MAE_COUNTER_TYPE_OR 0x2 651 651 + /* enum: LACP counters - linked to LACP balance table entries. */ 652 652 + #define MAE_COUNTER_TYPE_LACP 0x3 653 653 + 654 654 + /* MAE_COUNTER_ID enum: ID of allocated counter or counter list. */ 655 655 + /* enum: A counter ID that is guaranteed never to represent a real counter or 656 656 + * counter list. 657 657 + */ 658 658 + #define MAE_COUNTER_ID_NULL 0xffffffff 645 659 646 660 /* TABLE_ID enum: Unique IDs for tables. The 32-bit ID values have been 647 661 * structured with bits [31:24] reserved (0), [23:16] indicating which major ··· 658 656 * variations of the same table. (All of the tables currently defined within 659 657 * the streaming engines are listed here, but this does not imply that they are 660 658 * all supported - MC_CMD_TABLE_LIST returns the list of actually supported 661 661 - * tables.) 659 659 + * tables.) The DPU offload engines' enumerators follow a deliberate pattern: 660 660 + * 0x01010000 + is_dpu_net * 0x10000 + is_wr_or_tx * 0x8000 + is_lite_pipe * 661 661 + * 0x1000 + oe_engine_type * 0x100 + oe_instance_within_pipe * 0x10 662 662 */ 663 663 /* enum: Outer_Rule_Table in the MAE - refer to SF-123102-TC. */ 664 664 #define TABLE_ID_OUTER_RULE_TABLE 0x10000 ··· 698 694 #define TABLE_ID_RSS_CONTEXT_TABLE 0x20200 699 695 /* enum: Indirection_Table in VNIC Rx - refer to SF-123102-TC. */ 700 696 #define TABLE_ID_INDIRECTION_TABLE 0x20300 701 701 - 702 702 - /* TABLE_COMPRESSED_VLAN enum: Compressed VLAN TPID as used by some field 703 703 - * types; can be calculated by (((ether_type_msb >> 2) & 0x4) ^ 0x4) | 704 704 - * (ether_type_msb & 0x3); 697 697 + /* enum: DPU.host read pipe first CRC offload engine profiles - refer to 698 698 + * XN-200147-AN. 705 699 */ 706 706 - #define TABLE_COMPRESSED_VLAN_TPID_8100 0x5 /* enum */ 707 707 - #define TABLE_COMPRESSED_VLAN_TPID_88A8 0x4 /* enum */ 708 708 - #define TABLE_COMPRESSED_VLAN_TPID_9100 0x1 /* enum */ 709 709 - #define TABLE_COMPRESSED_VLAN_TPID_9200 0x2 /* enum */ 710 710 - #define TABLE_COMPRESSED_VLAN_TPID_9300 0x3 /* enum */ 711 711 - 712 712 - /* TABLE_NAT_DIR enum: NAT direction. */ 713 713 - #define TABLE_NAT_DIR_SOURCE 0x0 /* enum */ 714 714 - #define TABLE_NAT_DIR_DEST 0x1 /* enum */ 715 715 - 716 716 - /* TABLE_RSS_KEY_MODE enum: Defines how the value for Toeplitz hashing for RSS 717 717 - * is constructed as a concatenation (indicated here by "++") of packet header 718 718 - * fields. 700 700 + #define TABLE_ID_DPU_HOST_RD_CRC0_OE_PROFILE 0x1010000 701 701 + /* enum: DPU.host read pipe second CRC offload engine profiles - refer to 702 702 + * XN-200147-AN. 719 703 */ 720 720 - /* enum: IP src addr ++ IP dst addr */ 721 721 - #define TABLE_RSS_KEY_MODE_SA_DA 0x0 722 722 - /* enum: IP src addr ++ IP dst addr ++ TCP/UDP src port ++ TCP/UDP dst port */ 723 723 - #define TABLE_RSS_KEY_MODE_SA_DA_SP_DP 0x1 724 724 - /* enum: IP src addr */ 725 725 - #define TABLE_RSS_KEY_MODE_SA 0x2 726 726 - /* enum: IP dst addr */ 727 727 - #define TABLE_RSS_KEY_MODE_DA 0x3 728 728 - /* enum: IP src addr ++ TCP/UDP src port */ 729 729 - #define TABLE_RSS_KEY_MODE_SA_SP 0x4 730 730 - /* enum: IP dest addr ++ TCP dest port */ 731 731 - #define TABLE_RSS_KEY_MODE_DA_DP 0x5 732 732 - /* enum: Nothing (produces input of 0, resulting in output hash of 0) */ 733 733 - #define TABLE_RSS_KEY_MODE_NONE 0x7 734 734 - 735 735 - /* TABLE_RSS_SPREAD_MODE enum: RSS spreading mode. */ 736 736 - /* enum: RSS uses Indirection_Table lookup. */ 737 737 - #define TABLE_RSS_SPREAD_MODE_INDIRECTION 0x0 738 738 - /* enum: RSS uses even spreading calculation. */ 739 739 - #define TABLE_RSS_SPREAD_MODE_EVEN 0x1 704 704 + #define TABLE_ID_DPU_HOST_RD_CRC1_OE_PROFILE 0x1010010 705 705 + /* enum: DPU.host write pipe first CRC offload engine profiles - refer to 706 706 + * XN-200147-AN. 707 707 + */ 708 708 + #define TABLE_ID_DPU_HOST_WR_CRC0_OE_PROFILE 0x1018000 709 709 + /* enum: DPU.host write pipe second CRC offload engine profiles - refer to 710 710 + * XN-200147-AN. 711 711 + */ 712 712 + #define TABLE_ID_DPU_HOST_WR_CRC1_OE_PROFILE 0x1018010 713 713 + /* enum: DPU.net 'full' receive pipe CRC offload engine profiles - refer to 714 714 + * XN-200147-AN. 715 715 + */ 716 716 + #define TABLE_ID_DPU_NET_RX_CRC0_OE_PROFILE 0x1020000 717 717 + /* enum: DPU.net 'full' receive pipe first checksum offload engine profiles - 718 718 + * refer to XN-200147-AN. 719 719 + */ 720 720 + #define TABLE_ID_DPU_NET_RX_CSUM0_OE_PROFILE 0x1020100 721 721 + /* enum: DPU.net 'full' receive pipe second checksum offload engine profiles - 722 722 + * refer to XN-200147-AN. 723 723 + */ 724 724 + #define TABLE_ID_DPU_NET_RX_CSUM1_OE_PROFILE 0x1020110 725 725 + /* enum: DPU.net 'full' receive pipe AES-GCM offload engine profiles - refer to 726 726 + * XN-200147-AN. 727 727 + */ 728 728 + #define TABLE_ID_DPU_NET_RX_AES_GCM0_OE_PROFILE 0x1020200 729 729 + /* enum: DPU.net 'lite' receive pipe CRC offload engine profiles - refer to 730 730 + * XN-200147-AN. 731 731 + */ 732 732 + #define TABLE_ID_DPU_NET_RXLITE_CRC0_OE_PROFILE 0x1021000 733 733 + /* enum: DPU.net 'lite' receive pipe checksum offload engine profiles - refer 734 734 + * to XN-200147-AN. 735 735 + */ 736 736 + #define TABLE_ID_DPU_NET_RXLITE_CSUM0_OE_PROFILE 0x1021100 737 737 + /* enum: DPU.net 'full' transmit pipe CRC offload engine profiles - refer to 738 738 + * XN-200147-AN. 739 739 + */ 740 740 + #define TABLE_ID_DPU_NET_TX_CRC0_OE_PROFILE 0x1028000 741 741 + /* enum: DPU.net 'full' transmit pipe first checksum offload engine profiles - 742 742 + * refer to XN-200147-AN. 743 743 + */ 744 744 + #define TABLE_ID_DPU_NET_TX_CSUM0_OE_PROFILE 0x1028100 745 745 + /* enum: DPU.net 'full' transmit pipe second checksum offload engine profiles - 746 746 + * refer to XN-200147-AN. 747 747 + */ 748 748 + #define TABLE_ID_DPU_NET_TX_CSUM1_OE_PROFILE 0x1028110 749 749 + /* enum: DPU.net 'full' transmit pipe AES-GCM offload engine profiles - refer 750 750 + * to XN-200147-AN. 751 751 + */ 752 752 + #define TABLE_ID_DPU_NET_TX_AES_GCM0_OE_PROFILE 0x1028200 753 753 + /* enum: DPU.net 'lite' transmit pipe CRC offload engine profiles - refer to 754 754 + * XN-200147-AN. 755 755 + */ 756 756 + #define TABLE_ID_DPU_NET_TXLITE_CRC0_OE_PROFILE 0x1029000 757 757 + /* enum: DPU.net 'lite' transmit pipe checksum offload engine profiles - refer 758 758 + * to XN-200147-AN. 759 759 + */ 760 760 + #define TABLE_ID_DPU_NET_TXLITE_CSUM0_OE_PROFILE 0x1029100 740 761 741 762 /* TABLE_FIELD_ID enum: Unique IDs for fields. Related concepts have been 742 763 * loosely grouped together into blocks with gaps for expansion, but the values ··· 1055 1026 #define TABLE_FIELD_ID_BAL_TBL_BASE_DIV64 0xde 1056 1027 /* enum: Length of balance table region: 0=>64, 1=>128, 2=>256. */ 1057 1028 #define TABLE_FIELD_ID_BAL_TBL_LEN_ID 0xdf 1029 1029 + /* enum: LACP LAG ID (i.e. the low 3 bits of LACP LAG mport ID), indexing 1030 1030 + * LACP_LAG_Config_Table. Refer to SF-123102-TC. 1031 1031 + */ 1032 1032 + #define TABLE_FIELD_ID_LACP_LAG_ID 0xe0 1033 1033 + /* enum: Address in LACP_Balance_Table. The balance table is partitioned 1034 1034 + * between LAGs according to the settings in LACP_LAG_Config_Table and then 1035 1035 + * indexed by the LACP hash, providing the mapping to destination mports. Refer 1036 1036 + * to SF-123102-TC. 1037 1037 + */ 1038 1038 + #define TABLE_FIELD_ID_BAL_TBL_ADDR 0xe1 1058 1039 /* enum: UDP port to match for UDP-based encapsulations; required to be 0 for 1059 1040 * other encapsulation types. 1060 1041 */ ··· 1121 1082 #define TABLE_FIELD_ID_INDIR_TBL_LEN_ID 0x105 1122 1083 /* enum: An offset to be applied to the base destination queue ID. */ 1123 1084 #define TABLE_FIELD_ID_INDIR_OFFSET 0x106 1085 1085 + /* enum: DPU offload engine profile ID to address. */ 1086 1086 + #define TABLE_FIELD_ID_OE_PROFILE 0x3e8 1087 1087 + /* enum: Width of the CRC to calculate - see CRC_VARIANT enum. */ 1088 1088 + #define TABLE_FIELD_ID_CRC_VARIANT 0x3f2 1089 1089 + /* enum: If set, reflect the bits of each input byte, bit 7 is LSB, bit 0 is 1090 1090 + * MSB. If clear, bit 7 is MSB, bit 0 is LSB. 1091 1091 + */ 1092 1092 + #define TABLE_FIELD_ID_CRC_REFIN 0x3f3 1093 1093 + /* enum: If set, reflect the bits of each output byte, bit 7 is LSB, bit 0 is 1094 1094 + * MSB. If clear, bit 7 is MSB, bit 0 is LSB. 1095 1095 + */ 1096 1096 + #define TABLE_FIELD_ID_CRC_REFOUT 0x3f4 1097 1097 + /* enum: If set, invert every bit of the output value. */ 1098 1098 + #define TABLE_FIELD_ID_CRC_INVOUT 0x3f5 1099 1099 + /* enum: The CRC polynomial to use for checksumming, in normal form. */ 1100 1100 + #define TABLE_FIELD_ID_CRC_POLY 0x3f6 1101 1101 + /* enum: Operation for the checksum engine to perform - see DPU_CSUM_OP enum. 1102 1102 + */ 1103 1103 + #define TABLE_FIELD_ID_CSUM_OP 0x410 1104 1104 + /* enum: Byte offset of checksum relative to region_start (for VALIDATE_* 1105 1105 + * operations only). 1106 1106 + */ 1107 1107 + #define TABLE_FIELD_ID_CSUM_OFFSET 0x411 1108 1108 + /* enum: Indicates there is additional data on OPR bus that needs to be 1109 1109 + * incorporated into the payload checksum. 1110 1110 + */ 1111 1111 + #define TABLE_FIELD_ID_CSUM_OPR_ADDITIONAL_DATA 0x412 1112 1112 + /* enum: Log2 data size of additional data on OPR bus. */ 1113 1113 + #define TABLE_FIELD_ID_CSUM_OPR_DATA_SIZE_LOG2 0x413 1114 1114 + /* enum: 4 byte offset of where to find the additional data on the OPR bus. */ 1115 1115 + #define TABLE_FIELD_ID_CSUM_OPR_4B_OFF 0x414 1116 1116 + /* enum: Operation type for the AES-GCM core - see GCM_OP_CODE enum. */ 1117 1117 + #define TABLE_FIELD_ID_GCM_OP_CODE 0x41a 1118 1118 + /* enum: Key length - AES_KEY_LEN enum. */ 1119 1119 + #define TABLE_FIELD_ID_GCM_KEY_LEN 0x41b 1120 1120 + /* enum: OPR 4 byte offset for ICV or GHASH output (only in BULK_* mode) or 1121 1121 + * IPSEC descrypt output. 1122 1122 + */ 1123 1123 + #define TABLE_FIELD_ID_GCM_OPR_4B_OFFSET 0x41c 1124 1124 + /* enum: If OP_CODE is BULK_*, indicates Emit GHASH (Fragment mode). Else, 1125 1125 + * indicates IPSEC-ESN mode. 1126 1126 + */ 1127 1127 + #define TABLE_FIELD_ID_GCM_EMIT_GHASH_ISESN 0x41d 1128 1128 + /* enum: Replay Protection Enable. */ 1129 1129 + #define TABLE_FIELD_ID_GCM_REPLAY_PROTECT_EN 0x41e 1130 1130 + /* enum: IPSEC Encrypt ESP trailer NEXT_HEADER byte. */ 1131 1131 + #define TABLE_FIELD_ID_GCM_NEXT_HDR 0x41f 1132 1132 + /* enum: Replay Window Size. */ 1133 1133 + #define TABLE_FIELD_ID_GCM_REPLAY_WIN_SIZE 0x420 1124 1134 1125 1135 /* MCDI_EVENT structuredef: The structure of an MCDI_EVENT on Siena/EF10/EF100 1126 1136 * platforms ··· 1226 1138 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_OFST 0 1227 1139 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 1228 1140 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 1141 1141 + #define MCDI_EVENT_PORT_LINKCHANGE_PORT_HANDLE_OFST 0 1142 1142 + #define MCDI_EVENT_PORT_LINKCHANGE_PORT_HANDLE_LBN 0 1143 1143 + #define MCDI_EVENT_PORT_LINKCHANGE_PORT_HANDLE_WIDTH 24 1144 1144 + #define MCDI_EVENT_PORT_LINKCHANGE_SEQ_NUM_OFST 0 1145 1145 + #define MCDI_EVENT_PORT_LINKCHANGE_SEQ_NUM_LBN 24 1146 1146 + #define MCDI_EVENT_PORT_LINKCHANGE_SEQ_NUM_WIDTH 7 1147 1147 + #define MCDI_EVENT_PORT_LINKCHANGE_LINK_UP_OFST 0 1148 1148 + #define MCDI_EVENT_PORT_LINKCHANGE_LINK_UP_LBN 31 1149 1149 + #define MCDI_EVENT_PORT_LINKCHANGE_LINK_UP_WIDTH 1 1150 1150 + #define MCDI_EVENT_PORT_MODULECHANGE_PORT_HANDLE_OFST 0 1151 1151 + #define MCDI_EVENT_PORT_MODULECHANGE_PORT_HANDLE_LBN 0 1152 1152 + #define MCDI_EVENT_PORT_MODULECHANGE_PORT_HANDLE_WIDTH 24 1153 1153 + #define MCDI_EVENT_PORT_MODULECHANGE_SEQ_NUM_OFST 0 1154 1154 + #define MCDI_EVENT_PORT_MODULECHANGE_SEQ_NUM_LBN 24 1155 1155 + #define MCDI_EVENT_PORT_MODULECHANGE_SEQ_NUM_WIDTH 7 1156 1156 + #define MCDI_EVENT_PORT_MODULECHANGE_MDI_CONNECTED_OFST 0 1157 1157 + #define MCDI_EVENT_PORT_MODULECHANGE_MDI_CONNECTED_LBN 31 1158 1158 + #define MCDI_EVENT_PORT_MODULECHANGE_MDI_CONNECTED_WIDTH 1 1229 1159 #define MCDI_EVENT_SENSOREVT_MONITOR_OFST 0 1230 1160 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 1231 1161 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 ··· 1343 1237 #define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe 1344 1238 /* enum: Notify that invalid flash type detected */ 1345 1239 #define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf 1346 1346 - /* enum: Notify that the attempt to run FPGA Controller firmware timedout */ 1240 1240 + /* enum: Notify that the attempt to run FPGA Controller firmware timed out */ 1347 1241 #define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10 1348 1242 /* enum: Failure to probe one or more FPGA boot flash chips */ 1349 1243 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11 ··· 1361 1255 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8 1362 1256 /* enum: FC Assert happened, but the register information is not available */ 1363 1257 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0 1364 1364 - /* enum: The register information for FC Assert is ready for readinng by driver 1258 1258 + /* enum: The register information for FC Assert is ready for reading by driver 1365 1259 */ 1366 1260 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1 1367 1261 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_OFST 0 ··· 1470 1364 #define MCDI_EVENT_MODULECHANGE_SEQ_OFST 0 1471 1365 #define MCDI_EVENT_MODULECHANGE_SEQ_LBN 30 1472 1366 #define MCDI_EVENT_MODULECHANGE_SEQ_WIDTH 2 1367 1367 + #define MCDI_EVENT_DESC_PROXY_VIRTQ_VI_ID_OFST 0 1368 1368 + #define MCDI_EVENT_DESC_PROXY_VIRTQ_VI_ID_LBN 0 1369 1369 + #define MCDI_EVENT_DESC_PROXY_VIRTQ_VI_ID_WIDTH 16 1370 1370 + #define MCDI_EVENT_DESC_PROXY_VIRTQ_ID_OFST 0 1371 1371 + #define MCDI_EVENT_DESC_PROXY_VIRTQ_ID_LBN 16 1372 1372 + #define MCDI_EVENT_DESC_PROXY_VIRTQ_ID_WIDTH 16 1473 1373 #define MCDI_EVENT_DATA_LBN 0 1474 1374 #define MCDI_EVENT_DATA_WIDTH 32 1475 1375 /* Alias for PTP_DATA. */ ··· 1612 1500 * change to the journal. 1613 1501 */ 1614 1502 #define MCDI_EVENT_CODE_MPORT_JOURNAL_CHANGE 0x27 1503 1503 + /* enum: Notification that a source queue is enabled and attached to its proxy 1504 1504 + * sink queue. SRC field contains the handle of the affected descriptor proxy 1505 1505 + * function. DATA field contains the relative source queue number and absolute 1506 1506 + * VI ID. 1507 1507 + */ 1508 1508 + #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_QUEUE_START 0x28 1509 1509 + /* enum: Notification of a change in link state and/or link speed of a network 1510 1510 + * port link. This event applies to a network port identified by a handle, 1511 1511 + * PORT_HANDLE, which is discovered by the driver using the MC_CMD_ENUM_PORTS 1512 1512 + * command. 1513 1513 + */ 1514 1514 + #define MCDI_EVENT_CODE_PORT_LINKCHANGE 0x29 1515 1515 + /* enum: Notification of a change in the state of an MDI (external connector) 1516 1516 + * of a network port. This typically corresponds to module plug/unplug for 1517 1517 + * modular interfaces (e.g., SFP/QSFP and similar) or cable connect/disconnect. 1518 1518 + * This event applies to a network port identified by a handle, PORT_HANDLE, 1519 1519 + * which is discovered by the driver using the MC_CMD_ENUM_PORTS command. 1520 1520 + */ 1521 1521 + #define MCDI_EVENT_CODE_PORT_MODULECHANGE 0x2a 1522 1522 + /* enum: Notification that the port enumeration journal has changed since it 1523 1523 + * was last read and updates can be read using the MC_CMD_ENUM_PORTS command. 1524 1524 + * The firmware may moderate the events so that an event is not sent for every 1525 1525 + * change to the journal. 1526 1526 + */ 1527 1527 + #define MCDI_EVENT_CODE_ENUM_PORTS_CHANGE 0x2b 1615 1528 /* enum: Artificial event generated by host and posted via MC for test 1616 1529 * purposes. 1617 1530 */ ··· 1649 1512 #define MCDI_EVENT_LINKCHANGE_DATA_LEN 4 1650 1513 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 1651 1514 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 1515 1515 + #define MCDI_EVENT_PORT_LINKCHANGE_DATA_OFST 0 1516 1516 + #define MCDI_EVENT_PORT_LINKCHANGE_DATA_LEN 4 1517 1517 + #define MCDI_EVENT_PORT_LINKCHANGE_DATA_LBN 0 1518 1518 + #define MCDI_EVENT_PORT_LINKCHANGE_DATA_WIDTH 32 1519 1519 + #define MCDI_EVENT_PORT_MODULECHANGE_DATA_OFST 0 1520 1520 + #define MCDI_EVENT_PORT_MODULECHANGE_DATA_LEN 4 1521 1521 + #define MCDI_EVENT_PORT_MODULECHANGE_DATA_LBN 0 1522 1522 + #define MCDI_EVENT_PORT_MODULECHANGE_DATA_WIDTH 32 1652 1523 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 1653 1524 #define MCDI_EVENT_SENSOREVT_DATA_LEN 4 1654 1525 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 ··· 1813 1668 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LBN 0 1814 1669 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_WIDTH 32 1815 1670 1816 1816 - /* FCDI_EVENT structuredef */ 1817 1817 - #define FCDI_EVENT_LEN 8 1818 1818 - #define FCDI_EVENT_CONT_LBN 32 1819 1819 - #define FCDI_EVENT_CONT_WIDTH 1 1820 1820 - #define FCDI_EVENT_LEVEL_LBN 33 1821 1821 - #define FCDI_EVENT_LEVEL_WIDTH 3 1822 1822 - /* enum: Info. */ 1823 1823 - #define FCDI_EVENT_LEVEL_INFO 0x0 1824 1824 - /* enum: Warning. */ 1825 1825 - #define FCDI_EVENT_LEVEL_WARN 0x1 1826 1826 - /* enum: Error. */ 1827 1827 - #define FCDI_EVENT_LEVEL_ERR 0x2 1828 1828 - /* enum: Fatal. */ 1829 1829 - #define FCDI_EVENT_LEVEL_FATAL 0x3 1830 1830 - #define FCDI_EVENT_DATA_OFST 0 1831 1831 - #define FCDI_EVENT_DATA_LEN 4 1832 1832 - #define FCDI_EVENT_LINK_STATE_STATUS_OFST 0 1833 1833 - #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 1834 1834 - #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 1835 1835 - #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ 1836 1836 - #define FCDI_EVENT_LINK_UP 0x1 /* enum */ 1837 1837 - #define FCDI_EVENT_DATA_LBN 0 1838 1838 - #define FCDI_EVENT_DATA_WIDTH 32 1839 1839 - #define FCDI_EVENT_SRC_LBN 36 1840 1840 - #define FCDI_EVENT_SRC_WIDTH 8 1841 1841 - #define FCDI_EVENT_EV_CODE_LBN 60 1842 1842 - #define FCDI_EVENT_EV_CODE_WIDTH 4 1843 1843 - #define FCDI_EVENT_CODE_LBN 44 1844 1844 - #define FCDI_EVENT_CODE_WIDTH 8 1845 1845 - /* enum: The FC was rebooted. */ 1846 1846 - #define FCDI_EVENT_CODE_REBOOT 0x1 1847 1847 - /* enum: Bad assert. */ 1848 1848 - #define FCDI_EVENT_CODE_ASSERT 0x2 1849 1849 - /* enum: DDR3 test result. */ 1850 1850 - #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 1851 1851 - /* enum: Link status. */ 1852 1852 - #define FCDI_EVENT_CODE_LINK_STATE 0x4 1853 1853 - /* enum: A timed read is ready to be serviced. */ 1854 1854 - #define FCDI_EVENT_CODE_TIMED_READ 0x5 1855 1855 - /* enum: One or more PPS IN events */ 1856 1856 - #define FCDI_EVENT_CODE_PPS_IN 0x6 1857 1857 - /* enum: Tick event from PTP clock */ 1858 1858 - #define FCDI_EVENT_CODE_PTP_TICK 0x7 1859 1859 - /* enum: ECC error counters */ 1860 1860 - #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 1861 1861 - /* enum: Current status of PTP */ 1862 1862 - #define FCDI_EVENT_CODE_PTP_STATUS 0x9 1863 1863 - /* enum: Port id config to map MC-FC port idx */ 1864 1864 - #define FCDI_EVENT_CODE_PORT_CONFIG 0xa 1865 1865 - /* enum: Boot result or error code */ 1866 1866 - #define FCDI_EVENT_CODE_BOOT_RESULT 0xb 1867 1867 - #define FCDI_EVENT_REBOOT_SRC_LBN 36 1868 1868 - #define FCDI_EVENT_REBOOT_SRC_WIDTH 8 1869 1869 - #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */ 1870 1870 - #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */ 1871 1871 - #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 1872 1872 - #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4 1873 1873 - #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 1874 1874 - #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 1875 1875 - #define FCDI_EVENT_ASSERT_TYPE_LBN 36 1876 1876 - #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 1877 1877 - #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 1878 1878 - #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 1879 1879 - #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 1880 1880 - #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4 1881 1881 - #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 1882 1882 - #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 1883 1883 - #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 1884 1884 - #define FCDI_EVENT_LINK_STATE_DATA_LEN 4 1885 1885 - #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 1886 1886 - #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 1887 1887 - #define FCDI_EVENT_PTP_STATE_OFST 0 1888 1888 - #define FCDI_EVENT_PTP_STATE_LEN 4 1889 1889 - #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ 1890 1890 - #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ 1891 1891 - #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ 1892 1892 - #define FCDI_EVENT_PTP_STATE_LBN 0 1893 1893 - #define FCDI_EVENT_PTP_STATE_WIDTH 32 1894 1894 - #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 1895 1895 - #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 1896 1896 - #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 1897 1897 - #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4 1898 1898 - #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 1899 1899 - #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 1900 1900 - /* Index of MC port being referred to */ 1901 1901 - #define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36 1902 1902 - #define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8 1903 1903 - /* FC Port index that matches the MC port index in SRC */ 1904 1904 - #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0 1905 1905 - #define FCDI_EVENT_PORT_CONFIG_DATA_LEN 4 1906 1906 - #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0 1907 1907 - #define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32 1908 1908 - #define FCDI_EVENT_BOOT_RESULT_OFST 0 1909 1909 - #define FCDI_EVENT_BOOT_RESULT_LEN 4 1910 1910 - /* Enum values, see field(s): */ 1911 1911 - /* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */ 1912 1912 - #define FCDI_EVENT_BOOT_RESULT_LBN 0 1913 1913 - #define FCDI_EVENT_BOOT_RESULT_WIDTH 32 1914 1914 - 1915 1915 - /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events 1916 1916 - * to the MC. Note that this structure | is overlayed over a normal FCDI event 1917 1917 - * such that bits 32-63 containing | event code, level, source etc remain the 1918 1918 - * same. In this case the data | field of the header is defined to be the 1919 1919 - * number of timestamps 1920 1920 - */ 1921 1921 - #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 1922 1922 - #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 1923 1923 - #define FCDI_EXTENDED_EVENT_PPS_LENMAX_MCDI2 1016 1924 1924 - #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) 1925 1925 - #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_NUM(len) (((len)-8)/8) 1926 1926 - /* Number of timestamps following */ 1927 1927 - #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 1928 1928 - #define FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4 1929 1929 - #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 1930 1930 - #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 1931 1931 - /* Seconds field of a timestamp record */ 1932 1932 - #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 1933 1933 - #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4 1934 1934 - #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 1935 1935 - #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 1936 1936 - /* Nanoseconds field of a timestamp record */ 1937 1937 - #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 1938 1938 - #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4 1939 1939 - #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 1940 1940 - #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 1941 1941 - /* Timestamp records comprising the event */ 1942 1942 - #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 1943 1943 - #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 1944 1944 - #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 1945 1945 - #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LEN 4 1946 1946 - #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LBN 64 1947 1947 - #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_WIDTH 32 1948 1948 - #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 1949 1949 - #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LEN 4 1950 1950 - #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LBN 96 1951 1951 - #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_WIDTH 32 1952 1952 - #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 1953 1953 - #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 1954 1954 - #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM_MCDI2 126 1955 1955 - #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 1956 1956 - #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 1957 1957 - 1958 1958 - /* MUM_EVENT structuredef */ 1959 1959 - #define MUM_EVENT_LEN 8 1960 1960 - #define MUM_EVENT_CONT_LBN 32 1961 1961 - #define MUM_EVENT_CONT_WIDTH 1 1962 1962 - #define MUM_EVENT_LEVEL_LBN 33 1963 1963 - #define MUM_EVENT_LEVEL_WIDTH 3 1964 1964 - /* enum: Info. */ 1965 1965 - #define MUM_EVENT_LEVEL_INFO 0x0 1966 1966 - /* enum: Warning. */ 1967 1967 - #define MUM_EVENT_LEVEL_WARN 0x1 1968 1968 - /* enum: Error. */ 1969 1969 - #define MUM_EVENT_LEVEL_ERR 0x2 1970 1970 - /* enum: Fatal. */ 1971 1971 - #define MUM_EVENT_LEVEL_FATAL 0x3 1972 1972 - #define MUM_EVENT_DATA_OFST 0 1973 1973 - #define MUM_EVENT_DATA_LEN 4 1974 1974 - #define MUM_EVENT_SENSOR_ID_OFST 0 1975 1975 - #define MUM_EVENT_SENSOR_ID_LBN 0 1976 1976 - #define MUM_EVENT_SENSOR_ID_WIDTH 8 1977 1977 - /* Enum values, see field(s): */ 1978 1978 - /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 1979 1979 - #define MUM_EVENT_SENSOR_STATE_OFST 0 1980 1980 - #define MUM_EVENT_SENSOR_STATE_LBN 8 1981 1981 - #define MUM_EVENT_SENSOR_STATE_WIDTH 8 1982 1982 - #define MUM_EVENT_PORT_PHY_READY_OFST 0 1983 1983 - #define MUM_EVENT_PORT_PHY_READY_LBN 0 1984 1984 - #define MUM_EVENT_PORT_PHY_READY_WIDTH 1 1985 1985 - #define MUM_EVENT_PORT_PHY_LINK_UP_OFST 0 1986 1986 - #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1 1987 1987 - #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1 1988 1988 - #define MUM_EVENT_PORT_PHY_TX_LOL_OFST 0 1989 1989 - #define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2 1990 1990 - #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1 1991 1991 - #define MUM_EVENT_PORT_PHY_RX_LOL_OFST 0 1992 1992 - #define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3 1993 1993 - #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1 1994 1994 - #define MUM_EVENT_PORT_PHY_TX_LOS_OFST 0 1995 1995 - #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4 1996 1996 - #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1 1997 1997 - #define MUM_EVENT_PORT_PHY_RX_LOS_OFST 0 1998 1998 - #define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5 1999 1999 - #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1 2000 2000 - #define MUM_EVENT_PORT_PHY_TX_FAULT_OFST 0 2001 2001 - #define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6 2002 2002 - #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1 2003 2003 - #define MUM_EVENT_DATA_LBN 0 2004 2004 - #define MUM_EVENT_DATA_WIDTH 32 2005 2005 - #define MUM_EVENT_SRC_LBN 36 2006 2006 - #define MUM_EVENT_SRC_WIDTH 8 2007 2007 - #define MUM_EVENT_EV_CODE_LBN 60 2008 2008 - #define MUM_EVENT_EV_CODE_WIDTH 4 2009 2009 - #define MUM_EVENT_CODE_LBN 44 2010 2010 - #define MUM_EVENT_CODE_WIDTH 8 2011 2011 - /* enum: The MUM was rebooted. */ 2012 2012 - #define MUM_EVENT_CODE_REBOOT 0x1 2013 2013 - /* enum: Bad assert. */ 2014 2014 - #define MUM_EVENT_CODE_ASSERT 0x2 2015 2015 - /* enum: Sensor failure. */ 2016 2016 - #define MUM_EVENT_CODE_SENSOR 0x3 2017 2017 - /* enum: Link fault has been asserted, or has cleared. */ 2018 2018 - #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4 2019 2019 - #define MUM_EVENT_SENSOR_DATA_OFST 0 2020 2020 - #define MUM_EVENT_SENSOR_DATA_LEN 4 2021 2021 - #define MUM_EVENT_SENSOR_DATA_LBN 0 2022 2022 - #define MUM_EVENT_SENSOR_DATA_WIDTH 32 2023 2023 - #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0 2024 2024 - #define MUM_EVENT_PORT_PHY_FLAGS_LEN 4 2025 2025 - #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0 2026 2026 - #define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32 2027 2027 - #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0 2028 2028 - #define MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 4 2029 2029 - #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0 2030 2030 - #define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32 2031 2031 - #define MUM_EVENT_PORT_PHY_CAPS_OFST 0 2032 2032 - #define MUM_EVENT_PORT_PHY_CAPS_LEN 4 2033 2033 - #define MUM_EVENT_PORT_PHY_CAPS_LBN 0 2034 2034 - #define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32 2035 2035 - #define MUM_EVENT_PORT_PHY_TECH_OFST 0 2036 2036 - #define MUM_EVENT_PORT_PHY_TECH_LEN 4 2037 2037 - #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */ 2038 2038 - #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */ 2039 2039 - #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */ 2040 2040 - #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */ 2041 2041 - #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */ 2042 2042 - #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */ 2043 2043 - #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */ 2044 2044 - #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */ 2045 2045 - #define MUM_EVENT_PORT_PHY_TECH_LBN 0 2046 2046 - #define MUM_EVENT_PORT_PHY_TECH_WIDTH 32 2047 2047 - #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36 2048 2048 - #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4 2049 2049 - #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */ 2050 2050 - #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */ 2051 2051 - #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */ 2052 2052 - #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */ 2053 2053 - #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */ 2054 2054 - #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40 2055 2055 - #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4 2056 2056 - 2057 1671 2058 1672 /***********************************/ 2059 1673 /* MC_CMD_READ32 ··· 1870 1966 1871 1967 /* MC_CMD_WRITE32_OUT msgresponse */ 1872 1968 #define MC_CMD_WRITE32_OUT_LEN 0 1873 1873 - 1874 1874 - 1875 1875 - /***********************************/ 1876 1876 - /* MC_CMD_COPYCODE 1877 1877 - * Copy MC code between two locations and jump. Note - this command really 1878 1878 - * belongs to INSECURE category but is required by shmboot. The command handler 1879 1879 - * has additional checks to reject insecure calls. 1880 1880 - */ 1881 1881 - #define MC_CMD_COPYCODE 0x3 1882 1882 - #undef MC_CMD_0x3_PRIVILEGE_CTG 1883 1883 - 1884 1884 - #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1885 1885 - 1886 1886 - /* MC_CMD_COPYCODE_IN msgrequest */ 1887 1887 - #define MC_CMD_COPYCODE_IN_LEN 16 1888 1888 - /* Source address 1889 1889 - * 1890 1890 - * The main image should be entered via a copy of a single word from and to a 1891 1891 - * magic address, which controls various aspects of the boot. The magic address 1892 1892 - * is a bitfield, with each bit as documented below. 1893 1893 - */ 1894 1894 - #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 1895 1895 - #define MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4 1896 1896 - /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */ 1897 1897 - #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 1898 1898 - /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and 1899 1899 - * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below) 1900 1900 - */ 1901 1901 - #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 1902 1902 - /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT, 1903 1903 - * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see 1904 1904 - * below) 1905 1905 - */ 1906 1906 - #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc 1907 1907 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_OFST 0 1908 1908 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17 1909 1909 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1 1910 1910 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_OFST 0 1911 1911 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2 1912 1912 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1 1913 1913 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_OFST 0 1914 1914 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3 1915 1915 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1 1916 1916 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_OFST 0 1917 1917 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4 1918 1918 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1 1919 1919 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_OFST 0 1920 1920 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5 1921 1921 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1 1922 1922 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_OFST 0 1923 1923 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6 1924 1924 - #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1 1925 1925 - /* Destination address */ 1926 1926 - #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 1927 1927 - #define MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4 1928 1928 - #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 1929 1929 - #define MC_CMD_COPYCODE_IN_NUMWORDS_LEN 4 1930 1930 - /* Address of where to jump after copy. */ 1931 1931 - #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 1932 1932 - #define MC_CMD_COPYCODE_IN_JUMP_LEN 4 1933 1933 - /* enum: Control should return to the caller rather than jumping */ 1934 1934 - #define MC_CMD_COPYCODE_JUMP_NONE 0x1 1935 1935 - 1936 1936 - /* MC_CMD_COPYCODE_OUT msgresponse */ 1937 1937 - #define MC_CMD_COPYCODE_OUT_LEN 0 1938 1938 - 1939 1939 - 1940 1940 - /***********************************/ 1941 1941 - /* MC_CMD_SET_FUNC 1942 1942 - * Select function for function-specific commands. 1943 1943 - */ 1944 1944 - #define MC_CMD_SET_FUNC 0x4 1945 1945 - #undef MC_CMD_0x4_PRIVILEGE_CTG 1946 1946 - 1947 1947 - #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE 1948 1948 - 1949 1949 - /* MC_CMD_SET_FUNC_IN msgrequest */ 1950 1950 - #define MC_CMD_SET_FUNC_IN_LEN 4 1951 1951 - /* Set function */ 1952 1952 - #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 1953 1953 - #define MC_CMD_SET_FUNC_IN_FUNC_LEN 4 1954 1954 - 1955 1955 - /* MC_CMD_SET_FUNC_OUT msgresponse */ 1956 1956 - #define MC_CMD_SET_FUNC_OUT_LEN 0 1957 1969 1958 1970 1959 1971 /***********************************/ ··· 2079 2259 /* Log destination */ 2080 2260 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 2081 2261 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4 2262 2262 + /* enum property: bitmask */ 2082 2263 /* enum: UART. */ 2083 2264 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 2084 2265 /* enum: Event queue. */ ··· 2125 2304 2126 2305 /* MC_CMD_GET_VERSION_OUT msgresponse */ 2127 2306 #define MC_CMD_GET_VERSION_OUT_LEN 32 2307 2307 + /* This is normally the UTC build time in seconds since epoch or one of the 2308 2308 + * special values listed 2309 2309 + */ 2128 2310 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 2129 2311 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */ 2130 2312 /* Enum values, see field(s): */ ··· 2150 2326 2151 2327 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ 2152 2328 #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 2329 2329 + /* This is normally the UTC build time in seconds since epoch or one of the 2330 2330 + * special values listed 2331 2331 + */ 2153 2332 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 2154 2333 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */ 2155 2334 /* Enum values, see field(s): */ ··· 2183 2356 * (depending on which components exist on a particular adapter) 2184 2357 */ 2185 2358 #define MC_CMD_GET_VERSION_V2_OUT_LEN 304 2359 2359 + /* This is normally the UTC build time in seconds since epoch or one of the 2360 2360 + * special values listed 2361 2361 + */ 2186 2362 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 2187 2363 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */ 2188 2364 /* Enum values, see field(s): */ ··· 2325 2495 * (depending on which components exist on a particular adapter) 2326 2496 */ 2327 2497 #define MC_CMD_GET_VERSION_V3_OUT_LEN 328 2498 2498 + /* This is normally the UTC build time in seconds since epoch or one of the 2499 2499 + * special values listed 2500 2500 + */ 2328 2501 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 2329 2502 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */ 2330 2503 /* Enum values, see field(s): */ ··· 2474 2641 * version information 2475 2642 */ 2476 2643 #define MC_CMD_GET_VERSION_V4_OUT_LEN 392 2644 2644 + /* This is normally the UTC build time in seconds since epoch or one of the 2645 2645 + * special values listed 2646 2646 + */ 2477 2647 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 2478 2648 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */ 2479 2649 /* Enum values, see field(s): */ ··· 2639 2803 * and board version information 2640 2804 */ 2641 2805 #define MC_CMD_GET_VERSION_V5_OUT_LEN 424 2806 2806 + /* This is normally the UTC build time in seconds since epoch or one of the 2807 2807 + * special values listed 2808 2808 + */ 2642 2809 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 2643 2810 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */ 2644 2811 /* Enum values, see field(s): */ ··· 2904 3065 * subscribers. 2905 3066 */ 2906 3067 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b 2907 2907 - /* enum: Above this for future use. */ 2908 2908 - #define MC_CMD_PTP_OP_MAX 0x1c 3068 3068 + /* enum: X4 and later adapters should use this instead of 3069 3069 + * PTP_OP_TIME_EVENT_SUBSCRIBE. Subscribe to receive periodic time events 3070 3070 + * indicating the current NIC time 3071 3071 + */ 3072 3072 + #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE_V2 0x1c 3073 3073 + /* enum: For X4 and later NICs. Packet timestamps and time sync events have 3074 3074 + * IS_SET and IN_SYNC flags, that indicates whether time is updated and if it 3075 3075 + * is in sync with host. Once set, IN_SYNC flag is cleared by hardware after a 3076 3076 + * software configurable time out. Host driver need to query what is set and 3077 3077 + * what is maximum supported interval, this MCDI can be used to query these. 3078 3078 + */ 3079 3079 + #define MC_CMD_PTP_OP_GET_SYNC_TIMEOUT 0x1d 2909 3080 2910 3081 /* MC_CMD_PTP_IN_ENABLE msgrequest */ 2911 3082 #define MC_CMD_PTP_IN_ENABLE_LEN 16 ··· 3356 3507 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 3357 3508 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4 3358 3509 3510 3510 + /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2 msgrequest */ 3511 3511 + #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_LEN 16 3512 3512 + /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3513 3513 + /* MC_CMD_PTP_IN_CMD_LEN 4 */ 3514 3514 + /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3515 3515 + /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 3516 3516 + /* Event queue ID */ 3517 3517 + #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_QUEUE_ID_OFST 8 3518 3518 + #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_QUEUE_ID_LEN 4 3519 3519 + /* Space for flags. */ 3520 3520 + #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_FLAGS_OFST 12 3521 3521 + #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_FLAGS_LEN 4 3522 3522 + #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_REPORT_SYNC_STATUS_OFST 12 3523 3523 + #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_REPORT_SYNC_STATUS_LBN 31 3524 3524 + #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_REPORT_SYNC_STATUS_WIDTH 1 3525 3525 + 3359 3526 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ 3360 3527 #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 3361 3528 /* MC_CMD_PTP_IN_CMD_OFST 0 */ ··· 3404 3539 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4 3405 3540 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20 3406 3541 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4 3542 3542 + 3543 3543 + /* MC_CMD_PTP_IN_GET_SYNC_TIMEOUT msgrequest */ 3544 3544 + #define MC_CMD_PTP_IN_GET_SYNC_TIMEOUT_LEN 8 3545 3545 + /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3546 3546 + /* MC_CMD_PTP_IN_CMD_LEN 4 */ 3547 3547 + /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3548 3548 + /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 3407 3549 3408 3550 /* MC_CMD_PTP_OUT msgresponse */ 3409 3551 #define MC_CMD_PTP_OUT_LEN 0 ··· 3811 3939 /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */ 3812 3940 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0 3813 3941 3814 3814 - 3815 3815 - /***********************************/ 3816 3816 - /* MC_CMD_CSR_READ32 3817 3817 - * Read 32bit words from the indirect memory map. 3818 3818 - */ 3819 3819 - #define MC_CMD_CSR_READ32 0xc 3820 3820 - #undef MC_CMD_0xc_PRIVILEGE_CTG 3821 3821 - 3822 3822 - #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE 3823 3823 - 3824 3824 - /* MC_CMD_CSR_READ32_IN msgrequest */ 3825 3825 - #define MC_CMD_CSR_READ32_IN_LEN 12 3826 3826 - /* Address */ 3827 3827 - #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 3828 3828 - #define MC_CMD_CSR_READ32_IN_ADDR_LEN 4 3829 3829 - #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 3830 3830 - #define MC_CMD_CSR_READ32_IN_STEP_LEN 4 3831 3831 - #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 3832 3832 - #define MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 4 3833 3833 - 3834 3834 - /* MC_CMD_CSR_READ32_OUT msgresponse */ 3835 3835 - #define MC_CMD_CSR_READ32_OUT_LENMIN 4 3836 3836 - #define MC_CMD_CSR_READ32_OUT_LENMAX 252 3837 3837 - #define MC_CMD_CSR_READ32_OUT_LENMAX_MCDI2 1020 3838 3838 - #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 3839 3839 - #define MC_CMD_CSR_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4) 3840 3840 - /* The last dword is the status, not a value read */ 3841 3841 - #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 3842 3842 - #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 3843 3843 - #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 3844 3844 - #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 3845 3845 - #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM_MCDI2 255 3846 3846 - 3847 3847 - 3848 3848 - /***********************************/ 3849 3849 - /* MC_CMD_CSR_WRITE32 3850 3850 - * Write 32bit dwords to the indirect memory map. 3851 3851 - */ 3852 3852 - #define MC_CMD_CSR_WRITE32 0xd 3853 3853 - #undef MC_CMD_0xd_PRIVILEGE_CTG 3854 3854 - 3855 3855 - #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE 3856 3856 - 3857 3857 - /* MC_CMD_CSR_WRITE32_IN msgrequest */ 3858 3858 - #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 3859 3859 - #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 3860 3860 - #define MC_CMD_CSR_WRITE32_IN_LENMAX_MCDI2 1020 3861 3861 - #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 3862 3862 - #define MC_CMD_CSR_WRITE32_IN_BUFFER_NUM(len) (((len)-8)/4) 3863 3863 - /* Address */ 3864 3864 - #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 3865 3865 - #define MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4 3866 3866 - #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 3867 3867 - #define MC_CMD_CSR_WRITE32_IN_STEP_LEN 4 3868 3868 - #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 3869 3869 - #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 3870 3870 - #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 3871 3871 - #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 3872 3872 - #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM_MCDI2 253 3873 3873 - 3874 3874 - /* MC_CMD_CSR_WRITE32_OUT msgresponse */ 3875 3875 - #define MC_CMD_CSR_WRITE32_OUT_LEN 4 3876 3876 - #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 3877 3877 - #define MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4 3878 3878 - 3879 3879 - 3880 3880 - /***********************************/ 3881 3881 - /* MC_CMD_HP 3882 3882 - * These commands are used for HP related features. They are grouped under one 3883 3883 - * MCDI command to avoid creating too many MCDI commands. 3884 3884 - */ 3885 3885 - #define MC_CMD_HP 0x54 3886 3886 - #undef MC_CMD_0x54_PRIVILEGE_CTG 3887 3887 - 3888 3888 - #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3889 3889 - 3890 3890 - /* MC_CMD_HP_IN msgrequest */ 3891 3891 - #define MC_CMD_HP_IN_LEN 16 3892 3892 - /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at 3893 3893 - * the specified address with the specified interval.When address is NULL, 3894 3894 - * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current 3895 3895 - * state / 2: (debug) Show temperature reported by one of the supported 3896 3896 - * sensors. 3897 3897 - */ 3898 3898 - #define MC_CMD_HP_IN_SUBCMD_OFST 0 3899 3899 - #define MC_CMD_HP_IN_SUBCMD_LEN 4 3900 3900 - /* enum: OCSD (Option Card Sensor Data) sub-command. */ 3901 3901 - #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 3902 3902 - /* enum: Last known valid HP sub-command. */ 3903 3903 - #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 3904 3904 - /* The address to the array of sensor fields. (Or NULL to use a sub-command.) 3905 3905 - */ 3906 3906 - #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 3907 3907 - #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 3908 3908 - #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 3909 3909 - #define MC_CMD_HP_IN_OCSD_ADDR_LO_LEN 4 3910 3910 - #define MC_CMD_HP_IN_OCSD_ADDR_LO_LBN 32 3911 3911 - #define MC_CMD_HP_IN_OCSD_ADDR_LO_WIDTH 32 3912 3912 - #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 3913 3913 - #define MC_CMD_HP_IN_OCSD_ADDR_HI_LEN 4 3914 3914 - #define MC_CMD_HP_IN_OCSD_ADDR_HI_LBN 64 3915 3915 - #define MC_CMD_HP_IN_OCSD_ADDR_HI_WIDTH 32 3916 3916 - /* The requested update interval, in seconds. (Or the sub-command if ADDR is 3917 3917 - * NULL.) 3918 3918 - */ 3919 3919 - #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 3920 3920 - #define MC_CMD_HP_IN_OCSD_INTERVAL_LEN 4 3921 3921 - 3922 3922 - /* MC_CMD_HP_OUT msgresponse */ 3923 3923 - #define MC_CMD_HP_OUT_LEN 4 3924 3924 - #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 3925 3925 - #define MC_CMD_HP_OUT_OCSD_STATUS_LEN 4 3926 3926 - /* enum: OCSD stopped for this card. */ 3927 3927 - #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 3928 3928 - /* enum: OCSD was successfully started with the address provided. */ 3929 3929 - #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 3930 3930 - /* enum: OCSD was already started for this card. */ 3931 3931 - #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 3932 3932 - 3933 3933 - 3934 3934 - /***********************************/ 3935 3935 - /* MC_CMD_STACKINFO 3936 3936 - * Get stack information. 3937 3937 - */ 3938 3938 - #define MC_CMD_STACKINFO 0xf 3939 3939 - #undef MC_CMD_0xf_PRIVILEGE_CTG 3940 3940 - 3941 3941 - #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3942 3942 - 3943 3943 - /* MC_CMD_STACKINFO_IN msgrequest */ 3944 3944 - #define MC_CMD_STACKINFO_IN_LEN 0 3945 3945 - 3946 3946 - /* MC_CMD_STACKINFO_OUT msgresponse */ 3947 3947 - #define MC_CMD_STACKINFO_OUT_LENMIN 12 3948 3948 - #define MC_CMD_STACKINFO_OUT_LENMAX 252 3949 3949 - #define MC_CMD_STACKINFO_OUT_LENMAX_MCDI2 1020 3950 3950 - #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 3951 3951 - #define MC_CMD_STACKINFO_OUT_THREAD_INFO_NUM(len) (((len)-0)/12) 3952 3952 - /* (thread ptr, stack size, free space) for each thread in system */ 3953 3953 - #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 3954 3954 - #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 3955 3955 - #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 3956 3956 - #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 3957 3957 - #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM_MCDI2 85 3958 3958 - 3959 3959 - 3960 3960 - /***********************************/ 3961 3961 - /* MC_CMD_MDIO_READ 3962 3962 - * MDIO register read. 3963 3963 - */ 3964 3964 - #define MC_CMD_MDIO_READ 0x10 3965 3965 - #undef MC_CMD_0x10_PRIVILEGE_CTG 3966 3966 - 3967 3967 - #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3968 3968 - 3969 3969 - /* MC_CMD_MDIO_READ_IN msgrequest */ 3970 3970 - #define MC_CMD_MDIO_READ_IN_LEN 16 3971 3971 - /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 3972 3972 - * external devices. 3973 3973 - */ 3974 3974 - #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 3975 3975 - #define MC_CMD_MDIO_READ_IN_BUS_LEN 4 3976 3976 - /* enum: Internal. */ 3977 3977 - #define MC_CMD_MDIO_BUS_INTERNAL 0x0 3978 3978 - /* enum: External. */ 3979 3979 - #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 3980 3980 - /* Port address */ 3981 3981 - #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 3982 3982 - #define MC_CMD_MDIO_READ_IN_PRTAD_LEN 4 3983 3983 - /* Device Address or clause 22. */ 3984 3984 - #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 3985 3985 - #define MC_CMD_MDIO_READ_IN_DEVAD_LEN 4 3986 3986 - /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 3987 3987 - * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 3988 3988 - */ 3989 3989 - #define MC_CMD_MDIO_CLAUSE22 0x20 3990 3990 - /* Address */ 3991 3991 - #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 3992 3992 - #define MC_CMD_MDIO_READ_IN_ADDR_LEN 4 3993 3993 - 3994 3994 - /* MC_CMD_MDIO_READ_OUT msgresponse */ 3995 3995 - #define MC_CMD_MDIO_READ_OUT_LEN 8 3996 3996 - /* Value */ 3997 3997 - #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 3998 3998 - #define MC_CMD_MDIO_READ_OUT_VALUE_LEN 4 3999 3999 - /* Status the MDIO commands return the raw status bits from the MDIO block. A 4000 4000 - * "good" transaction should have the DONE bit set and all other bits clear. 4001 4001 - */ 4002 4002 - #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 4003 4003 - #define MC_CMD_MDIO_READ_OUT_STATUS_LEN 4 4004 4004 - /* enum: Good. */ 4005 4005 - #define MC_CMD_MDIO_STATUS_GOOD 0x8 4006 4006 - 4007 4007 - 4008 4008 - /***********************************/ 4009 4009 - /* MC_CMD_MDIO_WRITE 4010 4010 - * MDIO register write. 4011 4011 - */ 4012 4012 - #define MC_CMD_MDIO_WRITE 0x11 4013 4013 - #undef MC_CMD_0x11_PRIVILEGE_CTG 4014 4014 - 4015 4015 - #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4016 4016 - 4017 4017 - /* MC_CMD_MDIO_WRITE_IN msgrequest */ 4018 4018 - #define MC_CMD_MDIO_WRITE_IN_LEN 20 4019 4019 - /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 4020 4020 - * external devices. 4021 4021 - */ 4022 4022 - #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 4023 4023 - #define MC_CMD_MDIO_WRITE_IN_BUS_LEN 4 4024 4024 - /* enum: Internal. */ 4025 4025 - /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 4026 4026 - /* enum: External. */ 4027 4027 - /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 4028 4028 - /* Port address */ 4029 4029 - #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 4030 4030 - #define MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4 4031 4031 - /* Device Address or clause 22. */ 4032 4032 - #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 4033 4033 - #define MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4 4034 4034 - /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 4035 4035 - * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 4036 4036 - */ 4037 4037 - /* MC_CMD_MDIO_CLAUSE22 0x20 */ 4038 4038 - /* Address */ 4039 4039 - #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 4040 4040 - #define MC_CMD_MDIO_WRITE_IN_ADDR_LEN 4 4041 4041 - /* Value */ 4042 4042 - #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 4043 4043 - #define MC_CMD_MDIO_WRITE_IN_VALUE_LEN 4 4044 4044 - 4045 4045 - /* MC_CMD_MDIO_WRITE_OUT msgresponse */ 4046 4046 - #define MC_CMD_MDIO_WRITE_OUT_LEN 4 4047 4047 - /* Status; the MDIO commands return the raw status bits from the MDIO block. A 4048 4048 - * "good" transaction should have the DONE bit set and all other bits clear. 4049 4049 - */ 4050 4050 - #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 4051 4051 - #define MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4 4052 4052 - /* enum: Good. */ 4053 4053 - /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 4054 4054 - 4055 4055 - 4056 4056 - /***********************************/ 4057 4057 - /* MC_CMD_DBI_WRITE 4058 4058 - * Write DBI register(s). 4059 4059 - */ 4060 4060 - #define MC_CMD_DBI_WRITE 0x12 4061 4061 - #undef MC_CMD_0x12_PRIVILEGE_CTG 4062 4062 - 4063 4063 - #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE 4064 4064 - 4065 4065 - /* MC_CMD_DBI_WRITE_IN msgrequest */ 4066 4066 - #define MC_CMD_DBI_WRITE_IN_LENMIN 12 4067 4067 - #define MC_CMD_DBI_WRITE_IN_LENMAX 252 4068 4068 - #define MC_CMD_DBI_WRITE_IN_LENMAX_MCDI2 1020 4069 4069 - #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 4070 4070 - #define MC_CMD_DBI_WRITE_IN_DBIWROP_NUM(len) (((len)-0)/12) 4071 4071 - /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset 4072 4072 - * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. 4073 4073 - */ 4074 4074 - #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 4075 4075 - #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 4076 4076 - #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 4077 4077 - #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 4078 4078 - #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM_MCDI2 85 4079 4079 - 4080 4080 - /* MC_CMD_DBI_WRITE_OUT msgresponse */ 4081 4081 - #define MC_CMD_DBI_WRITE_OUT_LEN 0 4082 4082 - 4083 4083 - /* MC_CMD_DBIWROP_TYPEDEF structuredef */ 4084 4084 - #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 4085 4085 - #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 4086 4086 - #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 4 4087 4087 - #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 4088 4088 - #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 4089 4089 - #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 4090 4090 - #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4 4091 4091 - #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_OFST 4 4092 4092 - #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 4093 4093 - #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 4094 4094 - #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_OFST 4 4095 4095 - #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 4096 4096 - #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 4097 4097 - #define MC_CMD_DBIWROP_TYPEDEF_CS2_OFST 4 4098 4098 - #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 4099 4099 - #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 4100 4100 - #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 4101 4101 - #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 4102 4102 - #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 4103 4103 - #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 4 4104 4104 - #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 4105 4105 - #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 4106 4106 - 4107 4107 - 4108 4108 - /***********************************/ 4109 4109 - /* MC_CMD_PORT_READ32 4110 4110 - * Read a 32-bit register from the indirect port register map. The port to 4111 4111 - * access is implied by the Shared memory channel used. 4112 4112 - */ 4113 4113 - #define MC_CMD_PORT_READ32 0x14 4114 4114 - 4115 4115 - /* MC_CMD_PORT_READ32_IN msgrequest */ 4116 4116 - #define MC_CMD_PORT_READ32_IN_LEN 4 4117 4117 - /* Address */ 4118 4118 - #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 4119 4119 - #define MC_CMD_PORT_READ32_IN_ADDR_LEN 4 4120 4120 - 4121 4121 - /* MC_CMD_PORT_READ32_OUT msgresponse */ 4122 4122 - #define MC_CMD_PORT_READ32_OUT_LEN 8 4123 4123 - /* Value */ 4124 4124 - #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 4125 4125 - #define MC_CMD_PORT_READ32_OUT_VALUE_LEN 4 4126 4126 - /* Status */ 4127 4127 - #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 4128 4128 - #define MC_CMD_PORT_READ32_OUT_STATUS_LEN 4 4129 4129 - 4130 4130 - 4131 4131 - /***********************************/ 4132 4132 - /* MC_CMD_PORT_WRITE32 4133 4133 - * Write a 32-bit register to the indirect port register map. The port to 4134 4134 - * access is implied by the Shared memory channel used. 4135 4135 - */ 4136 4136 - #define MC_CMD_PORT_WRITE32 0x15 4137 4137 - 4138 4138 - /* MC_CMD_PORT_WRITE32_IN msgrequest */ 4139 4139 - #define MC_CMD_PORT_WRITE32_IN_LEN 8 4140 4140 - /* Address */ 4141 4141 - #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 4142 4142 - #define MC_CMD_PORT_WRITE32_IN_ADDR_LEN 4 4143 4143 - /* Value */ 4144 4144 - #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 4145 4145 - #define MC_CMD_PORT_WRITE32_IN_VALUE_LEN 4 4146 4146 - 4147 4147 - /* MC_CMD_PORT_WRITE32_OUT msgresponse */ 4148 4148 - #define MC_CMD_PORT_WRITE32_OUT_LEN 4 4149 4149 - /* Status */ 4150 4150 - #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 4151 4151 - #define MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4 4152 4152 - 4153 4153 - 4154 4154 - /***********************************/ 4155 4155 - /* MC_CMD_PORT_READ128 4156 4156 - * Read a 128-bit register from the indirect port register map. The port to 4157 4157 - * access is implied by the Shared memory channel used. 4158 4158 - */ 4159 4159 - #define MC_CMD_PORT_READ128 0x16 4160 4160 - 4161 4161 - /* MC_CMD_PORT_READ128_IN msgrequest */ 4162 4162 - #define MC_CMD_PORT_READ128_IN_LEN 4 4163 4163 - /* Address */ 4164 4164 - #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 4165 4165 - #define MC_CMD_PORT_READ128_IN_ADDR_LEN 4 4166 4166 - 4167 4167 - /* MC_CMD_PORT_READ128_OUT msgresponse */ 4168 4168 - #define MC_CMD_PORT_READ128_OUT_LEN 20 4169 4169 - /* Value */ 4170 4170 - #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 4171 4171 - #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 4172 4172 - /* Status */ 4173 4173 - #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 4174 4174 - #define MC_CMD_PORT_READ128_OUT_STATUS_LEN 4 4175 4175 - 4176 4176 - 4177 4177 - /***********************************/ 4178 4178 - /* MC_CMD_PORT_WRITE128 4179 4179 - * Write a 128-bit register to the indirect port register map. The port to 4180 4180 - * access is implied by the Shared memory channel used. 4181 4181 - */ 4182 4182 - #define MC_CMD_PORT_WRITE128 0x17 4183 4183 - 4184 4184 - /* MC_CMD_PORT_WRITE128_IN msgrequest */ 4185 4185 - #define MC_CMD_PORT_WRITE128_IN_LEN 20 4186 4186 - /* Address */ 4187 4187 - #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 4188 4188 - #define MC_CMD_PORT_WRITE128_IN_ADDR_LEN 4 4189 4189 - /* Value */ 4190 4190 - #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 4191 4191 - #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 4192 4192 - 4193 4193 - /* MC_CMD_PORT_WRITE128_OUT msgresponse */ 4194 4194 - #define MC_CMD_PORT_WRITE128_OUT_LEN 4 4195 4195 - /* Status */ 4196 4196 - #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 4197 4197 - #define MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 4 4198 4198 - 4199 4199 - /* MC_CMD_CAPABILITIES structuredef */ 4200 4200 - #define MC_CMD_CAPABILITIES_LEN 4 4201 4201 - /* Small buf table. */ 4202 4202 - #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 4203 4203 - #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 4204 4204 - /* Turbo mode (for Maranello). */ 4205 4205 - #define MC_CMD_CAPABILITIES_TURBO_LBN 1 4206 4206 - #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 4207 4207 - /* Turbo mode active (for Maranello). */ 4208 4208 - #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 4209 4209 - #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 4210 4210 - /* PTP offload. */ 4211 4211 - #define MC_CMD_CAPABILITIES_PTP_LBN 3 4212 4212 - #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 4213 4213 - /* AOE mode. */ 4214 4214 - #define MC_CMD_CAPABILITIES_AOE_LBN 4 4215 4215 - #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 4216 4216 - /* AOE mode active. */ 4217 4217 - #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 4218 4218 - #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 4219 4219 - /* AOE mode active. */ 4220 4220 - #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 4221 4221 - #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 4222 4222 - #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 4223 4223 - #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 3942 3942 + /* MC_CMD_PTP_OUT_GET_SYNC_TIMEOUT msgresponse */ 3943 3943 + #define MC_CMD_PTP_OUT_GET_SYNC_TIMEOUT_LEN 8 3944 3944 + /* Current value set in NIC, in seconds */ 3945 3945 + #define MC_CMD_PTP_OUT_GET_SYNC_TIMEOUT_CURRENT_OFST 0 3946 3946 + #define MC_CMD_PTP_OUT_GET_SYNC_TIMEOUT_CURRENT_LEN 4 3947 3947 + /* Maximum supported by NIC, in seconds */ 3948 3948 + #define MC_CMD_PTP_OUT_GET_SYNC_TIMEOUT_MAXIMUM_OFST 4 3949 3949 + #define MC_CMD_PTP_OUT_GET_SYNC_TIMEOUT_MAXIMUM_LEN 4 4224 3950 4225 3951 4226 3952 /***********************************/ ··· 3894 4424 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 3895 4425 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 3896 4426 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM_MCDI2 32 3897 3897 - 3898 3898 - 3899 3899 - /***********************************/ 3900 3900 - /* MC_CMD_DBI_READX 3901 3901 - * Read DBI register(s) -- extended functionality 3902 3902 - */ 3903 3903 - #define MC_CMD_DBI_READX 0x19 3904 3904 - #undef MC_CMD_0x19_PRIVILEGE_CTG 3905 3905 - 3906 3906 - #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE 3907 3907 - 3908 3908 - /* MC_CMD_DBI_READX_IN msgrequest */ 3909 3909 - #define MC_CMD_DBI_READX_IN_LENMIN 8 3910 3910 - #define MC_CMD_DBI_READX_IN_LENMAX 248 3911 3911 - #define MC_CMD_DBI_READX_IN_LENMAX_MCDI2 1016 3912 3912 - #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 3913 3913 - #define MC_CMD_DBI_READX_IN_DBIRDOP_NUM(len) (((len)-0)/8) 3914 3914 - /* Each Read op consists of an address (offset 0), VF/CS2) */ 3915 3915 - #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 3916 3916 - #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 3917 3917 - #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 3918 3918 - #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_LEN 4 3919 3919 - #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_LBN 0 3920 3920 - #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_WIDTH 32 3921 3921 - #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 3922 3922 - #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_LEN 4 3923 3923 - #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_LBN 32 3924 3924 - #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_WIDTH 32 3925 3925 - #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 3926 3926 - #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 3927 3927 - #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM_MCDI2 127 3928 3928 - 3929 3929 - /* MC_CMD_DBI_READX_OUT msgresponse */ 3930 3930 - #define MC_CMD_DBI_READX_OUT_LENMIN 4 3931 3931 - #define MC_CMD_DBI_READX_OUT_LENMAX 252 3932 3932 - #define MC_CMD_DBI_READX_OUT_LENMAX_MCDI2 1020 3933 3933 - #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 3934 3934 - #define MC_CMD_DBI_READX_OUT_VALUE_NUM(len) (((len)-0)/4) 3935 3935 - /* Value */ 3936 3936 - #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 3937 3937 - #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 3938 3938 - #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 3939 3939 - #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 3940 3940 - #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM_MCDI2 255 3941 3941 - 3942 3942 - /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ 3943 3943 - #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 3944 3944 - #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 3945 3945 - #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 4 3946 3946 - #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 3947 3947 - #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 3948 3948 - #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 3949 3949 - #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4 3950 3950 - #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_OFST 4 3951 3951 - #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 3952 3952 - #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 3953 3953 - #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_OFST 4 3954 3954 - #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 3955 3955 - #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 3956 3956 - #define MC_CMD_DBIRDOP_TYPEDEF_CS2_OFST 4 3957 3957 - #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 3958 3958 - #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 3959 3959 - #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 3960 3960 - #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 3961 3961 - 3962 3962 - 3963 3963 - /***********************************/ 3964 3964 - /* MC_CMD_SET_RAND_SEED 3965 3965 - * Set the 16byte seed for the MC pseudo-random generator. 3966 3966 - */ 3967 3967 - #define MC_CMD_SET_RAND_SEED 0x1a 3968 3968 - #undef MC_CMD_0x1a_PRIVILEGE_CTG 3969 3969 - 3970 3970 - #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE 3971 3971 - 3972 3972 - /* MC_CMD_SET_RAND_SEED_IN msgrequest */ 3973 3973 - #define MC_CMD_SET_RAND_SEED_IN_LEN 16 3974 3974 - /* Seed value. */ 3975 3975 - #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 3976 3976 - #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 3977 3977 - 3978 3978 - /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 3979 3979 - #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 3980 3980 - 3981 3981 - 3982 3982 - /***********************************/ 3983 3983 - /* MC_CMD_LTSSM_HIST 3984 3984 - * Retrieve the history of the LTSSM, if the build supports it. 3985 3985 - */ 3986 3986 - #define MC_CMD_LTSSM_HIST 0x1b 3987 3987 - 3988 3988 - /* MC_CMD_LTSSM_HIST_IN msgrequest */ 3989 3989 - #define MC_CMD_LTSSM_HIST_IN_LEN 0 3990 3990 - 3991 3991 - /* MC_CMD_LTSSM_HIST_OUT msgresponse */ 3992 3992 - #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 3993 3993 - #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 3994 3994 - #define MC_CMD_LTSSM_HIST_OUT_LENMAX_MCDI2 1020 3995 3995 - #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 3996 3996 - #define MC_CMD_LTSSM_HIST_OUT_DATA_NUM(len) (((len)-0)/4) 3997 3997 - /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ 3998 3998 - #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 3999 3999 - #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 4000 4000 - #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 4001 4001 - #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 4002 4002 - #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM_MCDI2 255 4003 4427 4004 4428 4005 4429 /***********************************/ ··· 4069 4705 /* Flags associated with this function */ 4070 4706 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 4071 4707 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4 4708 4708 + /* enum property: bitshift */ 4072 4709 /* enum: Labels the lowest-numbered function visible to the OS */ 4073 4710 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 4074 4711 /* enum: The function can control the link state of the physical port it is ··· 4094 4729 * also has the effect that only even-numbered RXQs will receive traffic. 4095 4730 */ 4096 4731 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TX_ONLY_VI_SPREADING_ENABLED 0x5 4097 4097 - 4098 4098 - 4099 4099 - /***********************************/ 4100 4100 - /* MC_CMD_SHMUART 4101 4101 - * Route UART output to circular buffer in shared memory instead. 4102 4102 - */ 4103 4103 - #define MC_CMD_SHMUART 0x1f 4104 4104 - 4105 4105 - /* MC_CMD_SHMUART_IN msgrequest */ 4106 4106 - #define MC_CMD_SHMUART_IN_LEN 4 4107 4107 - /* ??? */ 4108 4108 - #define MC_CMD_SHMUART_IN_FLAG_OFST 0 4109 4109 - #define MC_CMD_SHMUART_IN_FLAG_LEN 4 4110 4110 - 4111 4111 - /* MC_CMD_SHMUART_OUT msgresponse */ 4112 4112 - #define MC_CMD_SHMUART_OUT_LEN 0 4113 4732 4114 4733 4115 4734 /***********************************/ ··· 4136 4787 4137 4788 /* MC_CMD_ENTITY_RESET_OUT msgresponse */ 4138 4789 #define MC_CMD_ENTITY_RESET_OUT_LEN 0 4139 4139 - 4140 4140 - 4141 4141 - /***********************************/ 4142 4142 - /* MC_CMD_PCIE_CREDITS 4143 4143 - * Read instantaneous and minimum flow control thresholds. 4144 4144 - */ 4145 4145 - #define MC_CMD_PCIE_CREDITS 0x21 4146 4146 - 4147 4147 - /* MC_CMD_PCIE_CREDITS_IN msgrequest */ 4148 4148 - #define MC_CMD_PCIE_CREDITS_IN_LEN 8 4149 4149 - /* poll period. 0 is disabled */ 4150 4150 - #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 4151 4151 - #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 4 4152 4152 - /* wipe statistics */ 4153 4153 - #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 4154 4154 - #define MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 4 4155 4155 - 4156 4156 - /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 4157 4157 - #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 4158 4158 - #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 4159 4159 - #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 4160 4160 - #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 4161 4161 - #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 4162 4162 - #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 4163 4163 - #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 4164 4164 - #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 4165 4165 - #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 4166 4166 - #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 4167 4167 - #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 4168 4168 - #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 4169 4169 - #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 4170 4170 - #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 4171 4171 - #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 4172 4172 - #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 4173 4173 - #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 4174 4174 - 4175 4175 - 4176 4176 - /***********************************/ 4177 4177 - /* MC_CMD_RXD_MONITOR 4178 4178 - * Get histogram of RX queue fill level. 4179 4179 - */ 4180 4180 - #define MC_CMD_RXD_MONITOR 0x22 4181 4181 - 4182 4182 - /* MC_CMD_RXD_MONITOR_IN msgrequest */ 4183 4183 - #define MC_CMD_RXD_MONITOR_IN_LEN 12 4184 4184 - #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 4185 4185 - #define MC_CMD_RXD_MONITOR_IN_QID_LEN 4 4186 4186 - #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 4187 4187 - #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 4 4188 4188 - #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 4189 4189 - #define MC_CMD_RXD_MONITOR_IN_WIPE_LEN 4 4190 4190 - 4191 4191 - /* MC_CMD_RXD_MONITOR_OUT msgresponse */ 4192 4192 - #define MC_CMD_RXD_MONITOR_OUT_LEN 80 4193 4193 - #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 4194 4194 - #define MC_CMD_RXD_MONITOR_OUT_QID_LEN 4 4195 4195 - #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 4196 4196 - #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 4 4197 4197 - #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 4198 4198 - #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 4 4199 4199 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 4200 4200 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 4 4201 4201 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 4202 4202 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 4 4203 4203 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 4204 4204 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 4 4205 4205 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 4206 4206 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 4 4207 4207 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 4208 4208 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 4 4209 4209 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 4210 4210 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 4 4211 4211 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 4212 4212 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 4 4213 4213 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 4214 4214 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 4 4215 4215 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 4216 4216 - #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 4 4217 4217 - #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 4218 4218 - #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 4 4219 4219 - #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 4220 4220 - #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 4 4221 4221 - #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 4222 4222 - #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 4 4223 4223 - #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 4224 4224 - #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 4 4225 4225 - #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 4226 4226 - #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 4 4227 4227 - #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 4228 4228 - #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 4 4229 4229 - #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 4230 4230 - #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 4 4231 4231 - #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 4232 4232 - #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4 4233 4790 4234 4791 4235 4792 /***********************************/ ··· 4185 4930 4186 4931 /* MC_CMD_GET_PHY_CFG_IN msgrequest */ 4187 4932 #define MC_CMD_GET_PHY_CFG_IN_LEN 0 4933 4933 + 4934 4934 + /* MC_CMD_GET_PHY_CFG_IN_V2 msgrequest */ 4935 4935 + #define MC_CMD_GET_PHY_CFG_IN_V2_LEN 8 4936 4936 + /* Target port to request PHY state for. Uses MAE_LINK_ENDPOINT_SELECTOR which 4937 4937 + * identifies a real or virtual network port by MAE port and link end. See the 4938 4938 + * structure definition for more details 4939 4939 + */ 4940 4940 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_OFST 0 4941 4941 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LEN 8 4942 4942 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LO_OFST 0 4943 4943 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LO_LEN 4 4944 4944 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LO_LBN 0 4945 4945 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LO_WIDTH 32 4946 4946 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_HI_OFST 4 4947 4947 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_HI_LEN 4 4948 4948 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_HI_LBN 32 4949 4949 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_HI_WIDTH 32 4950 4950 + /* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */ 4951 4951 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_OFST 0 4952 4952 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_LEN 4 4953 4953 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FLAT_OFST 0 4954 4954 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FLAT_LEN 4 4955 4955 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_TYPE_OFST 3 4956 4956 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_TYPE_LEN 1 4957 4957 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0 4958 4958 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3 4959 4959 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0 4960 4960 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4 4961 4961 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20 4962 4962 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4 4963 4963 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16 4964 4964 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4 4965 4965 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2 4966 4966 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1 4967 4967 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0 4968 4968 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2 4969 4969 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LINK_END_OFST 4 4970 4970 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LINK_END_LEN 4 4971 4971 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_OFST 0 4972 4972 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_LEN 8 4973 4973 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_LO_OFST 0 4974 4974 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_LO_LEN 4 4975 4975 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_LO_LBN 0 4976 4976 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_LO_WIDTH 32 4977 4977 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_HI_OFST 4 4978 4978 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_HI_LEN 4 4979 4979 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_HI_LBN 32 4980 4980 + #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_HI_WIDTH 32 4188 4981 4189 4982 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 4190 4983 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 ··· 4329 5026 #define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_OFST 8 4330 5027 #define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 21 4331 5028 #define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1 5029 5029 + #define MC_CMD_PHY_CAP_200000FDX_OFST 8 5030 5030 + #define MC_CMD_PHY_CAP_200000FDX_LBN 22 5031 5031 + #define MC_CMD_PHY_CAP_200000FDX_WIDTH 1 4332 5032 /* ?? */ 4333 5033 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 4334 5034 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4 ··· 4365 5059 #define MC_CMD_MEDIA_DSFP 0x8 4366 5060 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 4367 5061 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4 5062 5062 + /* enum property: bitshift */ 4368 5063 /* enum: Native clause 22 */ 4369 5064 #define MC_CMD_MMD_CLAUSE22 0x0 4370 5065 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ ··· 4391 5084 #define MC_CMD_START_BIST 0x25 4392 5085 #undef MC_CMD_0x25_PRIVILEGE_CTG 4393 5086 4394 4394 - #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5087 5087 + #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 4395 5088 4396 5089 /* MC_CMD_START_BIST_IN msgrequest */ 4397 5090 #define MC_CMD_START_BIST_IN_LEN 4 ··· 4431 5124 #define MC_CMD_POLL_BIST 0x26 4432 5125 #undef MC_CMD_0x26_PRIVILEGE_CTG 4433 5126 4434 4434 - #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5127 5127 + #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 4435 5128 4436 5129 /* MC_CMD_POLL_BIST_IN msgrequest */ 4437 5130 #define MC_CMD_POLL_BIST_IN_LEN 0 ··· 4589 5282 4590 5283 4591 5284 /***********************************/ 4592 4592 - /* MC_CMD_FLUSH_RX_QUEUES 4593 4593 - * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ 4594 4594 - * flushes should be initiated via this MCDI operation, rather than via 4595 4595 - * directly writing FLUSH_CMD. 4596 4596 - * 4597 4597 - * The flush is completed (either done/fail) asynchronously (after this command 4598 4598 - * returns). The driver must still wait for flush done/failure events as usual. 4599 4599 - */ 4600 4600 - #define MC_CMD_FLUSH_RX_QUEUES 0x27 4601 4601 - 4602 4602 - /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 4603 4603 - #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 4604 4604 - #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 4605 4605 - #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX_MCDI2 1020 4606 4606 - #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 4607 4607 - #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_NUM(len) (((len)-0)/4) 4608 4608 - #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 4609 4609 - #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 4610 4610 - #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 4611 4611 - #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 4612 4612 - #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM_MCDI2 255 4613 4613 - 4614 4614 - /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 4615 4615 - #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 4616 4616 - 4617 4617 - 4618 4618 - /***********************************/ 4619 5285 /* MC_CMD_GET_LOOPBACK_MODES 4620 5286 * Returns a bitmask of loopback modes available at each speed. 4621 5287 */ ··· 4599 5319 4600 5320 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 4601 5321 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 5322 5322 + 5323 5323 + /* MC_CMD_GET_LOOPBACK_MODES_IN_V2 msgrequest */ 5324 5324 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_LEN 8 5325 5325 + /* Target port to request loopback modes for. Uses MAE_LINK_ENDPOINT_SELECTOR 5326 5326 + * which identifies a real or virtual network port by MAE port and link end. 5327 5327 + * See the structure definition for more details 5328 5328 + */ 5329 5329 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_OFST 0 5330 5330 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LEN 8 5331 5331 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LO_OFST 0 5332 5332 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LO_LEN 4 5333 5333 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LO_LBN 0 5334 5334 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LO_WIDTH 32 5335 5335 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_HI_OFST 4 5336 5336 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_HI_LEN 4 5337 5337 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_HI_LBN 32 5338 5338 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_HI_WIDTH 32 5339 5339 + /* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */ 5340 5340 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_OFST 0 5341 5341 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_LEN 4 5342 5342 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FLAT_OFST 0 5343 5343 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FLAT_LEN 4 5344 5344 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_TYPE_OFST 3 5345 5345 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_TYPE_LEN 1 5346 5346 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0 5347 5347 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3 5348 5348 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0 5349 5349 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4 5350 5350 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20 5351 5351 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4 5352 5352 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16 5353 5353 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4 5354 5354 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2 5355 5355 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1 5356 5356 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0 5357 5357 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2 5358 5358 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LINK_END_OFST 4 5359 5359 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LINK_END_LEN 4 5360 5360 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_OFST 0 5361 5361 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_LEN 8 5362 5362 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_LO_OFST 0 5363 5363 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_LO_LEN 4 5364 5364 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_LO_LBN 0 5365 5365 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_LO_WIDTH 32 5366 5366 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_HI_OFST 4 5367 5367 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_HI_LEN 4 5368 5368 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_HI_LBN 32 5369 5369 + #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_HI_WIDTH 32 4602 5370 4603 5371 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 4604 5372 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 ··· 4661 5333 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LEN 4 4662 5334 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LBN 32 4663 5335 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_WIDTH 32 5336 5336 + /* enum property: bitshift */ 4664 5337 /* enum: None. */ 4665 5338 #define MC_CMD_LOOPBACK_NONE 0x0 4666 5339 /* enum: Data. */ ··· 4751 5422 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LEN 4 4752 5423 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LBN 96 4753 5424 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_WIDTH 32 5425 5425 + /* enum property: bitshift */ 4754 5426 /* Enum values, see field(s): */ 4755 5427 /* 100M */ 4756 5428 /* Supported loopbacks. */ ··· 4765 5435 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LEN 4 4766 5436 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LBN 160 4767 5437 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_WIDTH 32 5438 5438 + /* enum property: bitshift */ 4768 5439 /* Enum values, see field(s): */ 4769 5440 /* 100M */ 4770 5441 /* Supported loopbacks. */ ··· 4779 5448 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LEN 4 4780 5449 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LBN 224 4781 5450 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_WIDTH 32 5451 5451 + /* enum property: bitshift */ 4782 5452 /* Enum values, see field(s): */ 4783 5453 /* 100M */ 4784 5454 /* Supported loopbacks. */ ··· 4793 5461 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LEN 4 4794 5462 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LBN 288 4795 5463 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_WIDTH 32 5464 5464 + /* enum property: bitshift */ 4796 5465 /* Enum values, see field(s): */ 4797 5466 /* 100M */ 4798 5467 ··· 4812 5479 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LEN 4 4813 5480 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LBN 32 4814 5481 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_WIDTH 32 5482 5482 + /* enum property: bitshift */ 4815 5483 /* enum: None. */ 4816 5484 /* MC_CMD_LOOPBACK_NONE 0x0 */ 4817 5485 /* enum: Data. */ ··· 4902 5568 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LEN 4 4903 5569 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LBN 96 4904 5570 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_WIDTH 32 5571 5571 + /* enum property: bitshift */ 4905 5572 /* Enum values, see field(s): */ 4906 5573 /* 100M */ 4907 5574 /* Supported loopbacks. */ ··· 4916 5581 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LEN 4 4917 5582 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LBN 160 4918 5583 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_WIDTH 32 5584 5584 + /* enum property: bitshift */ 4919 5585 /* Enum values, see field(s): */ 4920 5586 /* 100M */ 4921 5587 /* Supported loopbacks. */ ··· 4930 5594 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LEN 4 4931 5595 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LBN 224 4932 5596 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_WIDTH 32 5597 5597 + /* enum property: bitshift */ 4933 5598 /* Enum values, see field(s): */ 4934 5599 /* 100M */ 4935 5600 /* Supported loopbacks. */ ··· 4944 5607 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LEN 4 4945 5608 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LBN 288 4946 5609 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_WIDTH 32 5610 5610 + /* enum property: bitshift */ 4947 5611 /* Enum values, see field(s): */ 4948 5612 /* 100M */ 4949 5613 /* Supported 25G loopbacks. */ ··· 4958 5620 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LEN 4 4959 5621 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LBN 352 4960 5622 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_WIDTH 32 5623 5623 + /* enum property: bitshift */ 4961 5624 /* Enum values, see field(s): */ 4962 5625 /* 100M */ 4963 5626 /* Supported 50 loopbacks. */ ··· 4972 5633 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LEN 4 4973 5634 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LBN 416 4974 5635 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_WIDTH 32 5636 5636 + /* enum property: bitshift */ 4975 5637 /* Enum values, see field(s): */ 4976 5638 /* 100M */ 4977 5639 /* Supported 100G loopbacks. */ ··· 4986 5646 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LEN 4 4987 5647 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LBN 480 4988 5648 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_WIDTH 32 5649 5649 + /* enum property: bitshift */ 5650 5650 + /* Enum values, see field(s): */ 5651 5651 + /* 100M */ 5652 5652 + 5653 5653 + /* MC_CMD_GET_LOOPBACK_MODES_OUT_V3 msgresponse: Supported loopback modes for 5654 5654 + * newer NICs with 200G support 5655 5655 + */ 5656 5656 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_LEN 72 5657 5657 + /* Supported loopbacks. */ 5658 5658 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_OFST 0 5659 5659 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_LEN 8 5660 5660 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_LO_OFST 0 5661 5661 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_LO_LEN 4 5662 5662 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_LO_LBN 0 5663 5663 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_LO_WIDTH 32 5664 5664 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_HI_OFST 4 5665 5665 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_HI_LEN 4 5666 5666 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_HI_LBN 32 5667 5667 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_HI_WIDTH 32 5668 5668 + /* enum property: bitshift */ 5669 5669 + /* enum: None. */ 5670 5670 + /* MC_CMD_LOOPBACK_NONE 0x0 */ 5671 5671 + /* enum: Data. */ 5672 5672 + /* MC_CMD_LOOPBACK_DATA 0x1 */ 5673 5673 + /* enum: GMAC. */ 5674 5674 + /* MC_CMD_LOOPBACK_GMAC 0x2 */ 5675 5675 + /* enum: XGMII. */ 5676 5676 + /* MC_CMD_LOOPBACK_XGMII 0x3 */ 5677 5677 + /* enum: XGXS. */ 5678 5678 + /* MC_CMD_LOOPBACK_XGXS 0x4 */ 5679 5679 + /* enum: XAUI. */ 5680 5680 + /* MC_CMD_LOOPBACK_XAUI 0x5 */ 5681 5681 + /* enum: GMII. */ 5682 5682 + /* MC_CMD_LOOPBACK_GMII 0x6 */ 5683 5683 + /* enum: SGMII. */ 5684 5684 + /* MC_CMD_LOOPBACK_SGMII 0x7 */ 5685 5685 + /* enum: XGBR. */ 5686 5686 + /* MC_CMD_LOOPBACK_XGBR 0x8 */ 5687 5687 + /* enum: XFI. */ 5688 5688 + /* MC_CMD_LOOPBACK_XFI 0x9 */ 5689 5689 + /* enum: XAUI Far. */ 5690 5690 + /* MC_CMD_LOOPBACK_XAUI_FAR 0xa */ 5691 5691 + /* enum: GMII Far. */ 5692 5692 + /* MC_CMD_LOOPBACK_GMII_FAR 0xb */ 5693 5693 + /* enum: SGMII Far. */ 5694 5694 + /* MC_CMD_LOOPBACK_SGMII_FAR 0xc */ 5695 5695 + /* enum: XFI Far. */ 5696 5696 + /* MC_CMD_LOOPBACK_XFI_FAR 0xd */ 5697 5697 + /* enum: GPhy. */ 5698 5698 + /* MC_CMD_LOOPBACK_GPHY 0xe */ 5699 5699 + /* enum: PhyXS. */ 5700 5700 + /* MC_CMD_LOOPBACK_PHYXS 0xf */ 5701 5701 + /* enum: PCS. */ 5702 5702 + /* MC_CMD_LOOPBACK_PCS 0x10 */ 5703 5703 + /* enum: PMA-PMD. */ 5704 5704 + /* MC_CMD_LOOPBACK_PMAPMD 0x11 */ 5705 5705 + /* enum: Cross-Port. */ 5706 5706 + /* MC_CMD_LOOPBACK_XPORT 0x12 */ 5707 5707 + /* enum: XGMII-Wireside. */ 5708 5708 + /* MC_CMD_LOOPBACK_XGMII_WS 0x13 */ 5709 5709 + /* enum: XAUI Wireside. */ 5710 5710 + /* MC_CMD_LOOPBACK_XAUI_WS 0x14 */ 5711 5711 + /* enum: XAUI Wireside Far. */ 5712 5712 + /* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */ 5713 5713 + /* enum: XAUI Wireside near. */ 5714 5714 + /* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */ 5715 5715 + /* enum: GMII Wireside. */ 5716 5716 + /* MC_CMD_LOOPBACK_GMII_WS 0x17 */ 5717 5717 + /* enum: XFI Wireside. */ 5718 5718 + /* MC_CMD_LOOPBACK_XFI_WS 0x18 */ 5719 5719 + /* enum: XFI Wireside Far. */ 5720 5720 + /* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */ 5721 5721 + /* enum: PhyXS Wireside. */ 5722 5722 + /* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */ 5723 5723 + /* enum: PMA lanes MAC-Serdes. */ 5724 5724 + /* MC_CMD_LOOPBACK_PMA_INT 0x1b */ 5725 5725 + /* enum: KR Serdes Parallel (Encoder). */ 5726 5726 + /* MC_CMD_LOOPBACK_SD_NEAR 0x1c */ 5727 5727 + /* enum: KR Serdes Serial. */ 5728 5728 + /* MC_CMD_LOOPBACK_SD_FAR 0x1d */ 5729 5729 + /* enum: PMA lanes MAC-Serdes Wireside. */ 5730 5730 + /* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */ 5731 5731 + /* enum: KR Serdes Parallel Wireside (Full PCS). */ 5732 5732 + /* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */ 5733 5733 + /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 5734 5734 + /* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */ 5735 5735 + /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 5736 5736 + /* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */ 5737 5737 + /* enum: KR Serdes Serial Wireside. */ 5738 5738 + /* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */ 5739 5739 + /* enum: Near side of AOE Siena side port */ 5740 5740 + /* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */ 5741 5741 + /* enum: Medford Wireside datapath loopback */ 5742 5742 + /* MC_CMD_LOOPBACK_DATA_WS 0x24 */ 5743 5743 + /* enum: Force link up without setting up any physical loopback (snapper use 5744 5744 + * only) 5745 5745 + */ 5746 5746 + /* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */ 5747 5747 + /* Supported loopbacks. */ 5748 5748 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_OFST 8 5749 5749 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_LEN 8 5750 5750 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_LO_OFST 8 5751 5751 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_LO_LEN 4 5752 5752 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_LO_LBN 64 5753 5753 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_LO_WIDTH 32 5754 5754 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_HI_OFST 12 5755 5755 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_HI_LEN 4 5756 5756 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_HI_LBN 96 5757 5757 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_HI_WIDTH 32 5758 5758 + /* enum property: bitshift */ 5759 5759 + /* Enum values, see field(s): */ 5760 5760 + /* 100M */ 5761 5761 + /* Supported loopbacks. */ 5762 5762 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_OFST 16 5763 5763 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_LEN 8 5764 5764 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_LO_OFST 16 5765 5765 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_LO_LEN 4 5766 5766 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_LO_LBN 128 5767 5767 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_LO_WIDTH 32 5768 5768 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_HI_OFST 20 5769 5769 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_HI_LEN 4 5770 5770 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_HI_LBN 160 5771 5771 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_HI_WIDTH 32 5772 5772 + /* enum property: bitshift */ 5773 5773 + /* Enum values, see field(s): */ 5774 5774 + /* 100M */ 5775 5775 + /* Supported loopbacks. */ 5776 5776 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_OFST 24 5777 5777 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_LEN 8 5778 5778 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_LO_OFST 24 5779 5779 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_LO_LEN 4 5780 5780 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_LO_LBN 192 5781 5781 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_LO_WIDTH 32 5782 5782 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_HI_OFST 28 5783 5783 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_HI_LEN 4 5784 5784 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_HI_LBN 224 5785 5785 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_HI_WIDTH 32 5786 5786 + /* enum property: bitshift */ 5787 5787 + /* Enum values, see field(s): */ 5788 5788 + /* 100M */ 5789 5789 + /* Supported loopbacks. */ 5790 5790 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_OFST 32 5791 5791 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_LEN 8 5792 5792 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_LO_OFST 32 5793 5793 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_LO_LEN 4 5794 5794 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_LO_LBN 256 5795 5795 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_LO_WIDTH 32 5796 5796 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_HI_OFST 36 5797 5797 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_HI_LEN 4 5798 5798 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_HI_LBN 288 5799 5799 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_HI_WIDTH 32 5800 5800 + /* enum property: bitshift */ 5801 5801 + /* Enum values, see field(s): */ 5802 5802 + /* 100M */ 5803 5803 + /* Supported 25G loopbacks. */ 5804 5804 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_OFST 40 5805 5805 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_LEN 8 5806 5806 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_LO_OFST 40 5807 5807 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_LO_LEN 4 5808 5808 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_LO_LBN 320 5809 5809 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_LO_WIDTH 32 5810 5810 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_HI_OFST 44 5811 5811 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_HI_LEN 4 5812 5812 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_HI_LBN 352 5813 5813 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_HI_WIDTH 32 5814 5814 + /* enum property: bitshift */ 5815 5815 + /* Enum values, see field(s): */ 5816 5816 + /* 100M */ 5817 5817 + /* Supported 50 loopbacks. */ 5818 5818 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_OFST 48 5819 5819 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_LEN 8 5820 5820 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_LO_OFST 48 5821 5821 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_LO_LEN 4 5822 5822 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_LO_LBN 384 5823 5823 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_LO_WIDTH 32 5824 5824 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_HI_OFST 52 5825 5825 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_HI_LEN 4 5826 5826 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_HI_LBN 416 5827 5827 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_HI_WIDTH 32 5828 5828 + /* enum property: bitshift */ 5829 5829 + /* Enum values, see field(s): */ 5830 5830 + /* 100M */ 5831 5831 + /* Supported 100G loopbacks. */ 5832 5832 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_OFST 56 5833 5833 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_LEN 8 5834 5834 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_LO_OFST 56 5835 5835 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_LO_LEN 4 5836 5836 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_LO_LBN 448 5837 5837 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_LO_WIDTH 32 5838 5838 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_HI_OFST 60 5839 5839 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_HI_LEN 4 5840 5840 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_HI_LBN 480 5841 5841 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_HI_WIDTH 32 5842 5842 + /* enum property: bitshift */ 5843 5843 + /* Enum values, see field(s): */ 5844 5844 + /* 100M */ 5845 5845 + /* Supported 200G loopbacks. */ 5846 5846 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_OFST 64 5847 5847 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_LEN 8 5848 5848 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_LO_OFST 64 5849 5849 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_LO_LEN 4 5850 5850 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_LO_LBN 512 5851 5851 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_LO_WIDTH 32 5852 5852 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_HI_OFST 68 5853 5853 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_HI_LEN 4 5854 5854 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_HI_LBN 544 5855 5855 + #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_HI_WIDTH 32 5856 5856 + /* enum property: bitshift */ 4989 5857 /* Enum values, see field(s): */ 4990 5858 /* 100M */ 4991 5859 ··· 5221 5673 #define FEC_TYPE_TYPE_LEN 4 5222 5674 /* enum: No FEC */ 5223 5675 #define MC_CMD_FEC_NONE 0x0 5224 5224 - /* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */ 5676 5676 + /* enum: IEEE 802.3, Clause 74 BASE-R FEC (a.k.a Firecode) */ 5225 5677 #define MC_CMD_FEC_BASER 0x1 5226 5226 - /* enum: Clause 91/Clause 108 Reed-Solomon FEC */ 5678 5678 + /* enum: IEEE 802.3, Clause 91/Clause 108 Reed-Solomon FEC */ 5227 5679 #define MC_CMD_FEC_RS 0x2 5680 5680 + /* enum: IEEE 802.3, Clause 161, interleaved RS-FEC sublayer for 100GBASE-R 5681 5681 + * PHYs 5682 5682 + */ 5683 5683 + #define MC_CMD_FEC_IEEE_RS_INT 0x3 5684 5684 + /* enum: Ethernet Consortium, Low Latency RS-FEC. RS(272, 258). Replaces FEC 5685 5685 + * specified in Clause 119 for 100/200G PHY. Replaces FEC specified in Clause 5686 5686 + * 134 for 50G PHY. 5687 5687 + */ 5688 5688 + #define MC_CMD_FEC_ETCS_RS_LL 0x4 5689 5689 + /* enum: FEC mode selected automatically */ 5690 5690 + #define MC_CMD_FEC_AUTO 0x5 5228 5691 #define FEC_TYPE_TYPE_LBN 0 5229 5692 #define FEC_TYPE_TYPE_WIDTH 32 5693 5693 + 5694 5694 + /* MC_CMD_ETH_TECH structuredef: Ethernet technology as defined by IEEE802.3, 5695 5695 + * Ethernet Technology Consortium, proprietary technologies. The driver must 5696 5696 + * not use technologies labelled NONE and AUTO. 5697 5697 + */ 5698 5698 + #define MC_CMD_ETH_TECH_LEN 16 5699 5699 + /* The enums in this field can be used either as bitwise indices into a tech 5700 5700 + * mask (e.g. see MC_CMD_ETH_AN_FIELDS/TECH_MASK for example) or as regular 5701 5701 + * enums (e.g. see MC_CMD_LINK_CTRL_IN/ADVERTISED_TECH_ABILITIES_MASK). This 5702 5702 + * structure must be updated to add new technologies when projects that need 5703 5703 + * them arise. An incomplete list of possible expansion in the future include: 5704 5704 + * 100GBASE_KP4, 800GBASE_CR8, 800GBASE_KR8, 800GBASE_DR8, 800GBASE_SR8 5705 5705 + * 800GBASE_VR8 5706 5706 + */ 5707 5707 + #define MC_CMD_ETH_TECH_TECH_OFST 0 5708 5708 + #define MC_CMD_ETH_TECH_TECH_LEN 16 5709 5709 + /* enum: 1000BASE-KX - 1000BASE-X PCS/PMA over an electrical backplane PMD. See 5710 5710 + * IEEE 802.3 Clause 70 5711 5711 + */ 5712 5712 + #define MC_CMD_ETH_TECH_1000BASEKX 0x0 5713 5713 + /* enum: 10GBASE-R - PCS/PMA over an electrical backplane PMD. Refer to IEEE 5714 5714 + * 802.3 Clause 72 5715 5715 + */ 5716 5716 + #define MC_CMD_ETH_TECH_10GBASE_KR 0x1 5717 5717 + /* enum: 40GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3 5718 5718 + * Clause 84. 5719 5719 + */ 5720 5720 + #define MC_CMD_ETH_TECH_40GBASE_KR4 0x2 5721 5721 + /* enum: 40GBASE-R PCS/PMA over 4 lane shielded copper balanced cable PMD. See 5722 5722 + * IEEE 802.3 Clause 85 5723 5723 + */ 5724 5724 + #define MC_CMD_ETH_TECH_40GBASE_CR4 0x3 5725 5725 + /* enum: 40GBASE-R PCS/PMA over 4 lane multimode fiber PMD as specified in 5726 5726 + * Clause 86 5727 5727 + */ 5728 5728 + #define MC_CMD_ETH_TECH_40GBASE_SR4 0x4 5729 5729 + /* enum: 40GBASE-R PCS/PMA over 4 WDM lane single mode fiber PMD with long 5730 5730 + * reach. See IEEE 802.3 Clause 87 5731 5731 + */ 5732 5732 + #define MC_CMD_ETH_TECH_40GBASE_LR4 0x5 5733 5733 + /* enum: 25GBASE-R PCS/PMA over shielded balanced copper cable PMD. See IEEE 5734 5734 + * 802.3 Clause 110 5735 5735 + */ 5736 5736 + #define MC_CMD_ETH_TECH_25GBASE_CR 0x6 5737 5737 + /* enum: 25GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3 5738 5738 + * Clause 111 5739 5739 + */ 5740 5740 + #define MC_CMD_ETH_TECH_25GBASE_KR 0x7 5741 5741 + /* enum: 25GBASE-R PCS/PMA over multimode fiber PMD. Refer to IEEE 802.3 Clause 5742 5742 + * 112 5743 5743 + */ 5744 5744 + #define MC_CMD_ETH_TECH_25GBASE_SR 0x8 5745 5745 + /* enum: An Ethernet Physical layer operating at 50 Gb/s on twin-axial copper 5746 5746 + * cable. Refer to Ethernet Technology Consortium 25/50G Ethernet Spec. 5747 5747 + */ 5748 5748 + #define MC_CMD_ETH_TECH_50GBASE_CR2 0x9 5749 5749 + /* enum: An Ethernet Physical layer operating at 50 Gb/s on copper backplane. 5750 5750 + * Refer to Ethernet Technology Consortium 25/50G Ethernet Spec. 5751 5751 + */ 5752 5752 + #define MC_CMD_ETH_TECH_50GBASE_KR2 0xa 5753 5753 + /* enum: 100GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3 5754 5754 + * Clause 93 5755 5755 + */ 5756 5756 + #define MC_CMD_ETH_TECH_100GBASE_KR4 0xb 5757 5757 + /* enum: 100GBASE-R PCS/PMA over 4 lane multimode fiber PMD. See IEEE 802.3 5758 5758 + * Clause 95 5759 5759 + */ 5760 5760 + #define MC_CMD_ETH_TECH_100GBASE_SR4 0xc 5761 5761 + /* enum: 100GBASE-R PCS/PMA over 4 lane shielded copper balanced cable PMD. See 5762 5762 + * IEEE 802.3 Clause 92 5763 5763 + */ 5764 5764 + #define MC_CMD_ETH_TECH_100GBASE_CR4 0xd 5765 5765 + /* enum: 100GBASE-R PCS/PMA over 4 WDM lane single mode fiber PMD, with 5766 5766 + * long/extended reach,. See IEEE 802.3 Clause 88 5767 5767 + */ 5768 5768 + #define MC_CMD_ETH_TECH_100GBASE_LR4_ER4 0xe 5769 5769 + /* enum: An Ethernet Physical layer operating at 50 Gb/s on short reach fiber. 5770 5770 + * Refer to Ethernet Technology Consortium 25/50G Ethernet Spec. 5771 5771 + */ 5772 5772 + #define MC_CMD_ETH_TECH_50GBASE_SR2 0xf 5773 5773 + /* enum: 1000BASEX PCS/PMA. See IEEE 802.3 Clause 36 over undefined PMD, duplex 5774 5774 + * mode unknown 5775 5775 + */ 5776 5776 + #define MC_CMD_ETH_TECH_1000BASEX 0x10 5777 5777 + /* enum: Non-standardised. 10G direct attach */ 5778 5778 + #define MC_CMD_ETH_TECH_10GBASE_CR 0x11 5779 5779 + /* enum: 10GBASE-SR fiber over 850nm optics. See IEEE 802.3 Clause 52 */ 5780 5780 + #define MC_CMD_ETH_TECH_10GBASE_SR 0x12 5781 5781 + /* enum: 10GBASE-LR fiber over 1310nm optics. See IEEE 802.3 Clause 52 */ 5782 5782 + #define MC_CMD_ETH_TECH_10GBASE_LR 0x13 5783 5783 + /* enum: 10GBASE-LRM fiber over 1310 nm optics. See IEEE 802.3 Clause 68 */ 5784 5784 + #define MC_CMD_ETH_TECH_10GBASE_LRM 0x14 5785 5785 + /* enum: 10GBASE-ER fiber over 1550nm optics. See IEEE 802.3 Clause 52 */ 5786 5786 + #define MC_CMD_ETH_TECH_10GBASE_ER 0x15 5787 5787 + /* enum: 50GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3 5788 5788 + * Clause 137 5789 5789 + */ 5790 5790 + #define MC_CMD_ETH_TECH_50GBASE_KR 0x16 5791 5791 + /* enum: 50GBASE-SR PCS/PMA over multimode fiber PMD as specified in Clause 138 5792 5792 + */ 5793 5793 + #define MC_CMD_ETH_TECH_50GBASE_SR 0x17 5794 5794 + /* enum: 50GBASE-CR PCS/PMA over shielded copper balanced cable PMD. See IEEE 5795 5795 + * 802.3 Clause 136 5796 5796 + */ 5797 5797 + #define MC_CMD_ETH_TECH_50GBASE_CR 0x18 5798 5798 + /* enum: 50GBASE-R PCS/PMA over single mode fiber PMD as specified in Clause 5799 5799 + * 139. 5800 5800 + */ 5801 5801 + #define MC_CMD_ETH_TECH_50GBASE_LR_ER_FR 0x19 5802 5802 + /* enum: 100 Gb/s PHY using 100GBASE-R encoding over single-mode fiber with 5803 5803 + * reach up to at least 500 m (see IEEE 802.3 Clause 140) 5804 5804 + */ 5805 5805 + #define MC_CMD_ETH_TECH_50GBASE_DR 0x1a 5806 5806 + /* enum: 100GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3 5807 5807 + * Clause 137 5808 5808 + */ 5809 5809 + #define MC_CMD_ETH_TECH_100GBASE_KR2 0x1b 5810 5810 + /* enum: 100GBASE-R PCS/PMA over 2 lane multimode fiber PMD. See IEEE 802.3 5811 5811 + * Clause 138 5812 5812 + */ 5813 5813 + #define MC_CMD_ETH_TECH_100GBASE_SR2 0x1c 5814 5814 + /* enum: 100GBASE-R PCS/PMA over 2 lane shielded copper balanced cable PMD. See 5815 5815 + * IEEE 802.3 Clause 136 5816 5816 + */ 5817 5817 + #define MC_CMD_ETH_TECH_100GBASE_CR2 0x1d 5818 5818 + /* enum: Unknown source */ 5819 5819 + #define MC_CMD_ETH_TECH_100GBASE_LR2_ER2_FR2 0x1e 5820 5820 + /* enum: Unknown source */ 5821 5821 + #define MC_CMD_ETH_TECH_100GBASE_DR2 0x1f 5822 5822 + /* enum: 200GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3 5823 5823 + * Clause 137 5824 5824 + */ 5825 5825 + #define MC_CMD_ETH_TECH_200GBASE_KR4 0x20 5826 5826 + /* enum: 200GBASE-R PCS/PMA over 4 lane multimode fiber PMD. See IEEE 802.3 5827 5827 + * Clause 138 5828 5828 + */ 5829 5829 + #define MC_CMD_ETH_TECH_200GBASE_SR4 0x21 5830 5830 + /* enum: 200GBASE-R PCS/PMA over 4 WDM lane single-mode fiber PMD as specified 5831 5831 + * in Clause 122 5832 5832 + */ 5833 5833 + #define MC_CMD_ETH_TECH_200GBASE_LR4_ER4_FR4 0x22 5834 5834 + /* enum: 200GBASE-R PCS/PMA over 4-lane single-mode fiber PMD. See IEEE 802.3 5835 5835 + * Clause 121 5836 5836 + */ 5837 5837 + #define MC_CMD_ETH_TECH_200GBASE_DR4 0x23 5838 5838 + /* enum: 200GBASE-R PCS/PMA over 4 lane shielded copper balanced cable PMD as 5839 5839 + * specified in Clause 136 5840 5840 + */ 5841 5841 + #define MC_CMD_ETH_TECH_200GBASE_CR4 0x24 5842 5842 + /* enum: Ethernet Technology Consortium 400G AN Spec. 400GBASE-KR8 PMD uses 5843 5843 + * 802.3 Clause 137, but the number PMD lanes is 8. 5844 5844 + */ 5845 5845 + #define MC_CMD_ETH_TECH_400GBASE_KR8 0x25 5846 5846 + /* enum: 400GBASE-R PCS/PMA over 8-lane multimode fiber PMD. See IEEE 802.3 5847 5847 + * Clause 138 5848 5848 + */ 5849 5849 + #define MC_CMD_ETH_TECH_400GBASE_SR8 0x26 5850 5850 + /* enum: 400GBASE-R PCS/PMA over 8 WDM lane single-mode fiber PMD. See IEEE 5851 5851 + * 802.3 Clause 122 5852 5852 + */ 5853 5853 + #define MC_CMD_ETH_TECH_400GBASE_LR8_ER8_FR8 0x27 5854 5854 + /* enum: Unknown source */ 5855 5855 + #define MC_CMD_ETH_TECH_400GBASE_DR8 0x28 5856 5856 + /* enum: Ethernet Technology Consortium 400G AN Spec. 400GBASE-CR8 PMD uses 5857 5857 + * IEEE 802.3 Clause 136, but the number PMD lanes is 8. 5858 5858 + */ 5859 5859 + #define MC_CMD_ETH_TECH_400GBASE_CR8 0x29 5860 5860 + /* enum: 100GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3ck 5861 5861 + * Clause 163. 5862 5862 + */ 5863 5863 + #define MC_CMD_ETH_TECH_100GBASE_KR 0x2a 5864 5864 + /* enum: IEEE 802.3ck. 100G PHY with PMD as specified in Clause 167 over short 5865 5865 + * reach fiber 5866 5866 + */ 5867 5867 + #define MC_CMD_ETH_TECH_100GBASE_SR 0x2b 5868 5868 + /* enum: 100G PMD together with single-mode fiber medium. See IEEE 802.3 Clause 5869 5869 + * 140 5870 5870 + */ 5871 5871 + #define MC_CMD_ETH_TECH_100GBASE_LR_ER_FR 0x2c 5872 5872 + /* enum: 100GBASE-R PCS/PMA over shielded balanced copper cable PMD. See IEEE 5873 5873 + * 802.3 in Clause 162 IEEE 802.3ck. 5874 5874 + */ 5875 5875 + #define MC_CMD_ETH_TECH_100GBASE_CR 0x2d 5876 5876 + /* enum: 100G PMD together with single-mode fiber medium. See IEEE 802.3 Clause 5877 5877 + * 140 5878 5878 + */ 5879 5879 + #define MC_CMD_ETH_TECH_100GBASE_DR 0x2e 5880 5880 + /* enum: 200GBASE-R PCS/PMA over an electrical backplane PMD as specified in 5881 5881 + * Clause 163 IEEE 802.3ck 5882 5882 + */ 5883 5883 + #define MC_CMD_ETH_TECH_200GBASE_KR2 0x2f 5884 5884 + /* enum: 200G PHY with PMD as specified in Clause 167 over short reach fiber 5885 5885 + * IEEE 802.3ck 5886 5886 + */ 5887 5887 + #define MC_CMD_ETH_TECH_200GBASE_SR2 0x30 5888 5888 + /* enum: Unknown source */ 5889 5889 + #define MC_CMD_ETH_TECH_200GBASE_LR2_ER2_FR2 0x31 5890 5890 + /* enum: Unknown source */ 5891 5891 + #define MC_CMD_ETH_TECH_200GBASE_DR2 0x32 5892 5892 + /* enum: 200GBASE-R PCS/PMA over 2 lane shielded balanced copper cable PMD as 5893 5893 + * specified in Clause 162 IEEE 802.3ck. 5894 5894 + */ 5895 5895 + #define MC_CMD_ETH_TECH_200GBASE_CR2 0x33 5896 5896 + /* enum: 400GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3 5897 5897 + * Clause 163 IEEE 802.3ck. 5898 5898 + */ 5899 5899 + #define MC_CMD_ETH_TECH_400GBASE_KR4 0x34 5900 5900 + /* enum: 400G PHY with PMD over short reach fiber. See Clause 167 of IEEE 5901 5901 + * 802.3ck. 5902 5902 + */ 5903 5903 + #define MC_CMD_ETH_TECH_400GBASE_SR4 0x35 5904 5904 + /* enum: 400GBASE-R PCS/PMA over 4 WDM lane single-mode fiber PMD. See IEEE 5905 5905 + * 802.3 Clause 151 5906 5906 + */ 5907 5907 + #define MC_CMD_ETH_TECH_400GBASE_LR4_ER4_FR4 0x36 5908 5908 + /* enum: 400GBASE-R PCS/PMA over 4-lane single-mode fiber PMD as specified in 5909 5909 + * Clause 124 5910 5910 + */ 5911 5911 + #define MC_CMD_ETH_TECH_400GBASE_DR4 0x37 5912 5912 + /* enum: 400GBASE-R PCS/PMA over 4 lane shielded balanced copper cable PMD as 5913 5913 + * specified in Clause 162 of IEEE 802.3ck. 5914 5914 + */ 5915 5915 + #define MC_CMD_ETH_TECH_400GBASE_CR4 0x38 5916 5916 + /* enum: Automatic tech mode. The driver must not use this. */ 5917 5917 + #define MC_CMD_ETH_TECH_AUTO 0x39 5918 5918 + /* enum: See IEEE 802.3cc-2017 Clause 114 */ 5919 5919 + #define MC_CMD_ETH_TECH_25GBASE_LR_ER 0x3a 5920 5920 + /* enum: Up to 7 m over twinaxial copper cable assembly (10 lanes, 10 Gbit/s 5921 5921 + * each) See IEEE 802.3ba-2010 Clause 85 5922 5922 + */ 5923 5923 + #define MC_CMD_ETH_TECH_100GBASE_CR10 0x3b 5924 5924 + /* enum: Invalid tech mode. The driver must not use this. */ 5925 5925 + #define MC_CMD_ETH_TECH_NONE 0x7f 5926 5926 + #define MC_CMD_ETH_TECH_TECH_LBN 0 5927 5927 + #define MC_CMD_ETH_TECH_TECH_WIDTH 128 5928 5928 + 5929 5929 + /* MC_CMD_LINK_STATUS_FLAGS structuredef */ 5930 5930 + #define MC_CMD_LINK_STATUS_FLAGS_LEN 8 5931 5931 + /* Flags used to report the current configuration/state of the link. */ 5932 5932 + #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_OFST 0 5933 5933 + #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LEN 8 5934 5934 + #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_OFST 0 5935 5935 + #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_LEN 4 5936 5936 + #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_LBN 0 5937 5937 + #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_WIDTH 32 5938 5938 + #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_OFST 4 5939 5939 + #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_LEN 4 5940 5940 + #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_LBN 32 5941 5941 + #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_WIDTH 32 5942 5942 + /* enum property: bitshift */ 5943 5943 + /* enum: Whether we have overall link up */ 5944 5944 + #define MC_CMD_LINK_STATUS_FLAGS_LINK_UP 0x0 5945 5945 + /* enum: If set, the PHY has no external RX link synchronisation */ 5946 5946 + #define MC_CMD_LINK_STATUS_FLAGS_NO_PHY_LINK 0x1 5947 5947 + /* enum: If set, PMD/MDI is not connected (e.g. cable disconnected, module cage 5948 5948 + * empty) 5949 5949 + */ 5950 5950 + #define MC_CMD_LINK_STATUS_FLAGS_PMD_MDI_DISCONNECTED 0x2 5951 5951 + /* enum: Set on error while decoding module data (e.g. module EEPROM does not 5952 5952 + * contain valid values, has checksum errors, etc.) 5953 5953 + */ 5954 5954 + #define MC_CMD_LINK_STATUS_FLAGS_PMD_BAD 0x3 5955 5955 + /* enum: Set when module unsupported (e.g. unsupported link rate or link 5956 5956 + * technology) 5957 5957 + */ 5958 5958 + #define MC_CMD_LINK_STATUS_FLAGS_PMD_UNSUPPORTED 0x4 5959 5959 + /* enum: Set on error while communicating with the module (e.g. I2C errors 5960 5960 + * while reading EEPROM) 5961 5961 + */ 5962 5962 + #define MC_CMD_LINK_STATUS_FLAGS_PMD_COMMS_FAULT 0x5 5963 5963 + /* enum: Set on module overcurrent/overvoltage condition */ 5964 5964 + #define MC_CMD_LINK_STATUS_FLAGS_PMD_POWER_FAULT 0x6 5965 5965 + /* enum: Set on module overtemperature condition */ 5966 5966 + #define MC_CMD_LINK_STATUS_FLAGS_PMD_THERMAL_FAULT 0x7 5967 5967 + /* enum: If set, the module is indicating Loss of Signal */ 5968 5968 + #define MC_CMD_LINK_STATUS_FLAGS_PMD_LOS 0x8 5969 5969 + /* enum: If set, PMA is indicating loss of CDR lock (clock sync) */ 5970 5970 + #define MC_CMD_LINK_STATUS_FLAGS_PMA_NO_CDR_LOCK 0x9 5971 5971 + /* enum: If set, PMA is indicating loss of analog signal */ 5972 5972 + #define MC_CMD_LINK_STATUS_FLAGS_PMA_LOS 0xa 5973 5973 + /* enum: If set, PCS is indicating loss of block lock */ 5974 5974 + #define MC_CMD_LINK_STATUS_FLAGS_PCS_NO_BLOCK_LOCK 0xb 5975 5975 + /* enum: If set, PCS is indicating loss of alignment marker lock on one or more 5976 5976 + * lanes 5977 5977 + */ 5978 5978 + #define MC_CMD_LINK_STATUS_FLAGS_PCS_NO_AM_LOCK 0xc 5979 5979 + /* enum: If set, PCS is indicating loss of overall alignment lock */ 5980 5980 + #define MC_CMD_LINK_STATUS_FLAGS_PCS_NO_ALIGN_LOCK 0xd 5981 5981 + /* enum: If set, PCS is indicating high bit error rate condition. */ 5982 5982 + #define MC_CMD_LINK_STATUS_FLAGS_PCS_HI_BER 0xe 5983 5983 + /* enum: If set, FEC is indicating loss of FEC lock */ 5984 5984 + #define MC_CMD_LINK_STATUS_FLAGS_FEC_NO_LOCK 0xf 5985 5985 + /* enum: If set, indicates that the number of symbol errors in a 8192-codeword 5986 5986 + * window has exceeded the threshold K (417). 5987 5987 + */ 5988 5988 + #define MC_CMD_LINK_STATUS_FLAGS_FEC_HI_SER 0x10 5989 5989 + /* enum: If set, the receiver has detected the local FEC has degraded. */ 5990 5990 + #define MC_CMD_LINK_STATUS_FLAGS_FEC_LOCAL_DEGRADED 0x11 5991 5991 + /* enum: If set, the receiver has detected the remote FEC has degraded. */ 5992 5992 + #define MC_CMD_LINK_STATUS_FLAGS_FEC_RM_DEGRADED 0x12 5993 5993 + /* enum: If set, the number of symbol errors is over an internal threshold. */ 5994 5994 + #define MC_CMD_LINK_STATUS_FLAGS_FEC_DEGRADED_SER 0x13 5995 5995 + /* enum: If set, autonegotiation has detected an auto-negotiation capable link 5996 5996 + * partner 5997 5997 + */ 5998 5998 + #define MC_CMD_LINK_STATUS_FLAGS_AN_ABLE 0x14 5999 5999 + /* enum: If set, autonegotiation base page exchange has failed */ 6000 6000 + #define MC_CMD_LINK_STATUS_FLAGS_AN_BP_FAILED 0x15 6001 6001 + /* enum: If set, autonegotiation next page exchange has failed */ 6002 6002 + #define MC_CMD_LINK_STATUS_FLAGS_AN_NP_FAILED 0x16 6003 6003 + /* enum: If set, autonegotiation has failed to negotiate a common set of 6004 6004 + * capabilities 6005 6005 + */ 6006 6006 + #define MC_CMD_LINK_STATUS_FLAGS_AN_NO_HCD 0x17 6007 6007 + /* enum: If set, local end link training has failed to establish link training 6008 6008 + * frame lock on one or more lanes 6009 6009 + */ 6010 6010 + #define MC_CMD_LINK_STATUS_FLAGS_LT_NO_LOCAL_FRAME_LOCK 0x18 6011 6011 + /* enum: If set, remote end link training has failed to establish link training 6012 6012 + * frame lock on one or more lanes 6013 6013 + */ 6014 6014 + #define MC_CMD_LINK_STATUS_FLAGS_LT_NO_RM_FRAME_LOCK 0x19 6015 6015 + /* enum: If set, remote end has failed to assert Receiver Ready (link training 6016 6016 + * success) within the designated timeout 6017 6017 + */ 6018 6018 + #define MC_CMD_LINK_STATUS_FLAGS_LT_NO_RX_READY 0x1a 6019 6019 + #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LBN 0 6020 6020 + #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_WIDTH 64 6021 6021 + 6022 6022 + /* MC_CMD_PAUSE_MODE structuredef */ 6023 6023 + #define MC_CMD_PAUSE_MODE_LEN 1 6024 6024 + #define MC_CMD_PAUSE_MODE_TYPE_OFST 0 6025 6025 + #define MC_CMD_PAUSE_MODE_TYPE_LEN 1 6026 6026 + /* enum: See IEEE 802.3 Clause 73.6.6 */ 6027 6027 + #define MC_CMD_PAUSE_MODE_AN_PAUSE 0x0 6028 6028 + /* enum: See IEEE 802.3 Clause 73.6.6 */ 6029 6029 + #define MC_CMD_PAUSE_MODE_AN_ASYM_DIR 0x1 6030 6030 + #define MC_CMD_PAUSE_MODE_TYPE_LBN 0 6031 6031 + #define MC_CMD_PAUSE_MODE_TYPE_WIDTH 8 6032 6032 + 6033 6033 + /* MC_CMD_ETH_AN_FIELDS structuredef: Fields used for IEEE 802.3 Clause 73 6034 6034 + * Auto-Negotiation. Warning - This is fixed size and cannot be extended. This 6035 6035 + * structure is used to define autonegotiable abilities (advertised, link 6036 6036 + * partner and supported abilities). 6037 6037 + */ 6038 6038 + #define MC_CMD_ETH_AN_FIELDS_LEN 25 6039 6039 + /* Mask of Ethernet technologies. The bit indices in this mask are taken from 6040 6040 + * the TECH field in the MC_CMD_ETH_TECH structure. 6041 6041 + */ 6042 6042 + #define MC_CMD_ETH_AN_FIELDS_TECH_MASK_OFST 0 6043 6043 + #define MC_CMD_ETH_AN_FIELDS_TECH_MASK_LEN 16 6044 6044 + /* enum property: bitshift */ 6045 6045 + /* Enum values, see field(s): */ 6046 6046 + /* MC_CMD_ETH_TECH/TECH */ 6047 6047 + #define MC_CMD_ETH_AN_FIELDS_TECH_MASK_LBN 0 6048 6048 + #define MC_CMD_ETH_AN_FIELDS_TECH_MASK_WIDTH 128 6049 6049 + /* Mask of supported FEC modes */ 6050 6050 + #define MC_CMD_ETH_AN_FIELDS_FEC_MASK_OFST 16 6051 6051 + #define MC_CMD_ETH_AN_FIELDS_FEC_MASK_LEN 4 6052 6052 + /* enum property: bitshift */ 6053 6053 + /* Enum values, see field(s): */ 6054 6054 + /* FEC_TYPE/TYPE */ 6055 6055 + #define MC_CMD_ETH_AN_FIELDS_FEC_MASK_LBN 128 6056 6056 + #define MC_CMD_ETH_AN_FIELDS_FEC_MASK_WIDTH 32 6057 6057 + /* Mask of requested FEC modes */ 6058 6058 + #define MC_CMD_ETH_AN_FIELDS_FEC_REQ_OFST 20 6059 6059 + #define MC_CMD_ETH_AN_FIELDS_FEC_REQ_LEN 4 6060 6060 + /* enum property: bitshift */ 6061 6061 + /* Enum values, see field(s): */ 6062 6062 + /* FEC_TYPE/TYPE */ 6063 6063 + #define MC_CMD_ETH_AN_FIELDS_FEC_REQ_LBN 160 6064 6064 + #define MC_CMD_ETH_AN_FIELDS_FEC_REQ_WIDTH 32 6065 6065 + /* Bitmask of negotiated pause modes */ 6066 6066 + #define MC_CMD_ETH_AN_FIELDS_PAUSE_MASK_OFST 24 6067 6067 + #define MC_CMD_ETH_AN_FIELDS_PAUSE_MASK_LEN 1 6068 6068 + /* enum property: bitshift */ 6069 6069 + /* Enum values, see field(s): */ 6070 6070 + /* MC_CMD_PAUSE_MODE/TYPE */ 6071 6071 + #define MC_CMD_ETH_AN_FIELDS_PAUSE_MASK_LBN 192 6072 6072 + #define MC_CMD_ETH_AN_FIELDS_PAUSE_MASK_WIDTH 8 6073 6073 + 6074 6074 + /* MC_CMD_LOOPBACK_V2 structuredef: Loopback modes for use with the new 6075 6075 + * MC_CMD_LINK_CTRL and MC_CMD_LINK_STATE. These loopback modes are not 6076 6076 + * supported in other getlink/setlink commands. 6077 6077 + */ 6078 6078 + #define MC_CMD_LOOPBACK_V2_LEN 4 6079 6079 + #define MC_CMD_LOOPBACK_V2_MODE_OFST 0 6080 6080 + #define MC_CMD_LOOPBACK_V2_MODE_LEN 4 6081 6081 + /* enum: No loopback */ 6082 6082 + #define MC_CMD_LOOPBACK_V2_NONE 0x0 6083 6083 + /* enum: Let firmware choose a supported loopback mode */ 6084 6084 + #define MC_CMD_LOOPBACK_V2_AUTO 0x1 6085 6085 + /* enum: Loopback after the MAC */ 6086 6086 + #define MC_CMD_LOOPBACK_V2_POST_MAC 0x2 6087 6087 + /* enum: Loopback after the PCS */ 6088 6088 + #define MC_CMD_LOOPBACK_V2_POST_PCS 0x3 6089 6089 + /* enum: Loopback after the PMA */ 6090 6090 + #define MC_CMD_LOOPBACK_V2_POST_PMA 0x4 6091 6091 + /* enum: Loopback after the MDI Wireside */ 6092 6092 + #define MC_CMD_LOOPBACK_V2_POST_MDI_WS 0x5 6093 6093 + /* enum: Loopback after the PMA Wireside */ 6094 6094 + #define MC_CMD_LOOPBACK_V2_POST_PMA_WS 0x6 6095 6095 + /* enum: Loopback after the PCS Wireside */ 6096 6096 + #define MC_CMD_LOOPBACK_V2_POST_PCS_WS 0x7 6097 6097 + /* enum: Loopback after the MAC Wireside */ 6098 6098 + #define MC_CMD_LOOPBACK_V2_POST_MAC_WS 0x8 6099 6099 + /* enum: Loopback after the MAC FIFOs (before the MAC) */ 6100 6100 + #define MC_CMD_LOOPBACK_V2_PRE_MAC 0x9 6101 6101 + #define MC_CMD_LOOPBACK_V2_MODE_LBN 0 6102 6102 + #define MC_CMD_LOOPBACK_V2_MODE_WIDTH 32 6103 6103 + 6104 6104 + /* MC_CMD_FCNTL structuredef */ 6105 6105 + #define MC_CMD_FCNTL_LEN 4 6106 6106 + #define MC_CMD_FCNTL_MASK_OFST 0 6107 6107 + #define MC_CMD_FCNTL_MASK_LEN 4 6108 6108 + /* enum: Flow control is off. */ 6109 6109 + #define MC_CMD_FCNTL_OFF 0x0 6110 6110 + /* enum: Respond to flow control. */ 6111 6111 + #define MC_CMD_FCNTL_RESPOND 0x1 6112 6112 + /* enum: Respond to and Issue flow control. */ 6113 6113 + #define MC_CMD_FCNTL_BIDIR 0x2 6114 6114 + /* enum: Auto negotiate flow control. */ 6115 6115 + #define MC_CMD_FCNTL_AUTO 0x3 6116 6116 + /* enum: Priority flow control. This is only supported on KSB. */ 6117 6117 + #define MC_CMD_FCNTL_QBB 0x4 6118 6118 + /* enum: Issue flow control. */ 6119 6119 + #define MC_CMD_FCNTL_GENERATE 0x5 6120 6120 + #define MC_CMD_FCNTL_MASK_LBN 0 6121 6121 + #define MC_CMD_FCNTL_MASK_WIDTH 32 6122 6122 + 6123 6123 + /* MC_CMD_LINK_FLAGS structuredef */ 6124 6124 + #define MC_CMD_LINK_FLAGS_LEN 4 6125 6125 + /* The enums defined in this field are used as indices into the 6126 6126 + * MC_CMD_LINK_FLAGS bitmask. 6127 6127 + */ 6128 6128 + #define MC_CMD_LINK_FLAGS_MASK_OFST 0 6129 6129 + #define MC_CMD_LINK_FLAGS_MASK_LEN 4 6130 6130 + /* enum property: bitshift */ 6131 6131 + /* enum: Enable auto-negotiation. If AN is enabled, link technology and FEC 6132 6132 + * mode are determined by advertised capabilities and requested FEC modes, 6133 6133 + * combined with link partner capabilities. If AN is disabled, link technology 6134 6134 + * is forced to LINK_TECHNOLOGY and FEC mode is forced to FEC_MODE. Not valid 6135 6135 + * if loopback is enabled 6136 6136 + */ 6137 6137 + #define MC_CMD_LINK_FLAGS_AUTONEG_EN 0x0 6138 6138 + /* enum: Enable parallel detect. In addition to AN, try to sense partner forced 6139 6139 + * speed/FEC mode (when partner AN disabled). Only valid if AN is enabled. 6140 6140 + */ 6141 6141 + #define MC_CMD_LINK_FLAGS_PARALLEL_DETECT_EN 0x1 6142 6142 + /* enum: Force link down, in electrical idle. */ 6143 6143 + #define MC_CMD_LINK_FLAGS_LINK_DISABLE 0x2 6144 6144 + /* enum: Ignore the sequence number and always apply. */ 6145 6145 + #define MC_CMD_LINK_FLAGS_IGNORE_MODULE_SEQ 0x3 6146 6146 + #define MC_CMD_LINK_FLAGS_MASK_LBN 0 6147 6147 + #define MC_CMD_LINK_FLAGS_MASK_WIDTH 32 6148 6148 + 6149 6149 + 6150 6150 + /***********************************/ 6151 6151 + /* MC_CMD_LINK_CTRL 6152 6152 + * Write the unified MAC/PHY link configuration. Locks required: None. Return 6153 6153 + * code: 0, EINVAL, ETIME, EAGAIN 6154 6154 + */ 6155 6155 + #define MC_CMD_LINK_CTRL 0x6b 6156 6156 + #undef MC_CMD_0x6b_PRIVILEGE_CTG 6157 6157 + 6158 6158 + #define MC_CMD_0x6b_PRIVILEGE_CTG SRIOV_CTG_LINK 6159 6159 + 6160 6160 + /* MC_CMD_LINK_CTRL_IN msgrequest */ 6161 6161 + #define MC_CMD_LINK_CTRL_IN_LEN 40 6162 6162 + /* Handle to the port to set link state for. */ 6163 6163 + #define MC_CMD_LINK_CTRL_IN_PORT_HANDLE_OFST 0 6164 6164 + #define MC_CMD_LINK_CTRL_IN_PORT_HANDLE_LEN 4 6165 6165 + /* Control flags */ 6166 6166 + #define MC_CMD_LINK_CTRL_IN_CONTROL_FLAGS_OFST 4 6167 6167 + #define MC_CMD_LINK_CTRL_IN_CONTROL_FLAGS_LEN 4 6168 6168 + /* enum property: bitshift */ 6169 6169 + /* Enum values, see field(s): */ 6170 6170 + /* MC_CMD_LINK_FLAGS/MASK */ 6171 6171 + /* Reserved for future expansion, and included to provide padding for alignment 6172 6172 + * purposes. 6173 6173 + */ 6174 6174 + #define MC_CMD_LINK_CTRL_IN_RESERVED_OFST 8 6175 6175 + #define MC_CMD_LINK_CTRL_IN_RESERVED_LEN 8 6176 6176 + #define MC_CMD_LINK_CTRL_IN_RESERVED_LO_OFST 8 6177 6177 + #define MC_CMD_LINK_CTRL_IN_RESERVED_LO_LEN 4 6178 6178 + #define MC_CMD_LINK_CTRL_IN_RESERVED_LO_LBN 64 6179 6179 + #define MC_CMD_LINK_CTRL_IN_RESERVED_LO_WIDTH 32 6180 6180 + #define MC_CMD_LINK_CTRL_IN_RESERVED_HI_OFST 12 6181 6181 + #define MC_CMD_LINK_CTRL_IN_RESERVED_HI_LEN 4 6182 6182 + #define MC_CMD_LINK_CTRL_IN_RESERVED_HI_LBN 96 6183 6183 + #define MC_CMD_LINK_CTRL_IN_RESERVED_HI_WIDTH 32 6184 6184 + /* Technology abilities to advertise during auto-negotiation */ 6185 6185 + #define MC_CMD_LINK_CTRL_IN_ADVERTISED_TECH_ABILITIES_MASK_OFST 16 6186 6186 + #define MC_CMD_LINK_CTRL_IN_ADVERTISED_TECH_ABILITIES_MASK_LEN 16 6187 6187 + /* enum property: bitshift */ 6188 6188 + /* Enum values, see field(s): */ 6189 6189 + /* MC_CMD_ETH_TECH/TECH */ 6190 6190 + /* Pause abilities to advertise during auto-negotiation. Valid when auto- 6191 6191 + * negotation is enabled and MC_CMD_SET_MAC_IN/FCTL is set to 6192 6192 + * MC_CMD_FCNTL_AUTO. If auto-negotiation is disabled the driver must 6193 6193 + * explicitly configure pause mode with MC_CMD_SET_MAC. 6194 6194 + */ 6195 6195 + #define MC_CMD_LINK_CTRL_IN_ADVERTISED_PAUSE_ABILITIES_MASK_OFST 32 6196 6196 + #define MC_CMD_LINK_CTRL_IN_ADVERTISED_PAUSE_ABILITIES_MASK_LEN 1 6197 6197 + /* enum property: bitshift */ 6198 6198 + /* Enum values, see field(s): */ 6199 6199 + /* MC_CMD_PAUSE_MODE/TYPE */ 6200 6200 + /* When auto-negotiation is enabled, this is the FEC mode to request. Note that 6201 6201 + * a weaker FEC mode may get negotiated, depending on what the link partner 6202 6202 + * supports. The driver should subsequently use MC_CMD_GET_LINK to check the 6203 6203 + * actual negotiated FEC mode. When auto-negotiation is disabled, this is the 6204 6204 + * forced FEC mode. 6205 6205 + */ 6206 6206 + #define MC_CMD_LINK_CTRL_IN_FEC_MODE_OFST 33 6207 6207 + #define MC_CMD_LINK_CTRL_IN_FEC_MODE_LEN 1 6208 6208 + /* enum property: value */ 6209 6209 + /* Enum values, see field(s): */ 6210 6210 + /* FEC_TYPE/TYPE */ 6211 6211 + /* This is only to be used when auto-negotiation is disabled (forced speed or 6212 6212 + * loopback mode). If the specified value does not align with the values 6213 6213 + * defined in the enum MC_CMD_ETH_TECH/TECH, it is considered invalid. 6214 6214 + */ 6215 6215 + #define MC_CMD_LINK_CTRL_IN_LINK_TECHNOLOGY_OFST 36 6216 6216 + #define MC_CMD_LINK_CTRL_IN_LINK_TECHNOLOGY_LEN 2 6217 6217 + /* enum property: value */ 6218 6218 + /* Enum values, see field(s): */ 6219 6219 + /* MC_CMD_ETH_TECH/TECH */ 6220 6220 + /* The sequence number of the last MODULECHANGE event. If this doesn't match, 6221 6221 + * fail with EAGAIN. 6222 6222 + */ 6223 6223 + #define MC_CMD_LINK_CTRL_IN_MODULE_SEQ_OFST 38 6224 6224 + #define MC_CMD_LINK_CTRL_IN_MODULE_SEQ_LEN 1 6225 6225 + /* Loopback Mode. Only valid when auto-negotiation is disabled. */ 6226 6226 + #define MC_CMD_LINK_CTRL_IN_LOOPBACK_OFST 39 6227 6227 + #define MC_CMD_LINK_CTRL_IN_LOOPBACK_LEN 1 6228 6228 + /* enum property: value */ 6229 6229 + /* Enum values, see field(s): */ 6230 6230 + /* MC_CMD_LOOPBACK_V2/MODE */ 6231 6231 + 6232 6232 + /* MC_CMD_LINK_CTRL_OUT msgresponse */ 6233 6233 + #define MC_CMD_LINK_CTRL_OUT_LEN 0 6234 6234 + 6235 6235 + 6236 6236 + /***********************************/ 6237 6237 + /* MC_CMD_LINK_STATE 6238 6238 + */ 6239 6239 + #define MC_CMD_LINK_STATE 0x6c 6240 6240 + #undef MC_CMD_0x6c_PRIVILEGE_CTG 6241 6241 + 6242 6242 + #define MC_CMD_0x6c_PRIVILEGE_CTG SRIOV_CTG_LINK 6243 6243 + 6244 6244 + /* MC_CMD_LINK_STATE_IN msgrequest */ 6245 6245 + #define MC_CMD_LINK_STATE_IN_LEN 4 6246 6246 + /* Handle to the port to get link state for. */ 6247 6247 + #define MC_CMD_LINK_STATE_IN_PORT_HANDLE_OFST 0 6248 6248 + #define MC_CMD_LINK_STATE_IN_PORT_HANDLE_LEN 4 6249 6249 + 6250 6250 + /* MC_CMD_LINK_STATE_OUT msgresponse */ 6251 6251 + #define MC_CMD_LINK_STATE_OUT_LEN 114 6252 6252 + /* Flags used to report the current configuration/state of the link. */ 6253 6253 + #define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_OFST 0 6254 6254 + #define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LEN 8 6255 6255 + #define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_OFST 0 6256 6256 + #define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_LEN 4 6257 6257 + #define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_LBN 0 6258 6258 + #define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_WIDTH 32 6259 6259 + #define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_OFST 4 6260 6260 + #define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_LEN 4 6261 6261 + #define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_LBN 32 6262 6262 + #define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_WIDTH 32 6263 6263 + /* enum property: value */ 6264 6264 + /* Enum values, see field(s): */ 6265 6265 + /* MC_CMD_LINK_STATUS_FLAGS/STATUS_FLAGS */ 6266 6266 + /* Configured technology. If the specified value does not align with the values 6267 6267 + * defined in the enum MC_CMD_ETH_TECH/TECH, it is considered invalid. 6268 6268 + */ 6269 6269 + #define MC_CMD_LINK_STATE_OUT_LINK_TECHNOLOGY_OFST 8 6270 6270 + #define MC_CMD_LINK_STATE_OUT_LINK_TECHNOLOGY_LEN 2 6271 6271 + /* enum property: value */ 6272 6272 + /* Enum values, see field(s): */ 6273 6273 + /* MC_CMD_ETH_TECH/TECH */ 6274 6274 + /* Configured FEC mode */ 6275 6275 + #define MC_CMD_LINK_STATE_OUT_FEC_MODE_OFST 10 6276 6276 + #define MC_CMD_LINK_STATE_OUT_FEC_MODE_LEN 1 6277 6277 + /* enum property: value */ 6278 6278 + /* Enum values, see field(s): */ 6279 6279 + /* FEC_TYPE/TYPE */ 6280 6280 + /* Bitmask of auto-negotiated pause modes */ 6281 6281 + #define MC_CMD_LINK_STATE_OUT_PAUSE_MASK_OFST 11 6282 6282 + #define MC_CMD_LINK_STATE_OUT_PAUSE_MASK_LEN 1 6283 6283 + /* enum property: bitshift */ 6284 6284 + /* Enum values, see field(s): */ 6285 6285 + /* MC_CMD_PAUSE_MODE/TYPE */ 6286 6286 + /* Configured loopback mode */ 6287 6287 + #define MC_CMD_LINK_STATE_OUT_LOOPBACK_OFST 12 6288 6288 + #define MC_CMD_LINK_STATE_OUT_LOOPBACK_LEN 1 6289 6289 + /* enum property: value */ 6290 6290 + /* Enum values, see field(s): */ 6291 6291 + /* MC_CMD_LOOPBACK_V2/MODE */ 6292 6292 + /* Abilities requested by the driver to advertise during auto-negotiation */ 6293 6293 + #define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_OFST 16 6294 6294 + #define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_LEN 32 6295 6295 + /* See structuredef: MC_CMD_ETH_AN_FIELDS */ 6296 6296 + #define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_TECH_MASK_OFST 16 6297 6297 + #define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_TECH_MASK_LEN 16 6298 6298 + #define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_MASK_OFST 32 6299 6299 + #define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_MASK_LEN 4 6300 6300 + #define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_REQ_OFST 36 6301 6301 + #define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_REQ_LEN 4 6302 6302 + #define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_PAUSE_MASK_OFST 40 6303 6303 + #define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_PAUSE_MASK_LEN 1 6304 6304 + /* Abilities advertised by the link partner during auto-negotiation */ 6305 6305 + #define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_OFST 48 6306 6306 + #define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_LEN 32 6307 6307 + /* See structuredef: MC_CMD_ETH_AN_FIELDS */ 6308 6308 + #define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_TECH_MASK_OFST 48 6309 6309 + #define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_TECH_MASK_LEN 16 6310 6310 + #define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_MASK_OFST 64 6311 6311 + #define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_MASK_LEN 4 6312 6312 + #define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_REQ_OFST 68 6313 6313 + #define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_REQ_LEN 4 6314 6314 + #define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_PAUSE_MASK_OFST 72 6315 6315 + #define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_PAUSE_MASK_LEN 1 6316 6316 + /* Abilities supported by the local device (including cable abilities) For 6317 6317 + * fixed local device capbilities see MC_CMD_GET_LOCAL_DEVICE_INFO 6318 6318 + */ 6319 6319 + #define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_OFST 80 6320 6320 + #define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_LEN 28 6321 6321 + /* See structuredef: MC_CMD_ETH_AN_FIELDS */ 6322 6322 + #define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_TECH_MASK_OFST 80 6323 6323 + #define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_TECH_MASK_LEN 16 6324 6324 + #define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_MASK_OFST 96 6325 6325 + #define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_MASK_LEN 4 6326 6326 + #define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_REQ_OFST 100 6327 6327 + #define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_REQ_LEN 4 6328 6328 + #define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_PAUSE_MASK_OFST 104 6329 6329 + #define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_PAUSE_MASK_LEN 1 6330 6330 + /* Control flags */ 6331 6331 + #define MC_CMD_LINK_STATE_OUT_CONTROL_FLAGS_OFST 108 6332 6332 + #define MC_CMD_LINK_STATE_OUT_CONTROL_FLAGS_LEN 4 6333 6333 + /* enum property: bitshift */ 6334 6334 + /* Enum values, see field(s): */ 6335 6335 + /* MC_CMD_LINK_FLAGS/MASK */ 6336 6336 + /* Sequence number to synchronize link change events */ 6337 6337 + #define MC_CMD_LINK_STATE_OUT_PORT_LINKCHANGE_SEQ_NUM_OFST 112 6338 6338 + #define MC_CMD_LINK_STATE_OUT_PORT_LINKCHANGE_SEQ_NUM_LEN 1 6339 6339 + /* Sequence number to synchronize module change events */ 6340 6340 + #define MC_CMD_LINK_STATE_OUT_PORT_MODULECHANGE_SEQ_NUM_OFST 113 6341 6341 + #define MC_CMD_LINK_STATE_OUT_PORT_MODULECHANGE_SEQ_NUM_LEN 1 6342 6342 + 6343 6343 + /* MC_CMD_LINK_STATE_OUT_V2 msgresponse: Updated LINK_STATE_OUT with 6344 6344 + * LOCAL_AN_SUPPORT 6345 6345 + */ 6346 6346 + #define MC_CMD_LINK_STATE_OUT_V2_LEN 120 6347 6347 + /* Flags used to report the current configuration/state of the link. */ 6348 6348 + #define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_OFST 0 6349 6349 + #define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LEN 8 6350 6350 + #define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_OFST 0 6351 6351 + #define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_LEN 4 6352 6352 + #define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_LBN 0 6353 6353 + #define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_WIDTH 32 6354 6354 + #define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_OFST 4 6355 6355 + #define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_LEN 4 6356 6356 + #define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_LBN 32 6357 6357 + #define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_WIDTH 32 6358 6358 + /* enum property: value */ 6359 6359 + /* Enum values, see field(s): */ 6360 6360 + /* MC_CMD_LINK_STATUS_FLAGS/STATUS_FLAGS */ 6361 6361 + /* Configured technology. If the specified value does not align with the values 6362 6362 + * defined in the enum MC_CMD_ETH_TECH/TECH, it is considered invalid. 6363 6363 + */ 6364 6364 + #define MC_CMD_LINK_STATE_OUT_V2_LINK_TECHNOLOGY_OFST 8 6365 6365 + #define MC_CMD_LINK_STATE_OUT_V2_LINK_TECHNOLOGY_LEN 2 6366 6366 + /* enum property: value */ 6367 6367 + /* Enum values, see field(s): */ 6368 6368 + /* MC_CMD_ETH_TECH/TECH */ 6369 6369 + /* Configured FEC mode */ 6370 6370 + #define MC_CMD_LINK_STATE_OUT_V2_FEC_MODE_OFST 10 6371 6371 + #define MC_CMD_LINK_STATE_OUT_V2_FEC_MODE_LEN 1 6372 6372 + /* enum property: value */ 6373 6373 + /* Enum values, see field(s): */ 6374 6374 + /* FEC_TYPE/TYPE */ 6375 6375 + /* Bitmask of auto-negotiated pause modes */ 6376 6376 + #define MC_CMD_LINK_STATE_OUT_V2_PAUSE_MASK_OFST 11 6377 6377 + #define MC_CMD_LINK_STATE_OUT_V2_PAUSE_MASK_LEN 1 6378 6378 + /* enum property: bitshift */ 6379 6379 + /* Enum values, see field(s): */ 6380 6380 + /* MC_CMD_PAUSE_MODE/TYPE */ 6381 6381 + /* Configured loopback mode */ 6382 6382 + #define MC_CMD_LINK_STATE_OUT_V2_LOOPBACK_OFST 12 6383 6383 + #define MC_CMD_LINK_STATE_OUT_V2_LOOPBACK_LEN 1 6384 6384 + /* enum property: value */ 6385 6385 + /* Enum values, see field(s): */ 6386 6386 + /* MC_CMD_LOOPBACK_V2/MODE */ 6387 6387 + /* Abilities requested by the driver to advertise during auto-negotiation */ 6388 6388 + #define MC_CMD_LINK_STATE_OUT_V2_ADVERTISED_ABILITIES_OFST 16 6389 6389 + #define MC_CMD_LINK_STATE_OUT_V2_ADVERTISED_ABILITIES_LEN 32 6390 6390 + /* Abilities advertised by the link partner during auto-negotiation */ 6391 6391 + #define MC_CMD_LINK_STATE_OUT_V2_LINK_PARTNER_ABILITIES_OFST 48 6392 6392 + #define MC_CMD_LINK_STATE_OUT_V2_LINK_PARTNER_ABILITIES_LEN 32 6393 6393 + /* Abilities supported by the local device (including cable abilities) For 6394 6394 + * fixed local device capbilities see MC_CMD_GET_LOCAL_DEVICE_INFO 6395 6395 + */ 6396 6396 + #define MC_CMD_LINK_STATE_OUT_V2_SUPPORTED_ABILITIES_OFST 80 6397 6397 + #define MC_CMD_LINK_STATE_OUT_V2_SUPPORTED_ABILITIES_LEN 28 6398 6398 + /* Control flags */ 6399 6399 + #define MC_CMD_LINK_STATE_OUT_V2_CONTROL_FLAGS_OFST 108 6400 6400 + #define MC_CMD_LINK_STATE_OUT_V2_CONTROL_FLAGS_LEN 4 6401 6401 + /* enum property: bitshift */ 6402 6402 + /* Enum values, see field(s): */ 6403 6403 + /* MC_CMD_LINK_FLAGS/MASK */ 6404 6404 + /* Sequence number to synchronize link change events */ 6405 6405 + #define MC_CMD_LINK_STATE_OUT_V2_PORT_LINKCHANGE_SEQ_NUM_OFST 112 6406 6406 + #define MC_CMD_LINK_STATE_OUT_V2_PORT_LINKCHANGE_SEQ_NUM_LEN 1 6407 6407 + /* Sequence number to synchronize module change events */ 6408 6408 + #define MC_CMD_LINK_STATE_OUT_V2_PORT_MODULECHANGE_SEQ_NUM_OFST 113 6409 6409 + #define MC_CMD_LINK_STATE_OUT_V2_PORT_MODULECHANGE_SEQ_NUM_LEN 1 6410 6410 + /* Reports the auto-negotiation supported by the local device. This depends on 6411 6411 + * the port and module properties. 6412 6412 + */ 6413 6413 + #define MC_CMD_LINK_STATE_OUT_V2_LOCAL_AN_SUPPORT_OFST 116 6414 6414 + #define MC_CMD_LINK_STATE_OUT_V2_LOCAL_AN_SUPPORT_LEN 4 6415 6415 + /* Enum values, see field(s): */ 6416 6416 + /* AN_TYPE/TYPE */ 6417 6417 + 6418 6418 + /* MC_CMD_LINK_STATE_OUT_V3 msgresponse: Updated LINK_STATE_OUT_V2 for explicit 6419 6419 + * reporting of the link speed and duplex mode. 6420 6420 + */ 6421 6421 + #define MC_CMD_LINK_STATE_OUT_V3_LEN 128 6422 6422 + /* Flags used to report the current configuration/state of the link. */ 6423 6423 + #define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_OFST 0 6424 6424 + #define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LEN 8 6425 6425 + #define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_OFST 0 6426 6426 + #define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_LEN 4 6427 6427 + #define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_LBN 0 6428 6428 + #define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_WIDTH 32 6429 6429 + #define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_OFST 4 6430 6430 + #define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_LEN 4 6431 6431 + #define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_LBN 32 6432 6432 + #define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_WIDTH 32 6433 6433 + /* enum property: value */ 6434 6434 + /* Enum values, see field(s): */ 6435 6435 + /* MC_CMD_LINK_STATUS_FLAGS/STATUS_FLAGS */ 6436 6436 + /* Configured technology. If the specified value does not align with the values 6437 6437 + * defined in the enum MC_CMD_ETH_TECH/TECH, it is considered invalid. 6438 6438 + */ 6439 6439 + #define MC_CMD_LINK_STATE_OUT_V3_LINK_TECHNOLOGY_OFST 8 6440 6440 + #define MC_CMD_LINK_STATE_OUT_V3_LINK_TECHNOLOGY_LEN 2 6441 6441 + /* enum property: value */ 6442 6442 + /* Enum values, see field(s): */ 6443 6443 + /* MC_CMD_ETH_TECH/TECH */ 6444 6444 + /* Configured FEC mode */ 6445 6445 + #define MC_CMD_LINK_STATE_OUT_V3_FEC_MODE_OFST 10 6446 6446 + #define MC_CMD_LINK_STATE_OUT_V3_FEC_MODE_LEN 1 6447 6447 + /* enum property: value */ 6448 6448 + /* Enum values, see field(s): */ 6449 6449 + /* FEC_TYPE/TYPE */ 6450 6450 + /* Bitmask of auto-negotiated pause modes */ 6451 6451 + #define MC_CMD_LINK_STATE_OUT_V3_PAUSE_MASK_OFST 11 6452 6452 + #define MC_CMD_LINK_STATE_OUT_V3_PAUSE_MASK_LEN 1 6453 6453 + /* enum property: bitshift */ 6454 6454 + /* Enum values, see field(s): */ 6455 6455 + /* MC_CMD_PAUSE_MODE/TYPE */ 6456 6456 + /* Configured loopback mode */ 6457 6457 + #define MC_CMD_LINK_STATE_OUT_V3_LOOPBACK_OFST 12 6458 6458 + #define MC_CMD_LINK_STATE_OUT_V3_LOOPBACK_LEN 1 6459 6459 + /* enum property: value */ 6460 6460 + /* Enum values, see field(s): */ 6461 6461 + /* MC_CMD_LOOPBACK_V2/MODE */ 6462 6462 + /* Abilities requested by the driver to advertise during auto-negotiation */ 6463 6463 + #define MC_CMD_LINK_STATE_OUT_V3_ADVERTISED_ABILITIES_OFST 16 6464 6464 + #define MC_CMD_LINK_STATE_OUT_V3_ADVERTISED_ABILITIES_LEN 32 6465 6465 + /* Abilities advertised by the link partner during auto-negotiation */ 6466 6466 + #define MC_CMD_LINK_STATE_OUT_V3_LINK_PARTNER_ABILITIES_OFST 48 6467 6467 + #define MC_CMD_LINK_STATE_OUT_V3_LINK_PARTNER_ABILITIES_LEN 32 6468 6468 + /* Abilities supported by the local device (including cable abilities) For 6469 6469 + * fixed local device capbilities see MC_CMD_GET_LOCAL_DEVICE_INFO 6470 6470 + */ 6471 6471 + #define MC_CMD_LINK_STATE_OUT_V3_SUPPORTED_ABILITIES_OFST 80 6472 6472 + #define MC_CMD_LINK_STATE_OUT_V3_SUPPORTED_ABILITIES_LEN 28 6473 6473 + /* Control flags */ 6474 6474 + #define MC_CMD_LINK_STATE_OUT_V3_CONTROL_FLAGS_OFST 108 6475 6475 + #define MC_CMD_LINK_STATE_OUT_V3_CONTROL_FLAGS_LEN 4 6476 6476 + /* enum property: bitshift */ 6477 6477 + /* Enum values, see field(s): */ 6478 6478 + /* MC_CMD_LINK_FLAGS/MASK */ 6479 6479 + /* Sequence number to synchronize link change events */ 6480 6480 + #define MC_CMD_LINK_STATE_OUT_V3_PORT_LINKCHANGE_SEQ_NUM_OFST 112 6481 6481 + #define MC_CMD_LINK_STATE_OUT_V3_PORT_LINKCHANGE_SEQ_NUM_LEN 1 6482 6482 + /* Sequence number to synchronize module change events */ 6483 6483 + #define MC_CMD_LINK_STATE_OUT_V3_PORT_MODULECHANGE_SEQ_NUM_OFST 113 6484 6484 + #define MC_CMD_LINK_STATE_OUT_V3_PORT_MODULECHANGE_SEQ_NUM_LEN 1 6485 6485 + /* Reports the auto-negotiation supported by the local device. This depends on 6486 6486 + * the port and module properties. 6487 6487 + */ 6488 6488 + #define MC_CMD_LINK_STATE_OUT_V3_LOCAL_AN_SUPPORT_OFST 116 6489 6489 + #define MC_CMD_LINK_STATE_OUT_V3_LOCAL_AN_SUPPORT_LEN 4 6490 6490 + /* Enum values, see field(s): */ 6491 6491 + /* AN_TYPE/TYPE */ 6492 6492 + /* Autonegotiated speed in mbit/s. The link may still be down even if this 6493 6493 + * reads non-zero. LINK_SPEED field is intended to be used by drivers without 6494 6494 + * the most up-to-date MCDI definitions, unable to deduce the link speed from 6495 6495 + * the reported LINK_TECHNOLOGY field. 6496 6496 + */ 6497 6497 + #define MC_CMD_LINK_STATE_OUT_V3_LINK_SPEED_OFST 120 6498 6498 + #define MC_CMD_LINK_STATE_OUT_V3_LINK_SPEED_LEN 4 6499 6499 + #define MC_CMD_LINK_STATE_OUT_V3_FLAGS_OFST 124 6500 6500 + #define MC_CMD_LINK_STATE_OUT_V3_FLAGS_LEN 4 6501 6501 + #define MC_CMD_LINK_STATE_OUT_V3_FULL_DUPLEX_OFST 124 6502 6502 + #define MC_CMD_LINK_STATE_OUT_V3_FULL_DUPLEX_LBN 0 6503 6503 + #define MC_CMD_LINK_STATE_OUT_V3_FULL_DUPLEX_WIDTH 1 5230 6504 5231 6505 5232 6506 /***********************************/ ··· 6063 5693 6064 5694 /* MC_CMD_GET_LINK_IN msgrequest */ 6065 5695 #define MC_CMD_GET_LINK_IN_LEN 0 5696 5696 + 5697 5697 + /* MC_CMD_GET_LINK_IN_V2 msgrequest */ 5698 5698 + #define MC_CMD_GET_LINK_IN_V2_LEN 8 5699 5699 + /* Target port to request link state for. Uses MAE_LINK_ENDPOINT_SELECTOR which 5700 5700 + * identifies a real or virtual network port by MAE port and link end. See the 5701 5701 + * structure definition for more details. 5702 5702 + */ 5703 5703 + #define MC_CMD_GET_LINK_IN_V2_TARGET_OFST 0 5704 5704 + #define MC_CMD_GET_LINK_IN_V2_TARGET_LEN 8 5705 5705 + #define MC_CMD_GET_LINK_IN_V2_TARGET_LO_OFST 0 5706 5706 + #define MC_CMD_GET_LINK_IN_V2_TARGET_LO_LEN 4 5707 5707 + #define MC_CMD_GET_LINK_IN_V2_TARGET_LO_LBN 0 5708 5708 + #define MC_CMD_GET_LINK_IN_V2_TARGET_LO_WIDTH 32 5709 5709 + #define MC_CMD_GET_LINK_IN_V2_TARGET_HI_OFST 4 5710 5710 + #define MC_CMD_GET_LINK_IN_V2_TARGET_HI_LEN 4 5711 5711 + #define MC_CMD_GET_LINK_IN_V2_TARGET_HI_LBN 32 5712 5712 + #define MC_CMD_GET_LINK_IN_V2_TARGET_HI_WIDTH 32 5713 5713 + /* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */ 5714 5714 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_OFST 0 5715 5715 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_LEN 4 5716 5716 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FLAT_OFST 0 5717 5717 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FLAT_LEN 4 5718 5718 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_TYPE_OFST 3 5719 5719 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_TYPE_LEN 1 5720 5720 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0 5721 5721 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3 5722 5722 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0 5723 5723 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4 5724 5724 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20 5725 5725 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4 5726 5726 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16 5727 5727 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4 5728 5728 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2 5729 5729 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1 5730 5730 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0 5731 5731 + #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2 5732 5732 + #define MC_CMD_GET_LINK_IN_V2_TARGET_LINK_END_OFST 4 5733 5733 + #define MC_CMD_GET_LINK_IN_V2_TARGET_LINK_END_LEN 4 5734 5734 + #define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_OFST 0 5735 5735 + #define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_LEN 8 5736 5736 + #define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_LO_OFST 0 5737 5737 + #define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_LO_LEN 4 5738 5738 + #define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_LO_LBN 0 5739 5739 + #define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_LO_WIDTH 32 5740 5740 + #define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_HI_OFST 4 5741 5741 + #define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_HI_LEN 4 5742 5742 + #define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_HI_LBN 32 5743 5743 + #define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_HI_WIDTH 32 6066 5744 6067 5745 /* MC_CMD_GET_LINK_OUT msgresponse */ 6068 5746 #define MC_CMD_GET_LINK_OUT_LEN 28 ··· 6163 5745 /* This returns the negotiated flow control value. */ 6164 5746 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 6165 5747 #define MC_CMD_GET_LINK_OUT_FCNTL_LEN 4 5748 5748 + /* enum property: value */ 6166 5749 /* Enum values, see field(s): */ 6167 5750 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 6168 5751 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 ··· 6232 5813 /* This returns the negotiated flow control value. */ 6233 5814 #define MC_CMD_GET_LINK_OUT_V2_FCNTL_OFST 20 6234 5815 #define MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4 5816 5816 + /* enum property: value */ 6235 5817 /* Enum values, see field(s): */ 6236 5818 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 6237 5819 #define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_OFST 24 ··· 6389 5969 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_LBN 7 6390 5970 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_WIDTH 1 6391 5971 5972 5972 + /* MC_CMD_SET_LINK_IN_V3 msgrequest */ 5973 5973 + #define MC_CMD_SET_LINK_IN_V3_LEN 28 5974 5974 + /* Near-side advertised capabilities. Refer to 5975 5975 + * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 5976 5976 + */ 5977 5977 + #define MC_CMD_SET_LINK_IN_V3_CAP_OFST 0 5978 5978 + #define MC_CMD_SET_LINK_IN_V3_CAP_LEN 4 5979 5979 + /* Flags */ 5980 5980 + #define MC_CMD_SET_LINK_IN_V3_FLAGS_OFST 4 5981 5981 + #define MC_CMD_SET_LINK_IN_V3_FLAGS_LEN 4 5982 5982 + #define MC_CMD_SET_LINK_IN_V3_LOWPOWER_OFST 4 5983 5983 + #define MC_CMD_SET_LINK_IN_V3_LOWPOWER_LBN 0 5984 5984 + #define MC_CMD_SET_LINK_IN_V3_LOWPOWER_WIDTH 1 5985 5985 + #define MC_CMD_SET_LINK_IN_V3_POWEROFF_OFST 4 5986 5986 + #define MC_CMD_SET_LINK_IN_V3_POWEROFF_LBN 1 5987 5987 + #define MC_CMD_SET_LINK_IN_V3_POWEROFF_WIDTH 1 5988 5988 + #define MC_CMD_SET_LINK_IN_V3_TXDIS_OFST 4 5989 5989 + #define MC_CMD_SET_LINK_IN_V3_TXDIS_LBN 2 5990 5990 + #define MC_CMD_SET_LINK_IN_V3_TXDIS_WIDTH 1 5991 5991 + #define MC_CMD_SET_LINK_IN_V3_LINKDOWN_OFST 4 5992 5992 + #define MC_CMD_SET_LINK_IN_V3_LINKDOWN_LBN 3 5993 5993 + #define MC_CMD_SET_LINK_IN_V3_LINKDOWN_WIDTH 1 5994 5994 + /* Loopback mode. */ 5995 5995 + #define MC_CMD_SET_LINK_IN_V3_LOOPBACK_MODE_OFST 8 5996 5996 + #define MC_CMD_SET_LINK_IN_V3_LOOPBACK_MODE_LEN 4 5997 5997 + /* Enum values, see field(s): */ 5998 5998 + /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 5999 5999 + /* A loopback speed of "0" is supported, and means (choose any available 6000 6000 + * speed). 6001 6001 + */ 6002 6002 + #define MC_CMD_SET_LINK_IN_V3_LOOPBACK_SPEED_OFST 12 6003 6003 + #define MC_CMD_SET_LINK_IN_V3_LOOPBACK_SPEED_LEN 4 6004 6004 + #define MC_CMD_SET_LINK_IN_V3_MODULE_SEQ_OFST 16 6005 6005 + #define MC_CMD_SET_LINK_IN_V3_MODULE_SEQ_LEN 1 6006 6006 + #define MC_CMD_SET_LINK_IN_V3_MODULE_SEQ_NUMBER_OFST 16 6007 6007 + #define MC_CMD_SET_LINK_IN_V3_MODULE_SEQ_NUMBER_LBN 0 6008 6008 + #define MC_CMD_SET_LINK_IN_V3_MODULE_SEQ_NUMBER_WIDTH 7 6009 6009 + #define MC_CMD_SET_LINK_IN_V3_MODULE_SEQ_IGNORE_OFST 16 6010 6010 + #define MC_CMD_SET_LINK_IN_V3_MODULE_SEQ_IGNORE_LBN 7 6011 6011 + #define MC_CMD_SET_LINK_IN_V3_MODULE_SEQ_IGNORE_WIDTH 1 6012 6012 + /* Padding */ 6013 6013 + #define MC_CMD_SET_LINK_IN_V3_RESERVED_OFST 17 6014 6014 + #define MC_CMD_SET_LINK_IN_V3_RESERVED_LEN 3 6015 6015 + /* Target port to set link state for. Uses MAE_LINK_ENDPOINT_SELECTOR which 6016 6016 + * identifies a real or virtual network port by MAE port and link end. See the 6017 6017 + * structure definition for more details 6018 6018 + */ 6019 6019 + #define MC_CMD_SET_LINK_IN_V3_TARGET_OFST 20 6020 6020 + #define MC_CMD_SET_LINK_IN_V3_TARGET_LEN 8 6021 6021 + #define MC_CMD_SET_LINK_IN_V3_TARGET_LO_OFST 20 6022 6022 + #define MC_CMD_SET_LINK_IN_V3_TARGET_LO_LEN 4 6023 6023 + #define MC_CMD_SET_LINK_IN_V3_TARGET_LO_LBN 160 6024 6024 + #define MC_CMD_SET_LINK_IN_V3_TARGET_LO_WIDTH 32 6025 6025 + #define MC_CMD_SET_LINK_IN_V3_TARGET_HI_OFST 24 6026 6026 + #define MC_CMD_SET_LINK_IN_V3_TARGET_HI_LEN 4 6027 6027 + #define MC_CMD_SET_LINK_IN_V3_TARGET_HI_LBN 192 6028 6028 + #define MC_CMD_SET_LINK_IN_V3_TARGET_HI_WIDTH 32 6029 6029 + /* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */ 6030 6030 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_OFST 20 6031 6031 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_LEN 4 6032 6032 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FLAT_OFST 20 6033 6033 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FLAT_LEN 4 6034 6034 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_TYPE_OFST 23 6035 6035 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_TYPE_LEN 1 6036 6036 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 20 6037 6037 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3 6038 6038 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 160 6039 6039 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4 6040 6040 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 180 6041 6041 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4 6042 6042 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 176 6043 6043 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4 6044 6044 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 22 6045 6045 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1 6046 6046 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 20 6047 6047 + #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2 6048 6048 + #define MC_CMD_SET_LINK_IN_V3_TARGET_LINK_END_OFST 24 6049 6049 + #define MC_CMD_SET_LINK_IN_V3_TARGET_LINK_END_LEN 4 6050 6050 + #define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_OFST 20 6051 6051 + #define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_LEN 8 6052 6052 + #define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_LO_OFST 20 6053 6053 + #define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_LO_LEN 4 6054 6054 + #define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_LO_LBN 160 6055 6055 + #define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_LO_WIDTH 32 6056 6056 + #define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_HI_OFST 24 6057 6057 + #define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_HI_LEN 4 6058 6058 + #define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_HI_LBN 192 6059 6059 + #define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_HI_WIDTH 32 6060 6060 + 6392 6061 /* MC_CMD_SET_LINK_OUT msgresponse */ 6393 6062 #define MC_CMD_SET_LINK_OUT_LEN 0 6394 6063 ··· 6543 6034 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 6544 6035 #define MC_CMD_SET_MAC_IN_FCNTL_LEN 4 6545 6036 /* enum: Flow control is off. */ 6546 6546 - #define MC_CMD_FCNTL_OFF 0x0 6037 6037 + /* MC_CMD_FCNTL_OFF 0x0 */ 6547 6038 /* enum: Respond to flow control. */ 6548 6548 - #define MC_CMD_FCNTL_RESPOND 0x1 6039 6039 + /* MC_CMD_FCNTL_RESPOND 0x1 */ 6549 6040 /* enum: Respond to and Issue flow control. */ 6550 6550 - #define MC_CMD_FCNTL_BIDIR 0x2 6551 6551 - /* enum: Auto neg flow control. */ 6552 6552 - #define MC_CMD_FCNTL_AUTO 0x3 6553 6553 - /* enum: Priority flow control (eftest builds only). */ 6554 6554 - #define MC_CMD_FCNTL_QBB 0x4 6041 6041 + /* MC_CMD_FCNTL_BIDIR 0x2 */ 6042 6042 + /* enum: Auto negotiate flow control. */ 6043 6043 + /* MC_CMD_FCNTL_AUTO 0x3 */ 6044 6044 + /* enum: Priority flow control. This is only supported on KSB. */ 6045 6045 + /* MC_CMD_FCNTL_QBB 0x4 */ 6555 6046 /* enum: Issue flow control. */ 6556 6556 - #define MC_CMD_FCNTL_GENERATE 0x5 6047 6047 + /* MC_CMD_FCNTL_GENERATE 0x5 */ 6557 6048 #define MC_CMD_SET_MAC_IN_FLAGS_OFST 24 6558 6049 #define MC_CMD_SET_MAC_IN_FLAGS_LEN 4 6559 6050 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_OFST 24 ··· 6595 6086 /* MC_CMD_FCNTL_RESPOND 0x1 */ 6596 6087 /* enum: Respond to and Issue flow control. */ 6597 6088 /* MC_CMD_FCNTL_BIDIR 0x2 */ 6598 6598 - /* enum: Auto neg flow control. */ 6089 6089 + /* enum: Auto negotiate flow control. */ 6599 6090 /* MC_CMD_FCNTL_AUTO 0x3 */ 6600 6600 - /* enum: Priority flow control (eftest builds only). */ 6091 6091 + /* enum: Priority flow control. This is only supported on KSB. */ 6601 6092 /* MC_CMD_FCNTL_QBB 0x4 */ 6602 6093 /* enum: Issue flow control. */ 6603 6094 /* MC_CMD_FCNTL_GENERATE 0x5 */ ··· 6664 6155 /* MC_CMD_FCNTL_RESPOND 0x1 */ 6665 6156 /* enum: Respond to and Issue flow control. */ 6666 6157 /* MC_CMD_FCNTL_BIDIR 0x2 */ 6667 6667 - /* enum: Auto neg flow control. */ 6158 6158 + /* enum: Auto negotiate flow control. */ 6668 6159 /* MC_CMD_FCNTL_AUTO 0x3 */ 6669 6669 - /* enum: Priority flow control (eftest builds only). */ 6160 6160 + /* enum: Priority flow control. This is only supported on KSB. */ 6670 6161 /* MC_CMD_FCNTL_QBB 0x4 */ 6671 6162 /* enum: Issue flow control. */ 6672 6163 /* MC_CMD_FCNTL_GENERATE 0x5 */ ··· 6697 6188 #define MC_CMD_SET_MAC_V3_IN_CFG_FCS_OFST 28 6698 6189 #define MC_CMD_SET_MAC_V3_IN_CFG_FCS_LBN 4 6699 6190 #define MC_CMD_SET_MAC_V3_IN_CFG_FCS_WIDTH 1 6700 6700 - /* Identifies the MAC to update by the specifying the end of a logical MAE 6701 6701 - * link. Setting TARGET to MAE_LINK_ENDPOINT_COMPAT is equivalent to using the 6702 6702 - * previous version of the command (MC_CMD_SET_MAC_EXT). Not all possible 6703 6703 - * combinations of MPORT_END and MPORT_SELECTOR in TARGET will work in all 6704 6704 - * circumstances. 1. Some will always work (e.g. a VF can always address its 6705 6705 - * logical MAC using MPORT_SELECTOR=ASSIGNED,LINK_END=VNIC), 2. Some are not 6706 6706 - * meaningful and will always fail with EINVAL (e.g. attempting to address the 6707 6707 - * VNIC end of a link to a physical port), 3. Some are meaningful but require 6708 6708 - * the MCDI client to have the required permission and fail with EPERM 6709 6709 - * otherwise (e.g. trying to set the MAC on a VF the caller cannot administer), 6710 6710 - * and 4. Some could be implementation-specific and fail with ENOTSUP if not 6711 6711 - * available (no examples exist right now). See SF-123581-TC section 4.3 for 6712 6712 - * more details. 6191 6191 + /* Target port to set mac state for. Uses MAE_LINK_ENDPOINT_SELECTOR which 6192 6192 + * identifies a real or virtual network port by MAE port and link end. See the 6193 6193 + * structure definition for more details 6713 6194 */ 6714 6195 #define MC_CMD_SET_MAC_V3_IN_TARGET_OFST 32 6715 6196 #define MC_CMD_SET_MAC_V3_IN_TARGET_LEN 8 ··· 6711 6212 #define MC_CMD_SET_MAC_V3_IN_TARGET_HI_LEN 4 6712 6213 #define MC_CMD_SET_MAC_V3_IN_TARGET_HI_LBN 288 6713 6214 #define MC_CMD_SET_MAC_V3_IN_TARGET_HI_WIDTH 32 6215 6215 + /* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */ 6714 6216 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_OFST 32 6715 6217 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_LEN 4 6716 6218 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 32 ··· 6905 6405 #define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16 6906 6406 #define MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4 6907 6407 6408 6408 + /* MC_CMD_MAC_STATS_V2_IN msgrequest */ 6409 6409 + #define MC_CMD_MAC_STATS_V2_IN_LEN 28 6410 6410 + /* ??? */ 6411 6411 + #define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_OFST 0 6412 6412 + #define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_LEN 8 6413 6413 + #define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_LO_OFST 0 6414 6414 + #define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_LO_LEN 4 6415 6415 + #define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_LO_LBN 0 6416 6416 + #define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_LO_WIDTH 32 6417 6417 + #define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_HI_OFST 4 6418 6418 + #define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_HI_LEN 4 6419 6419 + #define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_HI_LBN 32 6420 6420 + #define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_HI_WIDTH 32 6421 6421 + #define MC_CMD_MAC_STATS_V2_IN_CMD_OFST 8 6422 6422 + #define MC_CMD_MAC_STATS_V2_IN_CMD_LEN 4 6423 6423 + #define MC_CMD_MAC_STATS_V2_IN_DMA_OFST 8 6424 6424 + #define MC_CMD_MAC_STATS_V2_IN_DMA_LBN 0 6425 6425 + #define MC_CMD_MAC_STATS_V2_IN_DMA_WIDTH 1 6426 6426 + #define MC_CMD_MAC_STATS_V2_IN_CLEAR_OFST 8 6427 6427 + #define MC_CMD_MAC_STATS_V2_IN_CLEAR_LBN 1 6428 6428 + #define MC_CMD_MAC_STATS_V2_IN_CLEAR_WIDTH 1 6429 6429 + #define MC_CMD_MAC_STATS_V2_IN_PERIODIC_CHANGE_OFST 8 6430 6430 + #define MC_CMD_MAC_STATS_V2_IN_PERIODIC_CHANGE_LBN 2 6431 6431 + #define MC_CMD_MAC_STATS_V2_IN_PERIODIC_CHANGE_WIDTH 1 6432 6432 + #define MC_CMD_MAC_STATS_V2_IN_PERIODIC_ENABLE_OFST 8 6433 6433 + #define MC_CMD_MAC_STATS_V2_IN_PERIODIC_ENABLE_LBN 3 6434 6434 + #define MC_CMD_MAC_STATS_V2_IN_PERIODIC_ENABLE_WIDTH 1 6435 6435 + #define MC_CMD_MAC_STATS_V2_IN_PERIODIC_CLEAR_OFST 8 6436 6436 + #define MC_CMD_MAC_STATS_V2_IN_PERIODIC_CLEAR_LBN 4 6437 6437 + #define MC_CMD_MAC_STATS_V2_IN_PERIODIC_CLEAR_WIDTH 1 6438 6438 + #define MC_CMD_MAC_STATS_V2_IN_PERIODIC_NOEVENT_OFST 8 6439 6439 + #define MC_CMD_MAC_STATS_V2_IN_PERIODIC_NOEVENT_LBN 5 6440 6440 + #define MC_CMD_MAC_STATS_V2_IN_PERIODIC_NOEVENT_WIDTH 1 6441 6441 + #define MC_CMD_MAC_STATS_V2_IN_PERIOD_MS_OFST 8 6442 6442 + #define MC_CMD_MAC_STATS_V2_IN_PERIOD_MS_LBN 16 6443 6443 + #define MC_CMD_MAC_STATS_V2_IN_PERIOD_MS_WIDTH 16 6444 6444 + /* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as 6445 6445 + * returned by MC_CMD_GET_CAPABILITIES_V4_OUT. For legacy firmware not 6446 6446 + * supporting MC_CMD_GET_CAPABILITIES_V4_OUT, DMA_LEN should be set to 6447 6447 + * MC_CMD_MAC_NSTATS * sizeof(uint64_t) 6448 6448 + */ 6449 6449 + #define MC_CMD_MAC_STATS_V2_IN_DMA_LEN_OFST 12 6450 6450 + #define MC_CMD_MAC_STATS_V2_IN_DMA_LEN_LEN 4 6451 6451 + /* port id so vadapter stats can be provided */ 6452 6452 + #define MC_CMD_MAC_STATS_V2_IN_PORT_ID_OFST 16 6453 6453 + #define MC_CMD_MAC_STATS_V2_IN_PORT_ID_LEN 4 6454 6454 + /* Target port to request statistics for. Uses MAE_LINK_ENDPOINT_SELECTOR which 6455 6455 + * identifies a real or virtual network port by MAE port and link end. See the 6456 6456 + * structure definition for more details 6457 6457 + */ 6458 6458 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_OFST 20 6459 6459 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_LEN 8 6460 6460 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_LO_OFST 20 6461 6461 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_LO_LEN 4 6462 6462 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_LO_LBN 160 6463 6463 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_LO_WIDTH 32 6464 6464 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_HI_OFST 24 6465 6465 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_HI_LEN 4 6466 6466 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_HI_LBN 192 6467 6467 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_HI_WIDTH 32 6468 6468 + /* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */ 6469 6469 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_OFST 20 6470 6470 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_LEN 4 6471 6471 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 20 6472 6472 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4 6473 6473 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 23 6474 6474 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1 6475 6475 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 20 6476 6476 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3 6477 6477 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 160 6478 6478 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4 6479 6479 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 180 6480 6480 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4 6481 6481 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 176 6482 6482 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4 6483 6483 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 22 6484 6484 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1 6485 6485 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 20 6486 6486 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2 6487 6487 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_LINK_END_OFST 24 6488 6488 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_LINK_END_LEN 4 6489 6489 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_OFST 20 6490 6490 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_LEN 8 6491 6491 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_LO_OFST 20 6492 6492 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_LO_LEN 4 6493 6493 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_LO_LBN 160 6494 6494 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_LO_WIDTH 32 6495 6495 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_HI_OFST 24 6496 6496 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_HI_LEN 4 6497 6497 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_HI_LBN 192 6498 6498 + #define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_HI_WIDTH 32 6499 6499 + 6908 6500 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 6909 6501 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 6910 6502 ··· 7013 6421 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LBN 32 7014 6422 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_WIDTH 32 7015 6423 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 6424 6424 + /* enum property: index */ 7016 6425 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 7017 6426 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */ 7018 6427 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ ··· 7176 6583 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LBN 32 7177 6584 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_WIDTH 32 7178 6585 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2 6586 6586 + /* enum property: index */ 7179 6587 /* enum: Start of FEC stats buffer space, Medford2 and up */ 7180 6588 #define MC_CMD_MAC_FEC_DMABUF_START 0x61 7181 6589 /* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2) ··· 7216 6622 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LBN 32 7217 6623 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_WIDTH 32 7218 6624 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3 6625 6625 + /* enum property: index */ 7219 6626 /* enum: Start of CTPIO stats buffer space, Medford2 and up */ 7220 6627 #define MC_CMD_MAC_CTPIO_DMABUF_START 0x68 7221 6628 /* enum: Number of CTPIO fallbacks because a DMA packet was in progress on the ··· 7297 6702 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LBN 32 7298 6703 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_WIDTH 32 7299 6704 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V4 6705 6705 + /* enum property: index */ 7300 6706 /* enum: Start of V4 stats buffer space */ 7301 6707 #define MC_CMD_MAC_V4_DMABUF_START 0x79 7302 6708 /* enum: RXDP counter: Number of packets truncated because scattering was ··· 7319 6723 /* Other enum values, see field(s): */ 7320 6724 /* MC_CMD_MAC_STATS_V3_OUT_NO_DMA/STATISTICS */ 7321 6725 6726 6726 + /* MC_CMD_MAC_STATS_V5_OUT_DMA msgresponse */ 6727 6727 + #define MC_CMD_MAC_STATS_V5_OUT_DMA_LEN 0 7322 6728 7323 7323 - /***********************************/ 7324 7324 - /* MC_CMD_SRIOV 7325 7325 - * to be documented 6729 6729 + /* MC_CMD_MAC_STATS_V5_OUT_NO_DMA msgresponse */ 6730 6730 + #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V5*64))>>3) 6731 6731 + #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_OFST 0 6732 6732 + #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LEN 8 6733 6733 + #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_OFST 0 6734 6734 + #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_LEN 4 6735 6735 + #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_LBN 0 6736 6736 + #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_WIDTH 32 6737 6737 + #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_OFST 4 6738 6738 + #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_LEN 4 6739 6739 + #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_LBN 32 6740 6740 + #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_WIDTH 32 6741 6741 + #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V5 6742 6742 + /* enum property: index */ 6743 6743 + /* enum: Start of V5 stats buffer space */ 6744 6744 + #define MC_CMD_MAC_V5_DMABUF_START 0x7c 6745 6745 + /* enum: Link toggle counter: Number of times the link has toggled between 6746 6746 + * up/down and down/up 7326 6747 */ 7327 7327 - #define MC_CMD_SRIOV 0x30 7328 7328 - 7329 7329 - /* MC_CMD_SRIOV_IN msgrequest */ 7330 7330 - #define MC_CMD_SRIOV_IN_LEN 12 7331 7331 - #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 7332 7332 - #define MC_CMD_SRIOV_IN_ENABLE_LEN 4 7333 7333 - #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 7334 7334 - #define MC_CMD_SRIOV_IN_VI_BASE_LEN 4 7335 7335 - #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 7336 7336 - #define MC_CMD_SRIOV_IN_VF_COUNT_LEN 4 7337 7337 - 7338 7338 - /* MC_CMD_SRIOV_OUT msgresponse */ 7339 7339 - #define MC_CMD_SRIOV_OUT_LEN 8 7340 7340 - #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 7341 7341 - #define MC_CMD_SRIOV_OUT_VI_SCALE_LEN 4 7342 7342 - #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 7343 7343 - #define MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 4 7344 7344 - 7345 7345 - /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 7346 7346 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 7347 7347 - /* this is only used for the first record */ 7348 7348 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 7349 7349 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 4 7350 7350 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 7351 7351 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 7352 7352 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 7353 7353 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 4 7354 7354 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 7355 7355 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 7356 7356 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 7357 7357 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 7358 7358 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 7359 7359 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LEN 4 7360 7360 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LBN 64 7361 7361 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_WIDTH 32 7362 7362 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 7363 7363 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LEN 4 7364 7364 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LBN 96 7365 7365 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_WIDTH 32 7366 7366 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 7367 7367 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 7368 7368 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 7369 7369 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 4 7370 7370 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 7371 7371 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 7372 7372 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 7373 7373 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 7374 7374 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 7375 7375 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 7376 7376 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LEN 4 7377 7377 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LBN 160 7378 7378 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_WIDTH 32 7379 7379 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 7380 7380 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LEN 4 7381 7381 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LBN 192 7382 7382 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_WIDTH 32 7383 7383 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 7384 7384 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 7385 7385 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 7386 7386 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 4 7387 7387 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 7388 7388 - #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 7389 7389 - 7390 7390 - 7391 7391 - /***********************************/ 7392 7392 - /* MC_CMD_MEMCPY 7393 7393 - * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data 7394 7394 - * embedded directly in the command. 7395 7395 - * 7396 7396 - * A common pattern is for a client to use generation counts to signal a dma 7397 7397 - * update of a datastructure. To facilitate this, this MCDI operation can 7398 7398 - * contain multiple requests which are executed in strict order. Requests take 7399 7399 - * the form of duplicating the entire MCDI request continuously (including the 7400 7400 - * requests record, which is ignored in all but the first structure) 7401 7401 - * 7402 7402 - * The source data can either come from a DMA from the host, or it can be 7403 7403 - * embedded within the request directly, thereby eliminating a DMA read. To 7404 7404 - * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and 7405 7405 - * ADDR_LO=offset, and inserts the data at %offset from the start of the 7406 7406 - * payload. It's the callers responsibility to ensure that the embedded data 7407 7407 - * doesn't overlap the records. 7408 7408 - * 7409 7409 - * Returns: 0, EINVAL (invalid RID) 6748 6748 + #define MC_CMD_MAC_LINK_TOGGLES 0x7c 6749 6749 + /* enum: This includes the space at offset 125 which is the final 6750 6750 + * GENERATION_END in a MAC_STATS_V5 response and otherwise unused. 7410 6751 */ 7411 7411 - #define MC_CMD_MEMCPY 0x31 7412 7412 - 7413 7413 - /* MC_CMD_MEMCPY_IN msgrequest */ 7414 7414 - #define MC_CMD_MEMCPY_IN_LENMIN 32 7415 7415 - #define MC_CMD_MEMCPY_IN_LENMAX 224 7416 7416 - #define MC_CMD_MEMCPY_IN_LENMAX_MCDI2 992 7417 7417 - #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 7418 7418 - #define MC_CMD_MEMCPY_IN_RECORD_NUM(len) (((len)-0)/32) 7419 7419 - /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ 7420 7420 - #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 7421 7421 - #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 7422 7422 - #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 7423 7423 - #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 7424 7424 - #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM_MCDI2 31 7425 7425 - 7426 7426 - /* MC_CMD_MEMCPY_OUT msgresponse */ 7427 7427 - #define MC_CMD_MEMCPY_OUT_LEN 0 6752 6752 + #define MC_CMD_MAC_NSTATS_V5 0x7e 6753 6753 + /* Other enum values, see field(s): */ 6754 6754 + /* MC_CMD_MAC_STATS_V4_OUT_NO_DMA/STATISTICS */ 7428 6755 7429 6756 7430 6757 /***********************************/ ··· 7503 6984 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 7504 6985 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 7505 6986 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4 6987 6987 + /* enum property: bitmask */ 7506 6988 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 7507 6989 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 7508 6990 7509 6991 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 7510 6992 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 7511 7511 - 7512 7512 - 7513 7513 - /***********************************/ 7514 7514 - /* MC_CMD_SET_MCAST_HASH 7515 7515 - * Set the MCAST hash value without otherwise reconfiguring the MAC 7516 7516 - */ 7517 7517 - #define MC_CMD_SET_MCAST_HASH 0x35 7518 7518 - 7519 7519 - /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 7520 7520 - #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 7521 7521 - #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 7522 7522 - #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 7523 7523 - #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 7524 7524 - #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 7525 7525 - 7526 7526 - /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 7527 7527 - #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 7528 6993 7529 6994 7530 6995 /***********************************/ ··· 7529 7026 /* Bit mask of supported types. */ 7530 7027 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 7531 7028 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4 7029 7029 + /* enum property: bitshift */ 7532 7030 /* enum: Disabled callisto. */ 7533 7031 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 7534 7032 /* enum: MC firmware. */ ··· 7656 7152 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_OFST 12 7657 7153 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7 7658 7154 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1 7155 7155 + #define MC_CMD_NVRAM_INFO_V2_OUT_WRITE_ONLY_OFST 12 7156 7156 + #define MC_CMD_NVRAM_INFO_V2_OUT_WRITE_ONLY_LBN 8 7157 7157 + #define MC_CMD_NVRAM_INFO_V2_OUT_WRITE_ONLY_WIDTH 1 7158 7158 + #define MC_CMD_NVRAM_INFO_V2_OUT_SEQUENTIAL_WRITE_OFST 12 7159 7159 + #define MC_CMD_NVRAM_INFO_V2_OUT_SEQUENTIAL_WRITE_LBN 9 7160 7160 + #define MC_CMD_NVRAM_INFO_V2_OUT_SEQUENTIAL_WRITE_WIDTH 1 7659 7161 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16 7660 7162 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4 7661 7163 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20 ··· 8009 7499 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x19 8010 7500 /* enum: The update operation is in-progress. */ 8011 7501 #define MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a 7502 7502 + /* enum: The update was an invalid user configuration file. */ 7503 7503 + #define MC_CMD_NVRAM_VERIFY_RC_BAD_CONFIG 0x1b 7504 7504 + /* enum: The write was to the AUTO partition but the data was not recognised as 7505 7505 + * a valid partition. 7506 7506 + */ 7507 7507 + #define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN_TYPE 0x1c 7508 7508 + 7509 7509 + /* MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT msgresponse */ 7510 7510 + #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_LEN 88 7511 7511 + /* Result of nvram update completion processing. Result codes that indicate an 7512 7512 + * internal build failure and therefore not expected to be seen by customers in 7513 7513 + * the field are marked with a prefix 'Internal-error'. 7514 7514 + */ 7515 7515 + #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_RESULT_CODE_OFST 0 7516 7516 + #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_RESULT_CODE_LEN 4 7517 7517 + /* enum: Invalid return code; only non-zero values are defined. Defined as 7518 7518 + * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT. 7519 7519 + */ 7520 7520 + /* MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0 */ 7521 7521 + /* enum: Verify succeeded without any errors. */ 7522 7522 + /* MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1 */ 7523 7523 + /* enum: CMS format verification failed due to an internal error. */ 7524 7524 + /* MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2 */ 7525 7525 + /* enum: Invalid CMS format in image metadata. */ 7526 7526 + /* MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3 */ 7527 7527 + /* enum: Message digest verification failed due to an internal error. */ 7528 7528 + /* MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4 */ 7529 7529 + /* enum: Error in message digest calculated over the reflash-header, payload 7530 7530 + * and reflash-trailer. 7531 7531 + */ 7532 7532 + /* MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5 */ 7533 7533 + /* enum: Signature verification failed due to an internal error. */ 7534 7534 + /* MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6 */ 7535 7535 + /* enum: There are no valid signatures in the image. */ 7536 7536 + /* MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7 */ 7537 7537 + /* enum: Trusted approvers verification failed due to an internal error. */ 7538 7538 + /* MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8 */ 7539 7539 + /* enum: The Trusted approver's list is empty. */ 7540 7540 + /* MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9 */ 7541 7541 + /* enum: Signature chain verification failed due to an internal error. */ 7542 7542 + /* MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa */ 7543 7543 + /* enum: The signers of the signatures in the image are not listed in the 7544 7544 + * Trusted approver's list. 7545 7545 + */ 7546 7546 + /* MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb */ 7547 7547 + /* enum: The image contains a test-signed certificate, but the adapter accepts 7548 7548 + * only production signed images. 7549 7549 + */ 7550 7550 + /* MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc */ 7551 7551 + /* enum: The image has a lower security level than the current firmware. */ 7552 7552 + /* MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd */ 7553 7553 + /* enum: Internal-error. The signed image is missing the 'contents' section, 7554 7554 + * where the 'contents' section holds the actual image payload to be applied. 7555 7555 + */ 7556 7556 + /* MC_CMD_NVRAM_VERIFY_RC_CONTENT_NOT_FOUND 0xe */ 7557 7557 + /* enum: Internal-error. The bundle header is invalid. */ 7558 7558 + /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_CONTENT_HEADER_INVALID 0xf */ 7559 7559 + /* enum: Internal-error. The bundle does not have a valid reflash image layout. 7560 7560 + */ 7561 7561 + /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_REFLASH_IMAGE_INVALID 0x10 */ 7562 7562 + /* enum: Internal-error. The bundle has an inconsistent layout of components or 7563 7563 + * incorrect checksum. 7564 7564 + */ 7565 7565 + /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_IMAGE_LAYOUT_INVALID 0x11 */ 7566 7566 + /* enum: Internal-error. The bundle manifest is inconsistent with components in 7567 7567 + * the bundle. 7568 7568 + */ 7569 7569 + /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_INVALID 0x12 */ 7570 7570 + /* enum: Internal-error. The number of components in a bundle do not match the 7571 7571 + * number of components advertised by the bundle manifest. 7572 7572 + */ 7573 7573 + /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_NUM_COMPONENTS_MISMATCH 0x13 */ 7574 7574 + /* enum: Internal-error. The bundle contains too many components for the MC 7575 7575 + * firmware to process 7576 7576 + */ 7577 7577 + /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_TOO_MANY_COMPONENTS 0x14 */ 7578 7578 + /* enum: Internal-error. The bundle manifest has an invalid/inconsistent 7579 7579 + * component. 7580 7580 + */ 7581 7581 + /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_INVALID 0x15 */ 7582 7582 + /* enum: Internal-error. The hash of a component does not match the hash stored 7583 7583 + * in the bundle manifest. 7584 7584 + */ 7585 7585 + /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_MISMATCH 0x16 */ 7586 7586 + /* enum: Internal-error. Component hash calculation failed. */ 7587 7587 + /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_FAILED 0x17 */ 7588 7588 + /* enum: Internal-error. The component does not have a valid reflash image 7589 7589 + * layout. 7590 7590 + */ 7591 7591 + /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_REFLASH_IMAGE_INVALID 0x18 */ 7592 7592 + /* enum: The bundle processing code failed to copy a component to its target 7593 7593 + * partition. 7594 7594 + */ 7595 7595 + /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x19 */ 7596 7596 + /* enum: The update operation is in-progress. */ 7597 7597 + /* MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a */ 7598 7598 + /* enum: The update was an invalid user configuration file. */ 7599 7599 + /* MC_CMD_NVRAM_VERIFY_RC_BAD_CONFIG 0x1b */ 7600 7600 + /* enum: The write was to the AUTO partition but the data was not recognised as 7601 7601 + * a valid partition. 7602 7602 + */ 7603 7603 + /* MC_CMD_NVRAM_VERIFY_RC_UNKNOWN_TYPE 0x1c */ 7604 7604 + /* If the update was a user configuration, what action(s) the user must take to 7605 7605 + * apply the new configuration. 7606 7606 + */ 7607 7607 + #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_ACTIONS_REQUIRED_OFST 4 7608 7608 + #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_ACTIONS_REQUIRED_LEN 4 7609 7609 + /* enum: No action required. */ 7610 7610 + #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_NONE 0x0 7611 7611 + /* enum: The MC firmware must be rebooted (eg with MC_CMD_REBOOT). */ 7612 7612 + #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_FIRMWARE_REBOOT 0x1 7613 7613 + /* enum: The host must be rebooted. */ 7614 7614 + #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_HOST_REBOOT 0x2 7615 7615 + /* enum: The firmware and host must be rebooted (in either order). */ 7616 7616 + #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_FIRMWARE_AND_HOST_REBOOT 0x3 7617 7617 + /* enum: The host must be fully powered off. */ 7618 7618 + #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_HOST_POWERCYCLE 0x4 7619 7619 + /* If the update failed with MC_CMD_NVRAM_VERIFY_RC_BAD_CONFIG, a null- 7620 7620 + * terminated US-ASCII string suitable for showing to the user. 7621 7621 + */ 7622 7622 + #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_ERROR_STRING_OFST 8 7623 7623 + #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_ERROR_STRING_LEN 80 8012 7624 8013 7625 8014 7626 /***********************************/ ··· 8154 7522 #define MC_CMD_REBOOT 0x3d 8155 7523 #undef MC_CMD_0x3d_PRIVILEGE_CTG 8156 7524 8157 8157 - #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7525 7525 + #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 8158 7526 8159 7527 /* MC_CMD_REBOOT_IN msgrequest */ 8160 7528 #define MC_CMD_REBOOT_IN_LEN 4 ··· 8164 7532 8165 7533 /* MC_CMD_REBOOT_OUT msgresponse */ 8166 7534 #define MC_CMD_REBOOT_OUT_LEN 0 8167 8167 - 8168 8168 - 8169 8169 - /***********************************/ 8170 8170 - /* MC_CMD_SCHEDINFO 8171 8171 - * Request scheduler info. Locks required: NONE. Returns: An array of 8172 8172 - * (timeslice,maximum overrun), one for each thread, in ascending order of 8173 8173 - * thread address. 8174 8174 - */ 8175 8175 - #define MC_CMD_SCHEDINFO 0x3e 8176 8176 - #undef MC_CMD_0x3e_PRIVILEGE_CTG 8177 8177 - 8178 8178 - #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8179 8179 - 8180 8180 - /* MC_CMD_SCHEDINFO_IN msgrequest */ 8181 8181 - #define MC_CMD_SCHEDINFO_IN_LEN 0 8182 8182 - 8183 8183 - /* MC_CMD_SCHEDINFO_OUT msgresponse */ 8184 8184 - #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 8185 8185 - #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 8186 8186 - #define MC_CMD_SCHEDINFO_OUT_LENMAX_MCDI2 1020 8187 8187 - #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 8188 8188 - #define MC_CMD_SCHEDINFO_OUT_DATA_NUM(len) (((len)-0)/4) 8189 8189 - #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 8190 8190 - #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 8191 8191 - #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 8192 8192 - #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 8193 8193 - #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM_MCDI2 255 8194 8194 - 8195 8195 - 8196 8196 - /***********************************/ 8197 8197 - /* MC_CMD_REBOOT_MODE 8198 8198 - * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot 8199 8199 - * mode to the specified value. Returns the old mode. 8200 8200 - */ 8201 8201 - #define MC_CMD_REBOOT_MODE 0x3f 8202 8202 - #undef MC_CMD_0x3f_PRIVILEGE_CTG 8203 8203 - 8204 8204 - #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE 8205 8205 - 8206 8206 - /* MC_CMD_REBOOT_MODE_IN msgrequest */ 8207 8207 - #define MC_CMD_REBOOT_MODE_IN_LEN 4 8208 8208 - #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 8209 8209 - #define MC_CMD_REBOOT_MODE_IN_VALUE_LEN 4 8210 8210 - /* enum: Normal. */ 8211 8211 - #define MC_CMD_REBOOT_MODE_NORMAL 0x0 8212 8212 - /* enum: Power-on Reset. */ 8213 8213 - #define MC_CMD_REBOOT_MODE_POR 0x2 8214 8214 - /* enum: Snapper. */ 8215 8215 - #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 8216 8216 - /* enum: snapper fake POR */ 8217 8217 - #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 8218 8218 - #define MC_CMD_REBOOT_MODE_IN_FAKE_OFST 0 8219 8219 - #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 8220 8220 - #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 8221 8221 - 8222 8222 - /* MC_CMD_REBOOT_MODE_OUT msgresponse */ 8223 8223 - #define MC_CMD_REBOOT_MODE_OUT_LEN 4 8224 8224 - #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 8225 8225 - #define MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4 8226 7535 8227 7536 8228 7537 /***********************************/ ··· 8634 8061 /* MC_CMD_GET_PHY_STATE_IN msgrequest */ 8635 8062 #define MC_CMD_GET_PHY_STATE_IN_LEN 0 8636 8063 8064 8064 + /* MC_CMD_GET_PHY_STATE_IN_V2 msgrequest */ 8065 8065 + #define MC_CMD_GET_PHY_STATE_IN_V2_LEN 8 8066 8066 + /* Target port to request PHY state for. Uses MAE_LINK_ENDPOINT_SELECTOR which 8067 8067 + * identifies a real or virtual network port by MAE port and link end. See the 8068 8068 + * structure definition for more details. 8069 8069 + */ 8070 8070 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_OFST 0 8071 8071 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LEN 8 8072 8072 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LO_OFST 0 8073 8073 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LO_LEN 4 8074 8074 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LO_LBN 0 8075 8075 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LO_WIDTH 32 8076 8076 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_HI_OFST 4 8077 8077 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_HI_LEN 4 8078 8078 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_HI_LBN 32 8079 8079 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_HI_WIDTH 32 8080 8080 + /* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */ 8081 8081 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_OFST 0 8082 8082 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_LEN 4 8083 8083 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FLAT_OFST 0 8084 8084 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FLAT_LEN 4 8085 8085 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_TYPE_OFST 3 8086 8086 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_TYPE_LEN 1 8087 8087 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0 8088 8088 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3 8089 8089 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0 8090 8090 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4 8091 8091 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20 8092 8092 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4 8093 8093 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16 8094 8094 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4 8095 8095 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2 8096 8096 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1 8097 8097 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0 8098 8098 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2 8099 8099 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LINK_END_OFST 4 8100 8100 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LINK_END_LEN 4 8101 8101 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_OFST 0 8102 8102 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_LEN 8 8103 8103 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_LO_OFST 0 8104 8104 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_LO_LEN 4 8105 8105 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_LO_LBN 0 8106 8106 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_LO_WIDTH 32 8107 8107 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_HI_OFST 4 8108 8108 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_HI_LEN 4 8109 8109 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_HI_LBN 32 8110 8110 + #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_HI_WIDTH 32 8111 8111 + 8637 8112 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 8638 8113 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 8639 8114 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 ··· 8690 8069 #define MC_CMD_PHY_STATE_OK 0x1 8691 8070 /* enum: Faulty. */ 8692 8071 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 8693 8693 - 8694 8694 - 8695 8695 - /***********************************/ 8696 8696 - /* MC_CMD_SETUP_8021QBB 8697 8697 - * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to 8698 8698 - * disable 802.Qbb for a given priority. 8699 8699 - */ 8700 8700 - #define MC_CMD_SETUP_8021QBB 0x44 8701 8701 - 8702 8702 - /* MC_CMD_SETUP_8021QBB_IN msgrequest */ 8703 8703 - #define MC_CMD_SETUP_8021QBB_IN_LEN 32 8704 8704 - #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 8705 8705 - #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 8706 8706 - 8707 8707 - /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 8708 8708 - #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 8709 8072 8710 8073 8711 8074 /***********************************/ ··· 8708 8103 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 8709 8104 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 8710 8105 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4 8711 8711 - 8712 8712 - 8713 8713 - /***********************************/ 8714 8714 - /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 8715 8715 - * Add a protocol offload to NIC for lights-out state. Locks required: None. 8716 8716 - * Returns: 0, ENOSYS 8717 8717 - */ 8718 8718 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 8719 8719 - #undef MC_CMD_0x46_PRIVILEGE_CTG 8720 8720 - 8721 8721 - #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK 8722 8722 - 8723 8723 - /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 8724 8724 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 8725 8725 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 8726 8726 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX_MCDI2 1020 8727 8727 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 8728 8728 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_NUM(len) (((len)-4)/4) 8729 8729 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 8730 8730 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 8731 8731 - #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 8732 8732 - #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 8733 8733 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 8734 8734 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 8735 8735 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 8736 8736 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 8737 8737 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM_MCDI2 254 8738 8738 - 8739 8739 - /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 8740 8740 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 8741 8741 - /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 8742 8742 - /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */ 8743 8743 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 8744 8744 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 8745 8745 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 8746 8746 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 4 8747 8747 - 8748 8748 - /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 8749 8749 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 8750 8750 - /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 8751 8751 - /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */ 8752 8752 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 8753 8753 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 8754 8754 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 8755 8755 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 8756 8756 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 8757 8757 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 8758 8758 - 8759 8759 - /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 8760 8760 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 8761 8761 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 8762 8762 - #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4 8763 8763 - 8764 8764 - 8765 8765 - /***********************************/ 8766 8766 - /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 8767 8767 - * Remove a protocol offload from NIC for lights-out state. Locks required: 8768 8768 - * None. Returns: 0, ENOSYS 8769 8769 - */ 8770 8770 - #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 8771 8771 - #undef MC_CMD_0x47_PRIVILEGE_CTG 8772 8772 - 8773 8773 - #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK 8774 8774 - 8775 8775 - /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 8776 8776 - #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 8777 8777 - #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 8778 8778 - #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 8779 8779 - #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 8780 8780 - #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 4 8781 8781 - 8782 8782 - /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 8783 8783 - #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 8784 8784 - 8785 8785 - 8786 8786 - /***********************************/ 8787 8787 - /* MC_CMD_MAC_RESET_RESTORE 8788 8788 - * Restore MAC after block reset. Locks required: None. Returns: 0. 8789 8789 - */ 8790 8790 - #define MC_CMD_MAC_RESET_RESTORE 0x48 8791 8791 - 8792 8792 - /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 8793 8793 - #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 8794 8794 - 8795 8795 - /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 8796 8796 - #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 8797 8797 - 8798 8798 - 8799 8799 - /***********************************/ 8800 8800 - /* MC_CMD_TESTASSERT 8801 8801 - * Deliberately trigger an assert-detonation in the firmware for testing 8802 8802 - * purposes (i.e. to allow tests that the driver copes gracefully). Locks 8803 8803 - * required: None Returns: 0 8804 8804 - */ 8805 8805 - #define MC_CMD_TESTASSERT 0x49 8806 8806 - #undef MC_CMD_0x49_PRIVILEGE_CTG 8807 8807 - 8808 8808 - #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8809 8809 - 8810 8810 - /* MC_CMD_TESTASSERT_IN msgrequest */ 8811 8811 - #define MC_CMD_TESTASSERT_IN_LEN 0 8812 8812 - 8813 8813 - /* MC_CMD_TESTASSERT_OUT msgresponse */ 8814 8814 - #define MC_CMD_TESTASSERT_OUT_LEN 0 8815 8815 - 8816 8816 - /* MC_CMD_TESTASSERT_V2_IN msgrequest */ 8817 8817 - #define MC_CMD_TESTASSERT_V2_IN_LEN 4 8818 8818 - /* How to provoke the assertion */ 8819 8819 - #define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0 8820 8820 - #define MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4 8821 8821 - /* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless 8822 8822 - * you're testing firmware, this is what you want. 8823 8823 - */ 8824 8824 - #define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0 8825 8825 - /* enum: Assert using assert(0); */ 8826 8826 - #define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1 8827 8827 - /* enum: Deliberately trigger a watchdog */ 8828 8828 - #define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2 8829 8829 - /* enum: Deliberately trigger a trap by loading from an invalid address */ 8830 8830 - #define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3 8831 8831 - /* enum: Deliberately trigger a trap by storing to an invalid address */ 8832 8832 - #define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4 8833 8833 - /* enum: Jump to an invalid address */ 8834 8834 - #define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5 8835 8835 - 8836 8836 - /* MC_CMD_TESTASSERT_V2_OUT msgresponse */ 8837 8837 - #define MC_CMD_TESTASSERT_V2_OUT_LEN 0 8838 8106 8839 8107 8840 8108 /***********************************/ ··· 8802 8324 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_BANK_LBN 16 8803 8325 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_BANK_WIDTH 16 8804 8326 8327 8327 + /* MC_CMD_GET_PHY_MEDIA_INFO_IN_V2 msgrequest */ 8328 8328 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_LEN 12 8329 8329 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_PAGE_OFST 0 8330 8330 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_PAGE_LEN 4 8331 8331 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_DSFP_PAGE_OFST 0 8332 8332 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_DSFP_PAGE_LBN 0 8333 8333 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_DSFP_PAGE_WIDTH 16 8334 8334 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_DSFP_BANK_OFST 0 8335 8335 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_DSFP_BANK_LBN 16 8336 8336 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_DSFP_BANK_WIDTH 16 8337 8337 + /* Target port to request PHY state for. Uses MAE_LINK_ENDPOINT_SELECTOR which 8338 8338 + * identifies a real or virtual network port by MAE port and link end. See the 8339 8339 + * structure definition for more details 8340 8340 + */ 8341 8341 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_OFST 4 8342 8342 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_LEN 8 8343 8343 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_LO_OFST 4 8344 8344 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_LO_LEN 4 8345 8345 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_LO_LBN 32 8346 8346 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_LO_WIDTH 32 8347 8347 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_HI_OFST 8 8348 8348 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_HI_LEN 4 8349 8349 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_HI_LBN 64 8350 8350 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_HI_WIDTH 32 8351 8351 + /* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */ 8352 8352 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_OFST 4 8353 8353 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_LEN 4 8354 8354 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FLAT_OFST 4 8355 8355 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FLAT_LEN 4 8356 8356 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_TYPE_OFST 7 8357 8357 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_TYPE_LEN 1 8358 8358 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 4 8359 8359 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3 8360 8360 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 32 8361 8361 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4 8362 8362 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 52 8363 8363 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4 8364 8364 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 48 8365 8365 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4 8366 8366 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 6 8367 8367 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1 8368 8368 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 4 8369 8369 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2 8370 8370 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_LINK_END_OFST 8 8371 8371 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_LINK_END_LEN 4 8372 8372 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_OFST 4 8373 8373 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_LEN 8 8374 8374 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_LO_OFST 4 8375 8375 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_LO_LEN 4 8376 8376 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_LO_LBN 32 8377 8377 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_LO_WIDTH 32 8378 8378 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_HI_OFST 8 8379 8379 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_HI_LEN 4 8380 8380 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_HI_LBN 64 8381 8381 + #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_HI_WIDTH 32 8382 8382 + 8805 8383 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 8806 8384 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 8807 8385 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 ··· 8882 8348 #define MC_CMD_NVRAM_TEST 0x4c 8883 8349 #undef MC_CMD_0x4c_PRIVILEGE_CTG 8884 8350 8885 8885 - #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8351 8351 + #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 8886 8352 8887 8353 /* MC_CMD_NVRAM_TEST_IN msgrequest */ 8888 8354 #define MC_CMD_NVRAM_TEST_IN_LEN 4 ··· 8901 8367 #define MC_CMD_NVRAM_TEST_FAIL 0x1 8902 8368 /* enum: Not supported. */ 8903 8369 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 8904 8904 - 8905 8905 - 8906 8906 - /***********************************/ 8907 8907 - /* MC_CMD_MRSFP_TWEAK 8908 8908 - * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. 8909 8909 - * I2C I/O expander bits are always read; if equaliser parameters are supplied, 8910 8910 - * they are configured first. Locks required: None. Return code: 0, EINVAL. 8911 8911 - */ 8912 8912 - #define MC_CMD_MRSFP_TWEAK 0x4d 8913 8913 - 8914 8914 - /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 8915 8915 - #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 8916 8916 - /* 0-6 low->high de-emph. */ 8917 8917 - #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 8918 8918 - #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 4 8919 8919 - /* 0-8 low->high ref.V */ 8920 8920 - #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 8921 8921 - #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 4 8922 8922 - /* 0-8 0-8 low->high boost */ 8923 8923 - #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 8924 8924 - #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 4 8925 8925 - /* 0-8 low->high ref.V */ 8926 8926 - #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 8927 8927 - #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 4 8928 8928 - 8929 8929 - /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 8930 8930 - #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 8931 8931 - 8932 8932 - /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 8933 8933 - #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 8934 8934 - /* input bits */ 8935 8935 - #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 8936 8936 - #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 4 8937 8937 - /* output bits */ 8938 8938 - #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 8939 8939 - #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 4 8940 8940 - /* direction */ 8941 8941 - #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 8942 8942 - #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 4 8943 8943 - /* enum: Out. */ 8944 8944 - #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 8945 8945 - /* enum: In. */ 8946 8946 - #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 8947 8947 - 8948 8948 - 8949 8949 - /***********************************/ 8950 8950 - /* MC_CMD_SENSOR_SET_LIMS 8951 8951 - * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: 8952 8952 - * ENOENT if the sensor specified does not exist, EINVAL if the limits are out 8953 8953 - * of range. 8954 8954 - */ 8955 8955 - #define MC_CMD_SENSOR_SET_LIMS 0x4e 8956 8956 - #undef MC_CMD_0x4e_PRIVILEGE_CTG 8957 8957 - 8958 8958 - #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE 8959 8959 - 8960 8960 - /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 8961 8961 - #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 8962 8962 - #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 8963 8963 - #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 4 8964 8964 - /* Enum values, see field(s): */ 8965 8965 - /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 8966 8966 - /* interpretation is is sensor-specific. */ 8967 8967 - #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 8968 8968 - #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 4 8969 8969 - /* interpretation is is sensor-specific. */ 8970 8970 - #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 8971 8971 - #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 4 8972 8972 - /* interpretation is is sensor-specific. */ 8973 8973 - #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 8974 8974 - #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 4 8975 8975 - /* interpretation is is sensor-specific. */ 8976 8976 - #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 8977 8977 - #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 4 8978 8978 - 8979 8979 - /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 8980 8980 - #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 8981 8981 - 8982 8982 - 8983 8983 - /***********************************/ 8984 8984 - /* MC_CMD_GET_RESOURCE_LIMITS 8985 8985 - */ 8986 8986 - #define MC_CMD_GET_RESOURCE_LIMITS 0x4f 8987 8987 - 8988 8988 - /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 8989 8989 - #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 8990 8990 - 8991 8991 - /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 8992 8992 - #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 8993 8993 - #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 8994 8994 - #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 4 8995 8995 - #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 8996 8996 - #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 4 8997 8997 - #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 8998 8998 - #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 4 8999 8999 - #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 9000 9000 - #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4 9001 8370 9002 8371 9003 8372 /***********************************/ ··· 9018 8581 /* Spacing of allocated MAC addresses */ 9019 8582 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 9020 8583 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4 9021 9021 - 9022 9022 - 9023 9023 - /***********************************/ 9024 9024 - /* MC_CMD_CLP 9025 9025 - * Perform a CLP related operation, see SF-110495-PS for details of CLP 9026 9026 - * processing. This command has been extended to accomodate the requirements of 9027 9027 - * different manufacturers which are to be found in SF-119187-TC, SF-119186-TC, 9028 9028 - * SF-120509-TC and SF-117282-PS. 9029 9029 - */ 9030 9030 - #define MC_CMD_CLP 0x56 9031 9031 - #undef MC_CMD_0x56_PRIVILEGE_CTG 9032 9032 - 9033 9033 - #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9034 9034 - 9035 9035 - /* MC_CMD_CLP_IN msgrequest */ 9036 9036 - #define MC_CMD_CLP_IN_LEN 4 9037 9037 - /* Sub operation */ 9038 9038 - #define MC_CMD_CLP_IN_OP_OFST 0 9039 9039 - #define MC_CMD_CLP_IN_OP_LEN 4 9040 9040 - /* enum: Return to factory default settings */ 9041 9041 - #define MC_CMD_CLP_OP_DEFAULT 0x1 9042 9042 - /* enum: Set MAC address */ 9043 9043 - #define MC_CMD_CLP_OP_SET_MAC 0x2 9044 9044 - /* enum: Get MAC address */ 9045 9045 - #define MC_CMD_CLP_OP_GET_MAC 0x3 9046 9046 - /* enum: Set UEFI/GPXE boot mode */ 9047 9047 - #define MC_CMD_CLP_OP_SET_BOOT 0x4 9048 9048 - /* enum: Get UEFI/GPXE boot mode */ 9049 9049 - #define MC_CMD_CLP_OP_GET_BOOT 0x5 9050 9050 - 9051 9051 - /* MC_CMD_CLP_OUT msgresponse */ 9052 9052 - #define MC_CMD_CLP_OUT_LEN 0 9053 9053 - 9054 9054 - /* MC_CMD_CLP_IN_DEFAULT msgrequest */ 9055 9055 - #define MC_CMD_CLP_IN_DEFAULT_LEN 4 9056 9056 - /* MC_CMD_CLP_IN_OP_OFST 0 */ 9057 9057 - /* MC_CMD_CLP_IN_OP_LEN 4 */ 9058 9058 - 9059 9059 - /* MC_CMD_CLP_OUT_DEFAULT msgresponse */ 9060 9060 - #define MC_CMD_CLP_OUT_DEFAULT_LEN 0 9061 9061 - 9062 9062 - /* MC_CMD_CLP_IN_SET_MAC msgrequest */ 9063 9063 - #define MC_CMD_CLP_IN_SET_MAC_LEN 12 9064 9064 - /* MC_CMD_CLP_IN_OP_OFST 0 */ 9065 9065 - /* MC_CMD_CLP_IN_OP_LEN 4 */ 9066 9066 - /* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:00 9067 9067 - * restores the permanent (factory-programmed) MAC address associated with the 9068 9068 - * port. A non-zero MAC address persists until a PCIe reset or a power cycle. 9069 9069 - */ 9070 9070 - #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 9071 9071 - #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 9072 9072 - /* Padding */ 9073 9073 - #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 9074 9074 - #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2 9075 9075 - 9076 9076 - /* MC_CMD_CLP_OUT_SET_MAC msgresponse */ 9077 9077 - #define MC_CMD_CLP_OUT_SET_MAC_LEN 0 9078 9078 - 9079 9079 - /* MC_CMD_CLP_IN_SET_MAC_V2 msgrequest */ 9080 9080 - #define MC_CMD_CLP_IN_SET_MAC_V2_LEN 16 9081 9081 - /* MC_CMD_CLP_IN_OP_OFST 0 */ 9082 9082 - /* MC_CMD_CLP_IN_OP_LEN 4 */ 9083 9083 - /* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:00 9084 9084 - * restores the permanent (factory-programmed) MAC address associated with the 9085 9085 - * port. A non-zero MAC address persists until a PCIe reset or a power cycle. 9086 9086 - */ 9087 9087 - #define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_OFST 4 9088 9088 - #define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_LEN 6 9089 9089 - /* Padding */ 9090 9090 - #define MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_OFST 10 9091 9091 - #define MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_LEN 2 9092 9092 - #define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_OFST 12 9093 9093 - #define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_LEN 4 9094 9094 - #define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_OFST 12 9095 9095 - #define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_LBN 0 9096 9096 - #define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_WIDTH 1 9097 9097 - 9098 9098 - /* MC_CMD_CLP_IN_GET_MAC msgrequest */ 9099 9099 - #define MC_CMD_CLP_IN_GET_MAC_LEN 4 9100 9100 - /* MC_CMD_CLP_IN_OP_OFST 0 */ 9101 9101 - /* MC_CMD_CLP_IN_OP_LEN 4 */ 9102 9102 - 9103 9103 - /* MC_CMD_CLP_IN_GET_MAC_V2 msgrequest */ 9104 9104 - #define MC_CMD_CLP_IN_GET_MAC_V2_LEN 8 9105 9105 - /* MC_CMD_CLP_IN_OP_OFST 0 */ 9106 9106 - /* MC_CMD_CLP_IN_OP_LEN 4 */ 9107 9107 - #define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_OFST 4 9108 9108 - #define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_LEN 4 9109 9109 - #define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_OFST 4 9110 9110 - #define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_LBN 0 9111 9111 - #define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_WIDTH 1 9112 9112 - 9113 9113 - /* MC_CMD_CLP_OUT_GET_MAC msgresponse */ 9114 9114 - #define MC_CMD_CLP_OUT_GET_MAC_LEN 8 9115 9115 - /* MAC address assigned to port */ 9116 9116 - #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0 9117 9117 - #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6 9118 9118 - /* Padding */ 9119 9119 - #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6 9120 9120 - #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2 9121 9121 - 9122 9122 - /* MC_CMD_CLP_IN_SET_BOOT msgrequest */ 9123 9123 - #define MC_CMD_CLP_IN_SET_BOOT_LEN 5 9124 9124 - /* MC_CMD_CLP_IN_OP_OFST 0 */ 9125 9125 - /* MC_CMD_CLP_IN_OP_LEN 4 */ 9126 9126 - /* Boot flag */ 9127 9127 - #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4 9128 9128 - #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1 9129 9129 - 9130 9130 - /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */ 9131 9131 - #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0 9132 9132 - 9133 9133 - /* MC_CMD_CLP_IN_GET_BOOT msgrequest */ 9134 9134 - #define MC_CMD_CLP_IN_GET_BOOT_LEN 4 9135 9135 - /* MC_CMD_CLP_IN_OP_OFST 0 */ 9136 9136 - /* MC_CMD_CLP_IN_OP_LEN 4 */ 9137 9137 - 9138 9138 - /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */ 9139 9139 - #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4 9140 9140 - /* Boot flag */ 9141 9141 - #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0 9142 9142 - #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1 9143 9143 - /* Padding */ 9144 9144 - #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 9145 9145 - #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 9146 9146 - 9147 9147 - 9148 9148 - /***********************************/ 9149 9149 - /* MC_CMD_MUM 9150 9150 - * Perform a MUM operation 9151 9151 - */ 9152 9152 - #define MC_CMD_MUM 0x57 9153 9153 - #undef MC_CMD_0x57_PRIVILEGE_CTG 9154 9154 - 9155 9155 - #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE 9156 9156 - 9157 9157 - /* MC_CMD_MUM_IN msgrequest */ 9158 9158 - #define MC_CMD_MUM_IN_LEN 4 9159 9159 - #define MC_CMD_MUM_IN_OP_HDR_OFST 0 9160 9160 - #define MC_CMD_MUM_IN_OP_HDR_LEN 4 9161 9161 - #define MC_CMD_MUM_IN_OP_OFST 0 9162 9162 - #define MC_CMD_MUM_IN_OP_LBN 0 9163 9163 - #define MC_CMD_MUM_IN_OP_WIDTH 8 9164 9164 - /* enum: NULL MCDI command to MUM */ 9165 9165 - #define MC_CMD_MUM_OP_NULL 0x1 9166 9166 - /* enum: Get MUM version */ 9167 9167 - #define MC_CMD_MUM_OP_GET_VERSION 0x2 9168 9168 - /* enum: Issue raw I2C command to MUM */ 9169 9169 - #define MC_CMD_MUM_OP_RAW_CMD 0x3 9170 9170 - /* enum: Read from registers on devices connected to MUM. */ 9171 9171 - #define MC_CMD_MUM_OP_READ 0x4 9172 9172 - /* enum: Write to registers on devices connected to MUM. */ 9173 9173 - #define MC_CMD_MUM_OP_WRITE 0x5 9174 9174 - /* enum: Control UART logging. */ 9175 9175 - #define MC_CMD_MUM_OP_LOG 0x6 9176 9176 - /* enum: Operations on MUM GPIO lines */ 9177 9177 - #define MC_CMD_MUM_OP_GPIO 0x7 9178 9178 - /* enum: Get sensor readings from MUM */ 9179 9179 - #define MC_CMD_MUM_OP_READ_SENSORS 0x8 9180 9180 - /* enum: Initiate clock programming on the MUM */ 9181 9181 - #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9 9182 9182 - /* enum: Initiate FPGA load from flash on the MUM */ 9183 9183 - #define MC_CMD_MUM_OP_FPGA_LOAD 0xa 9184 9184 - /* enum: Request sensor reading from MUM ADC resulting from earlier request via 9185 9185 - * MUM ATB 9186 9186 - */ 9187 9187 - #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb 9188 9188 - /* enum: Send commands relating to the QSFP ports via the MUM for PHY 9189 9189 - * operations 9190 9190 - */ 9191 9191 - #define MC_CMD_MUM_OP_QSFP 0xc 9192 9192 - /* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage 9193 9193 - * level) from MUM 9194 9194 - */ 9195 9195 - #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd 9196 9196 - 9197 9197 - /* MC_CMD_MUM_IN_NULL msgrequest */ 9198 9198 - #define MC_CMD_MUM_IN_NULL_LEN 4 9199 9199 - /* MUM cmd header */ 9200 9200 - #define MC_CMD_MUM_IN_CMD_OFST 0 9201 9201 - #define MC_CMD_MUM_IN_CMD_LEN 4 9202 9202 - 9203 9203 - /* MC_CMD_MUM_IN_GET_VERSION msgrequest */ 9204 9204 - #define MC_CMD_MUM_IN_GET_VERSION_LEN 4 9205 9205 - /* MUM cmd header */ 9206 9206 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9207 9207 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9208 9208 - 9209 9209 - /* MC_CMD_MUM_IN_READ msgrequest */ 9210 9210 - #define MC_CMD_MUM_IN_READ_LEN 16 9211 9211 - /* MUM cmd header */ 9212 9212 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9213 9213 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9214 9214 - /* ID of (device connected to MUM) to read from registers of */ 9215 9215 - #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4 9216 9216 - #define MC_CMD_MUM_IN_READ_DEVICE_LEN 4 9217 9217 - /* enum: Hittite HMC1035 clock generator on Sorrento board */ 9218 9218 - #define MC_CMD_MUM_DEV_HITTITE 0x1 9219 9219 - /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */ 9220 9220 - #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2 9221 9221 - /* 32-bit address to read from */ 9222 9222 - #define MC_CMD_MUM_IN_READ_ADDR_OFST 8 9223 9223 - #define MC_CMD_MUM_IN_READ_ADDR_LEN 4 9224 9224 - /* Number of words to read. */ 9225 9225 - #define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12 9226 9226 - #define MC_CMD_MUM_IN_READ_NUMWORDS_LEN 4 9227 9227 - 9228 9228 - /* MC_CMD_MUM_IN_WRITE msgrequest */ 9229 9229 - #define MC_CMD_MUM_IN_WRITE_LENMIN 16 9230 9230 - #define MC_CMD_MUM_IN_WRITE_LENMAX 252 9231 9231 - #define MC_CMD_MUM_IN_WRITE_LENMAX_MCDI2 1020 9232 9232 - #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num)) 9233 9233 - #define MC_CMD_MUM_IN_WRITE_BUFFER_NUM(len) (((len)-12)/4) 9234 9234 - /* MUM cmd header */ 9235 9235 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9236 9236 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9237 9237 - /* ID of (device connected to MUM) to write to registers of */ 9238 9238 - #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4 9239 9239 - #define MC_CMD_MUM_IN_WRITE_DEVICE_LEN 4 9240 9240 - /* enum: Hittite HMC1035 clock generator on Sorrento board */ 9241 9241 - /* MC_CMD_MUM_DEV_HITTITE 0x1 */ 9242 9242 - /* 32-bit address to write to */ 9243 9243 - #define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8 9244 9244 - #define MC_CMD_MUM_IN_WRITE_ADDR_LEN 4 9245 9245 - /* Words to write */ 9246 9246 - #define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12 9247 9247 - #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4 9248 9248 - #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1 9249 9249 - #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60 9250 9250 - #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM_MCDI2 252 9251 9251 - 9252 9252 - /* MC_CMD_MUM_IN_RAW_CMD msgrequest */ 9253 9253 - #define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17 9254 9254 - #define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252 9255 9255 - #define MC_CMD_MUM_IN_RAW_CMD_LENMAX_MCDI2 1020 9256 9256 - #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num)) 9257 9257 - #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_NUM(len) (((len)-16)/1) 9258 9258 - /* MUM cmd header */ 9259 9259 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9260 9260 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9261 9261 - /* MUM I2C cmd code */ 9262 9262 - #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4 9263 9263 - #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 4 9264 9264 - /* Number of bytes to write */ 9265 9265 - #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8 9266 9266 - #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 4 9267 9267 - /* Number of bytes to read */ 9268 9268 - #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12 9269 9269 - #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 4 9270 9270 - /* Bytes to write */ 9271 9271 - #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16 9272 9272 - #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1 9273 9273 - #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1 9274 9274 - #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236 9275 9275 - #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM_MCDI2 1004 9276 9276 - 9277 9277 - /* MC_CMD_MUM_IN_LOG msgrequest */ 9278 9278 - #define MC_CMD_MUM_IN_LOG_LEN 8 9279 9279 - /* MUM cmd header */ 9280 9280 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9281 9281 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9282 9282 - #define MC_CMD_MUM_IN_LOG_OP_OFST 4 9283 9283 - #define MC_CMD_MUM_IN_LOG_OP_LEN 4 9284 9284 - #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */ 9285 9285 - 9286 9286 - /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */ 9287 9287 - #define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12 9288 9288 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9289 9289 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9290 9290 - /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */ 9291 9291 - /* MC_CMD_MUM_IN_LOG_OP_LEN 4 */ 9292 9292 - /* Enable/disable debug output to UART */ 9293 9293 - #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8 9294 9294 - #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 4 9295 9295 - 9296 9296 - /* MC_CMD_MUM_IN_GPIO msgrequest */ 9297 9297 - #define MC_CMD_MUM_IN_GPIO_LEN 8 9298 9298 - /* MUM cmd header */ 9299 9299 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9300 9300 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9301 9301 - #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4 9302 9302 - #define MC_CMD_MUM_IN_GPIO_HDR_LEN 4 9303 9303 - #define MC_CMD_MUM_IN_GPIO_OPCODE_OFST 4 9304 9304 - #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0 9305 9305 - #define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8 9306 9306 - #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */ 9307 9307 - #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */ 9308 9308 - #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */ 9309 9309 - #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */ 9310 9310 - #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */ 9311 9311 - #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */ 9312 9312 - 9313 9313 - /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */ 9314 9314 - #define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8 9315 9315 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9316 9316 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9317 9317 - #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4 9318 9318 - #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 4 9319 9319 - 9320 9320 - /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */ 9321 9321 - #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16 9322 9322 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9323 9323 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9324 9324 - #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4 9325 9325 - #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4 9326 9326 - /* The first 32-bit word to be written to the GPIO OUT register. */ 9327 9327 - #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8 9328 9328 - #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4 9329 9329 - /* The second 32-bit word to be written to the GPIO OUT register. */ 9330 9330 - #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12 9331 9331 - #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4 9332 9332 - 9333 9333 - /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */ 9334 9334 - #define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8 9335 9335 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9336 9336 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9337 9337 - #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4 9338 9338 - #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 4 9339 9339 - 9340 9340 - /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */ 9341 9341 - #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16 9342 9342 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9343 9343 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9344 9344 - #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4 9345 9345 - #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4 9346 9346 - /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */ 9347 9347 - #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8 9348 9348 - #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4 9349 9349 - /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */ 9350 9350 - #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12 9351 9351 - #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4 9352 9352 - 9353 9353 - /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */ 9354 9354 - #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8 9355 9355 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9356 9356 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9357 9357 - #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4 9358 9358 - #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 4 9359 9359 - 9360 9360 - /* MC_CMD_MUM_IN_GPIO_OP msgrequest */ 9361 9361 - #define MC_CMD_MUM_IN_GPIO_OP_LEN 8 9362 9362 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9363 9363 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9364 9364 - #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4 9365 9365 - #define MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4 9366 9366 - #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_OFST 4 9367 9367 - #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8 9368 9368 - #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8 9369 9369 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */ 9370 9370 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */ 9371 9371 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */ 9372 9372 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */ 9373 9373 - #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_OFST 4 9374 9374 - #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16 9375 9375 - #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8 9376 9376 - 9377 9377 - /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */ 9378 9378 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8 9379 9379 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9380 9380 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9381 9381 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4 9382 9382 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 4 9383 9383 - 9384 9384 - /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */ 9385 9385 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8 9386 9386 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9387 9387 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9388 9388 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4 9389 9389 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4 9390 9390 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_OFST 4 9391 9391 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24 9392 9392 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8 9393 9393 - 9394 9394 - /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */ 9395 9395 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8 9396 9396 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9397 9397 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9398 9398 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4 9399 9399 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4 9400 9400 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_OFST 4 9401 9401 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24 9402 9402 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8 9403 9403 - 9404 9404 - /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */ 9405 9405 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8 9406 9406 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9407 9407 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9408 9408 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4 9409 9409 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4 9410 9410 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_OFST 4 9411 9411 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24 9412 9412 - #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8 9413 9413 - 9414 9414 - /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */ 9415 9415 - #define MC_CMD_MUM_IN_READ_SENSORS_LEN 8 9416 9416 - /* MUM cmd header */ 9417 9417 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9418 9418 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9419 9419 - #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4 9420 9420 - #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4 9421 9421 - #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_OFST 4 9422 9422 - #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0 9423 9423 - #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8 9424 9424 - #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_OFST 4 9425 9425 - #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8 9426 9426 - #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8 9427 9427 - 9428 9428 - /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */ 9429 9429 - #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12 9430 9430 - /* MUM cmd header */ 9431 9431 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9432 9432 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9433 9433 - /* Bit-mask of clocks to be programmed */ 9434 9434 - #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4 9435 9435 - #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 4 9436 9436 - #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */ 9437 9437 - #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */ 9438 9438 - #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */ 9439 9439 - /* Control flags for clock programming */ 9440 9440 - #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8 9441 9441 - #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4 9442 9442 - #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_OFST 8 9443 9443 - #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0 9444 9444 - #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1 9445 9445 - #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_OFST 8 9446 9446 - #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1 9447 9447 - #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1 9448 9448 - #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_OFST 8 9449 9449 - #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2 9450 9450 - #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1 9451 9451 - 9452 9452 - /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */ 9453 9453 - #define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8 9454 9454 - /* MUM cmd header */ 9455 9455 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9456 9456 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9457 9457 - /* Enable/Disable FPGA config from flash */ 9458 9458 - #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4 9459 9459 - #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 4 9460 9460 - 9461 9461 - /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */ 9462 9462 - #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4 9463 9463 - /* MUM cmd header */ 9464 9464 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9465 9465 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9466 9466 - 9467 9467 - /* MC_CMD_MUM_IN_QSFP msgrequest */ 9468 9468 - #define MC_CMD_MUM_IN_QSFP_LEN 12 9469 9469 - /* MUM cmd header */ 9470 9470 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9471 9471 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9472 9472 - #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4 9473 9473 - #define MC_CMD_MUM_IN_QSFP_HDR_LEN 4 9474 9474 - #define MC_CMD_MUM_IN_QSFP_OPCODE_OFST 4 9475 9475 - #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0 9476 9476 - #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4 9477 9477 - #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */ 9478 9478 - #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */ 9479 9479 - #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */ 9480 9480 - #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */ 9481 9481 - #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */ 9482 9482 - #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */ 9483 9483 - #define MC_CMD_MUM_IN_QSFP_IDX_OFST 8 9484 9484 - #define MC_CMD_MUM_IN_QSFP_IDX_LEN 4 9485 9485 - 9486 9486 - /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */ 9487 9487 - #define MC_CMD_MUM_IN_QSFP_INIT_LEN 16 9488 9488 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9489 9489 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9490 9490 - #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4 9491 9491 - #define MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 4 9492 9492 - #define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8 9493 9493 - #define MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 4 9494 9494 - #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12 9495 9495 - #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 4 9496 9496 - 9497 9497 - /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */ 9498 9498 - #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24 9499 9499 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9500 9500 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9501 9501 - #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4 9502 9502 - #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 4 9503 9503 - #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8 9504 9504 - #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 4 9505 9505 - #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12 9506 9506 - #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 4 9507 9507 - #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16 9508 9508 - #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 4 9509 9509 - #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20 9510 9510 - #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 4 9511 9511 - 9512 9512 - /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */ 9513 9513 - #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12 9514 9514 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9515 9515 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9516 9516 - #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4 9517 9517 - #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 4 9518 9518 - #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8 9519 9519 - #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 4 9520 9520 - 9521 9521 - /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */ 9522 9522 - #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16 9523 9523 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9524 9524 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9525 9525 - #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4 9526 9526 - #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 4 9527 9527 - #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8 9528 9528 - #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 4 9529 9529 - #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12 9530 9530 - #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 4 9531 9531 - 9532 9532 - /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */ 9533 9533 - #define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12 9534 9534 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9535 9535 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9536 9536 - #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4 9537 9537 - #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 4 9538 9538 - #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8 9539 9539 - #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 4 9540 9540 - 9541 9541 - /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */ 9542 9542 - #define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12 9543 9543 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9544 9544 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9545 9545 - #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4 9546 9546 - #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 4 9547 9547 - #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8 9548 9548 - #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 4 9549 9549 - 9550 9550 - /* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */ 9551 9551 - #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4 9552 9552 - /* MUM cmd header */ 9553 9553 - /* MC_CMD_MUM_IN_CMD_OFST 0 */ 9554 9554 - /* MC_CMD_MUM_IN_CMD_LEN 4 */ 9555 9555 - 9556 9556 - /* MC_CMD_MUM_OUT msgresponse */ 9557 9557 - #define MC_CMD_MUM_OUT_LEN 0 9558 9558 - 9559 9559 - /* MC_CMD_MUM_OUT_NULL msgresponse */ 9560 9560 - #define MC_CMD_MUM_OUT_NULL_LEN 0 9561 9561 - 9562 9562 - /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */ 9563 9563 - #define MC_CMD_MUM_OUT_GET_VERSION_LEN 12 9564 9564 - #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0 9565 9565 - #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 4 9566 9566 - #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4 9567 9567 - #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8 9568 9568 - #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4 9569 9569 - #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LEN 4 9570 9570 - #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LBN 32 9571 9571 - #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_WIDTH 32 9572 9572 - #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8 9573 9573 - #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LEN 4 9574 9574 - #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LBN 64 9575 9575 - #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_WIDTH 32 9576 9576 - 9577 9577 - /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */ 9578 9578 - #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1 9579 9579 - #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252 9580 9580 - #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX_MCDI2 1020 9581 9581 - #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num)) 9582 9582 - #define MC_CMD_MUM_OUT_RAW_CMD_DATA_NUM(len) (((len)-0)/1) 9583 9583 - /* returned data */ 9584 9584 - #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0 9585 9585 - #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1 9586 9586 - #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1 9587 9587 - #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252 9588 9588 - #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM_MCDI2 1020 9589 9589 - 9590 9590 - /* MC_CMD_MUM_OUT_READ msgresponse */ 9591 9591 - #define MC_CMD_MUM_OUT_READ_LENMIN 4 9592 9592 - #define MC_CMD_MUM_OUT_READ_LENMAX 252 9593 9593 - #define MC_CMD_MUM_OUT_READ_LENMAX_MCDI2 1020 9594 9594 - #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num)) 9595 9595 - #define MC_CMD_MUM_OUT_READ_BUFFER_NUM(len) (((len)-0)/4) 9596 9596 - #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0 9597 9597 - #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4 9598 9598 - #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1 9599 9599 - #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63 9600 9600 - #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM_MCDI2 255 9601 9601 - 9602 9602 - /* MC_CMD_MUM_OUT_WRITE msgresponse */ 9603 9603 - #define MC_CMD_MUM_OUT_WRITE_LEN 0 9604 9604 - 9605 9605 - /* MC_CMD_MUM_OUT_LOG msgresponse */ 9606 9606 - #define MC_CMD_MUM_OUT_LOG_LEN 0 9607 9607 - 9608 9608 - /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */ 9609 9609 - #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0 9610 9610 - 9611 9611 - /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */ 9612 9612 - #define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8 9613 9613 - /* The first 32-bit word read from the GPIO IN register. */ 9614 9614 - #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0 9615 9615 - #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4 9616 9616 - /* The second 32-bit word read from the GPIO IN register. */ 9617 9617 - #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4 9618 9618 - #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4 9619 9619 - 9620 9620 - /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */ 9621 9621 - #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0 9622 9622 - 9623 9623 - /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */ 9624 9624 - #define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8 9625 9625 - /* The first 32-bit word read from the GPIO OUT register. */ 9626 9626 - #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0 9627 9627 - #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4 9628 9628 - /* The second 32-bit word read from the GPIO OUT register. */ 9629 9629 - #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4 9630 9630 - #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4 9631 9631 - 9632 9632 - /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */ 9633 9633 - #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0 9634 9634 - 9635 9635 - /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */ 9636 9636 - #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8 9637 9637 - #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0 9638 9638 - #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 4 9639 9639 - #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4 9640 9640 - #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 4 9641 9641 - 9642 9642 - /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */ 9643 9643 - #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4 9644 9644 - #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0 9645 9645 - #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 4 9646 9646 - 9647 9647 - /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */ 9648 9648 - #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0 9649 9649 - 9650 9650 - /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */ 9651 9651 - #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0 9652 9652 - 9653 9653 - /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */ 9654 9654 - #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0 9655 9655 - 9656 9656 - /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */ 9657 9657 - #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4 9658 9658 - #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252 9659 9659 - #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX_MCDI2 1020 9660 9660 - #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num)) 9661 9661 - #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_NUM(len) (((len)-0)/4) 9662 9662 - #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0 9663 9663 - #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4 9664 9664 - #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1 9665 9665 - #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63 9666 9666 - #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM_MCDI2 255 9667 9667 - #define MC_CMD_MUM_OUT_READ_SENSORS_READING_OFST 0 9668 9668 - #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0 9669 9669 - #define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16 9670 9670 - #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_OFST 0 9671 9671 - #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16 9672 9672 - #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8 9673 9673 - #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_OFST 0 9674 9674 - #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24 9675 9675 - #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8 9676 9676 - 9677 9677 - /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */ 9678 9678 - #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4 9679 9679 - #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0 9680 9680 - #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 4 9681 9681 - 9682 9682 - /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */ 9683 9683 - #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0 9684 9684 - 9685 9685 - /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */ 9686 9686 - #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4 9687 9687 - #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0 9688 9688 - #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 4 9689 9689 - 9690 9690 - /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */ 9691 9691 - #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0 9692 9692 - 9693 9693 - /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */ 9694 9694 - #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8 9695 9695 - #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0 9696 9696 - #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4 9697 9697 - #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4 9698 9698 - #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4 9699 9699 - #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_OFST 4 9700 9700 - #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0 9701 9701 - #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1 9702 9702 - #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_OFST 4 9703 9703 - #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1 9704 9704 - #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1 9705 9705 - 9706 9706 - /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */ 9707 9707 - #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4 9708 9708 - #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0 9709 9709 - #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 4 9710 9710 - 9711 9711 - /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */ 9712 9712 - #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5 9713 9713 - #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252 9714 9714 - #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX_MCDI2 1020 9715 9715 - #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num)) 9716 9716 - #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1) 9717 9717 - /* in bytes */ 9718 9718 - #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0 9719 9719 - #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4 9720 9720 - #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4 9721 9721 - #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1 9722 9722 - #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1 9723 9723 - #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248 9724 9724 - #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM_MCDI2 1016 9725 9725 - 9726 9726 - /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */ 9727 9727 - #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8 9728 9728 - #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0 9729 9729 - #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 4 9730 9730 - #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4 9731 9731 - #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 4 9732 9732 - 9733 9733 - /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */ 9734 9734 - #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4 9735 9735 - #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0 9736 9736 - #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 4 9737 9737 - 9738 9738 - /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */ 9739 9739 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24 9740 9740 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248 9741 9741 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX_MCDI2 1016 9742 9742 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num)) 9743 9743 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_NUM(len) (((len)-8)/8) 9744 9744 - /* Discrete (soldered) DDR resistor strap info */ 9745 9745 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0 9746 9746 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4 9747 9747 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_OFST 0 9748 9748 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0 9749 9749 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16 9750 9750 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_OFST 0 9751 9751 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16 9752 9752 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16 9753 9753 - /* Number of SODIMM info records */ 9754 9754 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4 9755 9755 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4 9756 9756 - /* Array of SODIMM info records */ 9757 9757 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8 9758 9758 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8 9759 9759 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8 9760 9760 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LEN 4 9761 9761 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LBN 64 9762 9762 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_WIDTH 32 9763 9763 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12 9764 9764 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LEN 4 9765 9765 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LBN 96 9766 9766 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_WIDTH 32 9767 9767 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2 9768 9768 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30 9769 9769 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM_MCDI2 126 9770 9770 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_OFST 8 9771 9771 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0 9772 9772 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8 9773 9773 - /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */ 9774 9774 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0 9775 9775 - /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */ 9776 9776 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1 9777 9777 - /* enum: Total number of SODIMM banks */ 9778 9778 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2 9779 9779 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_OFST 8 9780 9780 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8 9781 9781 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8 9782 9782 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_OFST 8 9783 9783 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16 9784 9784 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4 9785 9785 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_OFST 8 9786 9786 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20 9787 9787 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4 9788 9788 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */ 9789 9789 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */ 9790 9790 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */ 9791 9791 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */ 9792 9792 - /* enum: Values 5-15 are reserved for future usage */ 9793 9793 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4 9794 9794 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_OFST 8 9795 9795 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24 9796 9796 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8 9797 9797 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_OFST 8 9798 9798 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32 9799 9799 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16 9800 9800 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_OFST 8 9801 9801 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48 9802 9802 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4 9803 9803 - /* enum: No module present */ 9804 9804 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0 9805 9805 - /* enum: Module present supported and powered on */ 9806 9806 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1 9807 9807 - /* enum: Module present but bad type */ 9808 9808 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2 9809 9809 - /* enum: Module present but incompatible voltage */ 9810 9810 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3 9811 9811 - /* enum: Module present but unknown SPD */ 9812 9812 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4 9813 9813 - /* enum: Module present but slot cannot support it */ 9814 9814 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5 9815 9815 - /* enum: Modules may or may not be present, but cannot establish contact by I2C 9816 9816 - */ 9817 9817 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6 9818 9818 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_OFST 8 9819 9819 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52 9820 9820 - #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12 9821 8584 9822 8585 /* MC_CMD_DYNAMIC_SENSORS_LIMITS structuredef: Set of sensor limits. This 9823 8586 * should match the equivalent structure in the sensor_query SPHINX service. ··· 9137 9500 * and a generation count for this version of the sensor table. On systems 9138 9501 * advertising the DYNAMIC_SENSORS capability bit, this replaces the 9139 9502 * MC_CMD_READ_SENSORS command. On multi-MC systems this may include sensors 9140 9140 - * added by the NMC. 9141 9141 - * 9142 9142 - * Sensor handles are persistent for the lifetime of the sensor and are used to 9143 9143 - * identify sensors in MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS and 9144 9144 - * MC_CMD_DYNAMIC_SENSORS_GET_VALUES. 9145 9145 - * 9146 9146 - * The generation count is maintained by the MC, is persistent across reboots 9147 9147 - * and will be incremented each time the sensor table is modified. When the 9148 9148 - * table is modified, a CODE_DYNAMIC_SENSORS_CHANGE event will be generated 9149 9149 - * containing the new generation count. The driver should compare this against 9150 9150 - * the current generation count, and if it is different, call 9151 9151 - * MC_CMD_DYNAMIC_SENSORS_LIST again to update it's copy of the sensor table. 9152 9152 - * 9153 9153 - * The sensor count is provided to allow a future path to supporting more than 9503 9503 + * added by the NMC. Sensor handles are persistent for the lifetime of the 9504 9504 + * sensor and are used to identify sensors in 9505 9505 + * MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS and 9506 9506 + * MC_CMD_DYNAMIC_SENSORS_GET_VALUES. The generation count is maintained by the 9507 9507 + * MC, is persistent across reboots and will be incremented each time the 9508 9508 + * sensor table is modified. When the table is modified, a 9509 9509 + * CODE_DYNAMIC_SENSORS_CHANGE event will be generated containing the new 9510 9510 + * generation count. The driver should compare this against the current 9511 9511 + * generation count, and if it is different, call MC_CMD_DYNAMIC_SENSORS_LIST 9512 9512 + * again to update it's copy of the sensor table. The sensor count is provided 9513 9513 + * to allow a future path to supporting more than 9154 9514 * MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 sensors, i.e. 9155 9515 * the maximum number that will fit in a single response. As this is a fairly 9156 9516 * large number (253) it is not anticipated that this will be needed in the 9157 9157 - * near future, so can currently be ignored. 9158 9158 - * 9159 9159 - * On Riverhead this command is implemented as a wrapper for `list` in the 9160 9160 - * sensor_query SPHINX service. 9517 9517 + * near future, so can currently be ignored. On Riverhead this command is 9518 9518 + * implemented as a wrapper for `list` in the sensor_query SPHINX service. 9161 9519 */ 9162 9520 #define MC_CMD_DYNAMIC_SENSORS_LIST 0x66 9163 9521 #undef MC_CMD_0x66_PRIVILEGE_CTG ··· 9189 9557 /***********************************/ 9190 9558 /* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 9191 9559 * Get descriptions for a set of sensors, specified as an array of sensor 9192 9192 - * handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST 9193 9193 - * 9194 9194 - * Any handles which do not correspond to a sensor currently managed by the MC 9195 9195 - * will be dropped from from the response. This may happen when a sensor table 9196 9196 - * update is in progress, and effectively means the set of usable sensors is 9197 9197 - * the intersection between the sets of sensors known to the driver and the MC. 9198 9198 - * 9199 9199 - * On Riverhead this command is implemented as a wrapper for 9200 9200 - * `get_descriptions` in the sensor_query SPHINX service. 9560 9560 + * handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST. Any handles which do not 9561 9561 + * correspond to a sensor currently managed by the MC will be dropped from from 9562 9562 + * the response. This may happen when a sensor table update is in progress, and 9563 9563 + * effectively means the set of usable sensors is the intersection between the 9564 9564 + * sets of sensors known to the driver and the MC. On Riverhead this command is 9565 9565 + * implemented as a wrapper for `get_descriptions` in the sensor_query SPHINX 9566 9566 + * service. 9201 9567 */ 9202 9568 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x67 9203 9569 #undef MC_CMD_0x67_PRIVILEGE_CTG ··· 9232 9602 /***********************************/ 9233 9603 /* MC_CMD_DYNAMIC_SENSORS_GET_READINGS 9234 9604 * Read the state and value for a set of sensors, specified as an array of 9235 9235 - * sensor handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST. 9236 9236 - * 9237 9237 - * In the case of a broken sensor, then the state of the response's 9238 9238 - * MC_CMD_DYNAMIC_SENSORS_VALUE entry will be set to BROKEN, and any value 9239 9239 - * provided should be treated as erroneous. 9240 9240 - * 9241 9241 - * Any handles which do not correspond to a sensor currently managed by the MC 9242 9242 - * will be dropped from from the response. This may happen when a sensor table 9243 9243 - * update is in progress, and effectively means the set of usable sensors is 9244 9244 - * the intersection between the sets of sensors known to the driver and the MC. 9245 9245 - * 9246 9246 - * On Riverhead this command is implemented as a wrapper for `get_readings` 9247 9247 - * in the sensor_query SPHINX service. 9605 9605 + * sensor handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST. In the case of a 9606 9606 + * broken sensor, then the state of the response's MC_CMD_DYNAMIC_SENSORS_VALUE 9607 9607 + * entry will be set to BROKEN, and any value provided should be treated as 9608 9608 + * erroneous. Any handles which do not correspond to a sensor currently managed 9609 9609 + * by the MC will be dropped from from the response. This may happen when a 9610 9610 + * sensor table update is in progress, and effectively means the set of usable 9611 9611 + * sensors is the intersection between the sets of sensors known to the driver 9612 9612 + * and the MC. On Riverhead this command is implemented as a wrapper for 9613 9613 + * `get_readings` in the sensor_query SPHINX service. 9248 9614 */ 9249 9615 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x68 9250 9616 #undef MC_CMD_0x68_PRIVILEGE_CTG ··· 9273 9647 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM 21 9274 9648 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM_MCDI2 85 9275 9649 9650 9650 + /* MC_CMD_MAC_FLAGS structuredef */ 9651 9651 + #define MC_CMD_MAC_FLAGS_LEN 4 9652 9652 + /* The enums defined in this field are used as indices into the 9653 9653 + * MC_CMD_MAC_FLAGS bitmask. 9654 9654 + */ 9655 9655 + #define MC_CMD_MAC_FLAGS_MASK_OFST 0 9656 9656 + #define MC_CMD_MAC_FLAGS_MASK_LEN 4 9657 9657 + /* enum property: bitshift */ 9658 9658 + /* enum: Include the FCS in the packet data delivered to the host. Ignored if 9659 9659 + * RX_INCLUDE_FCS not set in capabilities. 9660 9660 + */ 9661 9661 + #define MC_CMD_MAC_FLAGS_FLAG_INCLUDE_FCS 0x0 9662 9662 + #define MC_CMD_MAC_FLAGS_MASK_LBN 0 9663 9663 + #define MC_CMD_MAC_FLAGS_MASK_WIDTH 32 9664 9664 + 9665 9665 + /* MC_CMD_TRANSMISSION_MODE structuredef */ 9666 9666 + #define MC_CMD_TRANSMISSION_MODE_LEN 4 9667 9667 + #define MC_CMD_TRANSMISSION_MODE_MASK_OFST 0 9668 9668 + #define MC_CMD_TRANSMISSION_MODE_MASK_LEN 4 9669 9669 + /* enum property: value */ 9670 9670 + #define MC_CMD_TRANSMISSION_MODE_PROMSC_MODE 0x0 /* enum */ 9671 9671 + #define MC_CMD_TRANSMISSION_MODE_UNCST_MODE 0x1 /* enum */ 9672 9672 + #define MC_CMD_TRANSMISSION_MODE_BRDCST_MODE 0x2 /* enum */ 9673 9673 + #define MC_CMD_TRANSMISSION_MODE_MASK_LBN 0 9674 9674 + #define MC_CMD_TRANSMISSION_MODE_MASK_WIDTH 32 9675 9675 + 9676 9676 + /* MC_CMD_MAC_CONFIG_OPTIONS structuredef */ 9677 9677 + #define MC_CMD_MAC_CONFIG_OPTIONS_LEN 4 9678 9678 + #define MC_CMD_MAC_CONFIG_OPTIONS_MASK_OFST 0 9679 9679 + #define MC_CMD_MAC_CONFIG_OPTIONS_MASK_LEN 4 9680 9680 + /* enum property: bitmask */ 9681 9681 + /* enum: Configure the MAC address. */ 9682 9682 + #define MC_CMD_MAC_CONFIG_OPTIONS_CFG_ADDR 0x0 9683 9683 + /* enum: Configure the maximum frame length. */ 9684 9684 + #define MC_CMD_MAC_CONFIG_OPTIONS_CFG_MAX_FRAME_LEN 0x1 9685 9685 + /* enum: Configure flow control. */ 9686 9686 + #define MC_CMD_MAC_CONFIG_OPTIONS_CFG_FCNTL 0x2 9687 9687 + /* enum: Configure the transmission mode. */ 9688 9688 + #define MC_CMD_MAC_CONFIG_OPTIONS_CFG_TRANSMISSION_MODE 0x3 9689 9689 + /* enum: Configure FCS. */ 9690 9690 + #define MC_CMD_MAC_CONFIG_OPTIONS_CFG_INCLUDE_FCS 0x4 9691 9691 + #define MC_CMD_MAC_CONFIG_OPTIONS_MASK_LBN 0 9692 9692 + #define MC_CMD_MAC_CONFIG_OPTIONS_MASK_WIDTH 32 9693 9693 + 9276 9694 9277 9695 /***********************************/ 9278 9278 - /* MC_CMD_EVENT_CTRL 9279 9279 - * Configure which categories of unsolicited events the driver expects to 9280 9280 - * receive (Riverhead). 9696 9696 + /* MC_CMD_MAC_CTRL 9697 9697 + * Set MAC configuration. Return code: 0, EINVAL, ENOTSUP 9281 9698 */ 9282 9282 - #define MC_CMD_EVENT_CTRL 0x69 9283 9283 - #undef MC_CMD_0x69_PRIVILEGE_CTG 9699 9699 + #define MC_CMD_MAC_CTRL 0x1df 9700 9700 + #undef MC_CMD_0x1df_PRIVILEGE_CTG 9284 9701 9285 9285 - #define MC_CMD_0x69_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9702 9702 + #define MC_CMD_0x1df_PRIVILEGE_CTG SRIOV_CTG_LINK 9286 9703 9287 9287 - /* MC_CMD_EVENT_CTRL_IN msgrequest */ 9288 9288 - #define MC_CMD_EVENT_CTRL_IN_LENMIN 0 9289 9289 - #define MC_CMD_EVENT_CTRL_IN_LENMAX 252 9290 9290 - #define MC_CMD_EVENT_CTRL_IN_LENMAX_MCDI2 1020 9291 9291 - #define MC_CMD_EVENT_CTRL_IN_LEN(num) (0+4*(num)) 9292 9292 - #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_NUM(len) (((len)-0)/4) 9293 9293 - /* Array of event categories for which the driver wishes to receive events. */ 9294 9294 - #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_OFST 0 9295 9295 - #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_LEN 4 9296 9296 - #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MINNUM 0 9297 9297 - #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM 63 9298 9298 - #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM_MCDI2 255 9299 9299 - /* enum: Driver wishes to receive LINKCHANGE events. */ 9300 9300 - #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_LINKCHANGE 0x0 9301 9301 - /* enum: Driver wishes to receive SENSOR_CHANGE and SENSOR_STATE_CHANGE events. 9704 9704 + /* MC_CMD_MAC_CTRL_IN msgrequest */ 9705 9705 + #define MC_CMD_MAC_CTRL_IN_LEN 32 9706 9706 + /* Handle for selected network port. */ 9707 9707 + #define MC_CMD_MAC_CTRL_IN_PORT_HANDLE_OFST 0 9708 9708 + #define MC_CMD_MAC_CTRL_IN_PORT_HANDLE_LEN 4 9709 9709 + /* Select which parameters to configure. A parameter will only be modified if 9710 9710 + * the corresponding control flag is set. 9302 9711 */ 9303 9303 - #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_SENSOREVT 0x1 9304 9304 - /* enum: Driver wishes to receive receive errors. */ 9305 9305 - #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_RX_ERR 0x2 9306 9306 - /* enum: Driver wishes to receive transmit errors. */ 9307 9307 - #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_TX_ERR 0x3 9308 9308 - /* enum: Driver wishes to receive firmware alerts. */ 9309 9309 - #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_FWALERT 0x4 9310 9310 - /* enum: Driver wishes to receive reboot events. */ 9311 9311 - #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_MC_REBOOT 0x5 9712 9712 + #define MC_CMD_MAC_CTRL_IN_CONTROL_FLAGS_OFST 4 9713 9713 + #define MC_CMD_MAC_CTRL_IN_CONTROL_FLAGS_LEN 4 9714 9714 + /* enum property: bitshift */ 9715 9715 + /* Enum values, see field(s): */ 9716 9716 + /* MC_CMD_MAC_CONFIG_OPTIONS/MASK */ 9717 9717 + /* MAC address of the device. */ 9718 9718 + #define MC_CMD_MAC_CTRL_IN_ADDR_OFST 8 9719 9719 + #define MC_CMD_MAC_CTRL_IN_ADDR_LEN 8 9720 9720 + #define MC_CMD_MAC_CTRL_IN_ADDR_LO_OFST 8 9721 9721 + #define MC_CMD_MAC_CTRL_IN_ADDR_LO_LEN 4 9722 9722 + #define MC_CMD_MAC_CTRL_IN_ADDR_LO_LBN 64 9723 9723 + #define MC_CMD_MAC_CTRL_IN_ADDR_LO_WIDTH 32 9724 9724 + #define MC_CMD_MAC_CTRL_IN_ADDR_HI_OFST 12 9725 9725 + #define MC_CMD_MAC_CTRL_IN_ADDR_HI_LEN 4 9726 9726 + #define MC_CMD_MAC_CTRL_IN_ADDR_HI_LBN 96 9727 9727 + #define MC_CMD_MAC_CTRL_IN_ADDR_HI_WIDTH 32 9728 9728 + /* Includes the ethernet header, optional VLAN tags, payload and FCS. */ 9729 9729 + #define MC_CMD_MAC_CTRL_IN_MAX_FRAME_LEN_OFST 16 9730 9730 + #define MC_CMD_MAC_CTRL_IN_MAX_FRAME_LEN_LEN 4 9731 9731 + /* Settings for flow control. */ 9732 9732 + #define MC_CMD_MAC_CTRL_IN_FCNTL_OFST 20 9733 9733 + #define MC_CMD_MAC_CTRL_IN_FCNTL_LEN 4 9734 9734 + /* enum property: value */ 9735 9735 + /* Enum values, see field(s): */ 9736 9736 + /* MC_CMD_FCNTL/MASK */ 9737 9737 + /* Configure the MAC to transmit in one of promiscuous, unicast or broadcast 9738 9738 + * mode. 9739 9739 + */ 9740 9740 + #define MC_CMD_MAC_CTRL_IN_TRANSMISSION_MODE_OFST 24 9741 9741 + #define MC_CMD_MAC_CTRL_IN_TRANSMISSION_MODE_LEN 4 9742 9742 + /* enum property: value */ 9743 9743 + /* Enum values, see field(s): */ 9744 9744 + /* MC_CMD_TRANSMISSION_MODE/MASK */ 9745 9745 + /* Flags to control and expand the configuration of the MAC. */ 9746 9746 + #define MC_CMD_MAC_CTRL_IN_FLAGS_OFST 28 9747 9747 + #define MC_CMD_MAC_CTRL_IN_FLAGS_LEN 4 9748 9748 + /* enum property: bitshift */ 9749 9749 + /* Enum values, see field(s): */ 9750 9750 + /* MC_CMD_MAC_FLAGS/MASK */ 9312 9751 9313 9313 - /* MC_CMD_EVENT_CTRL_OUT msgrequest */ 9314 9314 - #define MC_CMD_EVENT_CTRL_OUT_LEN 0 9752 9752 + /* MC_CMD_MAC_CTRL_IN_V2 msgrequest: Updated MAC_CTRL with QBB mask */ 9753 9753 + #define MC_CMD_MAC_CTRL_IN_V2_LEN 33 9754 9754 + /* Handle for selected network port. */ 9755 9755 + #define MC_CMD_MAC_CTRL_IN_V2_PORT_HANDLE_OFST 0 9756 9756 + #define MC_CMD_MAC_CTRL_IN_V2_PORT_HANDLE_LEN 4 9757 9757 + /* Select which parameters to configure. A parameter will only be modified if 9758 9758 + * the corresponding control flag is set. 9759 9759 + */ 9760 9760 + #define MC_CMD_MAC_CTRL_IN_V2_CONTROL_FLAGS_OFST 4 9761 9761 + #define MC_CMD_MAC_CTRL_IN_V2_CONTROL_FLAGS_LEN 4 9762 9762 + /* enum property: bitshift */ 9763 9763 + /* Enum values, see field(s): */ 9764 9764 + /* MC_CMD_MAC_CONFIG_OPTIONS/MASK */ 9765 9765 + /* MAC address of the device. */ 9766 9766 + #define MC_CMD_MAC_CTRL_IN_V2_ADDR_OFST 8 9767 9767 + #define MC_CMD_MAC_CTRL_IN_V2_ADDR_LEN 8 9768 9768 + #define MC_CMD_MAC_CTRL_IN_V2_ADDR_LO_OFST 8 9769 9769 + #define MC_CMD_MAC_CTRL_IN_V2_ADDR_LO_LEN 4 9770 9770 + #define MC_CMD_MAC_CTRL_IN_V2_ADDR_LO_LBN 64 9771 9771 + #define MC_CMD_MAC_CTRL_IN_V2_ADDR_LO_WIDTH 32 9772 9772 + #define MC_CMD_MAC_CTRL_IN_V2_ADDR_HI_OFST 12 9773 9773 + #define MC_CMD_MAC_CTRL_IN_V2_ADDR_HI_LEN 4 9774 9774 + #define MC_CMD_MAC_CTRL_IN_V2_ADDR_HI_LBN 96 9775 9775 + #define MC_CMD_MAC_CTRL_IN_V2_ADDR_HI_WIDTH 32 9776 9776 + /* Includes the ethernet header, optional VLAN tags, payload and FCS. */ 9777 9777 + #define MC_CMD_MAC_CTRL_IN_V2_MAX_FRAME_LEN_OFST 16 9778 9778 + #define MC_CMD_MAC_CTRL_IN_V2_MAX_FRAME_LEN_LEN 4 9779 9779 + /* Settings for flow control. */ 9780 9780 + #define MC_CMD_MAC_CTRL_IN_V2_FCNTL_OFST 20 9781 9781 + #define MC_CMD_MAC_CTRL_IN_V2_FCNTL_LEN 4 9782 9782 + /* enum property: value */ 9783 9783 + /* Enum values, see field(s): */ 9784 9784 + /* MC_CMD_FCNTL/MASK */ 9785 9785 + /* Configure the MAC to transmit in one of promiscuous, unicast or broadcast 9786 9786 + * mode. 9787 9787 + */ 9788 9788 + #define MC_CMD_MAC_CTRL_IN_V2_TRANSMISSION_MODE_OFST 24 9789 9789 + #define MC_CMD_MAC_CTRL_IN_V2_TRANSMISSION_MODE_LEN 4 9790 9790 + /* enum property: value */ 9791 9791 + /* Enum values, see field(s): */ 9792 9792 + /* MC_CMD_TRANSMISSION_MODE/MASK */ 9793 9793 + /* Flags to control and expand the configuration of the MAC. */ 9794 9794 + #define MC_CMD_MAC_CTRL_IN_V2_FLAGS_OFST 28 9795 9795 + #define MC_CMD_MAC_CTRL_IN_V2_FLAGS_LEN 4 9796 9796 + /* enum property: bitshift */ 9797 9797 + /* Enum values, see field(s): */ 9798 9798 + /* MC_CMD_MAC_FLAGS/MASK */ 9799 9799 + /* Priority-based flow control mask (QBB). PRIO7 corresponds to the highest 9800 9800 + * priority, and PRIO0 to the lowest. This field is only used when CFG_FCNTL is 9801 9801 + * set and FCNTL is QBB 9802 9802 + */ 9803 9803 + #define MC_CMD_MAC_CTRL_IN_V2_PRIO_FCNTL_MASK_OFST 32 9804 9804 + #define MC_CMD_MAC_CTRL_IN_V2_PRIO_FCNTL_MASK_LEN 1 9805 9805 + /* enum property: bitmask */ 9806 9806 + #define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO0 0x0 /* enum */ 9807 9807 + #define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO1 0x1 /* enum */ 9808 9808 + #define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO2 0x2 /* enum */ 9809 9809 + #define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO3 0x3 /* enum */ 9810 9810 + #define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO4 0x4 /* enum */ 9811 9811 + #define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO5 0x5 /* enum */ 9812 9812 + #define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO6 0x6 /* enum */ 9813 9813 + #define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO7 0x7 /* enum */ 9814 9814 + 9815 9815 + /* MC_CMD_MAC_CTRL_OUT msgresponse */ 9816 9816 + #define MC_CMD_MAC_CTRL_OUT_LEN 0 9817 9817 + 9818 9818 + 9819 9819 + /***********************************/ 9820 9820 + /* MC_CMD_MAC_STATE 9821 9821 + * Read the MAC state. Return code: 0, ETIME. 9822 9822 + */ 9823 9823 + #define MC_CMD_MAC_STATE 0x1e0 9824 9824 + #undef MC_CMD_0x1e0_PRIVILEGE_CTG 9825 9825 + 9826 9826 + #define MC_CMD_0x1e0_PRIVILEGE_CTG SRIOV_CTG_LINK 9827 9827 + 9828 9828 + /* MC_CMD_MAC_STATE_IN msgrequest */ 9829 9829 + #define MC_CMD_MAC_STATE_IN_LEN 4 9830 9830 + /* Handle for selected network port. */ 9831 9831 + #define MC_CMD_MAC_STATE_IN_PORT_HANDLE_OFST 0 9832 9832 + #define MC_CMD_MAC_STATE_IN_PORT_HANDLE_LEN 4 9833 9833 + 9834 9834 + /* MC_CMD_MAC_STATE_OUT msgresponse */ 9835 9835 + #define MC_CMD_MAC_STATE_OUT_LEN 32 9836 9836 + /* The configured maximum frame length of the MAC. */ 9837 9837 + #define MC_CMD_MAC_STATE_OUT_MAX_FRAME_LEN_OFST 0 9838 9838 + #define MC_CMD_MAC_STATE_OUT_MAX_FRAME_LEN_LEN 4 9839 9839 + /* This returns the negotiated flow control value. */ 9840 9840 + #define MC_CMD_MAC_STATE_OUT_FCNTL_OFST 4 9841 9841 + #define MC_CMD_MAC_STATE_OUT_FCNTL_LEN 4 9842 9842 + /* enum property: value */ 9843 9843 + /* Enum values, see field(s): */ 9844 9844 + /* MC_CMD_FCNTL/MASK */ 9845 9845 + /* MAC address of the device. */ 9846 9846 + #define MC_CMD_MAC_STATE_OUT_ADDR_OFST 8 9847 9847 + #define MC_CMD_MAC_STATE_OUT_ADDR_LEN 8 9848 9848 + #define MC_CMD_MAC_STATE_OUT_ADDR_LO_OFST 8 9849 9849 + #define MC_CMD_MAC_STATE_OUT_ADDR_LO_LEN 4 9850 9850 + #define MC_CMD_MAC_STATE_OUT_ADDR_LO_LBN 64 9851 9851 + #define MC_CMD_MAC_STATE_OUT_ADDR_LO_WIDTH 32 9852 9852 + #define MC_CMD_MAC_STATE_OUT_ADDR_HI_OFST 12 9853 9853 + #define MC_CMD_MAC_STATE_OUT_ADDR_HI_LEN 4 9854 9854 + #define MC_CMD_MAC_STATE_OUT_ADDR_HI_LBN 96 9855 9855 + #define MC_CMD_MAC_STATE_OUT_ADDR_HI_WIDTH 32 9856 9856 + /* Flags indicating MAC faults. */ 9857 9857 + #define MC_CMD_MAC_STATE_OUT_MAC_FAULT_FLAGS_OFST 16 9858 9858 + #define MC_CMD_MAC_STATE_OUT_MAC_FAULT_FLAGS_LEN 4 9859 9859 + /* enum property: bitshift */ 9860 9860 + /* enum: Indicates a local MAC fault. */ 9861 9861 + #define MC_CMD_MAC_STATE_OUT_LOCAL 0x0 9862 9862 + /* enum: Indicates a remote MAC fault. */ 9863 9863 + #define MC_CMD_MAC_STATE_OUT_REMOTE 0x1 9864 9864 + /* enum: Indicates a pending reconfiguration of the MAC. */ 9865 9865 + #define MC_CMD_MAC_STATE_OUT_PENDING_RECONFIG 0x2 9866 9866 + /* The flags that were used to configure the MAC. This is a copy of the FLAGS 9867 9867 + * field in the MC_CMD_MAC_CTRL_IN command. 9868 9868 + */ 9869 9869 + #define MC_CMD_MAC_STATE_OUT_FLAGS_OFST 20 9870 9870 + #define MC_CMD_MAC_STATE_OUT_FLAGS_LEN 4 9871 9871 + /* enum property: bitshift */ 9872 9872 + /* Enum values, see field(s): */ 9873 9873 + /* MC_CMD_MAC_FLAGS/MASK */ 9874 9874 + /* The transmission mode that was used to configure the MAC. This is a copy of 9875 9875 + * the TRANSMISSION_MODE field in the MC_CMD_MAC_CTRL_IN command. 9876 9876 + */ 9877 9877 + #define MC_CMD_MAC_STATE_OUT_TRANSMISSION_MODE_OFST 24 9878 9878 + #define MC_CMD_MAC_STATE_OUT_TRANSMISSION_MODE_LEN 4 9879 9879 + /* enum property: value */ 9880 9880 + /* Enum values, see field(s): */ 9881 9881 + /* MC_CMD_TRANSMISSION_MODE/MASK */ 9882 9882 + /* The control flags that were used to configure the MAC. This is a copy of the 9883 9883 + * CONTROL field in the MC_CMD_MAC_CTRL_IN command. 9884 9884 + */ 9885 9885 + #define MC_CMD_MAC_STATE_OUT_CONTROL_FLAGS_OFST 28 9886 9886 + #define MC_CMD_MAC_STATE_OUT_CONTROL_FLAGS_LEN 4 9887 9887 + /* enum property: bitshift */ 9888 9888 + /* Enum values, see field(s): */ 9889 9889 + /* MC_CMD_MAC_CONFIG_OPTIONS/MASK */ 9890 9890 + 9891 9891 + 9892 9892 + /***********************************/ 9893 9893 + /* MC_CMD_GET_ASSIGNED_PORT_HANDLE 9894 9894 + * Obtain a handle that can be operated on to configure and query the status of 9895 9895 + * the link. ENOENT is returned when no port is assigned to the client. Return 9896 9896 + * code: 0, ENOENT 9897 9897 + */ 9898 9898 + #define MC_CMD_GET_ASSIGNED_PORT_HANDLE 0x1e2 9899 9899 + #undef MC_CMD_0x1e2_PRIVILEGE_CTG 9900 9900 + 9901 9901 + #define MC_CMD_0x1e2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9902 9902 + 9903 9903 + /* MC_CMD_GET_ASSIGNED_PORT_HANDLE_IN msgrequest */ 9904 9904 + #define MC_CMD_GET_ASSIGNED_PORT_HANDLE_IN_LEN 0 9905 9905 + 9906 9906 + /* MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT msgresponse */ 9907 9907 + #define MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_LEN 4 9908 9908 + /* Handle for assigned port. */ 9909 9909 + #define MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_PORT_HANDLE_OFST 0 9910 9910 + #define MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_PORT_HANDLE_LEN 4 9911 9911 + 9912 9912 + /* MC_CMD_STAT_ID structuredef */ 9913 9913 + #define MC_CMD_STAT_ID_LEN 4 9914 9914 + #define MC_CMD_STAT_ID_SOURCE_ID_OFST 0 9915 9915 + #define MC_CMD_STAT_ID_SOURCE_ID_LEN 2 9916 9916 + /* enum property: index */ 9917 9917 + /* enum: Internal markers (generation start and end markers) */ 9918 9918 + #define MC_CMD_STAT_ID_MARKER 0x1 9919 9919 + /* enum: Network port MAC statistics. */ 9920 9920 + #define MC_CMD_STAT_ID_MAC 0x2 9921 9921 + /* enum: Network port PHY statistics. */ 9922 9922 + #define MC_CMD_STAT_ID_PHY 0x3 9923 9923 + #define MC_CMD_STAT_ID_SOURCE_ID_LBN 0 9924 9924 + #define MC_CMD_STAT_ID_SOURCE_ID_WIDTH 16 9925 9925 + #define MC_CMD_STAT_ID_MARKER_STAT_ID_OFST 2 9926 9926 + #define MC_CMD_STAT_ID_MARKER_STAT_ID_LEN 2 9927 9927 + /* enum property: index */ 9928 9928 + /* enum: This value is used to mark the start of a generation of statistics for 9929 9929 + * DMA synchronization. It is incremented whenever a new set of statistics is 9930 9930 + * transferred. Always the first entry in the DMA buffer. 9931 9931 + */ 9932 9932 + #define MC_CMD_STAT_ID_GENERATION_START 0x1 9933 9933 + /* enum: This value is used to mark the end of a generation of statistics for 9934 9934 + * DMA synchronizaion. Always the last entry in the DMA buffer and set to the 9935 9935 + * same value as GENERATION_START. The host driver must compare the 9936 9936 + * GENERATION_START and GENERATION_END values to verify that the DMA buffer is 9937 9937 + * consistent upon copying the the DMA buffer. If they do not match, it means 9938 9938 + * that new DMA transfer has started while the host driver was copying the DMA 9939 9939 + * buffer. In this case, the host driver must repeat the copy operation. 9940 9940 + */ 9941 9941 + #define MC_CMD_STAT_ID_GENERATION_END 0x2 9942 9942 + #define MC_CMD_STAT_ID_MARKER_STAT_ID_LBN 16 9943 9943 + #define MC_CMD_STAT_ID_MARKER_STAT_ID_WIDTH 16 9944 9944 + #define MC_CMD_STAT_ID_MAC_STAT_ID_OFST 2 9945 9945 + #define MC_CMD_STAT_ID_MAC_STAT_ID_LEN 2 9946 9946 + /* enum property: index */ 9947 9947 + /* enum: Total number of packets transmitted (includes pause frames). */ 9948 9948 + #define MC_CMD_STAT_ID_TX_PKTS 0x1 9949 9949 + /* enum: Pause frames transmitted. */ 9950 9950 + #define MC_CMD_STAT_ID_TX_PAUSE_PKTS 0x2 9951 9951 + /* enum: Control frames transmitted. */ 9952 9952 + #define MC_CMD_STAT_ID_TX_CONTROL_PKTS 0x3 9953 9953 + /* enum: Unicast packets transmitted (includes pause frames). */ 9954 9954 + #define MC_CMD_STAT_ID_TX_UNICAST_PKTS 0x4 9955 9955 + /* enum: Multicast packets transmitted (includes pause frames). */ 9956 9956 + #define MC_CMD_STAT_ID_TX_MULTICAST_PKTS 0x5 9957 9957 + /* enum: Broadcast packets transmitted (includes pause frames). */ 9958 9958 + #define MC_CMD_STAT_ID_TX_BROADCAST_PKTS 0x6 9959 9959 + /* enum: Bytes transmitted (includes pause frames). */ 9960 9960 + #define MC_CMD_STAT_ID_TX_BYTES 0x7 9961 9961 + /* enum: Bytes transmitted with bad CRC. */ 9962 9962 + #define MC_CMD_STAT_ID_TX_BAD_BYTES 0x8 9963 9963 + /* enum: Bytes transmitted with good CRC. */ 9964 9964 + #define MC_CMD_STAT_ID_TX_GOOD_BYTES 0x9 9965 9965 + /* enum: Packets transmitted with length less than 64 bytes. */ 9966 9966 + #define MC_CMD_STAT_ID_TX_LT64_PKTS 0xa 9967 9967 + /* enum: Packets transmitted with length equal to 64 bytes. */ 9968 9968 + #define MC_CMD_STAT_ID_TX_64_PKTS 0xb 9969 9969 + /* enum: Packets transmitted with length between 65 and 127 bytes. */ 9970 9970 + #define MC_CMD_STAT_ID_TX_65_TO_127_PKTS 0xc 9971 9971 + /* enum: Packets transmitted with length between 128 and 255 bytes. */ 9972 9972 + #define MC_CMD_STAT_ID_TX_128_TO_255_PKTS 0xd 9973 9973 + /* enum: Packets transmitted with length between 256 and 511 bytes. */ 9974 9974 + #define MC_CMD_STAT_ID_TX_256_TO_511_PKTS 0xe 9975 9975 + /* enum: Packets transmitted with length between 512 and 1023 bytes. */ 9976 9976 + #define MC_CMD_STAT_ID_TX_512_TO_1023_PKTS 0xf 9977 9977 + /* enum: Packets transmitted with length between 1024 and 1518 bytes. */ 9978 9978 + #define MC_CMD_STAT_ID_TX_1024_TO_15XX_PKTS 0x10 9979 9979 + /* enum: Packets transmitted with length between 1519 and 9216 bytes. */ 9980 9980 + #define MC_CMD_STAT_ID_TX_15XX_TO_JUMBO_PKTS 0x11 9981 9981 + /* enum: Packets transmitted with length greater than 9216 bytes. */ 9982 9982 + #define MC_CMD_STAT_ID_TX_GTJUMBO_PKTS 0x12 9983 9983 + /* enum: Packets transmitted with bad FCS. */ 9984 9984 + #define MC_CMD_STAT_ID_TX_BAD_FCS_PKTS 0x13 9985 9985 + /* enum: Packets transmitted with good FCS. */ 9986 9986 + #define MC_CMD_STAT_ID_TX_GOOD_FCS_PKTS 0x14 9987 9987 + /* enum: Packets received. */ 9988 9988 + #define MC_CMD_STAT_ID_RX_PKTS 0x15 9989 9989 + /* enum: Pause frames received. */ 9990 9990 + #define MC_CMD_STAT_ID_RX_PAUSE_PKTS 0x16 9991 9991 + /* enum: Total number of good packets received. */ 9992 9992 + #define MC_CMD_STAT_ID_RX_GOOD_PKTS 0x17 9993 9993 + /* enum: Total number of BAD packets received. */ 9994 9994 + #define MC_CMD_STAT_ID_RX_BAD_PKTS 0x18 9995 9995 + /* enum: Total number of control frames received. */ 9996 9996 + #define MC_CMD_STAT_ID_RX_CONTROL_PKTS 0x19 9997 9997 + /* enum: Total number of unicast packets received. */ 9998 9998 + #define MC_CMD_STAT_ID_RX_UNICAST_PKTS 0x1a 9999 9999 + /* enum: Total number of multicast packets received. */ 10000 10000 + #define MC_CMD_STAT_ID_RX_MULTICAST_PKTS 0x1b 10001 10001 + /* enum: Total number of broadcast packets received. */ 10002 10002 + #define MC_CMD_STAT_ID_RX_BROADCAST_PKTS 0x1c 10003 10003 + /* enum: Total number of bytes received. */ 10004 10004 + #define MC_CMD_STAT_ID_RX_BYTES 0x1d 10005 10005 + /* enum: Total number of bytes received with bad CRC. */ 10006 10006 + #define MC_CMD_STAT_ID_RX_BAD_BYTES 0x1e 10007 10007 + /* enum: Total number of bytes received with GOOD CRC. */ 10008 10008 + #define MC_CMD_STAT_ID_RX_GOOD_BYTES 0x1f 10009 10009 + /* enum: Packets received with length equal to 64 bytes. */ 10010 10010 + #define MC_CMD_STAT_ID_RX_64_PKTS 0x20 10011 10011 + /* enum: Packets received with length between 65 and 127 bytes. */ 10012 10012 + #define MC_CMD_STAT_ID_RX_65_TO_127_PKTS 0x21 10013 10013 + /* enum: Packets received with length between 128 and 255 bytes. */ 10014 10014 + #define MC_CMD_STAT_ID_RX_128_TO_255_PKTS 0x22 10015 10015 + /* enum: Packets received with length between 256 and 511 bytes. */ 10016 10016 + #define MC_CMD_STAT_ID_RX_256_TO_511_PKTS 0x23 10017 10017 + /* enum: Packets received with length between 512 and 1023 bytes. */ 10018 10018 + #define MC_CMD_STAT_ID_RX_512_TO_1023_PKTS 0x24 10019 10019 + /* enum: Packets received with length between 1024 and 1518 bytes. */ 10020 10020 + #define MC_CMD_STAT_ID_RX_1024_TO_15XX_PKTS 0x25 10021 10021 + /* enum: Packets received with length between 1519 and 9216 bytes. */ 10022 10022 + #define MC_CMD_STAT_ID_RX_15XX_TO_JUMBO_PKTS 0x26 10023 10023 + /* enum: Packets received with length greater than 9216 bytes. */ 10024 10024 + #define MC_CMD_STAT_ID_RX_GTJUMBO_PKTS 0x27 10025 10025 + /* enum: Packets received with length less than 64 bytes. */ 10026 10026 + #define MC_CMD_STAT_ID_RX_UNDERSIZE_PKTS 0x28 10027 10027 + /* enum: Packets received with bad FCS. */ 10028 10028 + #define MC_CMD_STAT_ID_RX_BAD_FCS_PKTS 0x29 10029 10029 + /* enum: Packets received with GOOD FCS. */ 10030 10030 + #define MC_CMD_STAT_ID_RX_GOOD_FCS_PKTS 0x2a 10031 10031 + /* enum: Packets received with overflow. */ 10032 10032 + #define MC_CMD_STAT_ID_RX_OVERFLOW_PKTS 0x2b 10033 10033 + /* enum: Packets received with symbol error. */ 10034 10034 + #define MC_CMD_STAT_ID_RX_SYMBOL_ERROR_PKTS 0x2c 10035 10035 + /* enum: Packets received with alignment error. */ 10036 10036 + #define MC_CMD_STAT_ID_RX_ALIGN_ERROR_PKTS 0x2d 10037 10037 + /* enum: Packets received with length error. */ 10038 10038 + #define MC_CMD_STAT_ID_RX_LENGTH_ERROR_PKTS 0x2e 10039 10039 + /* enum: Packets received with internal error. */ 10040 10040 + #define MC_CMD_STAT_ID_RX_INTERNAL_ERROR_PKTS 0x2f 10041 10041 + /* enum: Packets received with jabber. These packets are larger than the 10042 10042 + * allowed maximum receive unit (MRU). This indicates that a packet either has 10043 10043 + * a bad CRC or has an RX error. 10044 10044 + */ 10045 10045 + #define MC_CMD_STAT_ID_RX_JABBER_PKTS 0x30 10046 10046 + /* enum: Packets dropped due to having no descriptor. This is a datapath stat 10047 10047 + */ 10048 10048 + #define MC_CMD_STAT_ID_RX_NODESC_DROPS 0x31 10049 10049 + /* enum: Packets received with lanes 0 and 1 character error. */ 10050 10050 + #define MC_CMD_STAT_ID_RX_LANES01_CHAR_ERR 0x32 10051 10051 + /* enum: Packets received with lanes 2 and 3 character error. */ 10052 10052 + #define MC_CMD_STAT_ID_RX_LANES23_CHAR_ERR 0x33 10053 10053 + /* enum: Packets received with lanes 0 and 1 disparity error. */ 10054 10054 + #define MC_CMD_STAT_ID_RX_LANES01_DISP_ERR 0x34 10055 10055 + /* enum: Packets received with lanes 2 and 3 disparity error. */ 10056 10056 + #define MC_CMD_STAT_ID_RX_LANES23_DISP_ERR 0x35 10057 10057 + /* enum: Packets received with match fault. */ 10058 10058 + #define MC_CMD_STAT_ID_RX_MATCH_FAULT 0x36 10059 10059 + #define MC_CMD_STAT_ID_MAC_STAT_ID_LBN 16 10060 10060 + #define MC_CMD_STAT_ID_MAC_STAT_ID_WIDTH 16 10061 10061 + /* Include FEC stats. */ 10062 10062 + #define MC_CMD_STAT_ID_PHY_STAT_ID_OFST 2 10063 10063 + #define MC_CMD_STAT_ID_PHY_STAT_ID_LEN 2 10064 10064 + /* enum property: index */ 10065 10065 + /* enum: Number of uncorrected FEC codewords on link (RS-FEC only from Medford2 10066 10066 + * onwards) 10067 10067 + */ 10068 10068 + #define MC_CMD_STAT_ID_FEC_UNCORRECTED_ERRORS 0x1 10069 10069 + /* enum: Number of corrected FEC codewords on link (RS-FEC only from Medford2 10070 10070 + * onwards) 10071 10071 + */ 10072 10072 + #define MC_CMD_STAT_ID_FEC_CORRECTED_ERRORS 0x2 10073 10073 + /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */ 10074 10074 + #define MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE0 0x3 10075 10075 + /* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */ 10076 10076 + #define MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE1 0x4 10077 10077 + /* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */ 10078 10078 + #define MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE2 0x5 10079 10079 + /* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */ 10080 10080 + #define MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE3 0x6 10081 10081 + #define MC_CMD_STAT_ID_PHY_STAT_ID_LBN 16 10082 10082 + #define MC_CMD_STAT_ID_PHY_STAT_ID_WIDTH 16 10083 10083 + 10084 10084 + /* MC_CMD_STAT_DESC structuredef: Structure describing the layout and size of 10085 10085 + * the stats DMA buffer descriptor. 10086 10086 + */ 10087 10087 + #define MC_CMD_STAT_DESC_LEN 8 10088 10088 + /* Unique identifier of the statistic. Formatted as MC_CMD_STAT_ID */ 10089 10089 + #define MC_CMD_STAT_DESC_STAT_ID_OFST 0 10090 10090 + #define MC_CMD_STAT_DESC_STAT_ID_LEN 4 10091 10091 + #define MC_CMD_STAT_DESC_STAT_ID_LBN 0 10092 10092 + #define MC_CMD_STAT_DESC_STAT_ID_WIDTH 32 10093 10093 + /* See structuredef: MC_CMD_STAT_ID */ 10094 10094 + #define MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_OFST 0 10095 10095 + #define MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_LEN 2 10096 10096 + #define MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_LBN 0 10097 10097 + #define MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_WIDTH 16 10098 10098 + #define MC_CMD_STAT_DESC_STAT_ID_MARKER_STAT_ID_OFST 2 10099 10099 + #define MC_CMD_STAT_DESC_STAT_ID_MARKER_STAT_ID_LEN 2 10100 10100 + #define MC_CMD_STAT_DESC_STAT_ID_MARKER_STAT_ID_LBN 16 10101 10101 + #define MC_CMD_STAT_DESC_STAT_ID_MARKER_STAT_ID_WIDTH 16 10102 10102 + #define MC_CMD_STAT_DESC_STAT_ID_MAC_STAT_ID_OFST 2 10103 10103 + #define MC_CMD_STAT_DESC_STAT_ID_MAC_STAT_ID_LEN 2 10104 10104 + #define MC_CMD_STAT_DESC_STAT_ID_MAC_STAT_ID_LBN 16 10105 10105 + #define MC_CMD_STAT_DESC_STAT_ID_MAC_STAT_ID_WIDTH 16 10106 10106 + #define MC_CMD_STAT_DESC_STAT_ID_PHY_STAT_ID_OFST 2 10107 10107 + #define MC_CMD_STAT_DESC_STAT_ID_PHY_STAT_ID_LEN 2 10108 10108 + #define MC_CMD_STAT_DESC_STAT_ID_PHY_STAT_ID_LBN 16 10109 10109 + #define MC_CMD_STAT_DESC_STAT_ID_PHY_STAT_ID_WIDTH 16 10110 10110 + /* Index of the statistic in the DMA buffer. */ 10111 10111 + #define MC_CMD_STAT_DESC_STAT_INDEX_OFST 4 10112 10112 + #define MC_CMD_STAT_DESC_STAT_INDEX_LEN 2 10113 10113 + #define MC_CMD_STAT_DESC_STAT_INDEX_LBN 32 10114 10114 + #define MC_CMD_STAT_DESC_STAT_INDEX_WIDTH 16 10115 10115 + /* Reserved for future extension (e.g. flags field) - currently always 0. */ 10116 10116 + #define MC_CMD_STAT_DESC_RESERVED_OFST 6 10117 10117 + #define MC_CMD_STAT_DESC_RESERVED_LEN 2 10118 10118 + #define MC_CMD_STAT_DESC_RESERVED_LBN 48 10119 10119 + #define MC_CMD_STAT_DESC_RESERVED_WIDTH 16 10120 10120 + 10121 10121 + 10122 10122 + /***********************************/ 10123 10123 + /* MC_CMD_MAC_STATISTICS_DESCRIPTOR 10124 10124 + * Get a list of descriptors that describe the layout and size of the stats 10125 10125 + * buffer required for retrieving statistics for a given port. Each entry in 10126 10126 + * the list is formatted as MC_CMD_STAT_DESC and provides the ID of each stat 10127 10127 + * and its location and size in the buffer. It also gives the overall minimum 10128 10128 + * size of the DMA buffer required when DMA mode is used. Note that the first 10129 10129 + * and last entries in the list are reserved for the generation start 10130 10130 + * (MC_CMD_MARKER_STAT_GENERATION_START) and end 10131 10131 + * (MC_CMD_MARKER_STAT_GENERATION_END) markers respectively, to be used for DMA 10132 10132 + * synchronisation as described in the documentation for the relevant enum 10133 10133 + * entries. The entries are present in the buffer even if DMA mode is not used. 10134 10134 + * Provisions are made (but currently unused) for extending the size of the 10135 10135 + * descriptors, extending the size of the list beyond the maximum MCDI response 10136 10136 + * size, as well as the dynamic runtime updates of the list. Returns: 0 on 10137 10137 + * success, ENOENT on non-existent port handle 10138 10138 + */ 10139 10139 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR 0x1e3 10140 10140 + #undef MC_CMD_0x1e3_PRIVILEGE_CTG 10141 10141 + 10142 10142 + #define MC_CMD_0x1e3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10143 10143 + 10144 10144 + /* MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN msgrequest */ 10145 10145 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_LEN 8 10146 10146 + /* Handle of port to get MAC statitstics descriptors for. */ 10147 10147 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_PORT_HANDLE_OFST 0 10148 10148 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_PORT_HANDLE_LEN 4 10149 10149 + /* Offset of the first entry to return, for cases where not all entries fit in 10150 10150 + * the MCDI response. Should be set to 0 on initial request, and on subsequent 10151 10151 + * requests updated by the number of entries already returned, as long as the 10152 10152 + * MORE_ENTRIES flag is set. 10153 10153 + */ 10154 10154 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_OFFSET_OFST 4 10155 10155 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_OFFSET_LEN 4 10156 10156 + 10157 10157 + /* MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT msgresponse */ 10158 10158 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMIN 28 10159 10159 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMAX 252 10160 10160 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMAX_MCDI2 1020 10161 10161 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LEN(num) (20+8*(num)) 10162 10162 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_NUM(len) (((len)-20)/8) 10163 10163 + /* Generation number of the stats buffer. This is incremented each time the 10164 10164 + * buffer is updated, and is used to verify the consistency of the buffer 10165 10165 + * contents. Reserved for future extension (dynamic list updates). Currently 10166 10166 + * always set to 0. 10167 10167 + */ 10168 10168 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_GENERATION_OFST 0 10169 10169 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_GENERATION_LEN 4 10170 10170 + /* Minimum size of the DMA buffer required to retrieve all statistics for the 10171 10171 + * port. This is the sum of the sizes of all the statistics, plus the size of 10172 10172 + * the generation markers. Minimum buffer size in bytes required to fit all 10173 10173 + * statistics. Drivers will typically round up this value to the granularity of 10174 10174 + * the host DMA allocation units. 10175 10175 + */ 10176 10176 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_DMA_BUFFER_SIZE_OFST 4 10177 10177 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_DMA_BUFFER_SIZE_LEN 4 10178 10178 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_FLAGS_OFST 8 10179 10179 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_FLAGS_LEN 4 10180 10180 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_MORE_ENTRIES_OFST 8 10181 10181 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_MORE_ENTRIES_LBN 0 10182 10182 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_MORE_ENTRIES_WIDTH 1 10183 10183 + /* Size of the individual descriptor entry in the list. Determines the entry 10184 10184 + * stride in the list. Currently always set to size of MC_CMD_STAT_DESC, larger 10185 10185 + * values can be used in the future for extending the descriptor, by appending 10186 10186 + * new data to the end of the existing structure. 10187 10187 + */ 10188 10188 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_SIZE_OFST 12 10189 10189 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_SIZE_LEN 4 10190 10190 + /* Number of entries returned in the descriptor list. */ 10191 10191 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_COUNT_OFST 16 10192 10192 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_COUNT_LEN 4 10193 10193 + /* List of descriptors. Each entry is formatted as MC_CMD_STAT_DESC and 10194 10194 + * provides the ID of each stat and its location and size in the buffer. The 10195 10195 + * first and last entries are reserved for the generation start and end markers 10196 10196 + * respectively. 10197 10197 + */ 10198 10198 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_OFST 20 10199 10199 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LEN 8 10200 10200 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LO_OFST 20 10201 10201 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LO_LEN 4 10202 10202 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LO_LBN 160 10203 10203 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LO_WIDTH 32 10204 10204 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_HI_OFST 24 10205 10205 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_HI_LEN 4 10206 10206 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_HI_LBN 192 10207 10207 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_HI_WIDTH 32 10208 10208 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_MINNUM 1 10209 10209 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_MAXNUM 29 10210 10210 + #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_MAXNUM_MCDI2 125 10211 10211 + 10212 10212 + 10213 10213 + /***********************************/ 10214 10214 + /* MC_CMD_MAC_STATISTICS 10215 10215 + * Get generic MAC statistics. This call retrieves unified statistics managed 10216 10216 + * by the MC. The MC will populate and provide all supported statistics in the 10217 10217 + * format as returned by MC_CMD_MAC_STATISTICS_DESCRIPTOR. Refer to the 10218 10218 + * aforementioned command for the format and contents of the stats DMA buffer. 10219 10219 + * To ensure consistent and accurate results, it is essential for the driver to 10220 10220 + * initialize the DMA buffer with zeros when DMA mode is used. Returns: 0 on 10221 10221 + * success, ETIME if the DMA buffer is not ready, ENOENT on non-existent port 10222 10222 + * handle, and EINVAL on invalid parameters (DMA buffer too small) 10223 10223 + */ 10224 10224 + #define MC_CMD_MAC_STATISTICS 0x1e4 10225 10225 + #undef MC_CMD_0x1e4_PRIVILEGE_CTG 10226 10226 + 10227 10227 + #define MC_CMD_0x1e4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10228 10228 + 10229 10229 + /* MC_CMD_MAC_STATISTICS_IN msgrequest */ 10230 10230 + #define MC_CMD_MAC_STATISTICS_IN_LEN 20 10231 10231 + /* Handle of port to get MAC statistics for. */ 10232 10232 + #define MC_CMD_MAC_STATISTICS_IN_PORT_HANDLE_OFST 0 10233 10233 + #define MC_CMD_MAC_STATISTICS_IN_PORT_HANDLE_LEN 4 10234 10234 + /* Contains options for querying the MAC statistics. */ 10235 10235 + #define MC_CMD_MAC_STATISTICS_IN_CMD_OFST 4 10236 10236 + #define MC_CMD_MAC_STATISTICS_IN_CMD_LEN 4 10237 10237 + #define MC_CMD_MAC_STATISTICS_IN_DMA_OFST 4 10238 10238 + #define MC_CMD_MAC_STATISTICS_IN_DMA_LBN 0 10239 10239 + #define MC_CMD_MAC_STATISTICS_IN_DMA_WIDTH 1 10240 10240 + #define MC_CMD_MAC_STATISTICS_IN_CLEAR_OFST 4 10241 10241 + #define MC_CMD_MAC_STATISTICS_IN_CLEAR_LBN 1 10242 10242 + #define MC_CMD_MAC_STATISTICS_IN_CLEAR_WIDTH 1 10243 10243 + #define MC_CMD_MAC_STATISTICS_IN_PERIODIC_CHANGE_OFST 4 10244 10244 + #define MC_CMD_MAC_STATISTICS_IN_PERIODIC_CHANGE_LBN 2 10245 10245 + #define MC_CMD_MAC_STATISTICS_IN_PERIODIC_CHANGE_WIDTH 1 10246 10246 + #define MC_CMD_MAC_STATISTICS_IN_PERIODIC_ENABLE_OFST 4 10247 10247 + #define MC_CMD_MAC_STATISTICS_IN_PERIODIC_ENABLE_LBN 3 10248 10248 + #define MC_CMD_MAC_STATISTICS_IN_PERIODIC_ENABLE_WIDTH 1 10249 10249 + #define MC_CMD_MAC_STATISTICS_IN_PERIODIC_NOEVENT_OFST 4 10250 10250 + #define MC_CMD_MAC_STATISTICS_IN_PERIODIC_NOEVENT_LBN 4 10251 10251 + #define MC_CMD_MAC_STATISTICS_IN_PERIODIC_NOEVENT_WIDTH 1 10252 10252 + #define MC_CMD_MAC_STATISTICS_IN_PERIOD_MS_OFST 4 10253 10253 + #define MC_CMD_MAC_STATISTICS_IN_PERIOD_MS_LBN 16 10254 10254 + #define MC_CMD_MAC_STATISTICS_IN_PERIOD_MS_WIDTH 16 10255 10255 + /* This is the address of the DMA buffer to use for transfer of the statistics. 10256 10256 + * Only valid if the DMA flag is set to 1. 10257 10257 + */ 10258 10258 + #define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_OFST 8 10259 10259 + #define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LEN 8 10260 10260 + #define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LO_OFST 8 10261 10261 + #define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LO_LEN 4 10262 10262 + #define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LO_LBN 64 10263 10263 + #define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LO_WIDTH 32 10264 10264 + #define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_HI_OFST 12 10265 10265 + #define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_HI_LEN 4 10266 10266 + #define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_HI_LBN 96 10267 10267 + #define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_HI_WIDTH 32 10268 10268 + /* This is the length of the DMA buffer to use for the transfer of the 10269 10269 + * statistics. The buffer should be at least DMA_BUFFER_SIZE long, as returned 10270 10270 + * by MC_CMD_MAC_STATISTICS_DESCRIPTOR. If the supplied buffer is too small, 10271 10271 + * the command will fail with EINVAL. Only valid if the DMA flag is set to 1. 10272 10272 + */ 10273 10273 + #define MC_CMD_MAC_STATISTICS_IN_DMA_LEN_OFST 16 10274 10274 + #define MC_CMD_MAC_STATISTICS_IN_DMA_LEN_LEN 4 10275 10275 + 10276 10276 + /* MC_CMD_MAC_STATISTICS_OUT msgresponse */ 10277 10277 + #define MC_CMD_MAC_STATISTICS_OUT_LENMIN 5 10278 10278 + #define MC_CMD_MAC_STATISTICS_OUT_LENMAX 252 10279 10279 + #define MC_CMD_MAC_STATISTICS_OUT_LENMAX_MCDI2 1020 10280 10280 + #define MC_CMD_MAC_STATISTICS_OUT_LEN(num) (4+1*(num)) 10281 10281 + #define MC_CMD_MAC_STATISTICS_OUT_DATA_NUM(len) (((len)-4)/1) 10282 10282 + /* length of the data in bytes */ 10283 10283 + #define MC_CMD_MAC_STATISTICS_OUT_DATALEN_OFST 0 10284 10284 + #define MC_CMD_MAC_STATISTICS_OUT_DATALEN_LEN 4 10285 10285 + #define MC_CMD_MAC_STATISTICS_OUT_DATA_OFST 4 10286 10286 + #define MC_CMD_MAC_STATISTICS_OUT_DATA_LEN 1 10287 10287 + #define MC_CMD_MAC_STATISTICS_OUT_DATA_MINNUM 1 10288 10288 + #define MC_CMD_MAC_STATISTICS_OUT_DATA_MAXNUM 248 10289 10289 + #define MC_CMD_MAC_STATISTICS_OUT_DATA_MAXNUM_MCDI2 1016 10290 10290 + 10291 10291 + /* NET_PORT_HANDLE_DESC structuredef: Network port descriptor containing a port 10292 10292 + * handle and attributes used, for example, in MC_CMD_ENUM_PORTS. 10293 10293 + */ 10294 10294 + #define NET_PORT_HANDLE_DESC_LEN 53 10295 10295 + /* The handle to identify the port */ 10296 10296 + #define NET_PORT_HANDLE_DESC_PORT_HANDLE_OFST 0 10297 10297 + #define NET_PORT_HANDLE_DESC_PORT_HANDLE_LEN 4 10298 10298 + #define NET_PORT_HANDLE_DESC_PORT_HANDLE_LBN 0 10299 10299 + #define NET_PORT_HANDLE_DESC_PORT_HANDLE_WIDTH 32 10300 10300 + /* Includes the type of port e.g. physical, virtual or MAE MPORT and other 10301 10301 + * properties relevant to the port. 10302 10302 + */ 10303 10303 + #define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_OFST 4 10304 10304 + #define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LEN 8 10305 10305 + #define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_OFST 4 10306 10306 + #define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_LEN 4 10307 10307 + #define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_LBN 32 10308 10308 + #define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_WIDTH 32 10309 10309 + #define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_HI_OFST 8 10310 10310 + #define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_HI_LEN 4 10311 10311 + #define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_HI_LBN 64 10312 10312 + #define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_HI_WIDTH 32 10313 10313 + #define NET_PORT_HANDLE_DESC_PORT_TYPE_OFST 4 10314 10314 + #define NET_PORT_HANDLE_DESC_PORT_TYPE_LBN 0 10315 10315 + #define NET_PORT_HANDLE_DESC_PORT_TYPE_WIDTH 3 10316 10316 + #define NET_PORT_HANDLE_DESC_PHYSICAL 0x0 /* enum */ 10317 10317 + #define NET_PORT_HANDLE_DESC_VIRTUAL 0x1 /* enum */ 10318 10318 + #define NET_PORT_HANDLE_DESC_MPORT 0x2 /* enum */ 10319 10319 + #define NET_PORT_HANDLE_DESC_IS_ZOMBIE_OFST 4 10320 10320 + #define NET_PORT_HANDLE_DESC_IS_ZOMBIE_LBN 8 10321 10321 + #define NET_PORT_HANDLE_DESC_IS_ZOMBIE_WIDTH 1 10322 10322 + #define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LBN 32 10323 10323 + #define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_WIDTH 64 10324 10324 + /* The dynamic change that led to the port enumeration */ 10325 10325 + #define NET_PORT_HANDLE_DESC_ENTRY_SRC_OFST 12 10326 10326 + #define NET_PORT_HANDLE_DESC_ENTRY_SRC_LEN 1 10327 10327 + /* enum: Indicates that the ENTRY_SRC field has not been initialized. */ 10328 10328 + #define NET_PORT_HANDLE_DESC_UNKNOWN 0x0 10329 10329 + /* enum: The port was enumerated at start of day. */ 10330 10330 + #define NET_PORT_HANDLE_DESC_PRESENT 0x1 10331 10331 + /* enum: The port was dynamically added. */ 10332 10332 + #define NET_PORT_HANDLE_DESC_ADDED 0x2 10333 10333 + /* enum: The port was dynamically deleted. */ 10334 10334 + #define NET_PORT_HANDLE_DESC_DELETED 0x3 10335 10335 + #define NET_PORT_HANDLE_DESC_ENTRY_SRC_LBN 96 10336 10336 + #define NET_PORT_HANDLE_DESC_ENTRY_SRC_WIDTH 8 10337 10337 + /* This is an opaque 40 byte label exposed to users as a unique identifier of 10338 10338 + * the port. It is represented as a zero-terminated ASCII string and assigned 10339 10339 + * by the port administrator which is typically either the firmware for a 10340 10340 + * physical port or the host software responsible for creating the virtual 10341 10341 + * port. The label is conveyed to the driver after assignment, which, unlike 10342 10342 + * the port administrator, does not need to know how to interpret the label. 10343 10343 + */ 10344 10344 + #define NET_PORT_HANDLE_DESC_PORT_LABEL_OFST 13 10345 10345 + #define NET_PORT_HANDLE_DESC_PORT_LABEL_LEN 40 10346 10346 + #define NET_PORT_HANDLE_DESC_PORT_LABEL_LBN 104 10347 10347 + #define NET_PORT_HANDLE_DESC_PORT_LABEL_WIDTH 320 10348 10348 + 10349 10349 + 10350 10350 + /***********************************/ 10351 10351 + /* MC_CMD_ENUM_PORTS 10352 10352 + * This command returns handles for all ports present in the system. The PCIe 10353 10353 + * function type of each port (either physical or virtual) is also reported. 10354 10354 + * After a start-of-day port enumeration, firmware keeps track of all available 10355 10355 + * ports upon creation or deletion and updates the ports if there is a change. 10356 10356 + * This command is cleared after a control interface reset (e.g. FLR, 10357 10357 + * ENTITY_RESET), in which case it must be called again to reenumerate the 10358 10358 + * ports. The command is also clear-on-read and repeated calls will drain the 10359 10359 + * buffer. 10360 10360 + */ 10361 10361 + #define MC_CMD_ENUM_PORTS 0x1e5 10362 10362 + #undef MC_CMD_0x1e5_PRIVILEGE_CTG 10363 10363 + 10364 10364 + #define MC_CMD_0x1e5_PRIVILEGE_CTG SRIOV_CTG_LINK 10365 10365 + 10366 10366 + /* MC_CMD_ENUM_PORTS_IN msgrequest */ 10367 10367 + #define MC_CMD_ENUM_PORTS_IN_LEN 0 10368 10368 + 10369 10369 + /* MC_CMD_ENUM_PORTS_OUT msgresponse */ 10370 10370 + #define MC_CMD_ENUM_PORTS_OUT_LENMIN 12 10371 10371 + #define MC_CMD_ENUM_PORTS_OUT_LENMAX 252 10372 10372 + #define MC_CMD_ENUM_PORTS_OUT_LENMAX_MCDI2 1020 10373 10373 + #define MC_CMD_ENUM_PORTS_OUT_LEN(num) (12+1*(num)) 10374 10374 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_NUM(len) (((len)-12)/1) 10375 10375 + /* Any unused flags are reserved and must be ignored. */ 10376 10376 + #define MC_CMD_ENUM_PORTS_OUT_FLAGS_OFST 0 10377 10377 + #define MC_CMD_ENUM_PORTS_OUT_FLAGS_LEN 4 10378 10378 + #define MC_CMD_ENUM_PORTS_OUT_MORE_OFST 0 10379 10379 + #define MC_CMD_ENUM_PORTS_OUT_MORE_LBN 0 10380 10380 + #define MC_CMD_ENUM_PORTS_OUT_MORE_WIDTH 1 10381 10381 + /* The number of NET_PORT_HANDLE_DESC structures in PORT_HANDLES. */ 10382 10382 + #define MC_CMD_ENUM_PORTS_OUT_PORT_COUNT_OFST 4 10383 10383 + #define MC_CMD_ENUM_PORTS_OUT_PORT_COUNT_LEN 4 10384 10384 + #define MC_CMD_ENUM_PORTS_OUT_SIZEOF_NET_PORT_HANDLE_DESC_OFST 8 10385 10385 + #define MC_CMD_ENUM_PORTS_OUT_SIZEOF_NET_PORT_HANDLE_DESC_LEN 4 10386 10386 + /* Array of NET_PORT_HANDLE_DESC structures. Callers must use must use the 10387 10387 + * SIZEOF_NET_PORT_HANDLE_DESC field field as the array stride between entries. 10388 10388 + * This may also allow for tail padding for alignment. Fields beyond 10389 10389 + * SIZEOF_NET_PORT_HANDLE_DESC are not present. 10390 10390 + */ 10391 10391 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_OFST 12 10392 10392 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_LEN 1 10393 10393 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_MINNUM 0 10394 10394 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_MAXNUM 240 10395 10395 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_MAXNUM_MCDI2 1008 10396 10396 + /* See structuredef: NET_PORT_HANDLE_DESC */ 10397 10397 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_HANDLE_OFST 12 10398 10398 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_HANDLE_LEN 4 10399 10399 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_OFST 16 10400 10400 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LEN 8 10401 10401 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LO_OFST 16 10402 10402 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LO_LEN 4 10403 10403 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LO_LBN 128 10404 10404 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LO_WIDTH 32 10405 10405 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_HI_OFST 20 10406 10406 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_HI_LEN 4 10407 10407 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_HI_LBN 160 10408 10408 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_HI_WIDTH 32 10409 10409 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_TYPE_LBN 128 10410 10410 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_TYPE_WIDTH 3 10411 10411 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_IS_ZOMBIE_LBN 136 10412 10412 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_IS_ZOMBIE_WIDTH 1 10413 10413 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_ENTRY_SRC_OFST 24 10414 10414 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_ENTRY_SRC_LEN 1 10415 10415 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_LABEL_OFST 25 10416 10416 + #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_LABEL_LEN 40 10417 10417 + 10418 10418 + 10419 10419 + /***********************************/ 10420 10420 + /* MC_CMD_GET_TRANSCEIVER_PROPERTIES 10421 10421 + * Read properties of the transceiver associated with the port. Can be either 10422 10422 + * for a fixed onboard transceiver or an inserted module. The returned data is 10423 10423 + * interpreted from the transceiver hardware and may be fixed up by the 10424 10424 + * firmware. Use MC_CMD_GET_MODULE_DATA to get raw undecoded data. 10425 10425 + */ 10426 10426 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES 0x1e6 10427 10427 + #undef MC_CMD_0x1e6_PRIVILEGE_CTG 10428 10428 + 10429 10429 + #define MC_CMD_0x1e6_PRIVILEGE_CTG SRIOV_CTG_LINK 10430 10430 + 10431 10431 + /* MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN msgrequest */ 10432 10432 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN_LEN 4 10433 10433 + /* Handle to port to get transceiver properties from. */ 10434 10434 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN_PORT_HANDLE_OFST 0 10435 10435 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN_PORT_HANDLE_LEN 4 10436 10436 + 10437 10437 + /* MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT msgresponse */ 10438 10438 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_LEN 89 10439 10439 + /* Supported technology abilities. */ 10440 10440 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_TECH_ABILITIES_MASK_OFST 0 10441 10441 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_TECH_ABILITIES_MASK_LEN 16 10442 10442 + /* enum property: bitshift */ 10443 10443 + /* Enum values, see field(s): */ 10444 10444 + /* MC_CMD_ETH_TECH/TECH */ 10445 10445 + /* Reserved for future expansion to accommodate future Ethernet technology 10446 10446 + * expansion. 10447 10447 + */ 10448 10448 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_RESERVED_OFST 16 10449 10449 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_RESERVED_LEN 16 10450 10450 + /* Preferred FEC modes. This is a function of the cable type and length. */ 10451 10451 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_PREFERRED_FEC_MASK_OFST 32 10452 10452 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_PREFERRED_FEC_MASK_LEN 4 10453 10453 + /* enum property: bitshift */ 10454 10454 + /* Enum values, see field(s): */ 10455 10455 + /* FEC_TYPE/TYPE */ 10456 10456 + /* SFF-8042 code reported by the module. */ 10457 10457 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_CODE_OFST 36 10458 10458 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_CODE_LEN 2 10459 10459 + /* Medium. */ 10460 10460 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_MEDIUM_OFST 38 10461 10461 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_MEDIUM_LEN 1 10462 10462 + /* enum property: value */ 10463 10463 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_UNKNOWN 0x0 /* enum */ 10464 10464 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_COPPER 0x1 /* enum */ 10465 10465 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_OPTICAL 0x2 /* enum */ 10466 10466 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_BACKPLANE 0x3 /* enum */ 10467 10467 + /* Identifies the tech */ 10468 10468 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_MEDIA_SUBTYPE_OFST 39 10469 10469 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_MEDIA_SUBTYPE_LEN 1 10470 10470 + /* enum property: value */ 10471 10471 + /* MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_UNKNOWN 0x0 */ 10472 10472 + /* enum: Ethernet over twisted-pair copper cables for distances up to 100 10473 10473 + * meters. 10474 10474 + */ 10475 10475 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_BASET 0x1 10476 10476 + /* enum: Ethernet over twin-axial, balanced copper cable. */ 10477 10477 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_CR 0x2 10478 10478 + /* enum: Ethernet over backplane for connections on the same board. */ 10479 10479 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_KX 0x3 10480 10480 + /* enum: Ethernet over a single backplane lane for connections between 10481 10481 + * different boards. 10482 10482 + */ 10483 10483 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_KR 0x4 10484 10484 + /* enum: Ethernet over copper backplane. */ 10485 10485 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_KP 0x5 10486 10486 + /* enum: Ethernet over fiber optic. */ 10487 10487 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_BASEX 0x6 10488 10488 + /* enum: Short range ethernet over multimode fiber optic (See IEEE 802.3 Clause 10489 10489 + * 49 and 52). 10490 10490 + */ 10491 10491 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_SR 0x7 10492 10492 + /* enum: Long range, extended range or far reach ethernet used with single mode 10493 10493 + * fiber optics. 10494 10494 + */ 10495 10495 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_LR_ER_FR 0x8 10496 10496 + /* enum: Long reach multimode ethernet over multimode optical fiber. */ 10497 10497 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_LRM 0x9 10498 10498 + /* enum: Very short reach PAM4 ethernet over multimode optical fiber (see IEEE 10499 10499 + * 802.3db). 10500 10500 + */ 10501 10501 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VR 0xa 10502 10502 + /* enum: BASE-R encoding and PAM4 over single-mode fiber with reach up to at 10503 10503 + * least 500 meters (803.2 Clause 121 and 124) 10504 10504 + */ 10505 10505 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_DR 0xb 10506 10506 + /* String of the vendor name as intepreted by NMC firmware. NMC firmware 10507 10507 + * applies workarounds for known buggy transceivers. The vendor name is 10508 10508 + * presented as 16 bytes of ASCII characters padded with spaces. It can also be 10509 10509 + * represented as 16 bytes of zeros if the field is unspecified for the 10510 10510 + * connected module. See SFF-8472/CMIS specifications for details. 10511 10511 + */ 10512 10512 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_NAME_OFST 40 10513 10513 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_NAME_LEN 1 10514 10514 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_NAME_NUM 16 10515 10515 + /* The vendor part number as intepreted by NMC firmware. The field is presented 10516 10516 + * as 16 bytes of ASCII chars padded with spaces. It can also be 16 bytes of 10517 10517 + * zeros if the field is unspecified for the connected module. 10518 10518 + */ 10519 10519 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_PN_OFST 56 10520 10520 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_PN_LEN 1 10521 10521 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_PN_NUM 16 10522 10522 + /* Serial number of the module presented as 16 bytes of ASCII characters padded 10523 10523 + * with spaces. It can also be 16 bytes of zeros if the field is unspecified 10524 10524 + * for the connected module. See SFF-8472/CMIS specifications for details. 10525 10525 + */ 10526 10526 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_SERIAL_NUMBER_OFST 72 10527 10527 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_SERIAL_NUMBER_LEN 1 10528 10528 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_SERIAL_NUMBER_NUM 16 10529 10529 + /* This reports the number of module changes detected by the NMC firmware. */ 10530 10530 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_PORT_MODULECHANGE_SEQ_NUM_OFST 88 10531 10531 + #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_PORT_MODULECHANGE_SEQ_NUM_LEN 1 10532 10532 + 10533 10533 + 10534 10534 + /***********************************/ 10535 10535 + /* MC_CMD_GET_FIXED_PORT_PROPERTIES 10536 10536 + */ 10537 10537 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES 0x1e7 10538 10538 + #undef MC_CMD_0x1e7_PRIVILEGE_CTG 10539 10539 + 10540 10540 + #define MC_CMD_0x1e7_PRIVILEGE_CTG SRIOV_CTG_LINK 10541 10541 + 10542 10542 + /* MC_CMD_GET_FIXED_PORT_PROPERTIES_IN msgrequest: In this context, the port 10543 10543 + * consists of the MAC and the PHY, and excludes any modules inserted into the 10544 10544 + * cage. This information is fixed for a given board but not for a given ASIC. 10545 10545 + * This command reports properties for the port as it is currently configured, 10546 10546 + * and not its hardware capabilities, which can be better than the current 10547 10547 + * configuration. 10548 10548 + */ 10549 10549 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_LEN 4 10550 10550 + /* Handle to the port to from which to retreive properties */ 10551 10551 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_PORT_HANDLE_OFST 0 10552 10552 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_PORT_HANDLE_LEN 4 10553 10553 + 10554 10554 + /* MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT msgresponse */ 10555 10555 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_LEN 36 10556 10556 + /* Supported capabilities of the port in its current configuration. */ 10557 10557 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_OFST 0 10558 10558 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_LEN 25 10559 10559 + /* See structuredef: MC_CMD_ETH_AN_FIELDS */ 10560 10560 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_TECH_MASK_OFST 0 10561 10561 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_TECH_MASK_LEN 16 10562 10562 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_MASK_OFST 16 10563 10563 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_MASK_LEN 4 10564 10564 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_REQ_OFST 20 10565 10565 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_REQ_LEN 4 10566 10566 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_PAUSE_MASK_OFST 24 10567 10567 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_PAUSE_MASK_LEN 1 10568 10568 + /* Number of lanes supported by the port in its current configuration. */ 10569 10569 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_NUM_LANES_OFST 25 10570 10570 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_NUM_LANES_LEN 1 10571 10571 + /* Bitmask of supported loopback modes. Where the response to this command 10572 10572 + * includes the LOOPBACK_MODES_MASK_V2 field, that field should be used in 10573 10573 + * preference to ensure that all available loopback modes are seen. 10574 10574 + */ 10575 10575 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_LOOPBACK_MODES_MASK_OFST 26 10576 10576 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_LOOPBACK_MODES_MASK_LEN 1 10577 10577 + /* enum property: bitshift */ 10578 10578 + /* Enum values, see field(s): */ 10579 10579 + /* MC_CMD_LOOPBACK_V2/MODE */ 10580 10580 + /* This field serves as a cage index that uniquely identifies the cage to which 10581 10581 + * the module is connected. This is useful when splitter cables that have 10582 10582 + * multiple ports on a single cage are used. 10583 10583 + */ 10584 10584 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MDI_INDEX_OFST 27 10585 10585 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MDI_INDEX_LEN 1 10586 10586 + /* This bitmask is used to specify the lanes within the cage identified by 10587 10587 + * MDI_INDEX that are allocated to the port. 10588 10588 + */ 10589 10589 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MDI_LANE_MASK_OFST 28 10590 10590 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MDI_LANE_MASK_LEN 1 10591 10591 + /* Maximum frame length supported by the port in its current configuration. */ 10592 10592 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MAX_FRAME_LEN_OFST 32 10593 10593 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MAX_FRAME_LEN_LEN 4 10594 10594 + 10595 10595 + /* MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2 msgresponse */ 10596 10596 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LEN 48 10597 10597 + /* Supported capabilities of the port in its current configuration. */ 10598 10598 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_ABILITIES_OFST 0 10599 10599 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_ABILITIES_LEN 25 10600 10600 + /* Number of lanes supported by the port in its current configuration. */ 10601 10601 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_NUM_LANES_OFST 25 10602 10602 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_NUM_LANES_LEN 1 10603 10603 + /* Bitmask of supported loopback modes. Where the response to this command 10604 10604 + * includes the LOOPBACK_MODES_MASK_V2 field, that field should be used in 10605 10605 + * preference to ensure that all available loopback modes are seen. 10606 10606 + */ 10607 10607 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_OFST 26 10608 10608 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_LEN 1 10609 10609 + /* enum property: bitshift */ 10610 10610 + /* Enum values, see field(s): */ 10611 10611 + /* MC_CMD_LOOPBACK_V2/MODE */ 10612 10612 + /* This field serves as a cage index that uniquely identifies the cage to which 10613 10613 + * the module is connected. This is useful when splitter cables that have 10614 10614 + * multiple ports on a single cage are used. 10615 10615 + */ 10616 10616 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MDI_INDEX_OFST 27 10617 10617 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MDI_INDEX_LEN 1 10618 10618 + /* This bitmask is used to specify the lanes within the cage identified by 10619 10619 + * MDI_INDEX that are allocated to the port. 10620 10620 + */ 10621 10621 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MDI_LANE_MASK_OFST 28 10622 10622 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MDI_LANE_MASK_LEN 1 10623 10623 + /* Maximum frame length supported by the port in its current configuration. */ 10624 10624 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MAX_FRAME_LEN_OFST 32 10625 10625 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MAX_FRAME_LEN_LEN 4 10626 10626 + /* Bitmask of supported loopback modes. This field replaces the 10627 10627 + * LOOPBACK_MODES_MASK field which is defined under version 1 of this command. 10628 10628 + */ 10629 10629 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_OFST 40 10630 10630 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LEN 8 10631 10631 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LO_OFST 40 10632 10632 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LO_LEN 4 10633 10633 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LO_LBN 320 10634 10634 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LO_WIDTH 32 10635 10635 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_HI_OFST 44 10636 10636 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_HI_LEN 4 10637 10637 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_HI_LBN 352 10638 10638 + #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_HI_WIDTH 32 10639 10639 + /* enum property: bitshift */ 10640 10640 + /* Enum values, see field(s): */ 10641 10641 + /* MC_CMD_LOOPBACK_V2/MODE */ 10642 10642 + 10643 10643 + 10644 10644 + /***********************************/ 10645 10645 + /* MC_CMD_GET_MODULE_DATA 10646 10646 + * Read media-specific data from the PHY (e.g. SFP/SFP+ module ID information 10647 10647 + * for SFP+ PHYs). This command returns raw data from the module's EEPROM and 10648 10648 + * it is not interpreted by the MC. Use MC_CMD_GET_TRANSCEIVER_PROPERTIES to 10649 10649 + * get interpreted data. Return code: 0, ENOENT 10650 10650 + */ 10651 10651 + #define MC_CMD_GET_MODULE_DATA 0x1e8 10652 10652 + #undef MC_CMD_0x1e8_PRIVILEGE_CTG 10653 10653 + 10654 10654 + #define MC_CMD_0x1e8_PRIVILEGE_CTG SRIOV_CTG_LINK 10655 10655 + 10656 10656 + /* MC_CMD_GET_MODULE_DATA_IN msgrequest */ 10657 10657 + #define MC_CMD_GET_MODULE_DATA_IN_LEN 16 10658 10658 + /* Handle to identify the port from which to request module properties. */ 10659 10659 + #define MC_CMD_GET_MODULE_DATA_IN_PORT_HANDLE_OFST 0 10660 10660 + #define MC_CMD_GET_MODULE_DATA_IN_PORT_HANDLE_LEN 4 10661 10661 + /* 7 bit I2C address of the device. DEPRECATED: This field is replaced by 10662 10662 + * MODULE_ADDR in V2. Use V2 of this command for proper alignment and easier 10663 10663 + * access. 10664 10664 + */ 10665 10665 + #define MC_CMD_GET_MODULE_DATA_IN_DEVADDR_LBN 32 10666 10666 + #define MC_CMD_GET_MODULE_DATA_IN_DEVADDR_WIDTH 7 10667 10667 + /* 0 if the page does not support banked access, non-zero otherwise. Non-zero 10668 10668 + * BANK is valid if OFFSET is in the range 80h - ffh, i.e. in the Upper Memory 10669 10669 + * region. 10670 10670 + */ 10671 10671 + #define MC_CMD_GET_MODULE_DATA_IN_BANK_OFST 6 10672 10672 + #define MC_CMD_GET_MODULE_DATA_IN_BANK_LEN 2 10673 10673 + /* 0 if paged access is not supported, non-zero otherwise. Non-zero PAGE is 10674 10674 + * valid if OFFSET is in the range 80h - ffh. 10675 10675 + */ 10676 10676 + #define MC_CMD_GET_MODULE_DATA_IN_PAGE_OFST 8 10677 10677 + #define MC_CMD_GET_MODULE_DATA_IN_PAGE_LEN 2 10678 10678 + /* Offset in the range 00h - 7fh to access lower memory. Offset in the range 10679 10679 + * 80h - ffh to access upper memory 10680 10680 + */ 10681 10681 + #define MC_CMD_GET_MODULE_DATA_IN_OFFSET_OFST 10 10682 10682 + #define MC_CMD_GET_MODULE_DATA_IN_OFFSET_LEN 1 10683 10683 + #define MC_CMD_GET_MODULE_DATA_IN_LENGTH_OFST 12 10684 10684 + #define MC_CMD_GET_MODULE_DATA_IN_LENGTH_LEN 4 10685 10685 + 10686 10686 + /* MC_CMD_GET_MODULE_DATA_IN_V2 msgrequest: Updated MC_CMD_GET_MODULE_DATA with 10687 10687 + * 8-bit wide ADDRESSING field. This new field provides a correctly aligned 10688 10688 + * container for the 7-bit DEVADDR field from V1, now renamed MODULE_ADDR, to 10689 10689 + * ensure proper alignment. 10690 10690 + */ 10691 10691 + #define MC_CMD_GET_MODULE_DATA_IN_V2_LEN 16 10692 10692 + /* Handle to identify the port from which to request module properties. */ 10693 10693 + #define MC_CMD_GET_MODULE_DATA_IN_V2_PORT_HANDLE_OFST 0 10694 10694 + #define MC_CMD_GET_MODULE_DATA_IN_V2_PORT_HANDLE_LEN 4 10695 10695 + /* 7 bit I2C address of the device. DEPRECATED: This field is replaced by 10696 10696 + * MODULE_ADDR in V2. Use V2 of this command for proper alignment and easier 10697 10697 + * access. 10698 10698 + */ 10699 10699 + #define MC_CMD_GET_MODULE_DATA_IN_V2_DEVADDR_LBN 32 10700 10700 + #define MC_CMD_GET_MODULE_DATA_IN_V2_DEVADDR_WIDTH 7 10701 10701 + /* 0 if the page does not support banked access, non-zero otherwise. Non-zero 10702 10702 + * BANK is valid if OFFSET is in the range 80h - ffh, i.e. in the Upper Memory 10703 10703 + * region. 10704 10704 + */ 10705 10705 + #define MC_CMD_GET_MODULE_DATA_IN_V2_BANK_OFST 6 10706 10706 + #define MC_CMD_GET_MODULE_DATA_IN_V2_BANK_LEN 2 10707 10707 + /* 0 if paged access is not supported, non-zero otherwise. Non-zero PAGE is 10708 10708 + * valid if OFFSET is in the range 80h - ffh. 10709 10709 + */ 10710 10710 + #define MC_CMD_GET_MODULE_DATA_IN_V2_PAGE_OFST 8 10711 10711 + #define MC_CMD_GET_MODULE_DATA_IN_V2_PAGE_LEN 2 10712 10712 + /* Offset in the range 00h - 7fh to access lower memory. Offset in the range 10713 10713 + * 80h - ffh to access upper memory 10714 10714 + */ 10715 10715 + #define MC_CMD_GET_MODULE_DATA_IN_V2_OFFSET_OFST 10 10716 10716 + #define MC_CMD_GET_MODULE_DATA_IN_V2_OFFSET_LEN 1 10717 10717 + #define MC_CMD_GET_MODULE_DATA_IN_V2_LENGTH_OFST 12 10718 10718 + #define MC_CMD_GET_MODULE_DATA_IN_V2_LENGTH_LEN 4 10719 10719 + /* Container for 7 bit I2C addresses. */ 10720 10720 + #define MC_CMD_GET_MODULE_DATA_IN_V2_ADDRESSING_OFST 4 10721 10721 + #define MC_CMD_GET_MODULE_DATA_IN_V2_ADDRESSING_LEN 1 10722 10722 + #define MC_CMD_GET_MODULE_DATA_IN_V2_MODULE_ADDR_OFST 4 10723 10723 + #define MC_CMD_GET_MODULE_DATA_IN_V2_MODULE_ADDR_LBN 0 10724 10724 + #define MC_CMD_GET_MODULE_DATA_IN_V2_MODULE_ADDR_WIDTH 7 10725 10725 + 10726 10726 + /* MC_CMD_GET_MODULE_DATA_OUT msgresponse */ 10727 10727 + #define MC_CMD_GET_MODULE_DATA_OUT_LENMIN 5 10728 10728 + #define MC_CMD_GET_MODULE_DATA_OUT_LENMAX 252 10729 10729 + #define MC_CMD_GET_MODULE_DATA_OUT_LENMAX_MCDI2 1020 10730 10730 + #define MC_CMD_GET_MODULE_DATA_OUT_LEN(num) (4+1*(num)) 10731 10731 + #define MC_CMD_GET_MODULE_DATA_OUT_DATA_NUM(len) (((len)-4)/1) 10732 10732 + /* length of the data in bytes */ 10733 10733 + #define MC_CMD_GET_MODULE_DATA_OUT_DATALEN_OFST 0 10734 10734 + #define MC_CMD_GET_MODULE_DATA_OUT_DATALEN_LEN 4 10735 10735 + #define MC_CMD_GET_MODULE_DATA_OUT_DATA_OFST 4 10736 10736 + #define MC_CMD_GET_MODULE_DATA_OUT_DATA_LEN 1 10737 10737 + #define MC_CMD_GET_MODULE_DATA_OUT_DATA_MINNUM 1 10738 10738 + #define MC_CMD_GET_MODULE_DATA_OUT_DATA_MAXNUM 248 10739 10739 + #define MC_CMD_GET_MODULE_DATA_OUT_DATA_MAXNUM_MCDI2 1016 10740 10740 + 10741 10741 + /* EVENT_MASK structuredef */ 10742 10742 + #define EVENT_MASK_LEN 4 10743 10743 + #define EVENT_MASK_TYPE_OFST 0 10744 10744 + #define EVENT_MASK_TYPE_LEN 4 10745 10745 + /* enum: PORT_LINKCHANGE event is enabled */ 10746 10746 + #define EVENT_MASK_PORT_LINKCHANGE 0x0 10747 10747 + /* enum: PORT_MODULECHANGE event is enabled */ 10748 10748 + #define EVENT_MASK_PORT_MODULECHANGE 0x1 10749 10749 + #define EVENT_MASK_TYPE_LBN 0 10750 10750 + #define EVENT_MASK_TYPE_WIDTH 32 10751 10751 + 10752 10752 + 10753 10753 + /***********************************/ 10754 10754 + /* MC_CMD_SET_NETPORT_EVENTS_MASK 10755 10755 + */ 10756 10756 + #define MC_CMD_SET_NETPORT_EVENTS_MASK 0x1e9 10757 10757 + #undef MC_CMD_0x1e9_PRIVILEGE_CTG 10758 10758 + 10759 10759 + #define MC_CMD_0x1e9_PRIVILEGE_CTG SRIOV_CTG_LINK 10760 10760 + 10761 10761 + /* MC_CMD_SET_NETPORT_EVENTS_MASK_IN msgrequest: Enable or disable delivery of 10762 10762 + * specified network port events for a given port identified by PORT_HANDLE. At 10763 10763 + * start of day, or after any control interface reset (FLR, ENTITY_RESET, 10764 10764 + * etc.), all event delivery is disabled for all ports associated with the 10765 10765 + * control interface. 10766 10766 + */ 10767 10767 + #define MC_CMD_SET_NETPORT_EVENTS_MASK_IN_LEN 8 10768 10768 + /* Handle to port to set event delivery mask. */ 10769 10769 + #define MC_CMD_SET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_OFST 0 10770 10770 + #define MC_CMD_SET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_LEN 4 10771 10771 + /* Bitmask of events to enable. Event delivery is enabled when corresponding 10772 10772 + * bit is 1, disabled when 0. 10773 10773 + */ 10774 10774 + #define MC_CMD_SET_NETPORT_EVENTS_MASK_IN_EVENT_MASK_OFST 4 10775 10775 + #define MC_CMD_SET_NETPORT_EVENTS_MASK_IN_EVENT_MASK_LEN 4 10776 10776 + /* enum property: bitshift */ 10777 10777 + /* Enum values, see field(s): */ 10778 10778 + /* EVENT_MASK/TYPE */ 10779 10779 + 10780 10780 + /* MC_CMD_SET_NETPORT_EVENTS_MASK_OUT msgresponse */ 10781 10781 + #define MC_CMD_SET_NETPORT_EVENTS_MASK_OUT_LEN 0 10782 10782 + 10783 10783 + 10784 10784 + /***********************************/ 10785 10785 + /* MC_CMD_GET_NETPORT_EVENTS_MASK 10786 10786 + */ 10787 10787 + #define MC_CMD_GET_NETPORT_EVENTS_MASK 0x1ea 10788 10788 + #undef MC_CMD_0x1ea_PRIVILEGE_CTG 10789 10789 + 10790 10790 + #define MC_CMD_0x1ea_PRIVILEGE_CTG SRIOV_CTG_LINK 10791 10791 + 10792 10792 + /* MC_CMD_GET_NETPORT_EVENTS_MASK_IN msgrequest: Get event delivery mask a 10793 10793 + * given port identified by PORT_HANDLE. 10794 10794 + */ 10795 10795 + #define MC_CMD_GET_NETPORT_EVENTS_MASK_IN_LEN 4 10796 10796 + /* Handle to port to get event deliver mask for. */ 10797 10797 + #define MC_CMD_GET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_OFST 0 10798 10798 + #define MC_CMD_GET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_LEN 4 10799 10799 + 10800 10800 + /* MC_CMD_GET_NETPORT_EVENTS_MASK_OUT msgresponse */ 10801 10801 + #define MC_CMD_GET_NETPORT_EVENTS_MASK_OUT_LEN 4 10802 10802 + /* Bitmask of events enabled. Event delivery is enabled when corresponding bit 10803 10803 + * is 1, disabled when 0. 10804 10804 + */ 10805 10805 + #define MC_CMD_GET_NETPORT_EVENTS_MASK_OUT_EVENT_MASK_OFST 0 10806 10806 + #define MC_CMD_GET_NETPORT_EVENTS_MASK_OUT_EVENT_MASK_LEN 4 10807 10807 + /* enum property: bitshift */ 10808 10808 + /* Enum values, see field(s): */ 10809 10809 + /* EVENT_MASK/TYPE */ 10810 10810 + 10811 10811 + 10812 10812 + /***********************************/ 10813 10813 + /* MC_CMD_GET_SUPPORTED_NETPORT_EVENTS 10814 10814 + */ 10815 10815 + #define MC_CMD_GET_SUPPORTED_NETPORT_EVENTS 0x1eb 10816 10816 + #undef MC_CMD_0x1eb_PRIVILEGE_CTG 10817 10817 + 10818 10818 + #define MC_CMD_0x1eb_PRIVILEGE_CTG SRIOV_CTG_LINK 10819 10819 + 10820 10820 + /* MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_IN msgrequest: Get network port events 10821 10821 + * supported by the platform. Information returned is fixed for a given NIC 10822 10822 + * platform. 10823 10823 + */ 10824 10824 + #define MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_IN_LEN 0 10825 10825 + 10826 10826 + /* MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT msgresponse */ 10827 10827 + #define MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT_LEN 4 10828 10828 + /* Bitmask of events enabled. Event delivery is enabled when corresponding bit 10829 10829 + * is 1, disabled when 0. 10830 10830 + */ 10831 10831 + #define MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT_EVENT_MASK_OFST 0 10832 10832 + #define MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT_EVENT_MASK_LEN 4 10833 10833 + /* enum property: bitshift */ 10834 10834 + /* Enum values, see field(s): */ 10835 10835 + /* EVENT_MASK/TYPE */ 10836 10836 + 10837 10837 + 10838 10838 + /***********************************/ 10839 10839 + /* MC_CMD_GET_NETPORT_STATISTICS 10840 10840 + * Get generic MAC statistics. This call retrieves unified statistics managed 10841 10841 + * by the MC. The MC will populate and provide all supported statistics in the 10842 10842 + * format as returned by MC_CMD_MAC_STATISTICS_DESCRIPTOR. Refer to the 10843 10843 + * aforementioned command for the format and contents of the stats DMA buffer. 10844 10844 + * To ensure consistent and accurate results, it is essential for the driver to 10845 10845 + * initialize the DMA buffer with zeros when DMA mode is used. Returns: 0 on 10846 10846 + * success, ETIME if the DMA buffer is not ready, ENOENT on non-existent port 10847 10847 + * handle, and EINVAL on invalid parameters (DMA buffer too small) 10848 10848 + */ 10849 10849 + #define MC_CMD_GET_NETPORT_STATISTICS 0x1fa 10850 10850 + #undef MC_CMD_0x1fa_PRIVILEGE_CTG 10851 10851 + 10852 10852 + #define MC_CMD_0x1fa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10853 10853 + 10854 10854 + /* MC_CMD_GET_NETPORT_STATISTICS_IN msgrequest */ 10855 10855 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_LEN 20 10856 10856 + /* Handle of port to get MAC statistics for. */ 10857 10857 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_PORT_HANDLE_OFST 0 10858 10858 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_PORT_HANDLE_LEN 4 10859 10859 + /* Contains options for querying the MAC statistics. */ 10860 10860 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_CMD_OFST 4 10861 10861 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_CMD_LEN 4 10862 10862 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_OFST 4 10863 10863 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_LBN 0 10864 10864 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_WIDTH 1 10865 10865 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_CLEAR_OFST 4 10866 10866 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_CLEAR_LBN 1 10867 10867 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_CLEAR_WIDTH 1 10868 10868 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_CHANGE_OFST 4 10869 10869 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_CHANGE_LBN 2 10870 10870 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_CHANGE_WIDTH 1 10871 10871 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_ENABLE_OFST 4 10872 10872 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_ENABLE_LBN 3 10873 10873 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_ENABLE_WIDTH 1 10874 10874 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_NOEVENT_OFST 4 10875 10875 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_NOEVENT_LBN 4 10876 10876 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_NOEVENT_WIDTH 1 10877 10877 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIOD_MS_OFST 4 10878 10878 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIOD_MS_LBN 15 10879 10879 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIOD_MS_WIDTH 17 10880 10880 + /* Specifies the physical address of the DMA buffer to use for statistics 10881 10881 + * transfer. This field must contain a valid address under either of these 10882 10882 + * conditions: 1. DMA flag is set (immediate DMA requested) 2. Both 10883 10883 + * PERIODIC_CHANGE and PERIODIC_ENABLE are set (periodic DMA configured) 10884 10884 + */ 10885 10885 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_OFST 8 10886 10886 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LEN 8 10887 10887 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO_OFST 8 10888 10888 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO_LEN 4 10889 10889 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO_LBN 64 10890 10890 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO_WIDTH 32 10891 10891 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI_OFST 12 10892 10892 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI_LEN 4 10893 10893 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI_LBN 96 10894 10894 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI_WIDTH 32 10895 10895 + /* Specifies the length of the DMA buffer in bytes for statistics transfer. The 10896 10896 + * buffer size must be at least DMA_BUFFER_SIZE bytes (as returned by 10897 10897 + * MC_CMD_MAC_STATISTICS_DESCRIPTOR). Providing an insufficient buffer size 10898 10898 + * will result in an EINVAL error. This field must contain a valid length under 10899 10899 + * either of these conditions: 1. DMA flag is set (immediate DMA requested) 2. 10900 10900 + * Both PERIODIC_CHANGE and PERIODIC_ENABLE are set (periodic DMA configured) 10901 10901 + */ 10902 10902 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_LEN_OFST 16 10903 10903 + #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_LEN_LEN 4 10904 10904 + 10905 10905 + /* MC_CMD_GET_NETPORT_STATISTICS_OUT msgresponse */ 10906 10906 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMIN 0 10907 10907 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMAX 248 10908 10908 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMAX_MCDI2 1016 10909 10909 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_LEN(num) (0+8*(num)) 10910 10910 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_NUM(len) (((len)-0)/8) 10911 10911 + /* Statistics buffer. Zero-length if DMA mode is used. The statistics buffer is 10912 10912 + * an array of 8-byte counter values, containing the generation start marker, 10913 10913 + * stats counters, and generation end marker. The index of each counter in the 10914 10914 + * array is reported by the MAC_STATISTICS_DESCRIPTOR command. The same layout 10915 10915 + * is used for the DMA buffer for DMA mode stats. 10916 10916 + */ 10917 10917 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_OFST 0 10918 10918 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LEN 8 10919 10919 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_OFST 0 10920 10920 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_LEN 4 10921 10921 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_LBN 0 10922 10922 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_WIDTH 32 10923 10923 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_OFST 4 10924 10924 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_LEN 4 10925 10925 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_LBN 32 10926 10926 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_WIDTH 32 10927 10927 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_MINNUM 0 10928 10928 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_MAXNUM 31 10929 10929 + #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_MAXNUM_MCDI2 127 9315 10930 9316 10931 /* EVB_PORT_ID structuredef */ 9317 10932 #define EVB_PORT_ID_LEN 4 ··· 10572 9705 #define EVB_PORT_ID_MAC3 0x2000003 10573 9706 #define EVB_PORT_ID_PORT_ID_LBN 0 10574 9707 #define EVB_PORT_ID_PORT_ID_WIDTH 32 10575 10575 - 10576 10576 - /* EVB_VLAN_TAG structuredef */ 10577 10577 - #define EVB_VLAN_TAG_LEN 2 10578 10578 - /* The VLAN tag value */ 10579 10579 - #define EVB_VLAN_TAG_VLAN_ID_LBN 0 10580 10580 - #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 10581 10581 - #define EVB_VLAN_TAG_MODE_LBN 12 10582 10582 - #define EVB_VLAN_TAG_MODE_WIDTH 4 10583 10583 - /* enum: Insert the VLAN. */ 10584 10584 - #define EVB_VLAN_TAG_INSERT 0x0 10585 10585 - /* enum: Replace the VLAN if already present. */ 10586 10586 - #define EVB_VLAN_TAG_REPLACE 0x1 10587 10587 - 10588 10588 - /* BUFTBL_ENTRY structuredef */ 10589 10589 - #define BUFTBL_ENTRY_LEN 12 10590 10590 - /* the owner ID */ 10591 10591 - #define BUFTBL_ENTRY_OID_OFST 0 10592 10592 - #define BUFTBL_ENTRY_OID_LEN 2 10593 10593 - #define BUFTBL_ENTRY_OID_LBN 0 10594 10594 - #define BUFTBL_ENTRY_OID_WIDTH 16 10595 10595 - /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ 10596 10596 - #define BUFTBL_ENTRY_PGSZ_OFST 2 10597 10597 - #define BUFTBL_ENTRY_PGSZ_LEN 2 10598 10598 - #define BUFTBL_ENTRY_PGSZ_LBN 16 10599 10599 - #define BUFTBL_ENTRY_PGSZ_WIDTH 16 10600 10600 - /* the raw 64-bit address field from the SMC, not adjusted for page size */ 10601 10601 - #define BUFTBL_ENTRY_RAWADDR_OFST 4 10602 10602 - #define BUFTBL_ENTRY_RAWADDR_LEN 8 10603 10603 - #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 10604 10604 - #define BUFTBL_ENTRY_RAWADDR_LO_LEN 4 10605 10605 - #define BUFTBL_ENTRY_RAWADDR_LO_LBN 32 10606 10606 - #define BUFTBL_ENTRY_RAWADDR_LO_WIDTH 32 10607 10607 - #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 10608 10608 - #define BUFTBL_ENTRY_RAWADDR_HI_LEN 4 10609 10609 - #define BUFTBL_ENTRY_RAWADDR_HI_LBN 64 10610 10610 - #define BUFTBL_ENTRY_RAWADDR_HI_WIDTH 32 10611 10611 - #define BUFTBL_ENTRY_RAWADDR_LBN 32 10612 10612 - #define BUFTBL_ENTRY_RAWADDR_WIDTH 64 10613 9708 10614 9709 /* NVRAM_PARTITION_TYPE structuredef */ 10615 9710 #define NVRAM_PARTITION_TYPE_LEN 2 ··· 10616 9787 #define NVRAM_PARTITION_TYPE_NMC_LOG 0x700 10617 9788 /* enum: Non-volatile log output of second core on dual-core device */ 10618 9789 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701 9790 9790 + /* enum: RAM (volatile) log output partition */ 9791 9791 + #define NVRAM_PARTITION_TYPE_RAM_LOG 0x702 10619 9792 /* enum: Device state dump output partition */ 10620 9793 #define NVRAM_PARTITION_TYPE_DUMP 0x800 10621 9794 /* enum: Crash log partition for NMC firmware */ ··· 10754 9923 #define NVRAM_PARTITION_TYPE_SUC_SOC_CONFIG 0x1f07 10755 9924 /* enum: System-on-Chip update information. */ 10756 9925 #define NVRAM_PARTITION_TYPE_SOC_UPDATE 0x2003 9926 9926 + /* enum: Virtual partition. Write-only. Writes will actually be sent to an 9927 9927 + * appropriate partition (for instance BUNDLE if the data starts with the magic 9928 9928 + * number for a bundle update), or discarded with an error if not recognised as 9929 9929 + * a supported type. 9930 9930 + */ 9931 9931 + #define NVRAM_PARTITION_TYPE_AUTO 0x2100 9932 9932 + /* enum: MC/NMC (first stage) bootloader firmware. (For X4, see XN-202072-PS 9933 9933 + * and XN-202084-SW section 3.1). 9934 9934 + */ 9935 9935 + #define NVRAM_PARTITION_TYPE_BOOTLOADER 0x2200 10757 9936 /* enum: Start of reserved value range (firmware may use for any purpose) */ 10758 9937 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 10759 9938 /* enum: End of reserved value range (firmware may use for any purpose) */ ··· 10821 9980 #define LICENSED_APP_ID_SCATRD 0x8000 10822 9981 #define LICENSED_APP_ID_ID_LBN 0 10823 9982 #define LICENSED_APP_ID_ID_WIDTH 32 10824 10824 - 10825 10825 - /* LICENSED_FEATURES structuredef */ 10826 10826 - #define LICENSED_FEATURES_LEN 8 10827 10827 - /* Bitmask of licensed firmware features */ 10828 10828 - #define LICENSED_FEATURES_MASK_OFST 0 10829 10829 - #define LICENSED_FEATURES_MASK_LEN 8 10830 10830 - #define LICENSED_FEATURES_MASK_LO_OFST 0 10831 10831 - #define LICENSED_FEATURES_MASK_LO_LEN 4 10832 10832 - #define LICENSED_FEATURES_MASK_LO_LBN 0 10833 10833 - #define LICENSED_FEATURES_MASK_LO_WIDTH 32 10834 10834 - #define LICENSED_FEATURES_MASK_HI_OFST 4 10835 10835 - #define LICENSED_FEATURES_MASK_HI_LEN 4 10836 10836 - #define LICENSED_FEATURES_MASK_HI_LBN 32 10837 10837 - #define LICENSED_FEATURES_MASK_HI_WIDTH 32 10838 10838 - #define LICENSED_FEATURES_RX_CUT_THROUGH_OFST 0 10839 10839 - #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0 10840 10840 - #define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1 10841 10841 - #define LICENSED_FEATURES_PIO_OFST 0 10842 10842 - #define LICENSED_FEATURES_PIO_LBN 1 10843 10843 - #define LICENSED_FEATURES_PIO_WIDTH 1 10844 10844 - #define LICENSED_FEATURES_EVQ_TIMER_OFST 0 10845 10845 - #define LICENSED_FEATURES_EVQ_TIMER_LBN 2 10846 10846 - #define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1 10847 10847 - #define LICENSED_FEATURES_CLOCK_OFST 0 10848 10848 - #define LICENSED_FEATURES_CLOCK_LBN 3 10849 10849 - #define LICENSED_FEATURES_CLOCK_WIDTH 1 10850 10850 - #define LICENSED_FEATURES_RX_TIMESTAMPS_OFST 0 10851 10851 - #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4 10852 10852 - #define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1 10853 10853 - #define LICENSED_FEATURES_TX_TIMESTAMPS_OFST 0 10854 10854 - #define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5 10855 10855 - #define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1 10856 10856 - #define LICENSED_FEATURES_RX_SNIFF_OFST 0 10857 10857 - #define LICENSED_FEATURES_RX_SNIFF_LBN 6 10858 10858 - #define LICENSED_FEATURES_RX_SNIFF_WIDTH 1 10859 10859 - #define LICENSED_FEATURES_TX_SNIFF_OFST 0 10860 10860 - #define LICENSED_FEATURES_TX_SNIFF_LBN 7 10861 10861 - #define LICENSED_FEATURES_TX_SNIFF_WIDTH 1 10862 10862 - #define LICENSED_FEATURES_PROXY_FILTER_OPS_OFST 0 10863 10863 - #define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8 10864 10864 - #define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1 10865 10865 - #define LICENSED_FEATURES_EVENT_CUT_THROUGH_OFST 0 10866 10866 - #define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9 10867 10867 - #define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 10868 10868 - #define LICENSED_FEATURES_MASK_LBN 0 10869 10869 - #define LICENSED_FEATURES_MASK_WIDTH 64 10870 10870 - 10871 10871 - /* LICENSED_V3_APPS structuredef */ 10872 10872 - #define LICENSED_V3_APPS_LEN 8 10873 10873 - /* Bitmask of licensed applications */ 10874 10874 - #define LICENSED_V3_APPS_MASK_OFST 0 10875 10875 - #define LICENSED_V3_APPS_MASK_LEN 8 10876 10876 - #define LICENSED_V3_APPS_MASK_LO_OFST 0 10877 10877 - #define LICENSED_V3_APPS_MASK_LO_LEN 4 10878 10878 - #define LICENSED_V3_APPS_MASK_LO_LBN 0 10879 10879 - #define LICENSED_V3_APPS_MASK_LO_WIDTH 32 10880 10880 - #define LICENSED_V3_APPS_MASK_HI_OFST 4 10881 10881 - #define LICENSED_V3_APPS_MASK_HI_LEN 4 10882 10882 - #define LICENSED_V3_APPS_MASK_HI_LBN 32 10883 10883 - #define LICENSED_V3_APPS_MASK_HI_WIDTH 32 10884 10884 - #define LICENSED_V3_APPS_ONLOAD_OFST 0 10885 10885 - #define LICENSED_V3_APPS_ONLOAD_LBN 0 10886 10886 - #define LICENSED_V3_APPS_ONLOAD_WIDTH 1 10887 10887 - #define LICENSED_V3_APPS_PTP_OFST 0 10888 10888 - #define LICENSED_V3_APPS_PTP_LBN 1 10889 10889 - #define LICENSED_V3_APPS_PTP_WIDTH 1 10890 10890 - #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_OFST 0 10891 10891 - #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2 10892 10892 - #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1 10893 10893 - #define LICENSED_V3_APPS_SOLARSECURE_OFST 0 10894 10894 - #define LICENSED_V3_APPS_SOLARSECURE_LBN 3 10895 10895 - #define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1 10896 10896 - #define LICENSED_V3_APPS_PERF_MONITOR_OFST 0 10897 10897 - #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4 10898 10898 - #define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1 10899 10899 - #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_OFST 0 10900 10900 - #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5 10901 10901 - #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1 10902 10902 - #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_OFST 0 10903 10903 - #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6 10904 10904 - #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1 10905 10905 - #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_OFST 0 10906 10906 - #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7 10907 10907 - #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1 10908 10908 - #define LICENSED_V3_APPS_TCP_DIRECT_OFST 0 10909 10909 - #define LICENSED_V3_APPS_TCP_DIRECT_LBN 8 10910 10910 - #define LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1 10911 10911 - #define LICENSED_V3_APPS_LOW_LATENCY_OFST 0 10912 10912 - #define LICENSED_V3_APPS_LOW_LATENCY_LBN 9 10913 10913 - #define LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1 10914 10914 - #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_OFST 0 10915 10915 - #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10 10916 10916 - #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1 10917 10917 - #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_OFST 0 10918 10918 - #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11 10919 10919 - #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1 10920 10920 - #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_OFST 0 10921 10921 - #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12 10922 10922 - #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1 10923 10923 - #define LICENSED_V3_APPS_SCALEOUT_ONLOAD_OFST 0 10924 10924 - #define LICENSED_V3_APPS_SCALEOUT_ONLOAD_LBN 13 10925 10925 - #define LICENSED_V3_APPS_SCALEOUT_ONLOAD_WIDTH 1 10926 10926 - #define LICENSED_V3_APPS_DSHBRD_OFST 0 10927 10927 - #define LICENSED_V3_APPS_DSHBRD_LBN 14 10928 10928 - #define LICENSED_V3_APPS_DSHBRD_WIDTH 1 10929 10929 - #define LICENSED_V3_APPS_SCATRD_OFST 0 10930 10930 - #define LICENSED_V3_APPS_SCATRD_LBN 15 10931 10931 - #define LICENSED_V3_APPS_SCATRD_WIDTH 1 10932 10932 - #define LICENSED_V3_APPS_MASK_LBN 0 10933 10933 - #define LICENSED_V3_APPS_MASK_WIDTH 64 10934 9983 10935 9984 /* LICENSED_V3_FEATURES structuredef */ 10936 9985 #define LICENSED_V3_FEATURES_LEN 8 ··· 10929 10198 #define RSS_MODE_HASH_DST_PORT_WIDTH 1 10930 10199 #define RSS_MODE_HASH_SELECTOR_LBN 0 10931 10200 #define RSS_MODE_HASH_SELECTOR_WIDTH 8 10932 10932 - 10933 10933 - /* CTPIO_STATS_MAP structuredef */ 10934 10934 - #define CTPIO_STATS_MAP_LEN 4 10935 10935 - /* The (function relative) VI number */ 10936 10936 - #define CTPIO_STATS_MAP_VI_OFST 0 10937 10937 - #define CTPIO_STATS_MAP_VI_LEN 2 10938 10938 - #define CTPIO_STATS_MAP_VI_LBN 0 10939 10939 - #define CTPIO_STATS_MAP_VI_WIDTH 16 10940 10940 - /* The target bucket for the VI */ 10941 10941 - #define CTPIO_STATS_MAP_BUCKET_OFST 2 10942 10942 - #define CTPIO_STATS_MAP_BUCKET_LEN 2 10943 10943 - #define CTPIO_STATS_MAP_BUCKET_LBN 16 10944 10944 - #define CTPIO_STATS_MAP_BUCKET_WIDTH 16 10945 10945 - 10946 10946 - 10947 10947 - /***********************************/ 10948 10948 - /* MC_CMD_READ_REGS 10949 10949 - * Get a dump of the MCPU registers 10950 10950 - */ 10951 10951 - #define MC_CMD_READ_REGS 0x50 10952 10952 - #undef MC_CMD_0x50_PRIVILEGE_CTG 10953 10953 - 10954 10954 - #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE 10955 10955 - 10956 10956 - /* MC_CMD_READ_REGS_IN msgrequest */ 10957 10957 - #define MC_CMD_READ_REGS_IN_LEN 0 10958 10958 - 10959 10959 - /* MC_CMD_READ_REGS_OUT msgresponse */ 10960 10960 - #define MC_CMD_READ_REGS_OUT_LEN 308 10961 10961 - /* Whether the corresponding register entry contains a valid value */ 10962 10962 - #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 10963 10963 - #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 10964 10964 - /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, 10965 10965 - * fir, fp) 10966 10966 - */ 10967 10967 - #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 10968 10968 - #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 10969 10969 - #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 10970 10201 10971 10202 10972 10203 /***********************************/ ··· 11333 10640 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3 11334 10641 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1 11335 10642 11336 11336 - /* QUEUE_CRC_MODE structuredef */ 11337 11337 - #define QUEUE_CRC_MODE_LEN 1 11338 11338 - #define QUEUE_CRC_MODE_MODE_LBN 0 11339 11339 - #define QUEUE_CRC_MODE_MODE_WIDTH 4 11340 11340 - /* enum: No CRC. */ 11341 11341 - #define QUEUE_CRC_MODE_NONE 0x0 11342 11342 - /* enum: CRC Fiber channel over ethernet. */ 11343 11343 - #define QUEUE_CRC_MODE_FCOE 0x1 11344 11344 - /* enum: CRC (digest) iSCSI header only. */ 11345 11345 - #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 11346 11346 - /* enum: CRC (digest) iSCSI header and payload. */ 11347 11347 - #define QUEUE_CRC_MODE_ISCSI 0x3 11348 11348 - /* enum: CRC Fiber channel over IP over ethernet. */ 11349 11349 - #define QUEUE_CRC_MODE_FCOIPOE 0x4 11350 11350 - /* enum: CRC MPA. */ 11351 11351 - #define QUEUE_CRC_MODE_MPA 0x5 11352 11352 - #define QUEUE_CRC_MODE_SPARE_LBN 4 11353 11353 - #define QUEUE_CRC_MODE_SPARE_WIDTH 4 11354 11354 - 11355 10643 11356 10644 /***********************************/ 11357 10645 /* MC_CMD_INIT_RXQ ··· 11501 10827 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_OFST 16 11502 10828 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_LBN 20 11503 10829 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_WIDTH 1 10830 10830 + #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SUPPRESS_RX_EVENTS_OFST 16 10831 10831 + #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SUPPRESS_RX_EVENTS_LBN 21 10832 10832 + #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SUPPRESS_RX_EVENTS_WIDTH 1 11504 10833 /* Owner ID to use if in buffer mode (zero if physical) */ 11505 10834 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 11506 10835 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4 ··· 11610 10933 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_OFST 16 11611 10934 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_LBN 20 11612 10935 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_WIDTH 1 10936 10936 + #define MC_CMD_INIT_RXQ_V3_IN_FLAG_SUPPRESS_RX_EVENTS_OFST 16 10937 10937 + #define MC_CMD_INIT_RXQ_V3_IN_FLAG_SUPPRESS_RX_EVENTS_LBN 21 10938 10938 + #define MC_CMD_INIT_RXQ_V3_IN_FLAG_SUPPRESS_RX_EVENTS_WIDTH 1 11613 10939 /* Owner ID to use if in buffer mode (zero if physical) */ 11614 10940 #define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_OFST 20 11615 10941 #define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4 ··· 11748 11068 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_OFST 16 11749 11069 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_LBN 20 11750 11070 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_WIDTH 1 11071 11071 + #define MC_CMD_INIT_RXQ_V4_IN_FLAG_SUPPRESS_RX_EVENTS_OFST 16 11072 11072 + #define MC_CMD_INIT_RXQ_V4_IN_FLAG_SUPPRESS_RX_EVENTS_LBN 21 11073 11073 + #define MC_CMD_INIT_RXQ_V4_IN_FLAG_SUPPRESS_RX_EVENTS_WIDTH 1 11751 11074 /* Owner ID to use if in buffer mode (zero if physical) */ 11752 11075 #define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_OFST 20 11753 11076 #define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_LEN 4 ··· 11899 11216 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_OFST 16 11900 11217 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_LBN 20 11901 11218 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_WIDTH 1 11219 11219 + #define MC_CMD_INIT_RXQ_V5_IN_FLAG_SUPPRESS_RX_EVENTS_OFST 16 11220 11220 + #define MC_CMD_INIT_RXQ_V5_IN_FLAG_SUPPRESS_RX_EVENTS_LBN 21 11221 11221 + #define MC_CMD_INIT_RXQ_V5_IN_FLAG_SUPPRESS_RX_EVENTS_WIDTH 1 11902 11222 /* Owner ID to use if in buffer mode (zero if physical) */ 11903 11223 #define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_OFST 20 11904 11224 #define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_LEN 4 ··· 12295 11609 12296 11610 /* MC_CMD_PROXY_CMD_OUT msgresponse */ 12297 11611 #define MC_CMD_PROXY_CMD_OUT_LEN 0 12298 12298 - 12299 12299 - /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to 12300 12300 - * manage proxied requests 12301 12301 - */ 12302 12302 - #define MC_PROXY_STATUS_BUFFER_LEN 16 12303 12303 - /* Handle allocated by the firmware for this proxy transaction */ 12304 12304 - #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0 12305 12305 - #define MC_PROXY_STATUS_BUFFER_HANDLE_LEN 4 12306 12306 - /* enum: An invalid handle. */ 12307 12307 - #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0 12308 12308 - #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0 12309 12309 - #define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32 12310 12310 - /* The requesting physical function number */ 12311 12311 - #define MC_PROXY_STATUS_BUFFER_PF_OFST 4 12312 12312 - #define MC_PROXY_STATUS_BUFFER_PF_LEN 2 12313 12313 - #define MC_PROXY_STATUS_BUFFER_PF_LBN 32 12314 12314 - #define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16 12315 12315 - /* The requesting virtual function number. Set to VF_NULL if the target is a 12316 12316 - * PF. 12317 12317 - */ 12318 12318 - #define MC_PROXY_STATUS_BUFFER_VF_OFST 6 12319 12319 - #define MC_PROXY_STATUS_BUFFER_VF_LEN 2 12320 12320 - #define MC_PROXY_STATUS_BUFFER_VF_LBN 48 12321 12321 - #define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16 12322 12322 - /* The target function RID. */ 12323 12323 - #define MC_PROXY_STATUS_BUFFER_RID_OFST 8 12324 12324 - #define MC_PROXY_STATUS_BUFFER_RID_LEN 2 12325 12325 - #define MC_PROXY_STATUS_BUFFER_RID_LBN 64 12326 12326 - #define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16 12327 12327 - /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */ 12328 12328 - #define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10 12329 12329 - #define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2 12330 12330 - #define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80 12331 12331 - #define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16 12332 12332 - /* If a request is authorized rather than carried out by the host, this is the 12333 12333 - * elevated privilege mask granted to the requesting function. 12334 12334 - */ 12335 12335 - #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12 12336 12336 - #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LEN 4 12337 12337 - #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96 12338 12338 - #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32 12339 12339 - 12340 12340 - 12341 12341 - /***********************************/ 12342 12342 - /* MC_CMD_PROXY_CONFIGURE 12343 12343 - * Enable/disable authorization of MCDI requests from unprivileged functions by 12344 12344 - * a designated admin function 12345 12345 - */ 12346 12346 - #define MC_CMD_PROXY_CONFIGURE 0x58 12347 12347 - #undef MC_CMD_0x58_PRIVILEGE_CTG 12348 12348 - 12349 12349 - #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12350 12350 - 12351 12351 - /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */ 12352 12352 - #define MC_CMD_PROXY_CONFIGURE_IN_LEN 108 12353 12353 - #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0 12354 12354 - #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_LEN 4 12355 12355 - #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_OFST 0 12356 12356 - #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0 12357 12357 - #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1 12358 12358 - /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 12359 12359 - * of blocks, each of the size REQUEST_BLOCK_SIZE. 12360 12360 - */ 12361 12361 - #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4 12362 12362 - #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8 12363 12363 - #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4 12364 12364 - #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_LEN 4 12365 12365 - #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_LBN 32 12366 12366 - #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_WIDTH 32 12367 12367 - #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8 12368 12368 - #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_LEN 4 12369 12369 - #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_LBN 64 12370 12370 - #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_WIDTH 32 12371 12371 - /* Must be a power of 2 */ 12372 12372 - #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12 12373 12373 - #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4 12374 12374 - /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 12375 12375 - * of blocks, each of the size REPLY_BLOCK_SIZE. 12376 12376 - */ 12377 12377 - #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16 12378 12378 - #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8 12379 12379 - #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16 12380 12380 - #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_LEN 4 12381 12381 - #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_LBN 128 12382 12382 - #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_WIDTH 32 12383 12383 - #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20 12384 12384 - #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_LEN 4 12385 12385 - #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_LBN 160 12386 12386 - #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_WIDTH 32 12387 12387 - /* Must be a power of 2 */ 12388 12388 - #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24 12389 12389 - #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4 12390 12390 - /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 12391 12391 - * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 12392 12392 - * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 12393 12393 - */ 12394 12394 - #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28 12395 12395 - #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8 12396 12396 - #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28 12397 12397 - #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_LEN 4 12398 12398 - #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_LBN 224 12399 12399 - #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_WIDTH 32 12400 12400 - #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32 12401 12401 - #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_LEN 4 12402 12402 - #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_LBN 256 12403 12403 - #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_WIDTH 32 12404 12404 - /* Must be a power of 2, or zero if this buffer is not provided */ 12405 12405 - #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36 12406 12406 - #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4 12407 12407 - /* Applies to all three buffers */ 12408 12408 - #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40 12409 12409 - #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_LEN 4 12410 12410 - /* A bit mask defining which MCDI operations may be proxied */ 12411 12411 - #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44 12412 12412 - #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64 12413 12413 - 12414 12414 - /* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */ 12415 12415 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112 12416 12416 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0 12417 12417 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_LEN 4 12418 12418 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_OFST 0 12419 12419 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0 12420 12420 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1 12421 12421 - /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 12422 12422 - * of blocks, each of the size REQUEST_BLOCK_SIZE. 12423 12423 - */ 12424 12424 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4 12425 12425 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8 12426 12426 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4 12427 12427 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_LEN 4 12428 12428 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_LBN 32 12429 12429 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_WIDTH 32 12430 12430 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8 12431 12431 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_LEN 4 12432 12432 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_LBN 64 12433 12433 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_WIDTH 32 12434 12434 - /* Must be a power of 2 */ 12435 12435 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12 12436 12436 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4 12437 12437 - /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 12438 12438 - * of blocks, each of the size REPLY_BLOCK_SIZE. 12439 12439 - */ 12440 12440 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16 12441 12441 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8 12442 12442 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16 12443 12443 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_LEN 4 12444 12444 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_LBN 128 12445 12445 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_WIDTH 32 12446 12446 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20 12447 12447 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_LEN 4 12448 12448 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_LBN 160 12449 12449 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_WIDTH 32 12450 12450 - /* Must be a power of 2 */ 12451 12451 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24 12452 12452 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4 12453 12453 - /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 12454 12454 - * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 12455 12455 - * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 12456 12456 - */ 12457 12457 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28 12458 12458 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8 12459 12459 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28 12460 12460 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_LEN 4 12461 12461 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_LBN 224 12462 12462 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_WIDTH 32 12463 12463 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32 12464 12464 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_LEN 4 12465 12465 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_LBN 256 12466 12466 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_WIDTH 32 12467 12467 - /* Must be a power of 2, or zero if this buffer is not provided */ 12468 12468 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36 12469 12469 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4 12470 12470 - /* Applies to all three buffers */ 12471 12471 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40 12472 12472 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_LEN 4 12473 12473 - /* A bit mask defining which MCDI operations may be proxied */ 12474 12474 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44 12475 12475 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64 12476 12476 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108 12477 12477 - #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_LEN 4 12478 12478 - 12479 12479 - /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ 12480 12480 - #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 12481 12481 - 12482 12482 - 12483 12483 - /***********************************/ 12484 12484 - /* MC_CMD_PROXY_COMPLETE 12485 12485 - * Tells FW that a requested proxy operation has either been completed (by 12486 12486 - * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the 12487 12487 - * function that enabled proxying/authorization (by using 12488 12488 - * MC_CMD_PROXY_CONFIGURE). 12489 12489 - */ 12490 12490 - #define MC_CMD_PROXY_COMPLETE 0x5f 12491 12491 - #undef MC_CMD_0x5f_PRIVILEGE_CTG 12492 12492 - 12493 12493 - #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12494 12494 - 12495 12495 - /* MC_CMD_PROXY_COMPLETE_IN msgrequest */ 12496 12496 - #define MC_CMD_PROXY_COMPLETE_IN_LEN 12 12497 12497 - #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0 12498 12498 - #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_LEN 4 12499 12499 - #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4 12500 12500 - #define MC_CMD_PROXY_COMPLETE_IN_STATUS_LEN 4 12501 12501 - /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply 12502 12502 - * is stored in the REPLY_BUFF. 12503 12503 - */ 12504 12504 - #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0 12505 12505 - /* enum: The operation has been authorized. The originating function may now 12506 12506 - * try again. 12507 12507 - */ 12508 12508 - #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1 12509 12509 - /* enum: The operation has been declined. */ 12510 12510 - #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2 12511 12511 - /* enum: The authorization failed because the relevant application did not 12512 12512 - * respond in time. 12513 12513 - */ 12514 12514 - #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3 12515 12515 - #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8 12516 12516 - #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_LEN 4 12517 12517 - 12518 12518 - /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */ 12519 12519 - #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0 12520 12520 - 12521 12521 - 12522 12522 - /***********************************/ 12523 12523 - /* MC_CMD_ALLOC_BUFTBL_CHUNK 12524 12524 - * Allocate a set of buffer table entries using the specified owner ID. This 12525 12525 - * operation allocates the required buffer table entries (and fails if it 12526 12526 - * cannot do so). The buffer table entries will initially be zeroed. 12527 12527 - */ 12528 12528 - #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 12529 12529 - #undef MC_CMD_0x87_PRIVILEGE_CTG 12530 12530 - 12531 12531 - #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 12532 12532 - 12533 12533 - /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ 12534 12534 - #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 12535 12535 - /* Owner ID to use */ 12536 12536 - #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 12537 12537 - #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 4 12538 12538 - /* Size of buffer table pages to use, in bytes (note that only a few values are 12539 12539 - * legal on any specific hardware). 12540 12540 - */ 12541 12541 - #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 12542 12542 - #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 4 12543 12543 - 12544 12544 - /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ 12545 12545 - #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 12546 12546 - #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 12547 12547 - #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 4 12548 12548 - #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 12549 12549 - #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 4 12550 12550 - /* Buffer table IDs for use in DMA descriptors. */ 12551 12551 - #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 12552 12552 - #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 4 12553 12553 - 12554 12554 - 12555 12555 - /***********************************/ 12556 12556 - /* MC_CMD_PROGRAM_BUFTBL_ENTRIES 12557 12557 - * Reprogram a set of buffer table entries in the specified chunk. 12558 12558 - */ 12559 12559 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 12560 12560 - #undef MC_CMD_0x88_PRIVILEGE_CTG 12561 12561 - 12562 12562 - #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 12563 12563 - 12564 12564 - /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ 12565 12565 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 12566 12566 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 12567 12567 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX_MCDI2 268 12568 12568 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) 12569 12569 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_NUM(len) (((len)-12)/8) 12570 12570 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 12571 12571 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4 12572 12572 - /* ID */ 12573 12573 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 12574 12574 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4 12575 12575 - /* Num entries */ 12576 12576 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 12577 12577 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4 12578 12578 - /* Buffer table entry address */ 12579 12579 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 12580 12580 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 12581 12581 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 12582 12582 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_LEN 4 12583 12583 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_LBN 96 12584 12584 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_WIDTH 32 12585 12585 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 12586 12586 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_LEN 4 12587 12587 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_LBN 128 12588 12588 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_WIDTH 32 12589 12589 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 12590 12590 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 12591 12591 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM_MCDI2 32 12592 12592 - 12593 12593 - /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ 12594 12594 - #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 12595 12595 - 12596 12596 - 12597 12597 - /***********************************/ 12598 12598 - /* MC_CMD_FREE_BUFTBL_CHUNK 12599 12599 - */ 12600 12600 - #define MC_CMD_FREE_BUFTBL_CHUNK 0x89 12601 12601 - #undef MC_CMD_0x89_PRIVILEGE_CTG 12602 12602 - 12603 12603 - #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 12604 12604 - 12605 12605 - /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ 12606 12606 - #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 12607 12607 - #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 12608 12608 - #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 4 12609 12609 - 12610 12610 - /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ 12611 12611 - #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 12612 11612 12613 11613 12614 11614 /***********************************/ ··· 13194 12822 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES 0x5 13195 12823 /* enum: read the supported encapsulation types for the VNIC */ 13196 12824 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_TYPES 0x6 12825 12825 + /* enum: read the supported RX filter matches for low-latency queues (as 12826 12826 + * allocated by MC_CMD_ALLOC_LL_QUEUES) 12827 12827 + */ 12828 12828 + #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_LL_RX_MATCHES 0x7 13197 12829 13198 12830 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ 13199 12831 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 ··· 13235 12859 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_OFST 4 13236 12860 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0 13237 12861 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1 12862 12862 + 12863 12863 + /* MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT msgresponse: 12864 12864 + * GET_PARSER_DISP_INFO response format for OP_GET_SECURITY_RULE_INFO. 12865 12865 + * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 12866 12866 + * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 12867 12867 + * been used in any released code and may change during development. This note 12868 12868 + * will be removed once it is regarded as stable. 12869 12869 + */ 12870 12870 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_LEN 36 12871 12871 + /* identifies the type of operation requested */ 12872 12872 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_OFST 0 12873 12873 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_LEN 4 12874 12874 + /* Enum values, see field(s): */ 12875 12875 + /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 12876 12876 + /* a version number representing the set of rule lookups that are implemented 12877 12877 + * by the currently running firmware 12878 12878 + */ 12879 12879 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_OFST 4 12880 12880 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_LEN 4 12881 12881 + /* enum: implements lookup sequences described in SF-114946-SW draft C */ 12882 12882 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_SF_114946_SW_C 0x0 12883 12883 + /* the number of nodes in the subnet map */ 12884 12884 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_OFST 8 12885 12885 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_LEN 4 12886 12886 + /* the number of entries in one subnet map node */ 12887 12887 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_OFST 12 12888 12888 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_LEN 4 12889 12889 + /* minimum valid value for a subnet ID in a subnet map leaf */ 12890 12890 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_OFST 16 12891 12891 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_LEN 4 12892 12892 + /* maximum valid value for a subnet ID in a subnet map leaf */ 12893 12893 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_OFST 20 12894 12894 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_LEN 4 12895 12895 + /* the number of entries in the local and remote port range maps */ 12896 12896 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_OFST 24 12897 12897 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_LEN 4 12898 12898 + /* minimum valid value for a portrange ID in a port range map leaf */ 12899 12899 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_OFST 28 12900 12900 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_LEN 4 12901 12901 + /* maximum valid value for a portrange ID in a port range map leaf */ 12902 12902 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_OFST 32 12903 12903 + #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_LEN 4 13238 12904 13239 12905 /* MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT msgresponse: This response is 13240 12906 * returned if a MC_CMD_GET_PARSER_DISP_INFO_IN request is sent with OP value ··· 13332 12914 13333 12915 13334 12916 /***********************************/ 13335 13335 - /* MC_CMD_PARSER_DISP_RW 13336 13336 - * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging. 13337 13337 - * Please note that this interface is only of use to debug tools which have 13338 13338 - * knowledge of firmware and hardware data structures; nothing here is intended 13339 13339 - * for use by normal driver code. Note that although this command is in the 13340 13340 - * Admin privilege group, in tamperproof adapters, only read operations are 13341 13341 - * permitted. 13342 13342 - */ 13343 13343 - #define MC_CMD_PARSER_DISP_RW 0xe5 13344 13344 - #undef MC_CMD_0xe5_PRIVILEGE_CTG 13345 13345 - 13346 13346 - #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13347 13347 - 13348 13348 - /* MC_CMD_PARSER_DISP_RW_IN msgrequest */ 13349 13349 - #define MC_CMD_PARSER_DISP_RW_IN_LEN 32 13350 13350 - /* identifies the target of the operation */ 13351 13351 - #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 13352 13352 - #define MC_CMD_PARSER_DISP_RW_IN_TARGET_LEN 4 13353 13353 - /* enum: RX dispatcher CPU */ 13354 13354 - #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 13355 13355 - /* enum: TX dispatcher CPU */ 13356 13356 - #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 13357 13357 - /* enum: Lookup engine (with original metadata format). Deprecated; used only 13358 13358 - * by cmdclient as a fallback for very old Huntington firmware, and not 13359 13359 - * supported in firmware beyond v6.4.0.1005. Use LUE_VERSIONED_METADATA 13360 13360 - * instead. 13361 13361 - */ 13362 13362 - #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 13363 13363 - /* enum: Lookup engine (with requested metadata format) */ 13364 13364 - #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 13365 13365 - /* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */ 13366 13366 - #define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0 13367 13367 - /* enum: RX1 dispatcher CPU (only valid for Medford) */ 13368 13368 - #define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4 13369 13369 - /* enum: Miscellaneous other state (only valid for Medford) */ 13370 13370 - #define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5 13371 13371 - /* identifies the type of operation requested */ 13372 13372 - #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 13373 13373 - #define MC_CMD_PARSER_DISP_RW_IN_OP_LEN 4 13374 13374 - /* enum: Read a word of DICPU DMEM or a LUE entry */ 13375 13375 - #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 13376 13376 - /* enum: Write a word of DICPU DMEM or a LUE entry. Not permitted on 13377 13377 - * tamperproof adapters. 13378 13378 - */ 13379 13379 - #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 13380 13380 - /* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). Not 13381 13381 - * permitted on tamperproof adapters. 13382 13382 - */ 13383 13383 - #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 13384 13384 - /* data memory address (DICPU targets) or LUE index (LUE targets) */ 13385 13385 - #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 13386 13386 - #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_LEN 4 13387 13387 - /* selector (for MISC_STATE target) */ 13388 13388 - #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8 13389 13389 - #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_LEN 4 13390 13390 - /* enum: Port to datapath mapping */ 13391 13391 - #define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1 13392 13392 - /* value to write (for DMEM writes) */ 13393 13393 - #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 13394 13394 - #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_LEN 4 13395 13395 - /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 13396 13396 - #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 13397 13397 - #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_LEN 4 13398 13398 - /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 13399 13399 - #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 13400 13400 - #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_LEN 4 13401 13401 - /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */ 13402 13402 - #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12 13403 13403 - #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_LEN 4 13404 13404 - /* value to write (for LUE writes) */ 13405 13405 - #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 13406 13406 - #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 13407 13407 - 13408 13408 - /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ 13409 13409 - #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 13410 13410 - /* value read (for DMEM reads) */ 13411 13411 - #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 13412 13412 - #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_LEN 4 13413 13413 - /* value read (for LUE reads) */ 13414 13414 - #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 13415 13415 - #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 13416 13416 - /* up to 8 32-bit words of additional soft state from the LUE manager (the 13417 13417 - * exact content is firmware-dependent and intended only for debug use) 13418 13418 - */ 13419 13419 - #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 13420 13420 - #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 13421 13421 - /* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */ 13422 13422 - #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0 13423 13423 - #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4 13424 13424 - #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4 13425 13425 - #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */ 13426 13426 - #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */ 13427 13427 - 13428 13428 - 13429 13429 - /***********************************/ 13430 13430 - /* MC_CMD_GET_PF_COUNT 13431 13431 - * Get number of PFs on the device. 13432 13432 - */ 13433 13433 - #define MC_CMD_GET_PF_COUNT 0xb6 13434 13434 - #undef MC_CMD_0xb6_PRIVILEGE_CTG 13435 13435 - 13436 13436 - #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13437 13437 - 13438 13438 - /* MC_CMD_GET_PF_COUNT_IN msgrequest */ 13439 13439 - #define MC_CMD_GET_PF_COUNT_IN_LEN 0 13440 13440 - 13441 13441 - /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ 13442 13442 - #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 13443 13443 - /* Identifies the number of PFs on the device. */ 13444 13444 - #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 13445 13445 - #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 13446 13446 - 13447 13447 - 13448 13448 - /***********************************/ 13449 13449 - /* MC_CMD_SET_PF_COUNT 13450 13450 - * Set number of PFs on the device. 13451 13451 - */ 13452 13452 - #define MC_CMD_SET_PF_COUNT 0xb7 13453 13453 - 13454 13454 - /* MC_CMD_SET_PF_COUNT_IN msgrequest */ 13455 13455 - #define MC_CMD_SET_PF_COUNT_IN_LEN 4 13456 13456 - /* New number of PFs on the device. */ 13457 13457 - #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 13458 13458 - #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_LEN 4 13459 13459 - 13460 13460 - /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ 13461 13461 - #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 13462 13462 - 13463 13463 - 13464 13464 - /***********************************/ 13465 12917 /* MC_CMD_GET_PORT_ASSIGNMENT 13466 12918 * Get port assignment for current PCI function. 13467 12919 */ ··· 13354 13066 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4 13355 13067 /* enum: Special value to indicate no port is assigned to a function. */ 13356 13068 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_NULL_PORT 0xffffffff 13357 13357 - 13358 13358 - 13359 13359 - /***********************************/ 13360 13360 - /* MC_CMD_SET_PORT_ASSIGNMENT 13361 13361 - * Set port assignment for current PCI function. 13362 13362 - */ 13363 13363 - #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 13364 13364 - #undef MC_CMD_0xb9_PRIVILEGE_CTG 13365 13365 - 13366 13366 - #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13367 13367 - 13368 13368 - /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ 13369 13369 - #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 13370 13370 - /* Identifies the port assignment for this function. */ 13371 13371 - #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 13372 13372 - #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 4 13373 13373 - 13374 13374 - /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ 13375 13375 - #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 13376 13069 13377 13070 13378 13071 /***********************************/ ··· 13453 13184 13454 13185 13455 13186 /***********************************/ 13456 13456 - /* MC_CMD_SET_SRIOV_CFG 13457 13457 - * Set SRIOV config for this PF. 13458 13458 - */ 13459 13459 - #define MC_CMD_SET_SRIOV_CFG 0xbb 13460 13460 - #undef MC_CMD_0xbb_PRIVILEGE_CTG 13461 13461 - 13462 13462 - #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13463 13463 - 13464 13464 - /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ 13465 13465 - #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 13466 13466 - /* Number of VFs currently enabled. */ 13467 13467 - #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 13468 13468 - #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 4 13469 13469 - /* Max number of VFs before sriov stride and offset may need to be changed. */ 13470 13470 - #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 13471 13471 - #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4 13472 13472 - #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 13473 13473 - #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4 13474 13474 - #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_OFST 8 13475 13475 - #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 13476 13476 - #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 13477 13477 - /* RID offset of first VF from PF, or 0 for no change, or 13478 13478 - * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. 13479 13479 - */ 13480 13480 - #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 13481 13481 - #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 4 13482 13482 - /* RID offset of each subsequent VF from the previous, 0 for no change, or 13483 13483 - * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. 13484 13484 - */ 13485 13485 - #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 13486 13486 - #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 4 13487 13487 - 13488 13488 - /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ 13489 13489 - #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 13490 13490 - 13491 13491 - 13492 13492 - /***********************************/ 13493 13493 - /* MC_CMD_GET_VI_ALLOC_INFO 13494 13494 - * Get information about number of VI's and base VI number allocated to this 13495 13495 - * function. This message is not available to dynamic clients created by 13496 13496 - * MC_CMD_CLIENT_ALLOC. 13497 13497 - */ 13498 13498 - #define MC_CMD_GET_VI_ALLOC_INFO 0x8d 13499 13499 - #undef MC_CMD_0x8d_PRIVILEGE_CTG 13500 13500 - 13501 13501 - #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13502 13502 - 13503 13503 - /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ 13504 13504 - #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 13505 13505 - 13506 13506 - /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ 13507 13507 - #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12 13508 13508 - /* The number of VIs allocated on this function */ 13509 13509 - #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 13510 13510 - #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 4 13511 13511 - /* The base absolute VI number allocated to this function. Required to 13512 13512 - * correctly interpret wakeup events. 13513 13513 - */ 13514 13514 - #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 13515 13515 - #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 4 13516 13516 - /* Function's port vi_shift value (always 0 on Huntington) */ 13517 13517 - #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 13518 13518 - #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4 13519 13519 - 13520 13520 - 13521 13521 - /***********************************/ 13522 13522 - /* MC_CMD_DUMP_VI_STATE 13523 13523 - * For CmdClient use. Dump pertinent information on a specific absolute VI. The 13524 13524 - * VI must be owned by the calling client or one of its ancestors; usership of 13525 13525 - * the VI (as set by MC_CMD_SET_VI_USER) is not sufficient. 13526 13526 - */ 13527 13527 - #define MC_CMD_DUMP_VI_STATE 0x8e 13528 13528 - #undef MC_CMD_0x8e_PRIVILEGE_CTG 13529 13529 - 13530 13530 - #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13531 13531 - 13532 13532 - /* MC_CMD_DUMP_VI_STATE_IN msgrequest */ 13533 13533 - #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 13534 13534 - /* The VI number to query. */ 13535 13535 - #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 13536 13536 - #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4 13537 13537 - 13538 13538 - /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ 13539 13539 - #define MC_CMD_DUMP_VI_STATE_OUT_LEN 100 13540 13540 - /* The PF part of the function owning this VI. */ 13541 13541 - #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 13542 13542 - #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 13543 13543 - /* The VF part of the function owning this VI. */ 13544 13544 - #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 13545 13545 - #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 13546 13546 - /* Base of VIs allocated to this function. */ 13547 13547 - #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 13548 13548 - #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 13549 13549 - /* Count of VIs allocated to the owner function. */ 13550 13550 - #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 13551 13551 - #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 13552 13552 - /* Base interrupt vector allocated to this function. */ 13553 13553 - #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 13554 13554 - #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 13555 13555 - /* Number of interrupt vectors allocated to this function. */ 13556 13556 - #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 13557 13557 - #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 13558 13558 - /* Raw evq ptr table data. */ 13559 13559 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 13560 13560 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 13561 13561 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 13562 13562 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_LEN 4 13563 13563 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_LBN 96 13564 13564 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_WIDTH 32 13565 13565 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 13566 13566 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_LEN 4 13567 13567 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_LBN 128 13568 13568 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_WIDTH 32 13569 13569 - /* Raw evq timer table data. */ 13570 13570 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 13571 13571 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 13572 13572 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 13573 13573 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_LEN 4 13574 13574 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_LBN 160 13575 13575 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_WIDTH 32 13576 13576 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 13577 13577 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_LEN 4 13578 13578 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_LBN 192 13579 13579 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_WIDTH 32 13580 13580 - /* Combined metadata field. */ 13581 13581 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 13582 13582 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4 13583 13583 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_OFST 28 13584 13584 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 13585 13585 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 13586 13586 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_OFST 28 13587 13587 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 13588 13588 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 13589 13589 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_OFST 28 13590 13590 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 13591 13591 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 13592 13592 - /* TXDPCPU raw table data for queue. */ 13593 13593 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 13594 13594 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 13595 13595 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 13596 13596 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_LEN 4 13597 13597 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_LBN 256 13598 13598 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_WIDTH 32 13599 13599 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 13600 13600 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_LEN 4 13601 13601 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_LBN 288 13602 13602 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_WIDTH 32 13603 13603 - /* TXDPCPU raw table data for queue. */ 13604 13604 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 13605 13605 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 13606 13606 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 13607 13607 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_LEN 4 13608 13608 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_LBN 320 13609 13609 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_WIDTH 32 13610 13610 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 13611 13611 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_LEN 4 13612 13612 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_LBN 352 13613 13613 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_WIDTH 32 13614 13614 - /* TXDPCPU raw table data for queue. */ 13615 13615 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 13616 13616 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 13617 13617 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 13618 13618 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_LEN 4 13619 13619 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_LBN 384 13620 13620 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_WIDTH 32 13621 13621 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 13622 13622 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_LEN 4 13623 13623 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_LBN 416 13624 13624 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_WIDTH 32 13625 13625 - /* Combined metadata field. */ 13626 13626 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 13627 13627 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 13628 13628 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 13629 13629 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_LEN 4 13630 13630 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_LBN 448 13631 13631 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_WIDTH 32 13632 13632 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 13633 13633 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_LEN 4 13634 13634 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_LBN 480 13635 13635 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_WIDTH 32 13636 13636 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_OFST 56 13637 13637 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 13638 13638 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 13639 13639 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_OFST 56 13640 13640 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 13641 13641 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 13642 13642 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_OFST 56 13643 13643 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 13644 13644 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 13645 13645 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_OFST 56 13646 13646 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 13647 13647 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 13648 13648 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_OFST 56 13649 13649 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 13650 13650 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 13651 13651 - /* RXDPCPU raw table data for queue. */ 13652 13652 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 13653 13653 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 13654 13654 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 13655 13655 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_LEN 4 13656 13656 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_LBN 512 13657 13657 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_WIDTH 32 13658 13658 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 13659 13659 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_LEN 4 13660 13660 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_LBN 544 13661 13661 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_WIDTH 32 13662 13662 - /* RXDPCPU raw table data for queue. */ 13663 13663 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 13664 13664 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 13665 13665 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 13666 13666 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_LEN 4 13667 13667 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_LBN 576 13668 13668 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_WIDTH 32 13669 13669 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 13670 13670 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_LEN 4 13671 13671 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_LBN 608 13672 13672 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_WIDTH 32 13673 13673 - /* Reserved, currently 0. */ 13674 13674 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 13675 13675 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 13676 13676 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 13677 13677 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_LEN 4 13678 13678 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_LBN 640 13679 13679 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_WIDTH 32 13680 13680 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 13681 13681 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_LEN 4 13682 13682 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_LBN 672 13683 13683 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_WIDTH 32 13684 13684 - /* Combined metadata field. */ 13685 13685 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 13686 13686 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 13687 13687 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 13688 13688 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_LEN 4 13689 13689 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_LBN 704 13690 13690 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_WIDTH 32 13691 13691 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 13692 13692 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_LEN 4 13693 13693 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_LBN 736 13694 13694 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_WIDTH 32 13695 13695 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_OFST 88 13696 13696 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 13697 13697 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 13698 13698 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_OFST 88 13699 13699 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 13700 13700 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 13701 13701 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_OFST 88 13702 13702 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 13703 13703 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 13704 13704 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_OFST 88 13705 13705 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 13706 13706 - #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 13707 13707 - /* Current user, as assigned by MC_CMD_SET_VI_USER. */ 13708 13708 - #define MC_CMD_DUMP_VI_STATE_OUT_USER_CLIENT_ID_OFST 96 13709 13709 - #define MC_CMD_DUMP_VI_STATE_OUT_USER_CLIENT_ID_LEN 4 13710 13710 - 13711 13711 - 13712 13712 - /***********************************/ 13713 13187 /* MC_CMD_ALLOC_PIOBUF 13714 13188 * Allocate a push I/O buffer for later use with a tx queue. 13715 13189 */ ··· 13503 13491 13504 13492 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ 13505 13493 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 13506 13506 - /* VI number to get information for. */ 13494 13494 + /* Queue handle, encodes queue type and VI number to get information for. */ 13507 13495 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 13508 13496 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4 13509 13497 13510 13510 - /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ 13511 13511 - #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 13512 13512 - /* Transaction processing steering hint 1 for use with the Rx Queue. */ 13513 13513 - #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 13514 13514 - #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 13515 13515 - /* Transaction processing steering hint 2 for use with the Ev Queue. */ 13516 13516 - #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 13517 13517 - #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 13518 13518 - /* Use Relaxed ordering model for TLPs on this VI. */ 13519 13519 - #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 13520 13520 - #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 13521 13521 - /* Use ID based ordering for TLPs on this VI. */ 13522 13522 - #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 13523 13523 - #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 13524 13524 - /* Set no snoop bit for TLPs on this VI. */ 13525 13525 - #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 13526 13526 - #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 13527 13527 - /* Enable TPH for TLPs on this VI. */ 13528 13528 - #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 13529 13529 - #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 13530 13530 - #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 13531 13531 - #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 4 13498 13498 + /* MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT msgresponse: This message has the same 13499 13499 + * layout as GET_VI_TLP_PROCESSING_OUT, but with corrected field ordering to 13500 13500 + * simplify use in drivers 13501 13501 + */ 13502 13502 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_LEN 4 13503 13503 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_DATA_OFST 0 13504 13504 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_DATA_LEN 4 13505 13505 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG1_RX_OFST 0 13506 13506 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG1_RX_LBN 0 13507 13507 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG1_RX_WIDTH 8 13508 13508 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG2_EV_OFST 0 13509 13509 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG2_EV_LBN 8 13510 13510 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG2_EV_WIDTH 8 13511 13511 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_OFST 0 13512 13512 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_LBN 16 13513 13513 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_WIDTH 1 13514 13514 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_PACKET_DATA_OFST 0 13515 13515 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_PACKET_DATA_LBN 16 13516 13516 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_PACKET_DATA_WIDTH 1 13517 13517 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_ID_BASED_ORDERING_OFST 0 13518 13518 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_ID_BASED_ORDERING_LBN 17 13519 13519 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_ID_BASED_ORDERING_WIDTH 1 13520 13520 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_NO_SNOOP_OFST 0 13521 13521 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_NO_SNOOP_LBN 18 13522 13522 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_NO_SNOOP_WIDTH 1 13523 13523 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_ON_OFST 0 13524 13524 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_ON_LBN 19 13525 13525 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_ON_WIDTH 1 13526 13526 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_SYNC_DATA_OFST 0 13527 13527 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_SYNC_DATA_LBN 20 13528 13528 + #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_SYNC_DATA_WIDTH 1 13532 13529 13533 13530 13534 13531 /***********************************/ 13535 13532 /* MC_CMD_SET_VI_TLP_PROCESSING 13536 13533 * Set TLP steering and ordering information for a VI. The caller must have the 13537 13534 * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or 13538 13538 - * an ancestor of the current user (see MC_CMD_SET_VI_USER). 13535 13535 + * an ancestor of the current user (see MC_CMD_SET_VI_USER). Note that LL 13536 13536 + * queues require this to be called after allocation but before initialisation 13537 13537 + * of the queue. TLP options of a queue are fixed after queue is initialised, 13538 13538 + * with the values set to current global value or they can be overriden using 13539 13539 + * this command. At LL queue allocation, all overrides are cleared. 13539 13540 */ 13540 13541 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 13541 13542 #undef MC_CMD_0xb1_PRIVILEGE_CTG 13542 13543 13543 13544 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13544 13545 13545 13545 - /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ 13546 13546 - #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 13547 13547 - /* VI number to set information for. */ 13548 13548 - #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 13549 13549 - #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4 13550 13550 - /* Transaction processing steering hint 1 for use with the Rx Queue. */ 13551 13551 - #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 13552 13552 - #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 13553 13553 - /* Transaction processing steering hint 2 for use with the Ev Queue. */ 13554 13554 - #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 13555 13555 - #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 13556 13556 - /* Use Relaxed ordering model for TLPs on this VI. */ 13557 13557 - #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 13558 13558 - #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 13559 13559 - /* Use ID based ordering for TLPs on this VI. */ 13560 13560 - #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 13561 13561 - #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 13562 13562 - /* Set the no snoop bit for TLPs on this VI. */ 13563 13563 - #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 13564 13564 - #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 13565 13565 - /* Enable TPH for TLPs on this VI. */ 13566 13566 - #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 13567 13567 - #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 13568 13568 - #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 13569 13569 - #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_LEN 4 13546 13546 + /* MC_CMD_SET_VI_TLP_PROCESSING_V2_IN msgrequest: This message has the same 13547 13547 + * layout as SET_VI_TLP_PROCESSING_OUT, but with corrected field ordering to 13548 13548 + * simplify use in drivers. 13549 13549 + */ 13550 13550 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_LEN 8 13551 13551 + /* Queue handle, encodes queue type and VI number to set information for. */ 13552 13552 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_INSTANCE_OFST 0 13553 13553 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_INSTANCE_LEN 4 13554 13554 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_DATA_OFST 4 13555 13555 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_DATA_LEN 4 13556 13556 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG1_RX_OFST 4 13557 13557 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG1_RX_LBN 0 13558 13558 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG1_RX_WIDTH 8 13559 13559 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG2_EV_OFST 4 13560 13560 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG2_EV_LBN 8 13561 13561 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG2_EV_WIDTH 8 13562 13562 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_OFST 4 13563 13563 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_LBN 16 13564 13564 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_WIDTH 1 13565 13565 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_PACKET_DATA_OFST 4 13566 13566 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_PACKET_DATA_LBN 16 13567 13567 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_PACKET_DATA_WIDTH 1 13568 13568 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_ID_BASED_ORDERING_OFST 4 13569 13569 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_ID_BASED_ORDERING_LBN 17 13570 13570 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_ID_BASED_ORDERING_WIDTH 1 13571 13571 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_NO_SNOOP_OFST 4 13572 13572 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_NO_SNOOP_LBN 18 13573 13573 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_NO_SNOOP_WIDTH 1 13574 13574 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_ON_OFST 4 13575 13575 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_ON_LBN 19 13576 13576 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_ON_WIDTH 1 13577 13577 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_SYNC_DATA_OFST 4 13578 13578 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_SYNC_DATA_LBN 20 13579 13579 + #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_SYNC_DATA_WIDTH 1 13570 13580 13571 13581 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ 13572 13582 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 13573 13583 13574 13584 13575 13585 /***********************************/ 13576 13576 - /* MC_CMD_GET_TLP_PROCESSING_GLOBALS 13577 13577 - * Get global PCIe steering and transaction processing configuration. 13578 13578 - */ 13579 13579 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc 13580 13580 - #undef MC_CMD_0xbc_PRIVILEGE_CTG 13581 13581 - 13582 13582 - #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13583 13583 - 13584 13584 - /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 13585 13585 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 13586 13586 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 13587 13587 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4 13588 13588 - /* enum: MISC. */ 13589 13589 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 13590 13590 - /* enum: IDO. */ 13591 13591 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 13592 13592 - /* enum: RO. */ 13593 13593 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 13594 13594 - /* enum: TPH Type. */ 13595 13595 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 13596 13596 - 13597 13597 - /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 13598 13598 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 13599 13599 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 13600 13600 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_LEN 4 13601 13601 - /* Enum values, see field(s): */ 13602 13602 - /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 13603 13603 - /* Amalgamated TLP info word. */ 13604 13604 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 13605 13605 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_LEN 4 13606 13606 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_OFST 4 13607 13607 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 13608 13608 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 13609 13609 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_OFST 4 13610 13610 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 13611 13611 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 13612 13612 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_OFST 4 13613 13613 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 13614 13614 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 13615 13615 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_OFST 4 13616 13616 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 13617 13617 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 13618 13618 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_OFST 4 13619 13619 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 13620 13620 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 13621 13621 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_OFST 4 13622 13622 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 13623 13623 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 13624 13624 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_OFST 4 13625 13625 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 13626 13626 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 13627 13627 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_OFST 4 13628 13628 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 13629 13629 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 13630 13630 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_OFST 4 13631 13631 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 13632 13632 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 13633 13633 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_OFST 4 13634 13634 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 13635 13635 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 13636 13636 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_OFST 4 13637 13637 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 13638 13638 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 13639 13639 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_OFST 4 13640 13640 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 13641 13641 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 13642 13642 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_OFST 4 13643 13643 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 13644 13644 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 13645 13645 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_OFST 4 13646 13646 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 13647 13647 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 13648 13648 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_OFST 4 13649 13649 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 13650 13650 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 13651 13651 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_OFST 4 13652 13652 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 13653 13653 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 13654 13654 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_OFST 4 13655 13655 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 13656 13656 - #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 13657 13657 - 13658 13658 - 13659 13659 - /***********************************/ 13660 13660 - /* MC_CMD_SET_TLP_PROCESSING_GLOBALS 13661 13661 - * Set global PCIe steering and transaction processing configuration. 13662 13662 - */ 13663 13663 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd 13664 13664 - #undef MC_CMD_0xbd_PRIVILEGE_CTG 13665 13665 - 13666 13666 - #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13667 13667 - 13668 13668 - /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 13669 13669 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 13670 13670 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 13671 13671 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4 13672 13672 - /* Enum values, see field(s): */ 13673 13673 - /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 13674 13674 - /* Amalgamated TLP info word. */ 13675 13675 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 13676 13676 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_LEN 4 13677 13677 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_OFST 4 13678 13678 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 13679 13679 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 13680 13680 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_OFST 4 13681 13681 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 13682 13682 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 13683 13683 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_OFST 4 13684 13684 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 13685 13685 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 13686 13686 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_OFST 4 13687 13687 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 13688 13688 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 13689 13689 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_OFST 4 13690 13690 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 13691 13691 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 13692 13692 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_OFST 4 13693 13693 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 13694 13694 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 13695 13695 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_OFST 4 13696 13696 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 13697 13697 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 13698 13698 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_OFST 4 13699 13699 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 13700 13700 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 13701 13701 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_OFST 4 13702 13702 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 13703 13703 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 13704 13704 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_OFST 4 13705 13705 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 13706 13706 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 13707 13707 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_OFST 4 13708 13708 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 13709 13709 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 13710 13710 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_OFST 4 13711 13711 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 13712 13712 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 13713 13713 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_OFST 4 13714 13714 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 13715 13715 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 13716 13716 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_OFST 4 13717 13717 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 13718 13718 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 13719 13719 - 13720 13720 - /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 13721 13721 - #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 13722 13722 - 13723 13723 - 13724 13724 - /***********************************/ 13725 13725 - /* MC_CMD_SATELLITE_DOWNLOAD 13726 13726 - * Download a new set of images to the satellite CPUs from the host. 13727 13727 - */ 13728 13728 - #define MC_CMD_SATELLITE_DOWNLOAD 0x91 13729 13729 - #undef MC_CMD_0x91_PRIVILEGE_CTG 13730 13730 - 13731 13731 - #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13732 13732 - 13733 13733 - /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs 13734 13734 - * are subtle, and so downloads must proceed in a number of phases. 13735 13735 - * 13736 13736 - * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. 13737 13737 - * 13738 13738 - * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download 13739 13739 - * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should 13740 13740 - * be a checksum (a simple 32-bit sum) of the transferred data. An individual 13741 13741 - * download may be aborted using CHUNK_ID_ABORT. 13742 13742 - * 13743 13743 - * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), 13744 13744 - * similar to PHASE_IMEMS. 13745 13745 - * 13746 13746 - * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. 13747 13747 - * 13748 13748 - * After any error (a requested abort is not considered to be an error) the 13749 13749 - * sequence must be restarted from PHASE_RESET. 13750 13750 - */ 13751 13751 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 13752 13752 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 13753 13753 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX_MCDI2 1020 13754 13754 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) 13755 13755 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_NUM(len) (((len)-16)/4) 13756 13756 - /* Download phase. (Note: the IDLE phase is used internally and is never valid 13757 13757 - * in a command from the host.) 13758 13758 - */ 13759 13759 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 13760 13760 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_LEN 4 13761 13761 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ 13762 13762 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ 13763 13763 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ 13764 13764 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ 13765 13765 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ 13766 13766 - /* Target for download. (These match the blob numbers defined in 13767 13767 - * mc_flash_layout.h.) 13768 13768 - */ 13769 13769 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 13770 13770 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_LEN 4 13771 13771 - /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 13772 13772 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 13773 13773 - /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 13774 13774 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 13775 13775 - /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 13776 13776 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 13777 13777 - /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 13778 13778 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 13779 13779 - /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 13780 13780 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 13781 13781 - /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 13782 13782 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 13783 13783 - /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 13784 13784 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 13785 13785 - /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 13786 13786 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 13787 13787 - /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 13788 13788 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 13789 13789 - /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 13790 13790 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 13791 13791 - /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 13792 13792 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa 13793 13793 - /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 13794 13794 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb 13795 13795 - /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 13796 13796 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc 13797 13797 - /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 13798 13798 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd 13799 13799 - /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 13800 13800 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe 13801 13801 - /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 13802 13802 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf 13803 13803 - /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ 13804 13804 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff 13805 13805 - /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ 13806 13806 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 13807 13807 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LEN 4 13808 13808 - /* enum: Last chunk, containing checksum rather than data */ 13809 13809 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff 13810 13810 - /* enum: Abort download of this item */ 13811 13811 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe 13812 13812 - /* Length of this chunk in bytes */ 13813 13813 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 13814 13814 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_LEN 4 13815 13815 - /* Data for this chunk */ 13816 13816 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 13817 13817 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 13818 13818 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 13819 13819 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 13820 13820 - #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM_MCDI2 251 13821 13821 - 13822 13822 - /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ 13823 13823 - #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 13824 13824 - /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 13825 13825 - #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 13826 13826 - #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_LEN 4 13827 13827 - /* Extra status information */ 13828 13828 - #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 13829 13829 - #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_LEN 4 13830 13830 - /* enum: Code download OK, completed. */ 13831 13831 - #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 13832 13832 - /* enum: Code download aborted as requested. */ 13833 13833 - #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 13834 13834 - /* enum: Code download OK so far, send next chunk. */ 13835 13835 - #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 13836 13836 - /* enum: Download phases out of sequence */ 13837 13837 - #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 13838 13838 - /* enum: Bad target for this phase */ 13839 13839 - #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 13840 13840 - /* enum: Chunk ID out of sequence */ 13841 13841 - #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 13842 13842 - /* enum: Chunk length zero or too large */ 13843 13843 - #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 13844 13844 - /* enum: Checksum was incorrect */ 13845 13845 - #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 13846 13846 - 13847 13847 - 13848 13848 - /***********************************/ 13849 13586 /* MC_CMD_GET_CAPABILITIES 13850 13850 - * Get device capabilities. 13851 13851 - * 13852 13852 - * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to 13853 13853 - * reference inherent device capabilities as opposed to current NVRAM config. 13587 13587 + * Get device capabilities. This is supplementary to the MC_CMD_GET_BOARD_CFG 13588 13588 + * command, and intended to reference inherent device capabilities as opposed 13589 13589 + * to current NVRAM config. 13854 13590 */ 13855 13591 #define MC_CMD_GET_CAPABILITIES 0xbe 13856 13592 #undef MC_CMD_0xbe_PRIVILEGE_CTG ··· 14250 14490 /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */ 14251 14491 /* enum: PF does not exist. */ 14252 14492 /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */ 14253 14253 - /* Number of VIs available for each external port */ 14493 14493 + /* Number of VIs available for external ports 0-3. For devices with more than 14494 14494 + * four ports, the remainder are in NUM_VIS_PER_PORT2 in 14495 14495 + * GET_CAPABILITIES_V12_OUT. 14496 14496 + */ 14254 14497 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58 14255 14498 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2 14256 14499 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4 ··· 14663 14900 /* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */ 14664 14901 /* enum: PF does not exist. */ 14665 14902 /* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */ 14666 14666 - /* Number of VIs available for each external port */ 14903 14903 + /* Number of VIs available for external ports 0-3. For devices with more than 14904 14904 + * four ports, the remainder are in NUM_VIS_PER_PORT2 in 14905 14905 + * GET_CAPABILITIES_V12_OUT. 14906 14906 + */ 14667 14907 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58 14668 14908 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2 14669 14909 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4 ··· 15101 15335 /* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */ 15102 15336 /* enum: PF does not exist. */ 15103 15337 /* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */ 15104 15104 - /* Number of VIs available for each external port */ 15338 15338 + /* Number of VIs available for external ports 0-3. For devices with more than 15339 15339 + * four ports, the remainder are in NUM_VIS_PER_PORT2 in 15340 15340 + * GET_CAPABILITIES_V12_OUT. 15341 15341 + */ 15105 15342 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 58 15106 15343 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 2 15107 15344 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4 ··· 15547 15778 /* MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff */ 15548 15779 /* enum: PF does not exist. */ 15549 15780 /* MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe */ 15550 15550 - /* Number of VIs available for each external port */ 15781 15781 + /* Number of VIs available for external ports 0-3. For devices with more than 15782 15782 + * four ports, the remainder are in NUM_VIS_PER_PORT2 in 15783 15783 + * GET_CAPABILITIES_V12_OUT. 15784 15784 + */ 15551 15785 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_OFST 58 15552 15786 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_LEN 2 15553 15787 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_NUM 4 ··· 15998 16226 /* MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff */ 15999 16227 /* enum: PF does not exist. */ 16000 16228 /* MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe */ 16001 16001 - /* Number of VIs available for each external port */ 16229 16229 + /* Number of VIs available for external ports 0-3. For devices with more than 16230 16230 + * four ports, the remainder are in NUM_VIS_PER_PORT2 in 16231 16231 + * GET_CAPABILITIES_V12_OUT. 16232 16232 + */ 16002 16233 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_OFST 58 16003 16234 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_LEN 2 16004 16235 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_NUM 4 ··· 16460 16685 /* MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff */ 16461 16686 /* enum: PF does not exist. */ 16462 16687 /* MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe */ 16463 16463 - /* Number of VIs available for each external port */ 16688 16688 + /* Number of VIs available for external ports 0-3. For devices with more than 16689 16689 + * four ports, the remainder are in NUM_VIS_PER_PORT2 in 16690 16690 + * GET_CAPABILITIES_V12_OUT. 16691 16691 + */ 16464 16692 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_OFST 58 16465 16693 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_LEN 2 16466 16694 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_NUM 4 ··· 16574 16796 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148 16575 16797 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12 16576 16798 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1 16799 16799 + #define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_OFST 148 16800 16800 + #define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_LBN 13 16801 16801 + #define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_WIDTH 1 16577 16802 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148 16578 16803 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14 16579 16804 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1 16805 16805 + #define MC_CMD_GET_CAPABILITIES_V7_OUT_CLIENT_CMD_VF_PROXY_OFST 148 16806 16806 + #define MC_CMD_GET_CAPABILITIES_V7_OUT_CLIENT_CMD_VF_PROXY_LBN 15 16807 16807 + #define MC_CMD_GET_CAPABILITIES_V7_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1 16808 16808 + #define MC_CMD_GET_CAPABILITIES_V7_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148 16809 16809 + #define MC_CMD_GET_CAPABILITIES_V7_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16 16810 16810 + #define MC_CMD_GET_CAPABILITIES_V7_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1 16811 16811 + #define MC_CMD_GET_CAPABILITIES_V7_OUT_CXL_CONFIG_ENABLE_OFST 148 16812 16812 + #define MC_CMD_GET_CAPABILITIES_V7_OUT_CXL_CONFIG_ENABLE_LBN 17 16813 16813 + #define MC_CMD_GET_CAPABILITIES_V7_OUT_CXL_CONFIG_ENABLE_WIDTH 1 16580 16814 16581 16815 /* MC_CMD_GET_CAPABILITIES_V8_OUT msgresponse */ 16582 16816 #define MC_CMD_GET_CAPABILITIES_V8_OUT_LEN 160 ··· 16979 17189 /* MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff */ 16980 17190 /* enum: PF does not exist. */ 16981 17191 /* MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe */ 16982 16982 - /* Number of VIs available for each external port */ 17192 17192 + /* Number of VIs available for external ports 0-3. For devices with more than 17193 17193 + * four ports, the remainder are in NUM_VIS_PER_PORT2 in 17194 17194 + * GET_CAPABILITIES_V12_OUT. 17195 17195 + */ 16983 17196 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_OFST 58 16984 17197 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_LEN 2 16985 17198 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_NUM 4 ··· 17093 17300 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148 17094 17301 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12 17095 17302 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1 17303 17303 + #define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_OFST 148 17304 17304 + #define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_LBN 13 17305 17305 + #define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_WIDTH 1 17096 17306 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148 17097 17307 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14 17098 17308 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1 17309 17309 + #define MC_CMD_GET_CAPABILITIES_V8_OUT_CLIENT_CMD_VF_PROXY_OFST 148 17310 17310 + #define MC_CMD_GET_CAPABILITIES_V8_OUT_CLIENT_CMD_VF_PROXY_LBN 15 17311 17311 + #define MC_CMD_GET_CAPABILITIES_V8_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1 17312 17312 + #define MC_CMD_GET_CAPABILITIES_V8_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148 17313 17313 + #define MC_CMD_GET_CAPABILITIES_V8_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16 17314 17314 + #define MC_CMD_GET_CAPABILITIES_V8_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1 17315 17315 + #define MC_CMD_GET_CAPABILITIES_V8_OUT_CXL_CONFIG_ENABLE_OFST 148 17316 17316 + #define MC_CMD_GET_CAPABILITIES_V8_OUT_CXL_CONFIG_ENABLE_LBN 17 17317 17317 + #define MC_CMD_GET_CAPABILITIES_V8_OUT_CXL_CONFIG_ENABLE_WIDTH 1 17099 17318 /* These bits are reserved for communicating test-specific capabilities to 17100 17319 * host-side test software. All production drivers should treat this field as 17101 17320 * opaque. ··· 17512 17707 /* MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff */ 17513 17708 /* enum: PF does not exist. */ 17514 17709 /* MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe */ 17515 17515 - /* Number of VIs available for each external port */ 17710 17710 + /* Number of VIs available for external ports 0-3. For devices with more than 17711 17711 + * four ports, the remainder are in NUM_VIS_PER_PORT2 in 17712 17712 + * GET_CAPABILITIES_V12_OUT. 17713 17713 + */ 17516 17714 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_OFST 58 17517 17715 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_LEN 2 17518 17716 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_NUM 4 ··· 17626 17818 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148 17627 17819 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12 17628 17820 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1 17821 17821 + #define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_OFST 148 17822 17822 + #define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_LBN 13 17823 17823 + #define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_WIDTH 1 17629 17824 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148 17630 17825 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14 17631 17826 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1 17827 17827 + #define MC_CMD_GET_CAPABILITIES_V9_OUT_CLIENT_CMD_VF_PROXY_OFST 148 17828 17828 + #define MC_CMD_GET_CAPABILITIES_V9_OUT_CLIENT_CMD_VF_PROXY_LBN 15 17829 17829 + #define MC_CMD_GET_CAPABILITIES_V9_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1 17830 17830 + #define MC_CMD_GET_CAPABILITIES_V9_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148 17831 17831 + #define MC_CMD_GET_CAPABILITIES_V9_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16 17832 17832 + #define MC_CMD_GET_CAPABILITIES_V9_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1 17833 17833 + #define MC_CMD_GET_CAPABILITIES_V9_OUT_CXL_CONFIG_ENABLE_OFST 148 17834 17834 + #define MC_CMD_GET_CAPABILITIES_V9_OUT_CXL_CONFIG_ENABLE_LBN 17 17835 17835 + #define MC_CMD_GET_CAPABILITIES_V9_OUT_CXL_CONFIG_ENABLE_WIDTH 1 17632 17836 /* These bits are reserved for communicating test-specific capabilities to 17633 17837 * host-side test software. All production drivers should treat this field as 17634 17838 * opaque. ··· 18080 18260 /* MC_CMD_GET_CAPABILITIES_V10_OUT_ACCESS_NOT_PERMITTED 0xff */ 18081 18261 /* enum: PF does not exist. */ 18082 18262 /* MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_PRESENT 0xfe */ 18083 18083 - /* Number of VIs available for each external port */ 18263 18263 + /* Number of VIs available for external ports 0-3. For devices with more than 18264 18264 + * four ports, the remainder are in NUM_VIS_PER_PORT2 in 18265 18265 + * GET_CAPABILITIES_V12_OUT. 18266 18266 + */ 18084 18267 #define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_OFST 58 18085 18268 #define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_LEN 2 18086 18269 #define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_NUM 4 ··· 18194 18371 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148 18195 18372 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12 18196 18373 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1 18374 18374 + #define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_OFST 148 18375 18375 + #define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_LBN 13 18376 18376 + #define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_WIDTH 1 18197 18377 #define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148 18198 18378 #define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14 18199 18379 #define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1 18380 18380 + #define MC_CMD_GET_CAPABILITIES_V10_OUT_CLIENT_CMD_VF_PROXY_OFST 148 18381 18381 + #define MC_CMD_GET_CAPABILITIES_V10_OUT_CLIENT_CMD_VF_PROXY_LBN 15 18382 18382 + #define MC_CMD_GET_CAPABILITIES_V10_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1 18383 18383 + #define MC_CMD_GET_CAPABILITIES_V10_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148 18384 18384 + #define MC_CMD_GET_CAPABILITIES_V10_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16 18385 18385 + #define MC_CMD_GET_CAPABILITIES_V10_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1 18386 18386 + #define MC_CMD_GET_CAPABILITIES_V10_OUT_CXL_CONFIG_ENABLE_OFST 148 18387 18387 + #define MC_CMD_GET_CAPABILITIES_V10_OUT_CXL_CONFIG_ENABLE_LBN 17 18388 18388 + #define MC_CMD_GET_CAPABILITIES_V10_OUT_CXL_CONFIG_ENABLE_WIDTH 1 18200 18389 /* These bits are reserved for communicating test-specific capabilities to 18201 18390 * host-side test software. All production drivers should treat this field as 18202 18391 * opaque. ··· 18273 18438 #define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_QUEUE_SIZES_OFST 188 18274 18439 #define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_QUEUE_SIZES_LEN 4 18275 18440 18441 18441 + /* MC_CMD_GET_CAPABILITIES_V11_OUT msgresponse */ 18442 18442 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_LEN 196 18443 18443 + /* First word of flags. */ 18444 18444 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS1_OFST 0 18445 18445 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS1_LEN 4 18446 18446 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VPORT_RECONFIGURE_OFST 0 18447 18447 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VPORT_RECONFIGURE_LBN 3 18448 18448 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VPORT_RECONFIGURE_WIDTH 1 18449 18449 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_STRIPING_OFST 0 18450 18450 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_STRIPING_LBN 4 18451 18451 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_STRIPING_WIDTH 1 18452 18452 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_QUERY_OFST 0 18453 18453 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_QUERY_LBN 5 18454 18454 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_QUERY_WIDTH 1 18455 18455 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0 18456 18456 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 18457 18457 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 18458 18458 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_DRV_ATTACH_PREBOOT_OFST 0 18459 18459 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_DRV_ATTACH_PREBOOT_LBN 7 18460 18460 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 18461 18461 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_FORCE_EVENT_MERGING_OFST 0 18462 18462 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_FORCE_EVENT_MERGING_LBN 8 18463 18463 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 18464 18464 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_SET_MAC_ENHANCED_OFST 0 18465 18465 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_SET_MAC_ENHANCED_LBN 9 18466 18466 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_SET_MAC_ENHANCED_WIDTH 1 18467 18467 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0 18468 18468 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 18469 18469 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 18470 18470 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0 18471 18471 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 18472 18472 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 18473 18473 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_SECURITY_FILTERING_OFST 0 18474 18474 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 18475 18475 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 18476 18476 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_ADDITIONAL_RSS_MODES_OFST 0 18477 18477 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_ADDITIONAL_RSS_MODES_LBN 13 18478 18478 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 18479 18479 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_QBB_OFST 0 18480 18480 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_QBB_LBN 14 18481 18481 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_QBB_WIDTH 1 18482 18482 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0 18483 18483 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 18484 18484 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 18485 18485 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_RSS_LIMITED_OFST 0 18486 18486 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_RSS_LIMITED_LBN 16 18487 18487 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_RSS_LIMITED_WIDTH 1 18488 18488 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_OFST 0 18489 18489 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_LBN 17 18490 18490 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_WIDTH 1 18491 18491 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_INCLUDE_FCS_OFST 0 18492 18492 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_INCLUDE_FCS_LBN 18 18493 18493 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_INCLUDE_FCS_WIDTH 1 18494 18494 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VLAN_INSERTION_OFST 0 18495 18495 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VLAN_INSERTION_LBN 19 18496 18496 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VLAN_INSERTION_WIDTH 1 18497 18497 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_OFST 0 18498 18498 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_LBN 20 18499 18499 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_WIDTH 1 18500 18500 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_OFST 0 18501 18501 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_LBN 21 18502 18502 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_WIDTH 1 18503 18503 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_0_OFST 0 18504 18504 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_0_LBN 22 18505 18505 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_0_WIDTH 1 18506 18506 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_14_OFST 0 18507 18507 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_14_LBN 23 18508 18508 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_14_WIDTH 1 18509 18509 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_TIMESTAMP_OFST 0 18510 18510 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_TIMESTAMP_LBN 24 18511 18511 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_TIMESTAMP_WIDTH 1 18512 18512 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_BATCHING_OFST 0 18513 18513 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_BATCHING_LBN 25 18514 18514 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_BATCHING_WIDTH 1 18515 18515 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MCAST_FILTER_CHAINING_OFST 0 18516 18516 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MCAST_FILTER_CHAINING_LBN 26 18517 18517 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MCAST_FILTER_CHAINING_WIDTH 1 18518 18518 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_PM_AND_RXDP_COUNTERS_OFST 0 18519 18519 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_PM_AND_RXDP_COUNTERS_LBN 27 18520 18520 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 18521 18521 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DISABLE_SCATTER_OFST 0 18522 18522 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DISABLE_SCATTER_LBN 28 18523 18523 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DISABLE_SCATTER_WIDTH 1 18524 18524 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0 18525 18525 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 18526 18526 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 18527 18527 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_OFST 0 18528 18528 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_LBN 30 18529 18529 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_WIDTH 1 18530 18530 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VXLAN_NVGRE_OFST 0 18531 18531 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VXLAN_NVGRE_LBN 31 18532 18532 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VXLAN_NVGRE_WIDTH 1 18533 18533 + /* RxDPCPU firmware id. */ 18534 18534 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DPCPU_FW_ID_OFST 4 18535 18535 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DPCPU_FW_ID_LEN 2 18536 18536 + /* enum: Standard RXDP firmware */ 18537 18537 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP 0x0 18538 18538 + /* enum: Low latency RXDP firmware */ 18539 18539 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_LOW_LATENCY 0x1 18540 18540 + /* enum: Packed stream RXDP firmware */ 18541 18541 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_PACKED_STREAM 0x2 18542 18542 + /* enum: Rules engine RXDP firmware */ 18543 18543 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_RULES_ENGINE 0x5 18544 18544 + /* enum: DPDK RXDP firmware */ 18545 18545 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_DPDK 0x6 18546 18546 + /* enum: BIST RXDP firmware */ 18547 18547 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_BIST 0x10a 18548 18548 + /* enum: RXDP Test firmware image 1 */ 18549 18549 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 18550 18550 + /* enum: RXDP Test firmware image 2 */ 18551 18551 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 18552 18552 + /* enum: RXDP Test firmware image 3 */ 18553 18553 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 18554 18554 + /* enum: RXDP Test firmware image 4 */ 18555 18555 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 18556 18556 + /* enum: RXDP Test firmware image 5 */ 18557 18557 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_BACKPRESSURE 0x105 18558 18558 + /* enum: RXDP Test firmware image 6 */ 18559 18559 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 18560 18560 + /* enum: RXDP Test firmware image 7 */ 18561 18561 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 18562 18562 + /* enum: RXDP Test firmware image 8 */ 18563 18563 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 18564 18564 + /* enum: RXDP Test firmware image 9 */ 18565 18565 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 18566 18566 + /* enum: RXDP Test firmware image 10 */ 18567 18567 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_SLOW 0x10c 18568 18568 + /* TxDPCPU firmware id. */ 18569 18569 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_DPCPU_FW_ID_OFST 6 18570 18570 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_DPCPU_FW_ID_LEN 2 18571 18571 + /* enum: Standard TXDP firmware */ 18572 18572 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP 0x0 18573 18573 + /* enum: Low latency TXDP firmware */ 18574 18574 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_LOW_LATENCY 0x1 18575 18575 + /* enum: High packet rate TXDP firmware */ 18576 18576 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_HIGH_PACKET_RATE 0x3 18577 18577 + /* enum: Rules engine TXDP firmware */ 18578 18578 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_RULES_ENGINE 0x5 18579 18579 + /* enum: DPDK TXDP firmware */ 18580 18580 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_DPDK 0x6 18581 18581 + /* enum: BIST TXDP firmware */ 18582 18582 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_BIST 0x12d 18583 18583 + /* enum: TXDP Test firmware image 1 */ 18584 18584 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 18585 18585 + /* enum: TXDP Test firmware image 2 */ 18586 18586 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 18587 18587 + /* enum: TXDP CSR bus test firmware */ 18588 18588 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_TEST_FW_CSR 0x103 18589 18589 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_OFST 8 18590 18590 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_LEN 2 18591 18591 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_REV_OFST 8 18592 18592 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_REV_LBN 0 18593 18593 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_REV_WIDTH 12 18594 18594 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_TYPE_OFST 8 18595 18595 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_TYPE_LBN 12 18596 18596 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 18597 18597 + /* enum: reserved value - do not use (may indicate alternative interpretation 18598 18598 + * of REV field in future) 18599 18599 + */ 18600 18600 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_RESERVED 0x0 18601 18601 + /* enum: Trivial RX PD firmware for early Huntington development (Huntington 18602 18602 + * development only) 18603 18603 + */ 18604 18604 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 18605 18605 + /* enum: RX PD firmware for telemetry prototyping (Medford2 development only) 18606 18606 + */ 18607 18607 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 18608 18608 + /* enum: RX PD firmware with approximately Siena-compatible behaviour 18609 18609 + * (Huntington development only) 18610 18610 + */ 18611 18611 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 18612 18612 + /* enum: Full featured RX PD production firmware */ 18613 18613 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 18614 18614 + /* enum: (deprecated original name for the FULL_FEATURED variant) */ 18615 18615 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_VSWITCH 0x3 18616 18616 + /* enum: siena_compat variant RX PD firmware using PM rather than MAC 18617 18617 + * (Huntington development only) 18618 18618 + */ 18619 18619 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 18620 18620 + /* enum: Low latency RX PD production firmware */ 18621 18621 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 18622 18622 + /* enum: Packed stream RX PD production firmware */ 18623 18623 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 18624 18624 + /* enum: RX PD firmware handling layer 2 only for high packet rate performance 18625 18625 + * tests (Medford development only) 18626 18626 + */ 18627 18627 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 18628 18628 + /* enum: Rules engine RX PD production firmware */ 18629 18629 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 18630 18630 + /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 18631 18631 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_L3XUDP 0x9 18632 18632 + /* enum: DPDK RX PD production firmware */ 18633 18633 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_DPDK 0xa 18634 18634 + /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 18635 18635 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 18636 18636 + /* enum: RX PD firmware parsing but not filtering network overlay tunnel 18637 18637 + * encapsulations (Medford development only) 18638 18638 + */ 18639 18639 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 18640 18640 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_OFST 10 18641 18641 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_LEN 2 18642 18642 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_REV_OFST 10 18643 18643 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_REV_LBN 0 18644 18644 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_REV_WIDTH 12 18645 18645 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_TYPE_OFST 10 18646 18646 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_TYPE_LBN 12 18647 18647 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 18648 18648 + /* enum: reserved value - do not use (may indicate alternative interpretation 18649 18649 + * of REV field in future) 18650 18650 + */ 18651 18651 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_RESERVED 0x0 18652 18652 + /* enum: Trivial TX PD firmware for early Huntington development (Huntington 18653 18653 + * development only) 18654 18654 + */ 18655 18655 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 18656 18656 + /* enum: TX PD firmware for telemetry prototyping (Medford2 development only) 18657 18657 + */ 18658 18658 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 18659 18659 + /* enum: TX PD firmware with approximately Siena-compatible behaviour 18660 18660 + * (Huntington development only) 18661 18661 + */ 18662 18662 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 18663 18663 + /* enum: Full featured TX PD production firmware */ 18664 18664 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 18665 18665 + /* enum: (deprecated original name for the FULL_FEATURED variant) */ 18666 18666 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_VSWITCH 0x3 18667 18667 + /* enum: siena_compat variant TX PD firmware using PM rather than MAC 18668 18668 + * (Huntington development only) 18669 18669 + */ 18670 18670 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 18671 18671 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 18672 18672 + /* enum: TX PD firmware handling layer 2 only for high packet rate performance 18673 18673 + * tests (Medford development only) 18674 18674 + */ 18675 18675 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 18676 18676 + /* enum: Rules engine TX PD production firmware */ 18677 18677 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 18678 18678 + /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 18679 18679 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_L3XUDP 0x9 18680 18680 + /* enum: DPDK TX PD production firmware */ 18681 18681 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_DPDK 0xa 18682 18682 + /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 18683 18683 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 18684 18684 + /* Hardware capabilities of NIC */ 18685 18685 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_HW_CAPABILITIES_OFST 12 18686 18686 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_HW_CAPABILITIES_LEN 4 18687 18687 + /* Licensed capabilities */ 18688 18688 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_LICENSE_CAPABILITIES_OFST 16 18689 18689 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_LICENSE_CAPABILITIES_LEN 4 18690 18690 + /* Second word of flags. Not present on older firmware (check the length). */ 18691 18691 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS2_OFST 20 18692 18692 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS2_LEN 4 18693 18693 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_OFST 20 18694 18694 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_LBN 0 18695 18695 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_WIDTH 1 18696 18696 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_ENCAP_OFST 20 18697 18697 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_ENCAP_LBN 1 18698 18698 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_ENCAP_WIDTH 1 18699 18699 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EVQ_TIMER_CTRL_OFST 20 18700 18700 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EVQ_TIMER_CTRL_LBN 2 18701 18701 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EVQ_TIMER_CTRL_WIDTH 1 18702 18702 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EVENT_CUT_THROUGH_OFST 20 18703 18703 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EVENT_CUT_THROUGH_LBN 3 18704 18704 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EVENT_CUT_THROUGH_WIDTH 1 18705 18705 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_CUT_THROUGH_OFST 20 18706 18706 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_CUT_THROUGH_LBN 4 18707 18707 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_CUT_THROUGH_WIDTH 1 18708 18708 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VFIFO_ULL_MODE_OFST 20 18709 18709 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VFIFO_ULL_MODE_LBN 5 18710 18710 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 18711 18711 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20 18712 18712 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 18713 18713 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 18714 18714 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20 18715 18715 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7 18716 18716 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1 18717 18717 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_V2_OFST 20 18718 18718 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_V2_LBN 7 18719 18719 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_V2_WIDTH 1 18720 18720 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_TIMESTAMPING_OFST 20 18721 18721 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_TIMESTAMPING_LBN 8 18722 18722 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 18723 18723 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TIMESTAMP_OFST 20 18724 18724 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TIMESTAMP_LBN 9 18725 18725 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TIMESTAMP_WIDTH 1 18726 18726 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_SNIFF_OFST 20 18727 18727 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_SNIFF_LBN 10 18728 18728 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_SNIFF_WIDTH 1 18729 18729 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_SNIFF_OFST 20 18730 18730 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_SNIFF_LBN 11 18731 18731 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_SNIFF_WIDTH 1 18732 18732 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20 18733 18733 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 18734 18734 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 18735 18735 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_BACKGROUND_OFST 20 18736 18736 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_BACKGROUND_LBN 13 18737 18737 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_BACKGROUND_WIDTH 1 18738 18738 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_DB_RETURN_OFST 20 18739 18739 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_DB_RETURN_LBN 14 18740 18740 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_DB_RETURN_WIDTH 1 18741 18741 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_CTPIO_OFST 20 18742 18742 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_CTPIO_LBN 15 18743 18743 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_CTPIO_WIDTH 1 18744 18744 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_SUPPORT_OFST 20 18745 18745 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_SUPPORT_LBN 16 18746 18746 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_SUPPORT_WIDTH 1 18747 18747 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_BOUND_OFST 20 18748 18748 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_BOUND_LBN 17 18749 18749 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_BOUND_WIDTH 1 18750 18750 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20 18751 18751 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 18752 18752 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 18753 18753 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_FLAG_OFST 20 18754 18754 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_FLAG_LBN 19 18755 18755 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_FLAG_WIDTH 1 18756 18756 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_OFST 20 18757 18757 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_LBN 20 18758 18758 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_WIDTH 1 18759 18759 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20 18760 18760 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 18761 18761 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 18762 18762 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20 18763 18763 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 18764 18764 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 18765 18765 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_L3XUDP_SUPPORT_OFST 20 18766 18766 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_L3XUDP_SUPPORT_LBN 22 18767 18767 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_L3XUDP_SUPPORT_WIDTH 1 18768 18768 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20 18769 18769 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 18770 18770 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 18771 18771 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_SPREADING_OFST 20 18772 18772 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_SPREADING_LBN 24 18773 18773 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_SPREADING_WIDTH 1 18774 18774 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_HLB_IDLE_OFST 20 18775 18775 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_HLB_IDLE_LBN 25 18776 18776 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_HLB_IDLE_WIDTH 1 18777 18777 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_NO_CONT_EV_OFST 20 18778 18778 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_NO_CONT_EV_LBN 26 18779 18779 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1 18780 18780 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20 18781 18781 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27 18782 18782 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1 18783 18783 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_BUNDLE_UPDATE_OFST 20 18784 18784 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_BUNDLE_UPDATE_LBN 28 18785 18785 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_BUNDLE_UPDATE_WIDTH 1 18786 18786 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V3_OFST 20 18787 18787 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V3_LBN 29 18788 18788 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V3_WIDTH 1 18789 18789 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_SENSORS_OFST 20 18790 18790 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_SENSORS_LBN 30 18791 18791 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_SENSORS_WIDTH 1 18792 18792 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20 18793 18793 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31 18794 18794 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1 18795 18795 + /* Number of FATSOv2 contexts per datapath supported by this NIC (when 18796 18796 + * TX_TSO_V2 == 1). Not present on older firmware (check the length). 18797 18797 + */ 18798 18798 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 18799 18799 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 18800 18800 + /* One byte per PF containing the number of the external port assigned to this 18801 18801 + * PF, indexed by PF number. Special values indicate that a PF is either not 18802 18802 + * present or not assigned. 18803 18803 + */ 18804 18804 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 18805 18805 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 18806 18806 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 18807 18807 + /* enum: The caller is not permitted to access information on this PF. */ 18808 18808 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_ACCESS_NOT_PERMITTED 0xff 18809 18809 + /* enum: PF does not exist. */ 18810 18810 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_PF_NOT_PRESENT 0xfe 18811 18811 + /* enum: PF does exist but is not assigned to any external port. */ 18812 18812 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_PF_NOT_ASSIGNED 0xfd 18813 18813 + /* enum: This value indicates that PF is assigned, but it cannot be expressed 18814 18814 + * in this field. It is intended for a possible future situation where a more 18815 18815 + * complex scheme of PFs to ports mapping is being used. The future driver 18816 18816 + * should look for a new field supporting the new scheme. The current/old 18817 18817 + * driver should treat this value as PF_NOT_ASSIGNED. 18818 18818 + */ 18819 18819 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 18820 18820 + /* One byte per PF containing the number of its VFs, indexed by PF number. A 18821 18821 + * special value indicates that a PF is not present. 18822 18822 + */ 18823 18823 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VFS_PER_PF_OFST 42 18824 18824 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VFS_PER_PF_LEN 1 18825 18825 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VFS_PER_PF_NUM 16 18826 18826 + /* enum: The caller is not permitted to access information on this PF. */ 18827 18827 + /* MC_CMD_GET_CAPABILITIES_V11_OUT_ACCESS_NOT_PERMITTED 0xff */ 18828 18828 + /* enum: PF does not exist. */ 18829 18829 + /* MC_CMD_GET_CAPABILITIES_V11_OUT_PF_NOT_PRESENT 0xfe */ 18830 18830 + /* Number of VIs available for external ports 0-3. For devices with more than 18831 18831 + * four ports, the remainder are in NUM_VIS_PER_PORT2 in 18832 18832 + * GET_CAPABILITIES_V12_OUT. 18833 18833 + */ 18834 18834 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VIS_PER_PORT_OFST 58 18835 18835 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VIS_PER_PORT_LEN 2 18836 18836 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VIS_PER_PORT_NUM 4 18837 18837 + /* Size of RX descriptor cache expressed as binary logarithm The actual size 18838 18838 + * equals (2 ^ RX_DESC_CACHE_SIZE) 18839 18839 + */ 18840 18840 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DESC_CACHE_SIZE_OFST 66 18841 18841 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DESC_CACHE_SIZE_LEN 1 18842 18842 + /* Size of TX descriptor cache expressed as binary logarithm The actual size 18843 18843 + * equals (2 ^ TX_DESC_CACHE_SIZE) 18844 18844 + */ 18845 18845 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_DESC_CACHE_SIZE_OFST 67 18846 18846 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_DESC_CACHE_SIZE_LEN 1 18847 18847 + /* Total number of available PIO buffers */ 18848 18848 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_PIO_BUFFS_OFST 68 18849 18849 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_PIO_BUFFS_LEN 2 18850 18850 + /* Size of a single PIO buffer */ 18851 18851 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_SIZE_PIO_BUFF_OFST 70 18852 18852 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_SIZE_PIO_BUFF_LEN 2 18853 18853 + /* On chips later than Medford the amount of address space assigned to each VI 18854 18854 + * is configurable. This is a global setting that the driver must query to 18855 18855 + * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 18856 18856 + * with 8k VI windows. 18857 18857 + */ 18858 18858 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_OFST 72 18859 18859 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_LEN 1 18860 18860 + /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 18861 18861 + * CTPIO is not mapped. 18862 18862 + */ 18863 18863 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_8K 0x0 18864 18864 + /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 18865 18865 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_16K 0x1 18866 18866 + /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 18867 18867 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_64K 0x2 18868 18868 + /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 18869 18869 + * (SF-115995-SW) in the present configuration of firmware and port mode. 18870 18870 + */ 18871 18871 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 18872 18872 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 18873 18873 + /* Number of buffers per adapter that can be used for VFIFO Stuffing 18874 18874 + * (SF-115995-SW) in the present configuration of firmware and port mode. 18875 18875 + */ 18876 18876 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 18877 18877 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 18878 18878 + /* Entry count in the MAC stats array, including the final GENERATION_END 18879 18879 + * entry. For MAC stats DMA, drivers should allocate a buffer large enough to 18880 18880 + * hold at least this many 64-bit stats values, if they wish to receive all 18881 18881 + * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the 18882 18882 + * stats array returned will be truncated. 18883 18883 + */ 18884 18884 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_NUM_STATS_OFST 76 18885 18885 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_NUM_STATS_LEN 2 18886 18886 + /* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field 18887 18887 + * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set. 18888 18888 + */ 18889 18889 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_MAX_OFST 80 18890 18890 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_MAX_LEN 4 18891 18891 + /* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in 18892 18892 + * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when 18893 18893 + * they create an RX queue. Due to hardware limitations, only a small number of 18894 18894 + * different buffer sizes may be available concurrently. Nonzero entries in 18895 18895 + * this array are the sizes of buffers which the system guarantees will be 18896 18896 + * available for use. If the list is empty, there are no limitations on 18897 18897 + * concurrent buffer sizes. 18898 18898 + */ 18899 18899 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84 18900 18900 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4 18901 18901 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16 18902 18902 + /* Third word of flags. Not present on older firmware (check the length). */ 18903 18903 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS3_OFST 148 18904 18904 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS3_LEN 4 18905 18905 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_WOL_ETHERWAKE_OFST 148 18906 18906 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_WOL_ETHERWAKE_LBN 0 18907 18907 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_WOL_ETHERWAKE_WIDTH 1 18908 18908 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_EVEN_SPREADING_OFST 148 18909 18909 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_EVEN_SPREADING_LBN 1 18910 18910 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_EVEN_SPREADING_WIDTH 1 18911 18911 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148 18912 18912 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2 18913 18913 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1 18914 18914 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_SUPPORTED_OFST 148 18915 18915 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_SUPPORTED_LBN 3 18916 18916 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_SUPPORTED_WIDTH 1 18917 18917 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VDPA_SUPPORTED_OFST 148 18918 18918 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VDPA_SUPPORTED_LBN 4 18919 18919 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_VDPA_SUPPORTED_WIDTH 1 18920 18920 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148 18921 18921 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5 18922 18922 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1 18923 18923 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148 18924 18924 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6 18925 18925 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1 18926 18926 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148 18927 18927 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7 18928 18928 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1 18929 18929 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148 18930 18930 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8 18931 18931 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1 18932 18932 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148 18933 18933 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9 18934 18934 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1 18935 18935 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148 18936 18936 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10 18937 18937 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1 18938 18938 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148 18939 18939 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11 18940 18940 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1 18941 18941 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148 18942 18942 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12 18943 18943 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1 18944 18944 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_OFST 148 18945 18945 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_LBN 13 18946 18946 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_WIDTH 1 18947 18947 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148 18948 18948 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14 18949 18949 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1 18950 18950 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_CLIENT_CMD_VF_PROXY_OFST 148 18951 18951 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_CLIENT_CMD_VF_PROXY_LBN 15 18952 18952 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1 18953 18953 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148 18954 18954 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16 18955 18955 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1 18956 18956 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_CXL_CONFIG_ENABLE_OFST 148 18957 18957 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_CXL_CONFIG_ENABLE_LBN 17 18958 18958 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_CXL_CONFIG_ENABLE_WIDTH 1 18959 18959 + /* These bits are reserved for communicating test-specific capabilities to 18960 18960 + * host-side test software. All production drivers should treat this field as 18961 18961 + * opaque. 18962 18962 + */ 18963 18963 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_OFST 152 18964 18964 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LEN 8 18965 18965 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LO_OFST 152 18966 18966 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LO_LEN 4 18967 18967 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LO_LBN 1216 18968 18968 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LO_WIDTH 32 18969 18969 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_HI_OFST 156 18970 18970 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_HI_LEN 4 18971 18971 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_HI_LBN 1248 18972 18972 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_HI_WIDTH 32 18973 18973 + /* The minimum size (in table entries) of indirection table to be allocated 18974 18974 + * from the pool for an RSS context. Note that the table size used must be a 18975 18975 + * power of 2. 18976 18976 + */ 18977 18977 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 160 18978 18978 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4 18979 18979 + /* The maximum size (in table entries) of indirection table to be allocated 18980 18980 + * from the pool for an RSS context. Note that the table size used must be a 18981 18981 + * power of 2. 18982 18982 + */ 18983 18983 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 164 18984 18984 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4 18985 18985 + /* The maximum number of queues that can be used by an RSS context in exclusive 18986 18986 + * mode. In exclusive mode the context has a configurable indirection table and 18987 18987 + * a configurable RSS key. 18988 18988 + */ 18989 18989 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 168 18990 18990 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4 18991 18991 + /* The maximum number of queues that can be used by an RSS context in even- 18992 18992 + * spreading mode. In even-spreading mode the context has no indirection table 18993 18993 + * but it does have a configurable RSS key. 18994 18994 + */ 18995 18995 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 172 18996 18996 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4 18997 18997 + /* The total number of RSS contexts supported. Note that the number of 18998 18998 + * available contexts using indirection tables is also limited by the 18999 18999 + * availability of indirection table space allocated from a common pool. 19000 19000 + */ 19001 19001 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_NUM_CONTEXTS_OFST 176 19002 19002 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_NUM_CONTEXTS_LEN 4 19003 19003 + /* The total amount of indirection table space that can be shared between RSS 19004 19004 + * contexts. 19005 19005 + */ 19006 19006 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_TABLE_POOL_SIZE_OFST 180 19007 19007 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_TABLE_POOL_SIZE_LEN 4 19008 19008 + /* A bitmap of the queue sizes the device can provide, where bit N being set 19009 19009 + * indicates that 2**N is a valid size. The device may be limited in the number 19010 19010 + * of different queue sizes that can exist simultaneously, so a bit being set 19011 19011 + * here does not guarantee that an attempt to create a queue of that size will 19012 19012 + * succeed. 19013 19013 + */ 19014 19014 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_SUPPORTED_QUEUE_SIZES_OFST 184 19015 19015 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_SUPPORTED_QUEUE_SIZES_LEN 4 19016 19016 + /* A bitmap of queue sizes that are always available, in the same format as 19017 19017 + * SUPPORTED_QUEUE_SIZES. Attempting to create a queue with one of these sizes 19018 19018 + * will never fail due to unavailability of the requested size. 19019 19019 + */ 19020 19020 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_QUEUE_SIZES_OFST 188 19021 19021 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_QUEUE_SIZES_LEN 4 19022 19022 + /* Number of available indirect memory maps. */ 19023 19023 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_INDIRECT_MAP_INDEX_COUNT_OFST 192 19024 19024 + #define MC_CMD_GET_CAPABILITIES_V11_OUT_INDIRECT_MAP_INDEX_COUNT_LEN 4 19025 19025 + 19026 19026 + /* MC_CMD_GET_CAPABILITIES_V12_OUT msgresponse */ 19027 19027 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_LEN 204 19028 19028 + /* First word of flags. */ 19029 19029 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS1_OFST 0 19030 19030 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS1_LEN 4 19031 19031 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VPORT_RECONFIGURE_OFST 0 19032 19032 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VPORT_RECONFIGURE_LBN 3 19033 19033 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VPORT_RECONFIGURE_WIDTH 1 19034 19034 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_STRIPING_OFST 0 19035 19035 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_STRIPING_LBN 4 19036 19036 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_STRIPING_WIDTH 1 19037 19037 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_QUERY_OFST 0 19038 19038 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_QUERY_LBN 5 19039 19039 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_QUERY_WIDTH 1 19040 19040 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0 19041 19041 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 19042 19042 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 19043 19043 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_DRV_ATTACH_PREBOOT_OFST 0 19044 19044 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_DRV_ATTACH_PREBOOT_LBN 7 19045 19045 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 19046 19046 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_FORCE_EVENT_MERGING_OFST 0 19047 19047 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_FORCE_EVENT_MERGING_LBN 8 19048 19048 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 19049 19049 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_SET_MAC_ENHANCED_OFST 0 19050 19050 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_SET_MAC_ENHANCED_LBN 9 19051 19051 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_SET_MAC_ENHANCED_WIDTH 1 19052 19052 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0 19053 19053 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 19054 19054 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 19055 19055 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0 19056 19056 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 19057 19057 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 19058 19058 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_SECURITY_FILTERING_OFST 0 19059 19059 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 19060 19060 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 19061 19061 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_ADDITIONAL_RSS_MODES_OFST 0 19062 19062 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_ADDITIONAL_RSS_MODES_LBN 13 19063 19063 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 19064 19064 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_QBB_OFST 0 19065 19065 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_QBB_LBN 14 19066 19066 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_QBB_WIDTH 1 19067 19067 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0 19068 19068 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 19069 19069 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 19070 19070 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_RSS_LIMITED_OFST 0 19071 19071 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_RSS_LIMITED_LBN 16 19072 19072 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_RSS_LIMITED_WIDTH 1 19073 19073 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_OFST 0 19074 19074 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_LBN 17 19075 19075 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_WIDTH 1 19076 19076 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_INCLUDE_FCS_OFST 0 19077 19077 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_INCLUDE_FCS_LBN 18 19078 19078 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_INCLUDE_FCS_WIDTH 1 19079 19079 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VLAN_INSERTION_OFST 0 19080 19080 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VLAN_INSERTION_LBN 19 19081 19081 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VLAN_INSERTION_WIDTH 1 19082 19082 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_OFST 0 19083 19083 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_LBN 20 19084 19084 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_WIDTH 1 19085 19085 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_OFST 0 19086 19086 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_LBN 21 19087 19087 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_WIDTH 1 19088 19088 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_0_OFST 0 19089 19089 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_0_LBN 22 19090 19090 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_0_WIDTH 1 19091 19091 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_14_OFST 0 19092 19092 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_14_LBN 23 19093 19093 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_14_WIDTH 1 19094 19094 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_TIMESTAMP_OFST 0 19095 19095 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_TIMESTAMP_LBN 24 19096 19096 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_TIMESTAMP_WIDTH 1 19097 19097 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_BATCHING_OFST 0 19098 19098 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_BATCHING_LBN 25 19099 19099 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_BATCHING_WIDTH 1 19100 19100 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MCAST_FILTER_CHAINING_OFST 0 19101 19101 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MCAST_FILTER_CHAINING_LBN 26 19102 19102 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MCAST_FILTER_CHAINING_WIDTH 1 19103 19103 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_PM_AND_RXDP_COUNTERS_OFST 0 19104 19104 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_PM_AND_RXDP_COUNTERS_LBN 27 19105 19105 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 19106 19106 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DISABLE_SCATTER_OFST 0 19107 19107 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DISABLE_SCATTER_LBN 28 19108 19108 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DISABLE_SCATTER_WIDTH 1 19109 19109 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0 19110 19110 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 19111 19111 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 19112 19112 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_OFST 0 19113 19113 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_LBN 30 19114 19114 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_WIDTH 1 19115 19115 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VXLAN_NVGRE_OFST 0 19116 19116 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VXLAN_NVGRE_LBN 31 19117 19117 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VXLAN_NVGRE_WIDTH 1 19118 19118 + /* RxDPCPU firmware id. */ 19119 19119 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DPCPU_FW_ID_OFST 4 19120 19120 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DPCPU_FW_ID_LEN 2 19121 19121 + /* enum: Standard RXDP firmware */ 19122 19122 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP 0x0 19123 19123 + /* enum: Low latency RXDP firmware */ 19124 19124 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_LOW_LATENCY 0x1 19125 19125 + /* enum: Packed stream RXDP firmware */ 19126 19126 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_PACKED_STREAM 0x2 19127 19127 + /* enum: Rules engine RXDP firmware */ 19128 19128 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_RULES_ENGINE 0x5 19129 19129 + /* enum: DPDK RXDP firmware */ 19130 19130 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_DPDK 0x6 19131 19131 + /* enum: BIST RXDP firmware */ 19132 19132 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_BIST 0x10a 19133 19133 + /* enum: RXDP Test firmware image 1 */ 19134 19134 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 19135 19135 + /* enum: RXDP Test firmware image 2 */ 19136 19136 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 19137 19137 + /* enum: RXDP Test firmware image 3 */ 19138 19138 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 19139 19139 + /* enum: RXDP Test firmware image 4 */ 19140 19140 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 19141 19141 + /* enum: RXDP Test firmware image 5 */ 19142 19142 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_BACKPRESSURE 0x105 19143 19143 + /* enum: RXDP Test firmware image 6 */ 19144 19144 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 19145 19145 + /* enum: RXDP Test firmware image 7 */ 19146 19146 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 19147 19147 + /* enum: RXDP Test firmware image 8 */ 19148 19148 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 19149 19149 + /* enum: RXDP Test firmware image 9 */ 19150 19150 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 19151 19151 + /* enum: RXDP Test firmware image 10 */ 19152 19152 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_SLOW 0x10c 19153 19153 + /* TxDPCPU firmware id. */ 19154 19154 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_DPCPU_FW_ID_OFST 6 19155 19155 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_DPCPU_FW_ID_LEN 2 19156 19156 + /* enum: Standard TXDP firmware */ 19157 19157 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP 0x0 19158 19158 + /* enum: Low latency TXDP firmware */ 19159 19159 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_LOW_LATENCY 0x1 19160 19160 + /* enum: High packet rate TXDP firmware */ 19161 19161 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_HIGH_PACKET_RATE 0x3 19162 19162 + /* enum: Rules engine TXDP firmware */ 19163 19163 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_RULES_ENGINE 0x5 19164 19164 + /* enum: DPDK TXDP firmware */ 19165 19165 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_DPDK 0x6 19166 19166 + /* enum: BIST TXDP firmware */ 19167 19167 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_BIST 0x12d 19168 19168 + /* enum: TXDP Test firmware image 1 */ 19169 19169 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 19170 19170 + /* enum: TXDP Test firmware image 2 */ 19171 19171 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 19172 19172 + /* enum: TXDP CSR bus test firmware */ 19173 19173 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_TEST_FW_CSR 0x103 19174 19174 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_OFST 8 19175 19175 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_LEN 2 19176 19176 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_REV_OFST 8 19177 19177 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_REV_LBN 0 19178 19178 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_REV_WIDTH 12 19179 19179 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_TYPE_OFST 8 19180 19180 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_TYPE_LBN 12 19181 19181 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 19182 19182 + /* enum: reserved value - do not use (may indicate alternative interpretation 19183 19183 + * of REV field in future) 19184 19184 + */ 19185 19185 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_RESERVED 0x0 19186 19186 + /* enum: Trivial RX PD firmware for early Huntington development (Huntington 19187 19187 + * development only) 19188 19188 + */ 19189 19189 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 19190 19190 + /* enum: RX PD firmware for telemetry prototyping (Medford2 development only) 19191 19191 + */ 19192 19192 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 19193 19193 + /* enum: RX PD firmware with approximately Siena-compatible behaviour 19194 19194 + * (Huntington development only) 19195 19195 + */ 19196 19196 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 19197 19197 + /* enum: Full featured RX PD production firmware */ 19198 19198 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 19199 19199 + /* enum: (deprecated original name for the FULL_FEATURED variant) */ 19200 19200 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_VSWITCH 0x3 19201 19201 + /* enum: siena_compat variant RX PD firmware using PM rather than MAC 19202 19202 + * (Huntington development only) 19203 19203 + */ 19204 19204 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 19205 19205 + /* enum: Low latency RX PD production firmware */ 19206 19206 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 19207 19207 + /* enum: Packed stream RX PD production firmware */ 19208 19208 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 19209 19209 + /* enum: RX PD firmware handling layer 2 only for high packet rate performance 19210 19210 + * tests (Medford development only) 19211 19211 + */ 19212 19212 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 19213 19213 + /* enum: Rules engine RX PD production firmware */ 19214 19214 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 19215 19215 + /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 19216 19216 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_L3XUDP 0x9 19217 19217 + /* enum: DPDK RX PD production firmware */ 19218 19218 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_DPDK 0xa 19219 19219 + /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 19220 19220 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 19221 19221 + /* enum: RX PD firmware parsing but not filtering network overlay tunnel 19222 19222 + * encapsulations (Medford development only) 19223 19223 + */ 19224 19224 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 19225 19225 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_OFST 10 19226 19226 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_LEN 2 19227 19227 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_REV_OFST 10 19228 19228 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_REV_LBN 0 19229 19229 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_REV_WIDTH 12 19230 19230 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_TYPE_OFST 10 19231 19231 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_TYPE_LBN 12 19232 19232 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 19233 19233 + /* enum: reserved value - do not use (may indicate alternative interpretation 19234 19234 + * of REV field in future) 19235 19235 + */ 19236 19236 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_RESERVED 0x0 19237 19237 + /* enum: Trivial TX PD firmware for early Huntington development (Huntington 19238 19238 + * development only) 19239 19239 + */ 19240 19240 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 19241 19241 + /* enum: TX PD firmware for telemetry prototyping (Medford2 development only) 19242 19242 + */ 19243 19243 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 19244 19244 + /* enum: TX PD firmware with approximately Siena-compatible behaviour 19245 19245 + * (Huntington development only) 19246 19246 + */ 19247 19247 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 19248 19248 + /* enum: Full featured TX PD production firmware */ 19249 19249 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 19250 19250 + /* enum: (deprecated original name for the FULL_FEATURED variant) */ 19251 19251 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_VSWITCH 0x3 19252 19252 + /* enum: siena_compat variant TX PD firmware using PM rather than MAC 19253 19253 + * (Huntington development only) 19254 19254 + */ 19255 19255 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 19256 19256 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 19257 19257 + /* enum: TX PD firmware handling layer 2 only for high packet rate performance 19258 19258 + * tests (Medford development only) 19259 19259 + */ 19260 19260 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 19261 19261 + /* enum: Rules engine TX PD production firmware */ 19262 19262 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 19263 19263 + /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 19264 19264 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_L3XUDP 0x9 19265 19265 + /* enum: DPDK TX PD production firmware */ 19266 19266 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_DPDK 0xa 19267 19267 + /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 19268 19268 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 19269 19269 + /* Hardware capabilities of NIC */ 19270 19270 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_HW_CAPABILITIES_OFST 12 19271 19271 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_HW_CAPABILITIES_LEN 4 19272 19272 + /* Licensed capabilities */ 19273 19273 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_LICENSE_CAPABILITIES_OFST 16 19274 19274 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_LICENSE_CAPABILITIES_LEN 4 19275 19275 + /* Second word of flags. Not present on older firmware (check the length). */ 19276 19276 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS2_OFST 20 19277 19277 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS2_LEN 4 19278 19278 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_OFST 20 19279 19279 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_LBN 0 19280 19280 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_WIDTH 1 19281 19281 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_ENCAP_OFST 20 19282 19282 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_ENCAP_LBN 1 19283 19283 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_ENCAP_WIDTH 1 19284 19284 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EVQ_TIMER_CTRL_OFST 20 19285 19285 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EVQ_TIMER_CTRL_LBN 2 19286 19286 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EVQ_TIMER_CTRL_WIDTH 1 19287 19287 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EVENT_CUT_THROUGH_OFST 20 19288 19288 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EVENT_CUT_THROUGH_LBN 3 19289 19289 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EVENT_CUT_THROUGH_WIDTH 1 19290 19290 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_CUT_THROUGH_OFST 20 19291 19291 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_CUT_THROUGH_LBN 4 19292 19292 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_CUT_THROUGH_WIDTH 1 19293 19293 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VFIFO_ULL_MODE_OFST 20 19294 19294 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VFIFO_ULL_MODE_LBN 5 19295 19295 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 19296 19296 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20 19297 19297 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 19298 19298 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 19299 19299 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20 19300 19300 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7 19301 19301 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1 19302 19302 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_V2_OFST 20 19303 19303 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_V2_LBN 7 19304 19304 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_V2_WIDTH 1 19305 19305 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_TIMESTAMPING_OFST 20 19306 19306 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_TIMESTAMPING_LBN 8 19307 19307 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 19308 19308 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TIMESTAMP_OFST 20 19309 19309 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TIMESTAMP_LBN 9 19310 19310 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TIMESTAMP_WIDTH 1 19311 19311 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_SNIFF_OFST 20 19312 19312 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_SNIFF_LBN 10 19313 19313 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_SNIFF_WIDTH 1 19314 19314 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_SNIFF_OFST 20 19315 19315 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_SNIFF_LBN 11 19316 19316 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_SNIFF_WIDTH 1 19317 19317 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20 19318 19318 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 19319 19319 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 19320 19320 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_BACKGROUND_OFST 20 19321 19321 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_BACKGROUND_LBN 13 19322 19322 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_BACKGROUND_WIDTH 1 19323 19323 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_DB_RETURN_OFST 20 19324 19324 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_DB_RETURN_LBN 14 19325 19325 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_DB_RETURN_WIDTH 1 19326 19326 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_CTPIO_OFST 20 19327 19327 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_CTPIO_LBN 15 19328 19328 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_CTPIO_WIDTH 1 19329 19329 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_SUPPORT_OFST 20 19330 19330 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_SUPPORT_LBN 16 19331 19331 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_SUPPORT_WIDTH 1 19332 19332 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_BOUND_OFST 20 19333 19333 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_BOUND_LBN 17 19334 19334 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_BOUND_WIDTH 1 19335 19335 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20 19336 19336 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 19337 19337 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 19338 19338 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_FLAG_OFST 20 19339 19339 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_FLAG_LBN 19 19340 19340 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_FLAG_WIDTH 1 19341 19341 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_OFST 20 19342 19342 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_LBN 20 19343 19343 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_WIDTH 1 19344 19344 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20 19345 19345 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 19346 19346 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 19347 19347 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20 19348 19348 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 19349 19349 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 19350 19350 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_L3XUDP_SUPPORT_OFST 20 19351 19351 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_L3XUDP_SUPPORT_LBN 22 19352 19352 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_L3XUDP_SUPPORT_WIDTH 1 19353 19353 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20 19354 19354 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 19355 19355 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 19356 19356 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_SPREADING_OFST 20 19357 19357 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_SPREADING_LBN 24 19358 19358 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_SPREADING_WIDTH 1 19359 19359 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_HLB_IDLE_OFST 20 19360 19360 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_HLB_IDLE_LBN 25 19361 19361 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_HLB_IDLE_WIDTH 1 19362 19362 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_NO_CONT_EV_OFST 20 19363 19363 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_NO_CONT_EV_LBN 26 19364 19364 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1 19365 19365 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20 19366 19366 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27 19367 19367 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1 19368 19368 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_BUNDLE_UPDATE_OFST 20 19369 19369 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_BUNDLE_UPDATE_LBN 28 19370 19370 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_BUNDLE_UPDATE_WIDTH 1 19371 19371 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V3_OFST 20 19372 19372 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V3_LBN 29 19373 19373 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V3_WIDTH 1 19374 19374 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_SENSORS_OFST 20 19375 19375 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_SENSORS_LBN 30 19376 19376 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_SENSORS_WIDTH 1 19377 19377 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20 19378 19378 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31 19379 19379 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1 19380 19380 + /* Number of FATSOv2 contexts per datapath supported by this NIC (when 19381 19381 + * TX_TSO_V2 == 1). Not present on older firmware (check the length). 19382 19382 + */ 19383 19383 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 19384 19384 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 19385 19385 + /* One byte per PF containing the number of the external port assigned to this 19386 19386 + * PF, indexed by PF number. Special values indicate that a PF is either not 19387 19387 + * present or not assigned. 19388 19388 + */ 19389 19389 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 19390 19390 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 19391 19391 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 19392 19392 + /* enum: The caller is not permitted to access information on this PF. */ 19393 19393 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_ACCESS_NOT_PERMITTED 0xff 19394 19394 + /* enum: PF does not exist. */ 19395 19395 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_PF_NOT_PRESENT 0xfe 19396 19396 + /* enum: PF does exist but is not assigned to any external port. */ 19397 19397 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_PF_NOT_ASSIGNED 0xfd 19398 19398 + /* enum: This value indicates that PF is assigned, but it cannot be expressed 19399 19399 + * in this field. It is intended for a possible future situation where a more 19400 19400 + * complex scheme of PFs to ports mapping is being used. The future driver 19401 19401 + * should look for a new field supporting the new scheme. The current/old 19402 19402 + * driver should treat this value as PF_NOT_ASSIGNED. 19403 19403 + */ 19404 19404 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 19405 19405 + /* One byte per PF containing the number of its VFs, indexed by PF number. A 19406 19406 + * special value indicates that a PF is not present. 19407 19407 + */ 19408 19408 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VFS_PER_PF_OFST 42 19409 19409 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VFS_PER_PF_LEN 1 19410 19410 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VFS_PER_PF_NUM 16 19411 19411 + /* enum: The caller is not permitted to access information on this PF. */ 19412 19412 + /* MC_CMD_GET_CAPABILITIES_V12_OUT_ACCESS_NOT_PERMITTED 0xff */ 19413 19413 + /* enum: PF does not exist. */ 19414 19414 + /* MC_CMD_GET_CAPABILITIES_V12_OUT_PF_NOT_PRESENT 0xfe */ 19415 19415 + /* Number of VIs available for external ports 0-3. For devices with more than 19416 19416 + * four ports, the remainder are in NUM_VIS_PER_PORT2 in 19417 19417 + * GET_CAPABILITIES_V12_OUT. 19418 19418 + */ 19419 19419 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT_OFST 58 19420 19420 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT_LEN 2 19421 19421 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT_NUM 4 19422 19422 + /* Size of RX descriptor cache expressed as binary logarithm The actual size 19423 19423 + * equals (2 ^ RX_DESC_CACHE_SIZE) 19424 19424 + */ 19425 19425 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DESC_CACHE_SIZE_OFST 66 19426 19426 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DESC_CACHE_SIZE_LEN 1 19427 19427 + /* Size of TX descriptor cache expressed as binary logarithm The actual size 19428 19428 + * equals (2 ^ TX_DESC_CACHE_SIZE) 19429 19429 + */ 19430 19430 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_DESC_CACHE_SIZE_OFST 67 19431 19431 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_DESC_CACHE_SIZE_LEN 1 19432 19432 + /* Total number of available PIO buffers */ 19433 19433 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_PIO_BUFFS_OFST 68 19434 19434 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_PIO_BUFFS_LEN 2 19435 19435 + /* Size of a single PIO buffer */ 19436 19436 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_SIZE_PIO_BUFF_OFST 70 19437 19437 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_SIZE_PIO_BUFF_LEN 2 19438 19438 + /* On chips later than Medford the amount of address space assigned to each VI 19439 19439 + * is configurable. This is a global setting that the driver must query to 19440 19440 + * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 19441 19441 + * with 8k VI windows. 19442 19442 + */ 19443 19443 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_OFST 72 19444 19444 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_LEN 1 19445 19445 + /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 19446 19446 + * CTPIO is not mapped. 19447 19447 + */ 19448 19448 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_8K 0x0 19449 19449 + /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 19450 19450 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_16K 0x1 19451 19451 + /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 19452 19452 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_64K 0x2 19453 19453 + /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 19454 19454 + * (SF-115995-SW) in the present configuration of firmware and port mode. 19455 19455 + */ 19456 19456 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 19457 19457 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 19458 19458 + /* Number of buffers per adapter that can be used for VFIFO Stuffing 19459 19459 + * (SF-115995-SW) in the present configuration of firmware and port mode. 19460 19460 + */ 19461 19461 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 19462 19462 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 19463 19463 + /* Entry count in the MAC stats array, including the final GENERATION_END 19464 19464 + * entry. For MAC stats DMA, drivers should allocate a buffer large enough to 19465 19465 + * hold at least this many 64-bit stats values, if they wish to receive all 19466 19466 + * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the 19467 19467 + * stats array returned will be truncated. 19468 19468 + */ 19469 19469 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_NUM_STATS_OFST 76 19470 19470 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_NUM_STATS_LEN 2 19471 19471 + /* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field 19472 19472 + * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set. 19473 19473 + */ 19474 19474 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_MAX_OFST 80 19475 19475 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_MAX_LEN 4 19476 19476 + /* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in 19477 19477 + * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when 19478 19478 + * they create an RX queue. Due to hardware limitations, only a small number of 19479 19479 + * different buffer sizes may be available concurrently. Nonzero entries in 19480 19480 + * this array are the sizes of buffers which the system guarantees will be 19481 19481 + * available for use. If the list is empty, there are no limitations on 19482 19482 + * concurrent buffer sizes. 19483 19483 + */ 19484 19484 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84 19485 19485 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4 19486 19486 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16 19487 19487 + /* Third word of flags. Not present on older firmware (check the length). */ 19488 19488 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS3_OFST 148 19489 19489 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS3_LEN 4 19490 19490 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_WOL_ETHERWAKE_OFST 148 19491 19491 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_WOL_ETHERWAKE_LBN 0 19492 19492 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_WOL_ETHERWAKE_WIDTH 1 19493 19493 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_EVEN_SPREADING_OFST 148 19494 19494 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_EVEN_SPREADING_LBN 1 19495 19495 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_EVEN_SPREADING_WIDTH 1 19496 19496 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148 19497 19497 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2 19498 19498 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1 19499 19499 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_SUPPORTED_OFST 148 19500 19500 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_SUPPORTED_LBN 3 19501 19501 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_SUPPORTED_WIDTH 1 19502 19502 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VDPA_SUPPORTED_OFST 148 19503 19503 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VDPA_SUPPORTED_LBN 4 19504 19504 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_VDPA_SUPPORTED_WIDTH 1 19505 19505 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148 19506 19506 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5 19507 19507 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1 19508 19508 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148 19509 19509 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6 19510 19510 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1 19511 19511 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148 19512 19512 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7 19513 19513 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1 19514 19514 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148 19515 19515 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8 19516 19516 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1 19517 19517 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148 19518 19518 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9 19519 19519 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1 19520 19520 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148 19521 19521 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10 19522 19522 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1 19523 19523 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148 19524 19524 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11 19525 19525 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1 19526 19526 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148 19527 19527 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12 19528 19528 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1 19529 19529 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_OFST 148 19530 19530 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_LBN 13 19531 19531 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_WIDTH 1 19532 19532 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148 19533 19533 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14 19534 19534 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1 19535 19535 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_CLIENT_CMD_VF_PROXY_OFST 148 19536 19536 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_CLIENT_CMD_VF_PROXY_LBN 15 19537 19537 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1 19538 19538 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148 19539 19539 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16 19540 19540 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1 19541 19541 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_CXL_CONFIG_ENABLE_OFST 148 19542 19542 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_CXL_CONFIG_ENABLE_LBN 17 19543 19543 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_CXL_CONFIG_ENABLE_WIDTH 1 19544 19544 + /* These bits are reserved for communicating test-specific capabilities to 19545 19545 + * host-side test software. All production drivers should treat this field as 19546 19546 + * opaque. 19547 19547 + */ 19548 19548 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_OFST 152 19549 19549 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LEN 8 19550 19550 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LO_OFST 152 19551 19551 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LO_LEN 4 19552 19552 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LO_LBN 1216 19553 19553 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LO_WIDTH 32 19554 19554 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_HI_OFST 156 19555 19555 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_HI_LEN 4 19556 19556 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_HI_LBN 1248 19557 19557 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_HI_WIDTH 32 19558 19558 + /* The minimum size (in table entries) of indirection table to be allocated 19559 19559 + * from the pool for an RSS context. Note that the table size used must be a 19560 19560 + * power of 2. 19561 19561 + */ 19562 19562 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 160 19563 19563 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4 19564 19564 + /* The maximum size (in table entries) of indirection table to be allocated 19565 19565 + * from the pool for an RSS context. Note that the table size used must be a 19566 19566 + * power of 2. 19567 19567 + */ 19568 19568 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 164 19569 19569 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4 19570 19570 + /* The maximum number of queues that can be used by an RSS context in exclusive 19571 19571 + * mode. In exclusive mode the context has a configurable indirection table and 19572 19572 + * a configurable RSS key. 19573 19573 + */ 19574 19574 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 168 19575 19575 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4 19576 19576 + /* The maximum number of queues that can be used by an RSS context in even- 19577 19577 + * spreading mode. In even-spreading mode the context has no indirection table 19578 19578 + * but it does have a configurable RSS key. 19579 19579 + */ 19580 19580 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 172 19581 19581 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4 19582 19582 + /* The total number of RSS contexts supported. Note that the number of 19583 19583 + * available contexts using indirection tables is also limited by the 19584 19584 + * availability of indirection table space allocated from a common pool. 19585 19585 + */ 19586 19586 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_NUM_CONTEXTS_OFST 176 19587 19587 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_NUM_CONTEXTS_LEN 4 19588 19588 + /* The total amount of indirection table space that can be shared between RSS 19589 19589 + * contexts. 19590 19590 + */ 19591 19591 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_TABLE_POOL_SIZE_OFST 180 19592 19592 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_TABLE_POOL_SIZE_LEN 4 19593 19593 + /* A bitmap of the queue sizes the device can provide, where bit N being set 19594 19594 + * indicates that 2**N is a valid size. The device may be limited in the number 19595 19595 + * of different queue sizes that can exist simultaneously, so a bit being set 19596 19596 + * here does not guarantee that an attempt to create a queue of that size will 19597 19597 + * succeed. 19598 19598 + */ 19599 19599 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_SUPPORTED_QUEUE_SIZES_OFST 184 19600 19600 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_SUPPORTED_QUEUE_SIZES_LEN 4 19601 19601 + /* A bitmap of queue sizes that are always available, in the same format as 19602 19602 + * SUPPORTED_QUEUE_SIZES. Attempting to create a queue with one of these sizes 19603 19603 + * will never fail due to unavailability of the requested size. 19604 19604 + */ 19605 19605 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_QUEUE_SIZES_OFST 188 19606 19606 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_QUEUE_SIZES_LEN 4 19607 19607 + /* Number of available indirect memory maps. */ 19608 19608 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_INDIRECT_MAP_INDEX_COUNT_OFST 192 19609 19609 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_INDIRECT_MAP_INDEX_COUNT_LEN 4 19610 19610 + /* Number of VIs available for external ports 4-7. Information for ports 0-3 is 19611 19611 + * in NUM_VIS_PER_PORT in GET_CAPABILITIES_V2_OUT. 19612 19612 + */ 19613 19613 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT2_OFST 196 19614 19614 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT2_LEN 2 19615 19615 + #define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT2_NUM 4 19616 19616 + 18276 19617 18277 19618 /***********************************/ 18278 19619 /* MC_CMD_V2_EXTN ··· 19479 18468 * are not defined. 19480 18469 */ 19481 18470 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1 19482 19482 - 19483 19483 - 19484 19484 - /***********************************/ 19485 19485 - /* MC_CMD_TCM_BUCKET_ALLOC 19486 19486 - * Allocate a pacer bucket (for qau rp or a snapper test) 18471 18471 + /* enum: MCDI command used for platform management. Typically, these commands 18472 18472 + * are used for low-level operations directed at the platform as a whole (e.g. 18473 18473 + * MMIO device enumeration) rather than individual functions and use a 18474 18474 + * dedicated comms channel (e.g. RPmsg/IPI). May be handled by the same or 18475 18475 + * different CPU as MCDI_MESSAGE_TYPE_MC. 19487 18476 */ 19488 19488 - #define MC_CMD_TCM_BUCKET_ALLOC 0xb2 19489 19489 - #undef MC_CMD_0xb2_PRIVILEGE_CTG 19490 19490 - 19491 19491 - #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 19492 19492 - 19493 19493 - /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ 19494 19494 - #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 19495 19495 - 19496 19496 - /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ 19497 19497 - #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 19498 19498 - /* the bucket id */ 19499 19499 - #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 19500 19500 - #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 4 19501 19501 - 19502 19502 - 19503 19503 - /***********************************/ 19504 19504 - /* MC_CMD_TCM_BUCKET_FREE 19505 19505 - * Free a pacer bucket 19506 19506 - */ 19507 19507 - #define MC_CMD_TCM_BUCKET_FREE 0xb3 19508 19508 - #undef MC_CMD_0xb3_PRIVILEGE_CTG 19509 19509 - 19510 19510 - #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 19511 19511 - 19512 19512 - /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ 19513 19513 - #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 19514 19514 - /* the bucket id */ 19515 19515 - #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 19516 19516 - #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_LEN 4 19517 19517 - 19518 19518 - /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ 19519 19519 - #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 19520 19520 - 19521 19521 - 19522 19522 - /***********************************/ 19523 19523 - /* MC_CMD_TCM_BUCKET_INIT 19524 19524 - * Initialise pacer bucket with a given rate 19525 19525 - */ 19526 19526 - #define MC_CMD_TCM_BUCKET_INIT 0xb4 19527 19527 - #undef MC_CMD_0xb4_PRIVILEGE_CTG 19528 19528 - 19529 19529 - #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 19530 19530 - 19531 19531 - /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ 19532 19532 - #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 19533 19533 - /* the bucket id */ 19534 19534 - #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 19535 19535 - #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_LEN 4 19536 19536 - /* the rate in mbps */ 19537 19537 - #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 19538 19538 - #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_LEN 4 19539 19539 - 19540 19540 - /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */ 19541 19541 - #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12 19542 19542 - /* the bucket id */ 19543 19543 - #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0 19544 19544 - #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_LEN 4 19545 19545 - /* the rate in mbps */ 19546 19546 - #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4 19547 19547 - #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_LEN 4 19548 19548 - /* the desired maximum fill level */ 19549 19549 - #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8 19550 19550 - #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_LEN 4 19551 19551 - 19552 19552 - /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ 19553 19553 - #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 19554 19554 - 19555 19555 - 19556 19556 - /***********************************/ 19557 19557 - /* MC_CMD_TCM_TXQ_INIT 19558 19558 - * Initialise txq in pacer with given options or set options 19559 19559 - */ 19560 19560 - #define MC_CMD_TCM_TXQ_INIT 0xb5 19561 19561 - #undef MC_CMD_0xb5_PRIVILEGE_CTG 19562 19562 - 19563 19563 - #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 19564 19564 - 19565 19565 - /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ 19566 19566 - #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 19567 19567 - /* the txq id */ 19568 19568 - #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 19569 19569 - #define MC_CMD_TCM_TXQ_INIT_IN_QID_LEN 4 19570 19570 - /* the static priority associated with the txq */ 19571 19571 - #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 19572 19572 - #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_LEN 4 19573 19573 - /* bitmask of the priority queues this txq is inserted into when inserted. */ 19574 19574 - #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 19575 19575 - #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 4 19576 19576 - #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_OFST 8 19577 19577 - #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0 19578 19578 - #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 19579 19579 - #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_OFST 8 19580 19580 - #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1 19581 19581 - #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1 19582 19582 - #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_OFST 8 19583 19583 - #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2 19584 19584 - #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1 19585 19585 - /* the reaction point (RP) bucket */ 19586 19586 - #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 19587 19587 - #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_LEN 4 19588 19588 - /* an already reserved bucket (typically set to bucket associated with outer 19589 19589 - * vswitch) 19590 19590 - */ 19591 19591 - #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 19592 19592 - #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_LEN 4 19593 19593 - /* an already reserved bucket (typically set to bucket associated with inner 19594 19594 - * vswitch) 19595 19595 - */ 19596 19596 - #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 19597 19597 - #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_LEN 4 19598 19598 - /* the min bucket (typically for ETS/minimum bandwidth) */ 19599 19599 - #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 19600 19600 - #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_LEN 4 19601 19601 - 19602 19602 - /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */ 19603 19603 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32 19604 19604 - /* the txq id */ 19605 19605 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0 19606 19606 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_LEN 4 19607 19607 - /* the static priority associated with the txq */ 19608 19608 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4 19609 19609 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_LEN 4 19610 19610 - /* bitmask of the priority queues this txq is inserted into when inserted. */ 19611 19611 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8 19612 19612 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 4 19613 19613 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_OFST 8 19614 19614 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0 19615 19615 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 19616 19616 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_OFST 8 19617 19617 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1 19618 19618 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1 19619 19619 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_OFST 8 19620 19620 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2 19621 19621 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1 19622 19622 - /* the reaction point (RP) bucket */ 19623 19623 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12 19624 19624 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_LEN 4 19625 19625 - /* an already reserved bucket (typically set to bucket associated with outer 19626 19626 - * vswitch) 19627 19627 - */ 19628 19628 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16 19629 19629 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_LEN 4 19630 19630 - /* an already reserved bucket (typically set to bucket associated with inner 19631 19631 - * vswitch) 19632 19632 - */ 19633 19633 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20 19634 19634 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_LEN 4 19635 19635 - /* the min bucket (typically for ETS/minimum bandwidth) */ 19636 19636 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24 19637 19637 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_LEN 4 19638 19638 - /* the static priority associated with the txq */ 19639 19639 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28 19640 19640 - #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_LEN 4 19641 19641 - 19642 19642 - /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ 19643 19643 - #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 18477 18477 + #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_PLATFORM 0x2 19644 18478 19645 18479 19646 18480 /***********************************/ ··· 19593 18737 19594 18738 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ 19595 18739 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 19596 19596 - 19597 19597 - 19598 19598 - /***********************************/ 19599 19599 - /* MC_CMD_VSWITCH_QUERY 19600 19600 - * read some config of v-switch. For now this command is an empty placeholder. 19601 19601 - * It may be used to check if a v-switch is connected to a given EVB port (if 19602 19602 - * not, then the command returns ENOENT). 19603 19603 - */ 19604 19604 - #define MC_CMD_VSWITCH_QUERY 0x63 19605 19605 - #undef MC_CMD_0x63_PRIVILEGE_CTG 19606 19606 - 19607 19607 - #define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL 19608 19608 - 19609 19609 - /* MC_CMD_VSWITCH_QUERY_IN msgrequest */ 19610 19610 - #define MC_CMD_VSWITCH_QUERY_IN_LEN 4 19611 19611 - /* The port to which the v-switch is connected. */ 19612 19612 - #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 19613 19613 - #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 4 19614 19614 - 19615 19615 - /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */ 19616 19616 - #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0 19617 18740 19618 18741 19619 18742 /***********************************/ ··· 19771 18936 19772 18937 19773 18938 /***********************************/ 19774 19774 - /* MC_CMD_VADAPTOR_GET_MAC 19775 19775 - * read the MAC address assigned to a v-adaptor. 19776 19776 - */ 19777 19777 - #define MC_CMD_VADAPTOR_GET_MAC 0x5e 19778 19778 - #undef MC_CMD_0x5e_PRIVILEGE_CTG 19779 19779 - 19780 19780 - #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 19781 19781 - 19782 19782 - /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */ 19783 19783 - #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4 19784 19784 - /* The port to which the v-adaptor is connected. */ 19785 19785 - #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 19786 19786 - #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 4 19787 19787 - 19788 19788 - /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */ 19789 19789 - #define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6 19790 19790 - /* The MAC address assigned to this v-adaptor */ 19791 19791 - #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 19792 19792 - #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 19793 19793 - 19794 19794 - 19795 19795 - /***********************************/ 19796 18939 /* MC_CMD_VADAPTOR_QUERY 19797 18940 * read some config of v-adaptor. 19798 18941 */ ··· 19824 19011 19825 19012 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ 19826 19013 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 19827 19827 - 19828 19828 - 19829 19829 - /***********************************/ 19830 19830 - /* MC_CMD_RDWR_A64_REGIONS 19831 19831 - * Assign the 64 bit region addresses. 19832 19832 - */ 19833 19833 - #define MC_CMD_RDWR_A64_REGIONS 0x9b 19834 19834 - #undef MC_CMD_0x9b_PRIVILEGE_CTG 19835 19835 - 19836 19836 - #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 19837 19837 - 19838 19838 - /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ 19839 19839 - #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 19840 19840 - #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 19841 19841 - #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 4 19842 19842 - #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 19843 19843 - #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 4 19844 19844 - #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 19845 19845 - #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 4 19846 19846 - #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 19847 19847 - #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 4 19848 19848 - /* Write enable bits 0-3, set to write, clear to read. */ 19849 19849 - #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 19850 19850 - #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 19851 19851 - #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 19852 19852 - #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 19853 19853 - 19854 19854 - /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included 19855 19855 - * regardless of state of write bits in the request. 19856 19856 - */ 19857 19857 - #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 19858 19858 - #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 19859 19859 - #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 4 19860 19860 - #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 19861 19861 - #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 4 19862 19862 - #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 19863 19863 - #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 4 19864 19864 - #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 19865 19865 - #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 4 19866 19866 - 19867 19867 - 19868 19868 - /***********************************/ 19869 19869 - /* MC_CMD_ONLOAD_STACK_ALLOC 19870 19870 - * Allocate an Onload stack ID. 19871 19871 - */ 19872 19872 - #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c 19873 19873 - #undef MC_CMD_0x9c_PRIVILEGE_CTG 19874 19874 - 19875 19875 - #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 19876 19876 - 19877 19877 - /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ 19878 19878 - #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 19879 19879 - /* The handle of the owning upstream port */ 19880 19880 - #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 19881 19881 - #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 19882 19882 - 19883 19883 - /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ 19884 19884 - #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 19885 19885 - /* The handle of the new Onload stack */ 19886 19886 - #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 19887 19887 - #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 4 19888 19888 - 19889 19889 - 19890 19890 - /***********************************/ 19891 19891 - /* MC_CMD_ONLOAD_STACK_FREE 19892 19892 - * Free an Onload stack ID. 19893 19893 - */ 19894 19894 - #define MC_CMD_ONLOAD_STACK_FREE 0x9d 19895 19895 - #undef MC_CMD_0x9d_PRIVILEGE_CTG 19896 19896 - 19897 19897 - #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 19898 19898 - 19899 19899 - /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ 19900 19900 - #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 19901 19901 - /* The handle of the Onload stack */ 19902 19902 - #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 19903 19903 - #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 4 19904 19904 - 19905 19905 - /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ 19906 19906 - #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 19907 19014 19908 19015 19909 19016 /***********************************/ ··· 20038 19305 20039 19306 20040 19307 /***********************************/ 20041 20041 - /* MC_CMD_RSS_CONTEXT_WRITE_TABLE 20042 20042 - * Write a portion of a selectable-size indirection table for an RSS context. 20043 20043 - * This command must be used instead of MC_CMD_RSS_CONTEXT_SET_TABLE if the 20044 20044 - * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES. 20045 20045 - */ 20046 20046 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE 0x13e 20047 20047 - #undef MC_CMD_0x13e_PRIVILEGE_CTG 20048 20048 - 20049 20049 - #define MC_CMD_0x13e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20050 20050 - 20051 20051 - /* MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN msgrequest */ 20052 20052 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMIN 8 20053 20053 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMAX 252 20054 20054 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMAX_MCDI2 1020 20055 20055 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LEN(num) (4+4*(num)) 20056 20056 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_NUM(len) (((len)-4)/4) 20057 20057 - /* The handle of the RSS context */ 20058 20058 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_OFST 0 20059 20059 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_LEN 4 20060 20060 - /* An array of index-value pairs to be written to the table. Structure is 20061 20061 - * MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY. 20062 20062 - */ 20063 20063 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_OFST 4 20064 20064 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_LEN 4 20065 20065 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MINNUM 1 20066 20066 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MAXNUM 62 20067 20067 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MAXNUM_MCDI2 254 20068 20068 - 20069 20069 - /* MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT msgresponse */ 20070 20070 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT_LEN 0 20071 20071 - 20072 20072 - /* MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY structuredef */ 20073 20073 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_LEN 4 20074 20074 - /* The index of the table entry to be written. */ 20075 20075 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_OFST 0 20076 20076 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LEN 2 20077 20077 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LBN 0 20078 20078 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_WIDTH 16 20079 20079 - /* The value to write into the table entry. */ 20080 20080 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_OFST 2 20081 20081 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_LEN 2 20082 20082 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_LBN 16 20083 20083 - #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_WIDTH 16 20084 20084 - 20085 20085 - 20086 20086 - /***********************************/ 20087 20087 - /* MC_CMD_RSS_CONTEXT_READ_TABLE 20088 20088 - * Read a portion of a selectable-size indirection table for an RSS context. 20089 20089 - * This command must be used instead of MC_CMD_RSS_CONTEXT_GET_TABLE if the 20090 20090 - * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES. 20091 20091 - */ 20092 20092 - #define MC_CMD_RSS_CONTEXT_READ_TABLE 0x13f 20093 20093 - #undef MC_CMD_0x13f_PRIVILEGE_CTG 20094 20094 - 20095 20095 - #define MC_CMD_0x13f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20096 20096 - 20097 20097 - /* MC_CMD_RSS_CONTEXT_READ_TABLE_IN msgrequest */ 20098 20098 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMIN 6 20099 20099 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMAX 252 20100 20100 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMAX_MCDI2 1020 20101 20101 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LEN(num) (4+2*(num)) 20102 20102 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_NUM(len) (((len)-4)/2) 20103 20103 - /* The handle of the RSS context */ 20104 20104 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_OFST 0 20105 20105 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_LEN 4 20106 20106 - /* An array containing the indices of the entries to be read. */ 20107 20107 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_OFST 4 20108 20108 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_LEN 2 20109 20109 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MINNUM 1 20110 20110 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MAXNUM 124 20111 20111 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MAXNUM_MCDI2 508 20112 20112 - 20113 20113 - /* MC_CMD_RSS_CONTEXT_READ_TABLE_OUT msgresponse */ 20114 20114 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMIN 2 20115 20115 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMAX 252 20116 20116 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMAX_MCDI2 1020 20117 20117 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LEN(num) (0+2*(num)) 20118 20118 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_NUM(len) (((len)-0)/2) 20119 20119 - /* A buffer containing the requested entries read from the table. */ 20120 20120 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_OFST 0 20121 20121 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_LEN 2 20122 20122 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MINNUM 1 20123 20123 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MAXNUM 126 20124 20124 - #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MAXNUM_MCDI2 510 20125 20125 - 20126 20126 - 20127 20127 - /***********************************/ 20128 19308 /* MC_CMD_RSS_CONTEXT_SET_FLAGS 20129 19309 * Set various control flags for an RSS context. 20130 19310 */ ··· 20168 19522 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_OFST 4 20169 19523 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28 20170 19524 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4 20171 20171 - 20172 20172 - 20173 20173 - /***********************************/ 20174 20174 - /* MC_CMD_DOT1P_MAPPING_ALLOC 20175 20175 - * Allocate a .1p mapping. 20176 20176 - */ 20177 20177 - #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 20178 20178 - #undef MC_CMD_0xa4_PRIVILEGE_CTG 20179 20179 - 20180 20180 - #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 20181 20181 - 20182 20182 - /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ 20183 20183 - #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 20184 20184 - /* The handle of the owning upstream port */ 20185 20185 - #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 20186 20186 - #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 20187 20187 - /* Number of queues spanned by this mapping, in the range 1-64; valid fixed 20188 20188 - * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and 20189 20189 - * referenced RSS contexts must span no more than this number. 20190 20190 - */ 20191 20191 - #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 20192 20192 - #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_LEN 4 20193 20193 - 20194 20194 - /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ 20195 20195 - #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 20196 20196 - /* The handle of the new .1p mapping. This should be considered opaque to the 20197 20197 - * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 20198 20198 - * handle. 20199 20199 - */ 20200 20200 - #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 20201 20201 - #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_LEN 4 20202 20202 - /* enum: guaranteed invalid .1p mapping handle value */ 20203 20203 - #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff 20204 20204 - 20205 20205 - 20206 20206 - /***********************************/ 20207 20207 - /* MC_CMD_DOT1P_MAPPING_FREE 20208 20208 - * Free a .1p mapping. 20209 20209 - */ 20210 20210 - #define MC_CMD_DOT1P_MAPPING_FREE 0xa5 20211 20211 - #undef MC_CMD_0xa5_PRIVILEGE_CTG 20212 20212 - 20213 20213 - #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 20214 20214 - 20215 20215 - /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ 20216 20216 - #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 20217 20217 - /* The handle of the .1p mapping */ 20218 20218 - #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 20219 20219 - #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_LEN 4 20220 20220 - 20221 20221 - /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ 20222 20222 - #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 20223 20223 - 20224 20224 - 20225 20225 - /***********************************/ 20226 20226 - /* MC_CMD_DOT1P_MAPPING_SET_TABLE 20227 20227 - * Set the mapping table for a .1p mapping. 20228 20228 - */ 20229 20229 - #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 20230 20230 - #undef MC_CMD_0xa6_PRIVILEGE_CTG 20231 20231 - 20232 20232 - #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 20233 20233 - 20234 20234 - /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ 20235 20235 - #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 20236 20236 - /* The handle of the .1p mapping */ 20237 20237 - #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 20238 20238 - #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4 20239 20239 - /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 20240 20240 - * handle) 20241 20241 - */ 20242 20242 - #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 20243 20243 - #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 20244 20244 - 20245 20245 - /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ 20246 20246 - #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 20247 20247 - 20248 20248 - 20249 20249 - /***********************************/ 20250 20250 - /* MC_CMD_DOT1P_MAPPING_GET_TABLE 20251 20251 - * Get the mapping table for a .1p mapping. 20252 20252 - */ 20253 20253 - #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 20254 20254 - #undef MC_CMD_0xa7_PRIVILEGE_CTG 20255 20255 - 20256 20256 - #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 20257 20257 - 20258 20258 - /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ 20259 20259 - #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 20260 20260 - /* The handle of the .1p mapping */ 20261 20261 - #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 20262 20262 - #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4 20263 20263 - 20264 20264 - /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ 20265 20265 - #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 20266 20266 - /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 20267 20267 - * handle) 20268 20268 - */ 20269 20269 - #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 20270 20270 - #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 20271 20271 - 20272 20272 - 20273 20273 - /***********************************/ 20274 20274 - /* MC_CMD_GET_VECTOR_CFG 20275 20275 - * Get Interrupt Vector config for this PF. 20276 20276 - */ 20277 20277 - #define MC_CMD_GET_VECTOR_CFG 0xbf 20278 20278 - #undef MC_CMD_0xbf_PRIVILEGE_CTG 20279 20279 - 20280 20280 - #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20281 20281 - 20282 20282 - /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ 20283 20283 - #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 20284 20284 - 20285 20285 - /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ 20286 20286 - #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 20287 20287 - /* Base absolute interrupt vector number. */ 20288 20288 - #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 20289 20289 - #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_LEN 4 20290 20290 - /* Number of interrupt vectors allocate to this PF. */ 20291 20291 - #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 20292 20292 - #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_LEN 4 20293 20293 - /* Number of interrupt vectors to allocate per VF. */ 20294 20294 - #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 20295 20295 - #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_LEN 4 20296 20296 - 20297 20297 - 20298 20298 - /***********************************/ 20299 20299 - /* MC_CMD_SET_VECTOR_CFG 20300 20300 - * Set Interrupt Vector config for this PF. 20301 20301 - */ 20302 20302 - #define MC_CMD_SET_VECTOR_CFG 0xc0 20303 20303 - #undef MC_CMD_0xc0_PRIVILEGE_CTG 20304 20304 - 20305 20305 - #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20306 20306 - 20307 20307 - /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ 20308 20308 - #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 20309 20309 - /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to 20310 20310 - * let the system find a suitable base. 20311 20311 - */ 20312 20312 - #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 20313 20313 - #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_LEN 4 20314 20314 - /* Number of interrupt vectors allocate to this PF. */ 20315 20315 - #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 20316 20316 - #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_LEN 4 20317 20317 - /* Number of interrupt vectors to allocate per VF. */ 20318 20318 - #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 20319 20319 - #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_LEN 4 20320 20320 - 20321 20321 - /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ 20322 20322 - #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 20323 19525 20324 19526 20325 19527 /***********************************/ ··· 20304 19810 20305 19811 20306 19812 /***********************************/ 20307 20307 - /* MC_CMD_EVB_PORT_QUERY 20308 20308 - * read some config of v-port. 20309 20309 - */ 20310 20310 - #define MC_CMD_EVB_PORT_QUERY 0x62 20311 20311 - #undef MC_CMD_0x62_PRIVILEGE_CTG 20312 20312 - 20313 20313 - #define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20314 20314 - 20315 20315 - /* MC_CMD_EVB_PORT_QUERY_IN msgrequest */ 20316 20316 - #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4 20317 20317 - /* The handle of the v-port */ 20318 20318 - #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0 20319 20319 - #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_LEN 4 20320 20320 - 20321 20321 - /* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */ 20322 20322 - #define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8 20323 20323 - /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 20324 20324 - #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0 20325 20325 - #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_LEN 4 20326 20326 - /* The number of VLAN tags that may be used on a v-adaptor connected to this 20327 20327 - * EVB port. 20328 20328 - */ 20329 20329 - #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4 20330 20330 - #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4 20331 20331 - 20332 20332 - 20333 20333 - /***********************************/ 20334 20334 - /* MC_CMD_DUMP_BUFTBL_ENTRIES 20335 20335 - * Dump buffer table entries, mainly for command client debug use. Dumps 20336 20336 - * absolute entries, and does not use chunk handles. All entries must be in 20337 20337 - * range, and used for q page mapping, Although the latter restriction may be 20338 20338 - * lifted in future. 20339 20339 - */ 20340 20340 - #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab 20341 20341 - #undef MC_CMD_0xab_PRIVILEGE_CTG 20342 20342 - 20343 20343 - #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_INSECURE 20344 20344 - 20345 20345 - /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ 20346 20346 - #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 20347 20347 - /* Index of the first buffer table entry. */ 20348 20348 - #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 20349 20349 - #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4 20350 20350 - /* Number of buffer table entries to dump. */ 20351 20351 - #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 20352 20352 - #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4 20353 20353 - 20354 20354 - /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ 20355 20355 - #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 20356 20356 - #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 20357 20357 - #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX_MCDI2 1020 20358 20358 - #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) 20359 20359 - #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_NUM(len) (((len)-0)/12) 20360 20360 - /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */ 20361 20361 - #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 20362 20362 - #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 20363 20363 - #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 20364 20364 - #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 20365 20365 - #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM_MCDI2 85 20366 20366 - 20367 20367 - 20368 20368 - /***********************************/ 20369 20369 - /* MC_CMD_SET_RXDP_CONFIG 20370 20370 - * Set global RXDP configuration settings 20371 20371 - */ 20372 20372 - #define MC_CMD_SET_RXDP_CONFIG 0xc1 20373 20373 - #undef MC_CMD_0xc1_PRIVILEGE_CTG 20374 20374 - 20375 20375 - #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 20376 20376 - 20377 20377 - /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ 20378 20378 - #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 20379 20379 - #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 20380 20380 - #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_LEN 4 20381 20381 - #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_OFST 0 20382 20382 - #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 20383 20383 - #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 20384 20384 - #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_OFST 0 20385 20385 - #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1 20386 20386 - #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2 20387 20387 - /* enum: pad to 64 bytes */ 20388 20388 - #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0 20389 20389 - /* enum: pad to 128 bytes (Medford only) */ 20390 20390 - #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1 20391 20391 - /* enum: pad to 256 bytes (Medford only) */ 20392 20392 - #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2 20393 20393 - 20394 20394 - /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ 20395 20395 - #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 20396 20396 - 20397 20397 - 20398 20398 - /***********************************/ 20399 20399 - /* MC_CMD_GET_RXDP_CONFIG 20400 20400 - * Get global RXDP configuration settings 20401 20401 - */ 20402 20402 - #define MC_CMD_GET_RXDP_CONFIG 0xc2 20403 20403 - #undef MC_CMD_0xc2_PRIVILEGE_CTG 20404 20404 - 20405 20405 - #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20406 20406 - 20407 20407 - /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ 20408 20408 - #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 20409 20409 - 20410 20410 - /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ 20411 20411 - #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 20412 20412 - #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 20413 20413 - #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_LEN 4 20414 20414 - #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_OFST 0 20415 20415 - #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 20416 20416 - #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 20417 20417 - #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_OFST 0 20418 20418 - #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1 20419 20419 - #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2 20420 20420 - /* Enum values, see field(s): */ 20421 20421 - /* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */ 20422 20422 - 20423 20423 - 20424 20424 - /***********************************/ 20425 19813 /* MC_CMD_GET_CLOCK 20426 19814 * Return the system and PDCPU clock frequencies. 20427 19815 */ ··· 20326 19950 20327 19951 20328 19952 /***********************************/ 20329 20329 - /* MC_CMD_SET_CLOCK 20330 20330 - * Control the system and DPCPU clock frequencies. Changes are lost reboot. 20331 20331 - */ 20332 20332 - #define MC_CMD_SET_CLOCK 0xad 20333 20333 - #undef MC_CMD_0xad_PRIVILEGE_CTG 20334 20334 - 20335 20335 - #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_INSECURE 20336 20336 - 20337 20337 - /* MC_CMD_SET_CLOCK_IN msgrequest */ 20338 20338 - #define MC_CMD_SET_CLOCK_IN_LEN 28 20339 20339 - /* Requested frequency in MHz for system clock domain */ 20340 20340 - #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 20341 20341 - #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_LEN 4 20342 20342 - /* enum: Leave the system clock domain frequency unchanged */ 20343 20343 - #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0 20344 20344 - /* Requested frequency in MHz for inter-core clock domain */ 20345 20345 - #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 20346 20346 - #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_LEN 4 20347 20347 - /* enum: Leave the inter-core clock domain frequency unchanged */ 20348 20348 - #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0 20349 20349 - /* Requested frequency in MHz for DPCPU clock domain */ 20350 20350 - #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 20351 20351 - #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_LEN 4 20352 20352 - /* enum: Leave the DPCPU clock domain frequency unchanged */ 20353 20353 - #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0 20354 20354 - /* Requested frequency in MHz for PCS clock domain */ 20355 20355 - #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12 20356 20356 - #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_LEN 4 20357 20357 - /* enum: Leave the PCS clock domain frequency unchanged */ 20358 20358 - #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0 20359 20359 - /* Requested frequency in MHz for MC clock domain */ 20360 20360 - #define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16 20361 20361 - #define MC_CMD_SET_CLOCK_IN_MC_FREQ_LEN 4 20362 20362 - /* enum: Leave the MC clock domain frequency unchanged */ 20363 20363 - #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0 20364 20364 - /* Requested frequency in MHz for rmon clock domain */ 20365 20365 - #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20 20366 20366 - #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_LEN 4 20367 20367 - /* enum: Leave the rmon clock domain frequency unchanged */ 20368 20368 - #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0 20369 20369 - /* Requested frequency in MHz for vswitch clock domain */ 20370 20370 - #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24 20371 20371 - #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_LEN 4 20372 20372 - /* enum: Leave the vswitch clock domain frequency unchanged */ 20373 20373 - #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0 20374 20374 - 20375 20375 - /* MC_CMD_SET_CLOCK_OUT msgresponse */ 20376 20376 - #define MC_CMD_SET_CLOCK_OUT_LEN 28 20377 20377 - /* Resulting system frequency in MHz */ 20378 20378 - #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 20379 20379 - #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_LEN 4 20380 20380 - /* enum: The system clock domain doesn't exist */ 20381 20381 - #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0 20382 20382 - /* Resulting inter-core frequency in MHz */ 20383 20383 - #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 20384 20384 - #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_LEN 4 20385 20385 - /* enum: The inter-core clock domain doesn't exist / isn't used */ 20386 20386 - #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0 20387 20387 - /* Resulting DPCPU frequency in MHz */ 20388 20388 - #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 20389 20389 - #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_LEN 4 20390 20390 - /* enum: The dpcpu clock domain doesn't exist */ 20391 20391 - #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0 20392 20392 - /* Resulting PCS frequency in MHz */ 20393 20393 - #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12 20394 20394 - #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_LEN 4 20395 20395 - /* enum: The PCS clock domain doesn't exist / isn't controlled */ 20396 20396 - #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0 20397 20397 - /* Resulting MC frequency in MHz */ 20398 20398 - #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16 20399 20399 - #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_LEN 4 20400 20400 - /* enum: The MC clock domain doesn't exist / isn't controlled */ 20401 20401 - #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0 20402 20402 - /* Resulting rmon frequency in MHz */ 20403 20403 - #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20 20404 20404 - #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_LEN 4 20405 20405 - /* enum: The rmon clock domain doesn't exist / isn't controlled */ 20406 20406 - #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0 20407 20407 - /* Resulting vswitch frequency in MHz */ 20408 20408 - #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24 20409 20409 - #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_LEN 4 20410 20410 - /* enum: The vswitch clock domain doesn't exist / isn't controlled */ 20411 20411 - #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0 20412 20412 - 20413 20413 - 20414 20414 - /***********************************/ 20415 20415 - /* MC_CMD_DPCPU_RPC 20416 20416 - * Send an arbitrary DPCPU message. 20417 20417 - */ 20418 20418 - #define MC_CMD_DPCPU_RPC 0xae 20419 20419 - #undef MC_CMD_0xae_PRIVILEGE_CTG 20420 20420 - 20421 20421 - #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_INSECURE 20422 20422 - 20423 20423 - /* MC_CMD_DPCPU_RPC_IN msgrequest */ 20424 20424 - #define MC_CMD_DPCPU_RPC_IN_LEN 36 20425 20425 - #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 20426 20426 - #define MC_CMD_DPCPU_RPC_IN_CPU_LEN 4 20427 20427 - /* enum: RxDPCPU0 */ 20428 20428 - #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0 20429 20429 - /* enum: TxDPCPU0 */ 20430 20430 - #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 20431 20431 - /* enum: TxDPCPU1 */ 20432 20432 - #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 20433 20433 - /* enum: RxDPCPU1 (Medford only) */ 20434 20434 - #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3 20435 20435 - /* enum: RxDPCPU (will be for the calling function; for now, just an alias of 20436 20436 - * DPCPU_RX0) 20437 20437 - */ 20438 20438 - #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80 20439 20439 - /* enum: TxDPCPU (will be for the calling function; for now, just an alias of 20440 20440 - * DPCPU_TX0) 20441 20441 - */ 20442 20442 - #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81 20443 20443 - /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be 20444 20444 - * initialised to zero 20445 20445 - */ 20446 20446 - #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 20447 20447 - #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 20448 20448 - #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_OFST 4 20449 20449 - #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 20450 20450 - #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 20451 20451 - #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ 20452 20452 - #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ 20453 20453 - #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ 20454 20454 - #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ 20455 20455 - #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ 20456 20456 - #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ 20457 20457 - #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ 20458 20458 - #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ 20459 20459 - #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ 20460 20460 - #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_OFST 4 20461 20461 - #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 20462 20462 - #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 20463 20463 - #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_OFST 4 20464 20464 - #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 20465 20465 - #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 20466 20466 - #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_OFST 4 20467 20467 - #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 20468 20468 - #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 20469 20469 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_OFST 4 20470 20470 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 20471 20471 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 20472 20472 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_OFST 4 20473 20473 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 20474 20474 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 20475 20475 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ 20476 20476 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ 20477 20477 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ 20478 20478 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ 20479 20479 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ 20480 20480 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_OFST 4 20481 20481 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 20482 20482 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 20483 20483 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_OFST 4 20484 20484 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 20485 20485 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 20486 20486 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_OFST 4 20487 20487 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 20488 20488 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 20489 20489 - #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_OFST 4 20490 20490 - #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 20491 20491 - #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 20492 20492 - #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ 20493 20493 - #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ 20494 20494 - #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ 20495 20495 - #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_OFST 4 20496 20496 - #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 20497 20497 - #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 20498 20498 - #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 20499 20499 - #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 20500 20500 - /* Register data to write. Only valid in write/write-read. */ 20501 20501 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 20502 20502 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_LEN 4 20503 20503 - /* Register address. */ 20504 20504 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 20505 20505 - #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_LEN 4 20506 20506 - 20507 20507 - /* MC_CMD_DPCPU_RPC_OUT msgresponse */ 20508 20508 - #define MC_CMD_DPCPU_RPC_OUT_LEN 36 20509 20509 - #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 20510 20510 - #define MC_CMD_DPCPU_RPC_OUT_RC_LEN 4 20511 20511 - /* DATA */ 20512 20512 - #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 20513 20513 - #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 20514 20514 - #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_OFST 4 20515 20515 - #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 20516 20516 - #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 20517 20517 - #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_OFST 4 20518 20518 - #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 20519 20519 - #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 20520 20520 - #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 20521 20521 - #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 20522 20522 - #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 20523 20523 - #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_LEN 4 20524 20524 - #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 20525 20525 - #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_LEN 4 20526 20526 - #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 20527 20527 - #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_LEN 4 20528 20528 - #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 20529 20529 - #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_LEN 4 20530 20530 - 20531 20531 - 20532 20532 - /***********************************/ 20533 19953 /* MC_CMD_TRIGGER_INTERRUPT 20534 19954 * Trigger an interrupt by prodding the BIU. 20535 19955 */ ··· 20342 20170 20343 20171 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ 20344 20172 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 20345 20345 - 20346 20346 - 20347 20347 - /***********************************/ 20348 20348 - /* MC_CMD_SHMBOOT_OP 20349 20349 - * Special operations to support (for now) shmboot. 20350 20350 - */ 20351 20351 - #define MC_CMD_SHMBOOT_OP 0xe6 20352 20352 - #undef MC_CMD_0xe6_PRIVILEGE_CTG 20353 20353 - 20354 20354 - #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 20355 20355 - 20356 20356 - /* MC_CMD_SHMBOOT_OP_IN msgrequest */ 20357 20357 - #define MC_CMD_SHMBOOT_OP_IN_LEN 4 20358 20358 - /* Identifies the operation to perform */ 20359 20359 - #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0 20360 20360 - #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 4 20361 20361 - /* enum: Copy slave_data section to the slave core. (Greenport only) */ 20362 20362 - #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0 20363 20363 - 20364 20364 - /* MC_CMD_SHMBOOT_OP_OUT msgresponse */ 20365 20365 - #define MC_CMD_SHMBOOT_OP_OUT_LEN 0 20366 20366 - 20367 20367 - 20368 20368 - /***********************************/ 20369 20369 - /* MC_CMD_CAP_BLK_READ 20370 20370 - * Read multiple 64bit words from capture block memory 20371 20371 - */ 20372 20372 - #define MC_CMD_CAP_BLK_READ 0xe7 20373 20373 - #undef MC_CMD_0xe7_PRIVILEGE_CTG 20374 20374 - 20375 20375 - #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_INSECURE 20376 20376 - 20377 20377 - /* MC_CMD_CAP_BLK_READ_IN msgrequest */ 20378 20378 - #define MC_CMD_CAP_BLK_READ_IN_LEN 12 20379 20379 - #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 20380 20380 - #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_LEN 4 20381 20381 - #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 20382 20382 - #define MC_CMD_CAP_BLK_READ_IN_ADDR_LEN 4 20383 20383 - #define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 20384 20384 - #define MC_CMD_CAP_BLK_READ_IN_COUNT_LEN 4 20385 20385 - 20386 20386 - /* MC_CMD_CAP_BLK_READ_OUT msgresponse */ 20387 20387 - #define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 20388 20388 - #define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 20389 20389 - #define MC_CMD_CAP_BLK_READ_OUT_LENMAX_MCDI2 1016 20390 20390 - #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) 20391 20391 - #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_NUM(len) (((len)-0)/8) 20392 20392 - #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 20393 20393 - #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 20394 20394 - #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 20395 20395 - #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_LEN 4 20396 20396 - #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_LBN 0 20397 20397 - #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_WIDTH 32 20398 20398 - #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 20399 20399 - #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_LEN 4 20400 20400 - #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_LBN 32 20401 20401 - #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_WIDTH 32 20402 20402 - #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 20403 20403 - #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 20404 20404 - #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM_MCDI2 127 20405 20173 20406 20174 20407 20175 /***********************************/ ··· 20492 20380 20493 20381 20494 20382 /***********************************/ 20495 20495 - /* MC_CMD_SET_PSU 20496 20496 - * Adjusts power supply parameters. This is a warranty-voiding operation. 20497 20497 - * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if 20498 20498 - * the parameter is out of range. 20499 20499 - */ 20500 20500 - #define MC_CMD_SET_PSU 0xea 20501 20501 - #undef MC_CMD_0xea_PRIVILEGE_CTG 20502 20502 - 20503 20503 - #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE 20504 20504 - 20505 20505 - /* MC_CMD_SET_PSU_IN msgrequest */ 20506 20506 - #define MC_CMD_SET_PSU_IN_LEN 12 20507 20507 - #define MC_CMD_SET_PSU_IN_PARAM_OFST 0 20508 20508 - #define MC_CMD_SET_PSU_IN_PARAM_LEN 4 20509 20509 - #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ 20510 20510 - #define MC_CMD_SET_PSU_IN_RAIL_OFST 4 20511 20511 - #define MC_CMD_SET_PSU_IN_RAIL_LEN 4 20512 20512 - #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ 20513 20513 - #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ 20514 20514 - /* desired value, eg voltage in mV */ 20515 20515 - #define MC_CMD_SET_PSU_IN_VALUE_OFST 8 20516 20516 - #define MC_CMD_SET_PSU_IN_VALUE_LEN 4 20517 20517 - 20518 20518 - /* MC_CMD_SET_PSU_OUT msgresponse */ 20519 20519 - #define MC_CMD_SET_PSU_OUT_LEN 0 20520 20520 - 20521 20521 - 20522 20522 - /***********************************/ 20523 20383 /* MC_CMD_GET_FUNCTION_INFO 20524 20384 * Get function information. PF and VF number. 20525 20385 */ ··· 20532 20448 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed 20533 20449 #undef MC_CMD_0xed_PRIVILEGE_CTG 20534 20450 20535 20535 - #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN 20451 20451 + #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 20536 20452 20537 20453 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ 20538 20454 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 ··· 20542 20458 20543 20459 20544 20460 /***********************************/ 20545 20545 - /* MC_CMD_UART_SEND_DATA 20546 20546 - * Send checksummed[sic] block of data over the uart. Response is a placeholder 20547 20547 - * should we wish to make this reliable; currently requests are fire-and- 20548 20548 - * forget. 20549 20549 - */ 20550 20550 - #define MC_CMD_UART_SEND_DATA 0xee 20551 20551 - #undef MC_CMD_0xee_PRIVILEGE_CTG 20552 20552 - 20553 20553 - #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20554 20554 - 20555 20555 - /* MC_CMD_UART_SEND_DATA_OUT msgrequest */ 20556 20556 - #define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 20557 20557 - #define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 20558 20558 - #define MC_CMD_UART_SEND_DATA_OUT_LENMAX_MCDI2 1020 20559 20559 - #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) 20560 20560 - #define MC_CMD_UART_SEND_DATA_OUT_DATA_NUM(len) (((len)-16)/1) 20561 20561 - /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ 20562 20562 - #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 20563 20563 - #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_LEN 4 20564 20564 - /* Offset at which to write the data */ 20565 20565 - #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 20566 20566 - #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_LEN 4 20567 20567 - /* Length of data */ 20568 20568 - #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 20569 20569 - #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_LEN 4 20570 20570 - /* Reserved for future use */ 20571 20571 - #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 20572 20572 - #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_LEN 4 20573 20573 - #define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 20574 20574 - #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 20575 20575 - #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 20576 20576 - #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 20577 20577 - #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM_MCDI2 1004 20578 20578 - 20579 20579 - /* MC_CMD_UART_SEND_DATA_IN msgresponse */ 20580 20580 - #define MC_CMD_UART_SEND_DATA_IN_LEN 0 20581 20581 - 20582 20582 - 20583 20583 - /***********************************/ 20584 20584 - /* MC_CMD_UART_RECV_DATA 20585 20585 - * Request checksummed[sic] block of data over the uart. Only a placeholder, 20586 20586 - * subject to change and not currently implemented. 20587 20587 - */ 20588 20588 - #define MC_CMD_UART_RECV_DATA 0xef 20589 20589 - #undef MC_CMD_0xef_PRIVILEGE_CTG 20590 20590 - 20591 20591 - #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20592 20592 - 20593 20593 - /* MC_CMD_UART_RECV_DATA_OUT msgrequest */ 20594 20594 - #define MC_CMD_UART_RECV_DATA_OUT_LEN 16 20595 20595 - /* CRC32 over OFFSET, LENGTH, RESERVED */ 20596 20596 - #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 20597 20597 - #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_LEN 4 20598 20598 - /* Offset from which to read the data */ 20599 20599 - #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 20600 20600 - #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_LEN 4 20601 20601 - /* Length of data */ 20602 20602 - #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 20603 20603 - #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_LEN 4 20604 20604 - /* Reserved for future use */ 20605 20605 - #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 20606 20606 - #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_LEN 4 20607 20607 - 20608 20608 - /* MC_CMD_UART_RECV_DATA_IN msgresponse */ 20609 20609 - #define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 20610 20610 - #define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 20611 20611 - #define MC_CMD_UART_RECV_DATA_IN_LENMAX_MCDI2 1020 20612 20612 - #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) 20613 20613 - #define MC_CMD_UART_RECV_DATA_IN_DATA_NUM(len) (((len)-16)/1) 20614 20614 - /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ 20615 20615 - #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 20616 20616 - #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_LEN 4 20617 20617 - /* Offset at which to write the data */ 20618 20618 - #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 20619 20619 - #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_LEN 4 20620 20620 - /* Length of data */ 20621 20621 - #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 20622 20622 - #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_LEN 4 20623 20623 - /* Reserved for future use */ 20624 20624 - #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 20625 20625 - #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_LEN 4 20626 20626 - #define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 20627 20627 - #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 20628 20628 - #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 20629 20629 - #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 20630 20630 - #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM_MCDI2 1004 20631 20631 - 20632 20632 - 20633 20633 - /***********************************/ 20634 20634 - /* MC_CMD_READ_FUSES 20635 20635 - * Read data programmed into the device One-Time-Programmable (OTP) Fuses 20636 20636 - */ 20637 20637 - #define MC_CMD_READ_FUSES 0xf0 20638 20638 - #undef MC_CMD_0xf0_PRIVILEGE_CTG 20639 20639 - 20640 20640 - #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE 20641 20641 - 20642 20642 - /* MC_CMD_READ_FUSES_IN msgrequest */ 20643 20643 - #define MC_CMD_READ_FUSES_IN_LEN 8 20644 20644 - /* Offset in OTP to read */ 20645 20645 - #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 20646 20646 - #define MC_CMD_READ_FUSES_IN_OFFSET_LEN 4 20647 20647 - /* Length of data to read in bytes */ 20648 20648 - #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 20649 20649 - #define MC_CMD_READ_FUSES_IN_LENGTH_LEN 4 20650 20650 - 20651 20651 - /* MC_CMD_READ_FUSES_OUT msgresponse */ 20652 20652 - #define MC_CMD_READ_FUSES_OUT_LENMIN 4 20653 20653 - #define MC_CMD_READ_FUSES_OUT_LENMAX 252 20654 20654 - #define MC_CMD_READ_FUSES_OUT_LENMAX_MCDI2 1020 20655 20655 - #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) 20656 20656 - #define MC_CMD_READ_FUSES_OUT_DATA_NUM(len) (((len)-4)/1) 20657 20657 - /* Length of returned OTP data in bytes */ 20658 20658 - #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 20659 20659 - #define MC_CMD_READ_FUSES_OUT_LENGTH_LEN 4 20660 20660 - /* Returned data */ 20661 20661 - #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 20662 20662 - #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 20663 20663 - #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 20664 20664 - #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 20665 20665 - #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM_MCDI2 1016 20666 20666 - 20667 20667 - 20668 20668 - /***********************************/ 20669 20461 /* MC_CMD_KR_TUNE 20670 20462 * Get or set KR Serdes RXEQ and TX Driver settings 20671 20463 */ 20672 20464 #define MC_CMD_KR_TUNE 0xf1 20673 20465 #undef MC_CMD_0xf1_PRIVILEGE_CTG 20674 20466 20675 20675 - #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 20467 20467 + #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 20676 20468 20677 20469 /* MC_CMD_KR_TUNE_IN msgrequest */ 20678 20470 #define MC_CMD_KR_TUNE_IN_LENMIN 4 ··· 21098 21138 21099 21139 21100 21140 /***********************************/ 21101 21101 - /* MC_CMD_PCIE_TUNE 21102 21102 - * Get or set PCIE Serdes RXEQ and TX Driver settings 21103 21103 - */ 21104 21104 - #define MC_CMD_PCIE_TUNE 0xf2 21105 21105 - #undef MC_CMD_0xf2_PRIVILEGE_CTG 21106 21106 - 21107 21107 - #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21108 21108 - 21109 21109 - /* MC_CMD_PCIE_TUNE_IN msgrequest */ 21110 21110 - #define MC_CMD_PCIE_TUNE_IN_LENMIN 4 21111 21111 - #define MC_CMD_PCIE_TUNE_IN_LENMAX 252 21112 21112 - #define MC_CMD_PCIE_TUNE_IN_LENMAX_MCDI2 1020 21113 21113 - #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) 21114 21114 - #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_NUM(len) (((len)-4)/4) 21115 21115 - /* Requested operation */ 21116 21116 - #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 21117 21117 - #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 21118 21118 - /* enum: Get current RXEQ settings */ 21119 21119 - #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 21120 21120 - /* enum: Override RXEQ settings */ 21121 21121 - #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 21122 21122 - /* enum: Get current TX Driver settings */ 21123 21123 - #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 21124 21124 - /* enum: Override TX Driver settings */ 21125 21125 - #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 21126 21126 - /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ 21127 21127 - #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 21128 21128 - /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The 21129 21129 - * caller should call this command repeatedly after starting eye plot, until no 21130 21130 - * more data is returned. 21131 21131 - */ 21132 21132 - #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 21133 21133 - /* enum: Enable the SERDES BIST and set it to generate a 200MHz square wave */ 21134 21134 - #define MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7 21135 21135 - /* Align the arguments to 32 bits */ 21136 21136 - #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 21137 21137 - #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 21138 21138 - /* Arguments specific to the operation */ 21139 21139 - #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 21140 21140 - #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 21141 21141 - #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 21142 21142 - #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 21143 21143 - #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM_MCDI2 254 21144 21144 - 21145 21145 - /* MC_CMD_PCIE_TUNE_OUT msgresponse */ 21146 21146 - #define MC_CMD_PCIE_TUNE_OUT_LEN 0 21147 21147 - 21148 21148 - /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ 21149 21149 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 21150 21150 - /* Requested operation */ 21151 21151 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 21152 21152 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 21153 21153 - /* Align the arguments to 32 bits */ 21154 21154 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 21155 21155 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 21156 21156 - 21157 21157 - /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ 21158 21158 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 21159 21159 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 21160 21160 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX_MCDI2 1020 21161 21161 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 21162 21162 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4) 21163 21163 - /* RXEQ Parameter */ 21164 21164 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 21165 21165 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 21166 21166 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 21167 21167 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 21168 21168 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255 21169 21169 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_OFST 0 21170 21170 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 21171 21171 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 21172 21172 - /* enum: Attenuation (0-15) */ 21173 21173 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 21174 21174 - /* enum: CTLE Boost (0-15) */ 21175 21175 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 21176 21176 - /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 21177 21177 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 21178 21178 - /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 21179 21179 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 21180 21180 - /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 21181 21181 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 21182 21182 - /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 21183 21183 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 21184 21184 - /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 21185 21185 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 21186 21186 - /* enum: DFE DLev */ 21187 21187 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7 21188 21188 - /* enum: Figure of Merit */ 21189 21189 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8 21190 21190 - /* enum: CTLE EQ Capacitor (HF Gain) */ 21191 21191 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 21192 21192 - /* enum: CTLE EQ Resistor (DC Gain) */ 21193 21193 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 21194 21194 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_OFST 0 21195 21195 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 21196 21196 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5 21197 21197 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 21198 21198 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 21199 21199 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 21200 21200 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 21201 21201 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ 21202 21202 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ 21203 21203 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ 21204 21204 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ 21205 21205 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */ 21206 21206 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */ 21207 21207 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */ 21208 21208 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */ 21209 21209 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */ 21210 21210 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */ 21211 21211 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */ 21212 21212 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */ 21213 21213 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */ 21214 21214 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_OFST 0 21215 21215 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13 21216 21216 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 21217 21217 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_OFST 0 21218 21218 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14 21219 21219 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10 21220 21220 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_OFST 0 21221 21221 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 21222 21222 - #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 21223 21223 - 21224 21224 - /* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */ 21225 21225 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8 21226 21226 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252 21227 21227 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX_MCDI2 1020 21228 21228 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 21229 21229 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4) 21230 21230 - /* Requested operation */ 21231 21231 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0 21232 21232 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1 21233 21233 - /* Align the arguments to 32 bits */ 21234 21234 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1 21235 21235 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3 21236 21236 - /* RXEQ Parameter */ 21237 21237 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4 21238 21238 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4 21239 21239 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 21240 21240 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 21241 21241 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM_MCDI2 254 21242 21242 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_OFST 4 21243 21243 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 21244 21244 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 21245 21245 - /* Enum values, see field(s): */ 21246 21246 - /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */ 21247 21247 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_OFST 4 21248 21248 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 21249 21249 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5 21250 21250 - /* Enum values, see field(s): */ 21251 21251 - /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 21252 21252 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_OFST 4 21253 21253 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13 21254 21254 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 21255 21255 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_OFST 4 21256 21256 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14 21257 21257 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2 21258 21258 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_OFST 4 21259 21259 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 21260 21260 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 21261 21261 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_OFST 4 21262 21262 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 21263 21263 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 21264 21264 - 21265 21265 - /* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */ 21266 21266 - #define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0 21267 21267 - 21268 21268 - /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ 21269 21269 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 21270 21270 - /* Requested operation */ 21271 21271 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 21272 21272 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 21273 21273 - /* Align the arguments to 32 bits */ 21274 21274 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 21275 21275 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 21276 21276 - 21277 21277 - /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ 21278 21278 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 21279 21279 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 21280 21280 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX_MCDI2 1020 21281 21281 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 21282 21282 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4) 21283 21283 - /* RXEQ Parameter */ 21284 21284 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 21285 21285 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 21286 21286 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 21287 21287 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 21288 21288 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255 21289 21289 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_OFST 0 21290 21290 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 21291 21291 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 21292 21292 - /* enum: TxMargin (PIPE) */ 21293 21293 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 21294 21294 - /* enum: TxSwing (PIPE) */ 21295 21295 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 21296 21296 - /* enum: De-emphasis coefficient C(-1) (PIPE) */ 21297 21297 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 21298 21298 - /* enum: De-emphasis coefficient C(0) (PIPE) */ 21299 21299 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 21300 21300 - /* enum: De-emphasis coefficient C(+1) (PIPE) */ 21301 21301 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 21302 21302 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_OFST 0 21303 21303 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 21304 21304 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 21305 21305 - /* Enum values, see field(s): */ 21306 21306 - /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 21307 21307 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_OFST 0 21308 21308 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 21309 21309 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 21310 21310 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_OFST 0 21311 21311 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 21312 21312 - #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 21313 21313 - 21314 21314 - /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ 21315 21315 - #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 21316 21316 - /* Requested operation */ 21317 21317 - #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 21318 21318 - #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 21319 21319 - /* Align the arguments to 32 bits */ 21320 21320 - #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 21321 21321 - #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 21322 21322 - #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 21323 21323 - #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_LEN 4 21324 21324 - 21325 21325 - /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ 21326 21326 - #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 21327 21327 - 21328 21328 - /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ 21329 21329 - #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 21330 21330 - /* Requested operation */ 21331 21331 - #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 21332 21332 - #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 21333 21333 - /* Align the arguments to 32 bits */ 21334 21334 - #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 21335 21335 - #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 21336 21336 - 21337 21337 - /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 21338 21338 - #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 21339 21339 - #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 21340 21340 - #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX_MCDI2 1020 21341 21341 - #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 21342 21342 - #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2) 21343 21343 - #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 21344 21344 - #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 21345 21345 - #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 21346 21346 - #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 21347 21347 - #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM_MCDI2 510 21348 21348 - 21349 21349 - /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN msgrequest */ 21350 21350 - #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0 21351 21351 - 21352 21352 - /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT msgrequest */ 21353 21353 - #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0 21354 21354 - 21355 21355 - 21356 21356 - /***********************************/ 21357 21141 /* MC_CMD_LICENSING 21358 21142 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 21359 21143 * - not used for V3 licensing ··· 21236 21532 21237 21533 21238 21534 /***********************************/ 21239 21239 - /* MC_CMD_LICENSING_GET_ID_V3 21240 21240 - * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license 21241 21241 - * partition - V3 licensing (Medford) 21242 21242 - */ 21243 21243 - #define MC_CMD_LICENSING_GET_ID_V3 0xd1 21244 21244 - #undef MC_CMD_0xd1_PRIVILEGE_CTG 21245 21245 - 21246 21246 - #define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21247 21247 - 21248 21248 - /* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */ 21249 21249 - #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0 21250 21250 - 21251 21251 - /* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */ 21252 21252 - #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8 21253 21253 - #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252 21254 21254 - #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX_MCDI2 1020 21255 21255 - #define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num)) 21256 21256 - #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_NUM(len) (((len)-8)/1) 21257 21257 - /* type of license (eg 3) */ 21258 21258 - #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0 21259 21259 - #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4 21260 21260 - /* length of the license ID (in bytes) */ 21261 21261 - #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4 21262 21262 - #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_LEN 4 21263 21263 - /* the unique license ID of the adapter */ 21264 21264 - #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8 21265 21265 - #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1 21266 21266 - #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0 21267 21267 - #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244 21268 21268 - #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM_MCDI2 1012 21269 21269 - 21270 21270 - 21271 21271 - /***********************************/ 21272 21272 - /* MC_CMD_MC2MC_PROXY 21273 21273 - * Execute an arbitrary MCDI command on the slave MC of a dual-core device. 21274 21274 - * This will fail on a single-core system. 21275 21275 - */ 21276 21276 - #define MC_CMD_MC2MC_PROXY 0xf4 21277 21277 - #undef MC_CMD_0xf4_PRIVILEGE_CTG 21278 21278 - 21279 21279 - #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21280 21280 - 21281 21281 - /* MC_CMD_MC2MC_PROXY_IN msgrequest */ 21282 21282 - #define MC_CMD_MC2MC_PROXY_IN_LEN 0 21283 21283 - 21284 21284 - /* MC_CMD_MC2MC_PROXY_OUT msgresponse */ 21285 21285 - #define MC_CMD_MC2MC_PROXY_OUT_LEN 0 21286 21286 - 21287 21287 - 21288 21288 - /***********************************/ 21289 21535 /* MC_CMD_GET_LICENSED_APP_STATE 21290 21536 * Query the state of an individual licensed application. (Note that the actual 21291 21537 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation ··· 21261 21607 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 21262 21608 /* enum: a valid license is present for the application */ 21263 21609 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 21264 21264 - 21265 21265 - 21266 21266 - /***********************************/ 21267 21267 - /* MC_CMD_GET_LICENSED_V3_APP_STATE 21268 21268 - * Query the state of an individual licensed application. (Note that the actual 21269 21269 - * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 21270 21270 - * operation or a reboot of the MC.) Used for V3 licensing (Medford) 21271 21271 - */ 21272 21272 - #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2 21273 21273 - #undef MC_CMD_0xd2_PRIVILEGE_CTG 21274 21274 - 21275 21275 - #define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21276 21276 - 21277 21277 - /* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */ 21278 21278 - #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8 21279 21279 - /* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit 21280 21280 - * mask 21281 21281 - */ 21282 21282 - #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0 21283 21283 - #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8 21284 21284 - #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0 21285 21285 - #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_LEN 4 21286 21286 - #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_LBN 0 21287 21287 - #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_WIDTH 32 21288 21288 - #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4 21289 21289 - #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_LEN 4 21290 21290 - #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_LBN 32 21291 21291 - #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_WIDTH 32 21292 21292 - 21293 21293 - /* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */ 21294 21294 - #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4 21295 21295 - /* state of this application */ 21296 21296 - #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0 21297 21297 - #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 4 21298 21298 - /* enum: no (or invalid) license is present for the application */ 21299 21299 - #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0 21300 21300 - /* enum: a valid license is present for the application */ 21301 21301 - #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1 21302 21302 - 21303 21303 - 21304 21304 - /***********************************/ 21305 21305 - /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES 21306 21306 - * Query the state of an one or more licensed features. (Note that the actual 21307 21307 - * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 21308 21308 - * operation or a reboot of the MC.) Used for V3 licensing (Medford) 21309 21309 - */ 21310 21310 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3 21311 21311 - #undef MC_CMD_0xd3_PRIVILEGE_CTG 21312 21312 - 21313 21313 - #define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21314 21314 - 21315 21315 - /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */ 21316 21316 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8 21317 21317 - /* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or 21318 21318 - * more bits set 21319 21319 - */ 21320 21320 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0 21321 21321 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8 21322 21322 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0 21323 21323 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_LEN 4 21324 21324 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_LBN 0 21325 21325 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_WIDTH 32 21326 21326 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4 21327 21327 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_LEN 4 21328 21328 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_LBN 32 21329 21329 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_WIDTH 32 21330 21330 - 21331 21331 - /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */ 21332 21332 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8 21333 21333 - /* states of these features - bit set for licensed, clear for not licensed */ 21334 21334 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0 21335 21335 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8 21336 21336 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0 21337 21337 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_LEN 4 21338 21338 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_LBN 0 21339 21339 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_WIDTH 32 21340 21340 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4 21341 21341 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_LEN 4 21342 21342 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_LBN 32 21343 21343 - #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_WIDTH 32 21344 21344 - 21345 21345 - 21346 21346 - /***********************************/ 21347 21347 - /* MC_CMD_LICENSED_APP_OP 21348 21348 - * Perform an action for an individual licensed application - not used for V3 21349 21349 - * licensing. 21350 21350 - */ 21351 21351 - #define MC_CMD_LICENSED_APP_OP 0xf6 21352 21352 - #undef MC_CMD_0xf6_PRIVILEGE_CTG 21353 21353 - 21354 21354 - #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21355 21355 - 21356 21356 - /* MC_CMD_LICENSED_APP_OP_IN msgrequest */ 21357 21357 - #define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 21358 21358 - #define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 21359 21359 - #define MC_CMD_LICENSED_APP_OP_IN_LENMAX_MCDI2 1020 21360 21360 - #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) 21361 21361 - #define MC_CMD_LICENSED_APP_OP_IN_ARGS_NUM(len) (((len)-8)/4) 21362 21362 - /* application ID */ 21363 21363 - #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 21364 21364 - #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4 21365 21365 - /* the type of operation requested */ 21366 21366 - #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 21367 21367 - #define MC_CMD_LICENSED_APP_OP_IN_OP_LEN 4 21368 21368 - /* enum: validate application */ 21369 21369 - #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 21370 21370 - /* enum: mask application */ 21371 21371 - #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1 21372 21372 - /* arguments specific to this particular operation */ 21373 21373 - #define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 21374 21374 - #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 21375 21375 - #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 21376 21376 - #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 21377 21377 - #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM_MCDI2 253 21378 21378 - 21379 21379 - /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ 21380 21380 - #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 21381 21381 - #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 21382 21382 - #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX_MCDI2 1020 21383 21383 - #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) 21384 21384 - #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_NUM(len) (((len)-0)/4) 21385 21385 - /* result specific to this particular operation */ 21386 21386 - #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 21387 21387 - #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 21388 21388 - #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 21389 21389 - #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 21390 21390 - #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM_MCDI2 255 21391 21391 - 21392 21392 - /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ 21393 21393 - #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 21394 21394 - /* application ID */ 21395 21395 - #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 21396 21396 - #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_LEN 4 21397 21397 - /* the type of operation requested */ 21398 21398 - #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 21399 21399 - #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_LEN 4 21400 21400 - /* validation challenge */ 21401 21401 - #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 21402 21402 - #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 21403 21403 - 21404 21404 - /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ 21405 21405 - #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 21406 21406 - /* feature expiry (time_t) */ 21407 21407 - #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 21408 21408 - #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_LEN 4 21409 21409 - /* validation response */ 21410 21410 - #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 21411 21411 - #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 21412 21412 - 21413 21413 - /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */ 21414 21414 - #define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12 21415 21415 - /* application ID */ 21416 21416 - #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0 21417 21417 - #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_LEN 4 21418 21418 - /* the type of operation requested */ 21419 21419 - #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4 21420 21420 - #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_LEN 4 21421 21421 - /* flag */ 21422 21422 - #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8 21423 21423 - #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_LEN 4 21424 21424 - 21425 21425 - /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */ 21426 21426 - #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0 21427 21427 - 21428 21428 - 21429 21429 - /***********************************/ 21430 21430 - /* MC_CMD_LICENSED_V3_VALIDATE_APP 21431 21431 - * Perform validation for an individual licensed application - V3 licensing 21432 21432 - * (Medford) 21433 21433 - */ 21434 21434 - #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4 21435 21435 - #undef MC_CMD_0xd4_PRIVILEGE_CTG 21436 21436 - 21437 21437 - #define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21438 21438 - 21439 21439 - /* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */ 21440 21440 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 56 21441 21441 - /* challenge for validation (384 bits) */ 21442 21442 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0 21443 21443 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 48 21444 21444 - /* application ID expressed as a single bit mask */ 21445 21445 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48 21446 21446 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8 21447 21447 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48 21448 21448 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_LEN 4 21449 21449 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_LBN 384 21450 21450 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_WIDTH 32 21451 21451 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52 21452 21452 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_LEN 4 21453 21453 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_LBN 416 21454 21454 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_WIDTH 32 21455 21455 - 21456 21456 - /* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */ 21457 21457 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116 21458 21458 - /* validation response to challenge in the form of ECDSA signature consisting 21459 21459 - * of two 384-bit integers, r and s, in big-endian order. The signature signs a 21460 21460 - * SHA-384 digest of a message constructed from the concatenation of the input 21461 21461 - * message and the remaining fields of this output message, e.g. challenge[48 21462 21462 - * bytes] ... expiry_time[4 bytes] ... 21463 21463 - */ 21464 21464 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0 21465 21465 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 96 21466 21466 - /* application expiry time */ 21467 21467 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 96 21468 21468 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_LEN 4 21469 21469 - /* application expiry units */ 21470 21470 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100 21471 21471 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 4 21472 21472 - /* enum: expiry units are accounting units */ 21473 21473 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0 21474 21474 - /* enum: expiry units are calendar days */ 21475 21475 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1 21476 21476 - /* base MAC address of the NIC stored in NVRAM (note that this is a constant 21477 21477 - * value for a given NIC regardless which function is calling, effectively this 21478 21478 - * is PF0 base MAC address) 21479 21479 - */ 21480 21480 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_OFST 104 21481 21481 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_LEN 6 21482 21482 - /* MAC address of v-adaptor associated with the client. If no such v-adapator 21483 21483 - * exists, then the field is filled with 0xFF. 21484 21484 - */ 21485 21485 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_OFST 110 21486 21486 - #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_LEN 6 21487 21487 - 21488 21488 - 21489 21489 - /***********************************/ 21490 21490 - /* MC_CMD_LICENSED_V3_MASK_FEATURES 21491 21491 - * Mask features - V3 licensing (Medford) 21492 21492 - */ 21493 21493 - #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5 21494 21494 - #undef MC_CMD_0xd5_PRIVILEGE_CTG 21495 21495 - 21496 21496 - #define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21497 21497 - 21498 21498 - /* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */ 21499 21499 - #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12 21500 21500 - /* mask to be applied to features to be changed */ 21501 21501 - #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0 21502 21502 - #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8 21503 21503 - #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0 21504 21504 - #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_LEN 4 21505 21505 - #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_LBN 0 21506 21506 - #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_WIDTH 32 21507 21507 - #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4 21508 21508 - #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_LEN 4 21509 21509 - #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_LBN 32 21510 21510 - #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_WIDTH 32 21511 21511 - /* whether to turn on or turn off the masked features */ 21512 21512 - #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8 21513 21513 - #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4 21514 21514 - /* enum: turn the features off */ 21515 21515 - #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0 21516 21516 - /* enum: turn the features back on */ 21517 21517 - #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1 21518 21518 - 21519 21519 - /* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */ 21520 21520 - #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0 21521 21521 - 21522 21522 - 21523 21523 - /***********************************/ 21524 21524 - /* MC_CMD_LICENSING_V3_TEMPORARY 21525 21525 - * Perform operations to support installation of a single temporary license in 21526 21526 - * the adapter, in addition to those found in the licensing partition. See 21527 21527 - * SF-116124-SW for an overview of how this could be used. The license is 21528 21528 - * stored in MC persistent data and so will survive a MC reboot, but will be 21529 21529 - * erased when the adapter is power cycled 21530 21530 - */ 21531 21531 - #define MC_CMD_LICENSING_V3_TEMPORARY 0xd6 21532 21532 - #undef MC_CMD_0xd6_PRIVILEGE_CTG 21533 21533 - 21534 21534 - #define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21535 21535 - 21536 21536 - /* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */ 21537 21537 - #define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4 21538 21538 - /* operation code */ 21539 21539 - #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0 21540 21540 - #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_LEN 4 21541 21541 - /* enum: install a new license, overwriting any existing temporary license. 21542 21542 - * This is an asynchronous operation owing to the time taken to validate an 21543 21543 - * ECDSA license 21544 21544 - */ 21545 21545 - #define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0 21546 21546 - /* enum: clear the license immediately rather than waiting for the next power 21547 21547 - * cycle 21548 21548 - */ 21549 21549 - #define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1 21550 21550 - /* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET 21551 21551 - * operation 21552 21552 - */ 21553 21553 - #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2 21554 21554 - 21555 21555 - /* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */ 21556 21556 - #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164 21557 21557 - #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0 21558 21558 - #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_LEN 4 21559 21559 - /* ECDSA license and signature */ 21560 21560 - #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4 21561 21561 - #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 160 21562 21562 - 21563 21563 - /* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */ 21564 21564 - #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4 21565 21565 - #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0 21566 21566 - #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_LEN 4 21567 21567 - 21568 21568 - /* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */ 21569 21569 - #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4 21570 21570 - #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0 21571 21571 - #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_LEN 4 21572 21572 - 21573 21573 - /* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */ 21574 21574 - #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 12 21575 21575 - /* status code */ 21576 21576 - #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0 21577 21577 - #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 4 21578 21578 - /* enum: finished validating and installing license */ 21579 21579 - #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0 21580 21580 - /* enum: license validation and installation in progress */ 21581 21581 - #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1 21582 21582 - /* enum: licensing error. More specific error messages are not provided to 21583 21583 - * avoid exposing details of the licensing system to the client 21584 21584 - */ 21585 21585 - #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2 21586 21586 - /* bitmask of licensed features */ 21587 21587 - #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4 21588 21588 - #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8 21589 21589 - #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4 21590 21590 - #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_LEN 4 21591 21591 - #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_LBN 32 21592 21592 - #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_WIDTH 32 21593 21593 - #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8 21594 21594 - #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_LEN 4 21595 21595 - #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_LBN 64 21596 21596 - #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_WIDTH 32 21597 21597 - 21598 21598 - 21599 21599 - /***********************************/ 21600 21600 - /* MC_CMD_SET_PORT_SNIFF_CONFIG 21601 21601 - * Configure RX port sniffing for the physical port associated with the calling 21602 21602 - * function. Only a privileged function may change the port sniffing 21603 21603 - * configuration. A copy of all traffic delivered to the host (non-promiscuous 21604 21604 - * mode) or all traffic arriving at the port (promiscuous mode) may be 21605 21605 - * delivered to a specific queue, or a set of queues with RSS. 21606 21606 - */ 21607 21607 - #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 21608 21608 - #undef MC_CMD_0xf7_PRIVILEGE_CTG 21609 21609 - 21610 21610 - #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21611 21611 - 21612 21612 - /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ 21613 21613 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 21614 21614 - /* configuration flags */ 21615 21615 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 21616 21616 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4 21617 21617 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_OFST 0 21618 21618 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 21619 21619 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 21620 21620 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_OFST 0 21621 21621 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 21622 21622 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 21623 21623 - /* receive queue handle (for RSS mode, this is the base queue) */ 21624 21624 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 21625 21625 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4 21626 21626 - /* receive mode */ 21627 21627 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 21628 21628 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4 21629 21629 - /* enum: receive to just the specified queue */ 21630 21630 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 21631 21631 - /* enum: receive to multiple queues using RSS context */ 21632 21632 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 21633 21633 - /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 21634 21634 - * that these handles should be considered opaque to the host, although a value 21635 21635 - * of 0xFFFFFFFF is guaranteed never to be a valid handle. 21636 21636 - */ 21637 21637 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 21638 21638 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4 21639 21639 - 21640 21640 - /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ 21641 21641 - #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 21642 21642 - 21643 21643 - 21644 21644 - /***********************************/ 21645 21645 - /* MC_CMD_GET_PORT_SNIFF_CONFIG 21646 21646 - * Obtain the current RX port sniffing configuration for the physical port 21647 21647 - * associated with the calling function. Only a privileged function may read 21648 21648 - * the configuration. 21649 21649 - */ 21650 21650 - #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 21651 21651 - #undef MC_CMD_0xf8_PRIVILEGE_CTG 21652 21652 - 21653 21653 - #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21654 21654 - 21655 21655 - /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ 21656 21656 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 21657 21657 - 21658 21658 - /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ 21659 21659 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 21660 21660 - /* configuration flags */ 21661 21661 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 21662 21662 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4 21663 21663 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_OFST 0 21664 21664 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 21665 21665 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 21666 21666 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_OFST 0 21667 21667 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 21668 21668 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 21669 21669 - /* receiving queue handle (for RSS mode, this is the base queue) */ 21670 21670 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 21671 21671 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4 21672 21672 - /* receive mode */ 21673 21673 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 21674 21674 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4 21675 21675 - /* enum: receiving to just the specified queue */ 21676 21676 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 21677 21677 - /* enum: receiving to multiple queues using RSS context */ 21678 21678 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 21679 21679 - /* RSS context (for RX_MODE_RSS) */ 21680 21680 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 21681 21681 - #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4 21682 21610 21683 21611 21684 21612 /***********************************/ ··· 21306 22070 21307 22071 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */ 21308 22072 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0 21309 21309 - 21310 21310 - 21311 21311 - /***********************************/ 21312 21312 - /* MC_CMD_GET_PARSER_DISP_CONFIG 21313 21313 - * Read configuration related to the parser-dispatcher subsystem. 21314 21314 - */ 21315 21315 - #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa 21316 21316 - #undef MC_CMD_0xfa_PRIVILEGE_CTG 21317 21317 - 21318 21318 - #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21319 21319 - 21320 21320 - /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */ 21321 21321 - #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8 21322 21322 - /* the type of configuration setting to read */ 21323 21323 - #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 21324 21324 - #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4 21325 21325 - /* Enum values, see field(s): */ 21326 21326 - /* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */ 21327 21327 - /* handle for the entity to query: queue handle, EVB port ID, etc. depending on 21328 21328 - * the type of configuration setting being read 21329 21329 - */ 21330 21330 - #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 21331 21331 - #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4 21332 21332 - 21333 21333 - /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */ 21334 21334 - #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4 21335 21335 - #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252 21336 21336 - #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX_MCDI2 1020 21337 21337 - #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num)) 21338 21338 - #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_NUM(len) (((len)-0)/4) 21339 21339 - /* current value: the details depend on the type of configuration setting being 21340 21340 - * read 21341 21341 - */ 21342 21342 - #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0 21343 21343 - #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4 21344 21344 - #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1 21345 21345 - #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63 21346 21346 - #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM_MCDI2 255 21347 21347 - 21348 21348 - 21349 21349 - /***********************************/ 21350 21350 - /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG 21351 21351 - * Configure TX port sniffing for the physical port associated with the calling 21352 21352 - * function. Only a privileged function may change the port sniffing 21353 21353 - * configuration. A copy of all traffic transmitted through the port may be 21354 21354 - * delivered to a specific queue, or a set of queues with RSS. Note that these 21355 21355 - * packets are delivered with transmit timestamps in the packet prefix, not 21356 21356 - * receive timestamps, so it is likely that the queue(s) will need to be 21357 21357 - * dedicated as TX sniff receivers. 21358 21358 - */ 21359 21359 - #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb 21360 21360 - #undef MC_CMD_0xfb_PRIVILEGE_CTG 21361 21361 - 21362 21362 - #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21363 21363 - 21364 21364 - /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 21365 21365 - #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16 21366 21366 - /* configuration flags */ 21367 21367 - #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 21368 21368 - #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4 21369 21369 - #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_OFST 0 21370 21370 - #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 21371 21371 - #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 21372 21372 - /* receive queue handle (for RSS mode, this is the base queue) */ 21373 21373 - #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 21374 21374 - #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4 21375 21375 - /* receive mode */ 21376 21376 - #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 21377 21377 - #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4 21378 21378 - /* enum: receive to just the specified queue */ 21379 21379 - #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 21380 21380 - /* enum: receive to multiple queues using RSS context */ 21381 21381 - #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 21382 21382 - /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 21383 21383 - * that these handles should be considered opaque to the host, although a value 21384 21384 - * of 0xFFFFFFFF is guaranteed never to be a valid handle. 21385 21385 - */ 21386 21386 - #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 21387 21387 - #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4 21388 21388 - 21389 21389 - /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 21390 21390 - #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0 21391 21391 - 21392 21392 - 21393 21393 - /***********************************/ 21394 21394 - /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG 21395 21395 - * Obtain the current TX port sniffing configuration for the physical port 21396 21396 - * associated with the calling function. Only a privileged function may read 21397 21397 - * the configuration. 21398 21398 - */ 21399 21399 - #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc 21400 21400 - #undef MC_CMD_0xfc_PRIVILEGE_CTG 21401 21401 - 21402 21402 - #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21403 21403 - 21404 21404 - /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 21405 21405 - #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0 21406 21406 - 21407 21407 - /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 21408 21408 - #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16 21409 21409 - /* configuration flags */ 21410 21410 - #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 21411 21411 - #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4 21412 21412 - #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_OFST 0 21413 21413 - #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 21414 21414 - #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 21415 21415 - /* receiving queue handle (for RSS mode, this is the base queue) */ 21416 21416 - #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 21417 21417 - #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4 21418 21418 - /* receive mode */ 21419 21419 - #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 21420 21420 - #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4 21421 21421 - /* enum: receiving to just the specified queue */ 21422 21422 - #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 21423 21423 - /* enum: receiving to multiple queues using RSS context */ 21424 21424 - #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 21425 21425 - /* RSS context (for RX_MODE_RSS) */ 21426 21426 - #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 21427 21427 - #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4 21428 21428 - 21429 21429 - 21430 21430 - /***********************************/ 21431 21431 - /* MC_CMD_RMON_STATS_RX_ERRORS 21432 21432 - * Per queue rx error stats. 21433 21433 - */ 21434 21434 - #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe 21435 21435 - #undef MC_CMD_0xfe_PRIVILEGE_CTG 21436 21436 - 21437 21437 - #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21438 21438 - 21439 21439 - /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */ 21440 21440 - #define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8 21441 21441 - /* The rx queue to get stats for. */ 21442 21442 - #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0 21443 21443 - #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_LEN 4 21444 21444 - #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4 21445 21445 - #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_LEN 4 21446 21446 - #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_OFST 4 21447 21447 - #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0 21448 21448 - #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1 21449 21449 - 21450 21450 - /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */ 21451 21451 - #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16 21452 21452 - #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0 21453 21453 - #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_LEN 4 21454 21454 - #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4 21455 21455 - #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_LEN 4 21456 21456 - #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8 21457 21457 - #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_LEN 4 21458 21458 - #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12 21459 21459 - #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_LEN 4 21460 21460 - 21461 21461 - 21462 21462 - /***********************************/ 21463 21463 - /* MC_CMD_GET_PCIE_RESOURCE_INFO 21464 21464 - * Find out about available PCIE resources 21465 21465 - */ 21466 21466 - #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd 21467 21467 - #undef MC_CMD_0xfd_PRIVILEGE_CTG 21468 21468 - 21469 21469 - #define MC_CMD_0xfd_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21470 21470 - 21471 21471 - /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */ 21472 21472 - #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0 21473 21473 - 21474 21474 - /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */ 21475 21475 - #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28 21476 21476 - /* The maximum number of PFs the device can expose */ 21477 21477 - #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0 21478 21478 - #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_LEN 4 21479 21479 - /* The maximum number of VFs the device can expose in total */ 21480 21480 - #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4 21481 21481 - #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_LEN 4 21482 21482 - /* The maximum number of MSI-X vectors the device can provide in total */ 21483 21483 - #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8 21484 21484 - #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_LEN 4 21485 21485 - /* the number of MSI-X vectors the device will allocate by default to each PF 21486 21486 - */ 21487 21487 - #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12 21488 21488 - #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_LEN 4 21489 21489 - /* the number of MSI-X vectors the device will allocate by default to each VF 21490 21490 - */ 21491 21491 - #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16 21492 21492 - #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_LEN 4 21493 21493 - /* the maximum number of MSI-X vectors the device can allocate to any one PF */ 21494 21494 - #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20 21495 21495 - #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_LEN 4 21496 21496 - /* the maximum number of MSI-X vectors the device can allocate to any one VF */ 21497 21497 - #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24 21498 21498 - #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_LEN 4 21499 21499 - 21500 21500 - 21501 21501 - /***********************************/ 21502 21502 - /* MC_CMD_GET_PORT_MODES 21503 21503 - * Find out about available port modes 21504 21504 - */ 21505 21505 - #define MC_CMD_GET_PORT_MODES 0xff 21506 21506 - #undef MC_CMD_0xff_PRIVILEGE_CTG 21507 21507 - 21508 21508 - #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21509 21509 - 21510 21510 - /* MC_CMD_GET_PORT_MODES_IN msgrequest */ 21511 21511 - #define MC_CMD_GET_PORT_MODES_IN_LEN 0 21512 21512 - 21513 21513 - /* MC_CMD_GET_PORT_MODES_OUT msgresponse */ 21514 21514 - #define MC_CMD_GET_PORT_MODES_OUT_LEN 12 21515 21515 - /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) 21516 21516 - * that are supported for customer use in production firmware. 21517 21517 - */ 21518 21518 - #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0 21519 21519 - #define MC_CMD_GET_PORT_MODES_OUT_MODES_LEN 4 21520 21520 - /* Default (canonical) board mode */ 21521 21521 - #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4 21522 21522 - #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_LEN 4 21523 21523 - /* Current board mode */ 21524 21524 - #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8 21525 21525 - #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4 21526 21526 - 21527 21527 - /* MC_CMD_GET_PORT_MODES_OUT_V2 msgresponse */ 21528 21528 - #define MC_CMD_GET_PORT_MODES_OUT_V2_LEN 16 21529 21529 - /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) 21530 21530 - * that are supported for customer use in production firmware. 21531 21531 - */ 21532 21532 - #define MC_CMD_GET_PORT_MODES_OUT_V2_MODES_OFST 0 21533 21533 - #define MC_CMD_GET_PORT_MODES_OUT_V2_MODES_LEN 4 21534 21534 - /* Default (canonical) board mode */ 21535 21535 - #define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_OFST 4 21536 21536 - #define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_LEN 4 21537 21537 - /* Current board mode */ 21538 21538 - #define MC_CMD_GET_PORT_MODES_OUT_V2_CURRENT_MODE_OFST 8 21539 21539 - #define MC_CMD_GET_PORT_MODES_OUT_V2_CURRENT_MODE_LEN 4 21540 21540 - /* Bitmask of engineering port modes available on the board (indexed by 21541 21541 - * TLV_PORT_MODE_*). A superset of MC_CMD_GET_PORT_MODES_OUT/MODES that 21542 21542 - * contains all modes implemented in firmware for a particular board. Modes 21543 21543 - * listed in MODES are considered production modes and should be exposed in 21544 21544 - * userland tools. Modes listed in ENGINEERING_MODES, but not in MODES 21545 21545 - * should be considered hidden (not to be exposed in userland tools) and for 21546 21546 - * engineering use only. There are no other semantic differences and any mode 21547 21547 - * listed in either MODES or ENGINEERING_MODES can be set on the board. 21548 21548 - */ 21549 21549 - #define MC_CMD_GET_PORT_MODES_OUT_V2_ENGINEERING_MODES_OFST 12 21550 21550 - #define MC_CMD_GET_PORT_MODES_OUT_V2_ENGINEERING_MODES_LEN 4 21551 21551 - 21552 21552 - 21553 21553 - /***********************************/ 21554 21554 - /* MC_CMD_OVERRIDE_PORT_MODE 21555 21555 - * Override flash config port mode for subsequent MC reboot(s). Override data 21556 21556 - * is stored in the presistent data section of DMEM and activated on next MC 21557 21557 - * warm reboot. A cold reboot resets the override. It is assumed that a 21558 21558 - * sufficient number of PFs are available and that port mapping is valid for 21559 21559 - * the new port mode, as the override does not affect PF configuration. 21560 21560 - */ 21561 21561 - #define MC_CMD_OVERRIDE_PORT_MODE 0x137 21562 21562 - #undef MC_CMD_0x137_PRIVILEGE_CTG 21563 21563 - 21564 21564 - #define MC_CMD_0x137_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21565 21565 - 21566 21566 - /* MC_CMD_OVERRIDE_PORT_MODE_IN msgrequest */ 21567 21567 - #define MC_CMD_OVERRIDE_PORT_MODE_IN_LEN 8 21568 21568 - #define MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_OFST 0 21569 21569 - #define MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_LEN 4 21570 21570 - #define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_OFST 0 21571 21571 - #define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_LBN 0 21572 21572 - #define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_WIDTH 1 21573 21573 - /* New mode (TLV_PORT_MODE_*) to set, if override enabled */ 21574 21574 - #define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_OFST 4 21575 21575 - #define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_LEN 4 21576 21576 - 21577 21577 - /* MC_CMD_OVERRIDE_PORT_MODE_OUT msgresponse */ 21578 21578 - #define MC_CMD_OVERRIDE_PORT_MODE_OUT_LEN 0 21579 21579 - 21580 21580 - 21581 21581 - /***********************************/ 21582 21582 - /* MC_CMD_READ_ATB 21583 21583 - * Sample voltages on the ATB 21584 21584 - */ 21585 21585 - #define MC_CMD_READ_ATB 0x100 21586 21586 - #undef MC_CMD_0x100_PRIVILEGE_CTG 21587 21587 - 21588 21588 - #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_INSECURE 21589 21589 - 21590 21590 - /* MC_CMD_READ_ATB_IN msgrequest */ 21591 21591 - #define MC_CMD_READ_ATB_IN_LEN 16 21592 21592 - #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0 21593 21593 - #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_LEN 4 21594 21594 - #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */ 21595 21595 - #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */ 21596 21596 - #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */ 21597 21597 - #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4 21598 21598 - #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_LEN 4 21599 21599 - #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8 21600 21600 - #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_LEN 4 21601 21601 - #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12 21602 21602 - #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_LEN 4 21603 21603 - 21604 21604 - /* MC_CMD_READ_ATB_OUT msgresponse */ 21605 21605 - #define MC_CMD_READ_ATB_OUT_LEN 4 21606 21606 - #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0 21607 21607 - #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_LEN 4 21608 22073 21609 22074 21610 22075 /***********************************/ ··· 21475 22538 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 21476 22539 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4 21477 22540 21478 21478 - 21479 21479 - /***********************************/ 21480 21480 - /* MC_CMD_GET_SNAPSHOT_LENGTH 21481 21481 - * Obtain the current range of allowable values for the SNAPSHOT_LENGTH 21482 21482 - * parameter to MC_CMD_INIT_RXQ. 21483 21483 - */ 21484 21484 - #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101 21485 21485 - #undef MC_CMD_0x101_PRIVILEGE_CTG 21486 21486 - 21487 21487 - #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21488 21488 - 21489 21489 - /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */ 21490 21490 - #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0 21491 21491 - 21492 21492 - /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */ 21493 21493 - #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8 21494 21494 - /* Minimum acceptable snapshot length. */ 21495 21495 - #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0 21496 21496 - #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_LEN 4 21497 21497 - /* Maximum acceptable snapshot length. */ 21498 21498 - #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4 21499 21499 - #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_LEN 4 21500 21500 - 21501 21501 - 21502 21502 - /***********************************/ 21503 21503 - /* MC_CMD_FUSE_DIAGS 21504 21504 - * Additional fuse diagnostics 21505 21505 - */ 21506 21506 - #define MC_CMD_FUSE_DIAGS 0x102 21507 21507 - #undef MC_CMD_0x102_PRIVILEGE_CTG 21508 21508 - 21509 21509 - #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE 21510 21510 - 21511 21511 - /* MC_CMD_FUSE_DIAGS_IN msgrequest */ 21512 21512 - #define MC_CMD_FUSE_DIAGS_IN_LEN 0 21513 21513 - 21514 21514 - /* MC_CMD_FUSE_DIAGS_OUT msgresponse */ 21515 21515 - #define MC_CMD_FUSE_DIAGS_OUT_LEN 48 21516 21516 - /* Total number of mismatched bits between pairs in area 0 */ 21517 21517 - #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0 21518 21518 - #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_LEN 4 21519 21519 - /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */ 21520 21520 - #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4 21521 21521 - #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_LEN 4 21522 21522 - /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */ 21523 21523 - #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8 21524 21524 - #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_LEN 4 21525 21525 - /* Checksum of data after logical OR of pairs in area 0 */ 21526 21526 - #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12 21527 21527 - #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_LEN 4 21528 21528 - /* Total number of mismatched bits between pairs in area 1 */ 21529 21529 - #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16 21530 21530 - #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_LEN 4 21531 21531 - /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */ 21532 21532 - #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20 21533 21533 - #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_LEN 4 21534 21534 - /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */ 21535 21535 - #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24 21536 21536 - #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_LEN 4 21537 21537 - /* Checksum of data after logical OR of pairs in area 1 */ 21538 21538 - #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28 21539 21539 - #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_LEN 4 21540 21540 - /* Total number of mismatched bits between pairs in area 2 */ 21541 21541 - #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32 21542 21542 - #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_LEN 4 21543 21543 - /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */ 21544 21544 - #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36 21545 21545 - #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_LEN 4 21546 21546 - /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */ 21547 21547 - #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40 21548 21548 - #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_LEN 4 21549 21549 - /* Checksum of data after logical OR of pairs in area 2 */ 21550 21550 - #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44 21551 21551 - #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 4 21552 21552 - 21553 21553 - 21554 21554 - /***********************************/ 21555 21555 - /* MC_CMD_PRIVILEGE_MODIFY 21556 21556 - * Modify the privileges of a set of PCIe functions. Note that this operation 21557 21557 - * only effects non-admin functions unless the admin privilege itself is 21558 21558 - * included in one of the masks provided. 21559 21559 - */ 21560 21560 - #define MC_CMD_PRIVILEGE_MODIFY 0x60 21561 21561 - #undef MC_CMD_0x60_PRIVILEGE_CTG 21562 21562 - 21563 21563 - #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21564 21564 - 21565 21565 - /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */ 21566 21566 - #define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16 21567 21567 - /* The groups of functions to have their privilege masks modified. */ 21568 21568 - #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0 21569 21569 - #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 4 21570 21570 - #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */ 21571 21571 - #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */ 21572 21572 - #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */ 21573 21573 - #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */ 21574 21574 - #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */ 21575 21575 - #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */ 21576 21576 - /* For VFS_OF_PF specify the PF, for ONE specify the target function */ 21577 21577 - #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4 21578 21578 - #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4 21579 21579 - #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_OFST 4 21580 21580 - #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0 21581 21581 - #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16 21582 21582 - #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_OFST 4 21583 21583 - #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16 21584 21584 - #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16 21585 21585 - /* Privileges to be added to the target functions. For privilege definitions 21586 21586 - * refer to the command MC_CMD_PRIVILEGE_MASK 21587 21587 - */ 21588 21588 - #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8 21589 21589 - #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_LEN 4 21590 21590 - /* Privileges to be removed from the target functions. For privilege 21591 21591 - * definitions refer to the command MC_CMD_PRIVILEGE_MASK 21592 21592 - */ 21593 21593 - #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12 21594 21594 - #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_LEN 4 21595 21595 - 21596 21596 - /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */ 21597 21597 - #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0 21598 21598 - 21599 21599 - 21600 21600 - /***********************************/ 21601 21601 - /* MC_CMD_XPM_READ_BYTES 21602 21602 - * Read XPM memory 21603 21603 - */ 21604 21604 - #define MC_CMD_XPM_READ_BYTES 0x103 21605 21605 - #undef MC_CMD_0x103_PRIVILEGE_CTG 21606 21606 - 21607 21607 - #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21608 21608 - 21609 21609 - /* MC_CMD_XPM_READ_BYTES_IN msgrequest */ 21610 21610 - #define MC_CMD_XPM_READ_BYTES_IN_LEN 8 21611 21611 - /* Start address (byte) */ 21612 21612 - #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0 21613 21613 - #define MC_CMD_XPM_READ_BYTES_IN_ADDR_LEN 4 21614 21614 - /* Count (bytes) */ 21615 21615 - #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4 21616 21616 - #define MC_CMD_XPM_READ_BYTES_IN_COUNT_LEN 4 21617 21617 - 21618 21618 - /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */ 21619 21619 - #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0 21620 21620 - #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252 21621 21621 - #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX_MCDI2 1020 21622 21622 - #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num)) 21623 21623 - #define MC_CMD_XPM_READ_BYTES_OUT_DATA_NUM(len) (((len)-0)/1) 21624 21624 - /* Data */ 21625 21625 - #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0 21626 21626 - #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1 21627 21627 - #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0 21628 21628 - #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252 21629 21629 - #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM_MCDI2 1020 21630 21630 - 21631 21631 - 21632 21632 - /***********************************/ 21633 21633 - /* MC_CMD_XPM_WRITE_BYTES 21634 21634 - * Write XPM memory 21635 21635 - */ 21636 21636 - #define MC_CMD_XPM_WRITE_BYTES 0x104 21637 21637 - #undef MC_CMD_0x104_PRIVILEGE_CTG 21638 21638 - 21639 21639 - #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_INSECURE 21640 21640 - 21641 21641 - /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */ 21642 21642 - #define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8 21643 21643 - #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252 21644 21644 - #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX_MCDI2 1020 21645 21645 - #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num)) 21646 21646 - #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_NUM(len) (((len)-8)/1) 21647 21647 - /* Start address (byte) */ 21648 21648 - #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0 21649 21649 - #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_LEN 4 21650 21650 - /* Count (bytes) */ 21651 21651 - #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4 21652 21652 - #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_LEN 4 21653 21653 - /* Data */ 21654 21654 - #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8 21655 21655 - #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1 21656 21656 - #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0 21657 21657 - #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244 21658 21658 - #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM_MCDI2 1012 21659 21659 - 21660 21660 - /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */ 21661 21661 - #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0 21662 21662 - 21663 21663 - 21664 21664 - /***********************************/ 21665 21665 - /* MC_CMD_XPM_READ_SECTOR 21666 21666 - * Read XPM sector 21667 21667 - */ 21668 21668 - #define MC_CMD_XPM_READ_SECTOR 0x105 21669 21669 - #undef MC_CMD_0x105_PRIVILEGE_CTG 21670 21670 - 21671 21671 - #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_INSECURE 21672 21672 - 21673 21673 - /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */ 21674 21674 - #define MC_CMD_XPM_READ_SECTOR_IN_LEN 8 21675 21675 - /* Sector index */ 21676 21676 - #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0 21677 21677 - #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_LEN 4 21678 21678 - /* Sector size */ 21679 21679 - #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4 21680 21680 - #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_LEN 4 21681 21681 - 21682 21682 - /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */ 21683 21683 - #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4 21684 21684 - #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36 21685 21685 - #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX_MCDI2 36 21686 21686 - #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num)) 21687 21687 - #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_NUM(len) (((len)-4)/1) 21688 21688 - /* Sector type */ 21689 21689 - #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0 21690 21690 - #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_LEN 4 21691 21691 - #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */ 21692 21692 - #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */ 21693 21693 - #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */ 21694 21694 - #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_DATA 0x3 /* enum */ 21695 21695 - #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */ 21696 21696 - /* Sector data */ 21697 21697 - #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4 21698 21698 - #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1 21699 21699 - #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0 21700 21700 - #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32 21701 21701 - #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM_MCDI2 32 21702 21702 - 21703 21703 - 21704 21704 - /***********************************/ 21705 21705 - /* MC_CMD_XPM_WRITE_SECTOR 21706 21706 - * Write XPM sector 21707 21707 - */ 21708 21708 - #define MC_CMD_XPM_WRITE_SECTOR 0x106 21709 21709 - #undef MC_CMD_0x106_PRIVILEGE_CTG 21710 21710 - 21711 21711 - #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_INSECURE 21712 21712 - 21713 21713 - /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */ 21714 21714 - #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12 21715 21715 - #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44 21716 21716 - #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX_MCDI2 44 21717 21717 - #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num)) 21718 21718 - #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_NUM(len) (((len)-12)/1) 21719 21719 - /* If writing fails due to an uncorrectable error, try up to RETRIES following 21720 21720 - * sectors (or until no more space available). If 0, only one write attempt is 21721 21721 - * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair 21722 21722 - * mechanism. 21723 21723 - */ 21724 21724 - #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0 21725 21725 - #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1 21726 21726 - #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1 21727 21727 - #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3 21728 21728 - /* Sector type */ 21729 21729 - #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4 21730 21730 - #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_LEN 4 21731 21731 - /* Enum values, see field(s): */ 21732 21732 - /* MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ 21733 21733 - /* Sector size */ 21734 21734 - #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8 21735 21735 - #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_LEN 4 21736 21736 - /* Sector data */ 21737 21737 - #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12 21738 21738 - #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1 21739 21739 - #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0 21740 21740 - #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32 21741 21741 - #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM_MCDI2 32 21742 21742 - 21743 21743 - /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */ 21744 21744 - #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4 21745 21745 - /* New sector index */ 21746 21746 - #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0 21747 21747 - #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_LEN 4 21748 21748 - 21749 21749 - 21750 21750 - /***********************************/ 21751 21751 - /* MC_CMD_XPM_INVALIDATE_SECTOR 21752 21752 - * Invalidate XPM sector 21753 21753 - */ 21754 21754 - #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107 21755 21755 - #undef MC_CMD_0x107_PRIVILEGE_CTG 21756 21756 - 21757 21757 - #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_INSECURE 21758 21758 - 21759 21759 - /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */ 21760 21760 - #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4 21761 21761 - /* Sector index */ 21762 21762 - #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0 21763 21763 - #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_LEN 4 21764 21764 - 21765 21765 - /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */ 21766 21766 - #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0 21767 21767 - 21768 21768 - 21769 21769 - /***********************************/ 21770 21770 - /* MC_CMD_XPM_BLANK_CHECK 21771 21771 - * Blank-check XPM memory and report bad locations 21772 21772 - */ 21773 21773 - #define MC_CMD_XPM_BLANK_CHECK 0x108 21774 21774 - #undef MC_CMD_0x108_PRIVILEGE_CTG 21775 21775 - 21776 21776 - #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_INSECURE 21777 21777 - 21778 21778 - /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */ 21779 21779 - #define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8 21780 21780 - /* Start address (byte) */ 21781 21781 - #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0 21782 21782 - #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_LEN 4 21783 21783 - /* Count (bytes) */ 21784 21784 - #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4 21785 21785 - #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_LEN 4 21786 21786 - 21787 21787 - /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */ 21788 21788 - #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4 21789 21789 - #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252 21790 21790 - #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX_MCDI2 1020 21791 21791 - #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num)) 21792 21792 - #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_NUM(len) (((len)-4)/2) 21793 21793 - /* Total number of bad (non-blank) locations */ 21794 21794 - #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0 21795 21795 - #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_LEN 4 21796 21796 - /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit 21797 21797 - * into MCDI response) 21798 21798 - */ 21799 21799 - #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4 21800 21800 - #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2 21801 21801 - #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0 21802 21802 - #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124 21803 21803 - #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM_MCDI2 508 21804 21804 - 21805 21805 - 21806 21806 - /***********************************/ 21807 21807 - /* MC_CMD_XPM_REPAIR 21808 21808 - * Blank-check and repair XPM memory 21809 21809 - */ 21810 21810 - #define MC_CMD_XPM_REPAIR 0x109 21811 21811 - #undef MC_CMD_0x109_PRIVILEGE_CTG 21812 21812 - 21813 21813 - #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_INSECURE 21814 21814 - 21815 21815 - /* MC_CMD_XPM_REPAIR_IN msgrequest */ 21816 21816 - #define MC_CMD_XPM_REPAIR_IN_LEN 8 21817 21817 - /* Start address (byte) */ 21818 21818 - #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0 21819 21819 - #define MC_CMD_XPM_REPAIR_IN_ADDR_LEN 4 21820 21820 - /* Count (bytes) */ 21821 21821 - #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4 21822 21822 - #define MC_CMD_XPM_REPAIR_IN_COUNT_LEN 4 21823 21823 - 21824 21824 - /* MC_CMD_XPM_REPAIR_OUT msgresponse */ 21825 21825 - #define MC_CMD_XPM_REPAIR_OUT_LEN 0 21826 21826 - 21827 21827 - 21828 21828 - /***********************************/ 21829 21829 - /* MC_CMD_XPM_DECODER_TEST 21830 21830 - * Test XPM memory address decoders for gross manufacturing defects. Can only 21831 21831 - * be performed on an unprogrammed part. 21832 21832 - */ 21833 21833 - #define MC_CMD_XPM_DECODER_TEST 0x10a 21834 21834 - #undef MC_CMD_0x10a_PRIVILEGE_CTG 21835 21835 - 21836 21836 - #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_INSECURE 21837 21837 - 21838 21838 - /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */ 21839 21839 - #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0 21840 21840 - 21841 21841 - /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */ 21842 21842 - #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0 21843 21843 - 21844 21844 - 21845 21845 - /***********************************/ 21846 21846 - /* MC_CMD_XPM_WRITE_TEST 21847 21847 - * XPM memory write test. Test XPM write logic for gross manufacturing defects 21848 21848 - * by writing to a dedicated test row. There are 16 locations in the test row 21849 21849 - * and the test can only be performed on locations that have not been 21850 21850 - * previously used (i.e. can be run at most 16 times). The test will pick the 21851 21851 - * first available location to use, or fail with ENOSPC if none left. 21852 21852 - */ 21853 21853 - #define MC_CMD_XPM_WRITE_TEST 0x10b 21854 21854 - #undef MC_CMD_0x10b_PRIVILEGE_CTG 21855 21855 - 21856 21856 - #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_INSECURE 21857 21857 - 21858 21858 - /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */ 21859 21859 - #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0 21860 21860 - 21861 21861 - /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ 21862 21862 - #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 21863 21863 - 21864 21864 - 21865 21865 - /***********************************/ 21866 21866 - /* MC_CMD_EXEC_SIGNED 21867 21867 - * Check the CMAC of the contents of IMEM and DMEM against the value supplied 21868 21868 - * and if correct begin execution from the start of IMEM. The caller supplies a 21869 21869 - * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC 21870 21870 - * computation runs from the start of IMEM, and from the start of DMEM + 16k, 21871 21871 - * to match flash booting. The command will respond with EINVAL if the CMAC 21872 21872 - * does match, otherwise it will respond with success before it jumps to IMEM. 21873 21873 - */ 21874 21874 - #define MC_CMD_EXEC_SIGNED 0x10c 21875 21875 - #undef MC_CMD_0x10c_PRIVILEGE_CTG 21876 21876 - 21877 21877 - #define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21878 21878 - 21879 21879 - /* MC_CMD_EXEC_SIGNED_IN msgrequest */ 21880 21880 - #define MC_CMD_EXEC_SIGNED_IN_LEN 28 21881 21881 - /* the length of code to include in the CMAC */ 21882 21882 - #define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0 21883 21883 - #define MC_CMD_EXEC_SIGNED_IN_CODELEN_LEN 4 21884 21884 - /* the length of date to include in the CMAC */ 21885 21885 - #define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4 21886 21886 - #define MC_CMD_EXEC_SIGNED_IN_DATALEN_LEN 4 21887 21887 - /* the XPM sector containing the key to use */ 21888 21888 - #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8 21889 21889 - #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_LEN 4 21890 21890 - /* the expected CMAC value */ 21891 21891 - #define MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12 21892 21892 - #define MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16 21893 21893 - 21894 21894 - /* MC_CMD_EXEC_SIGNED_OUT msgresponse */ 21895 21895 - #define MC_CMD_EXEC_SIGNED_OUT_LEN 0 21896 21896 - 21897 21897 - 21898 21898 - /***********************************/ 21899 21899 - /* MC_CMD_PREPARE_SIGNED 21900 21900 - * Prepare to upload a signed image. This will scrub the specified length of 21901 21901 - * the data region, which must be at least as large as the DATALEN supplied to 21902 21902 - * MC_CMD_EXEC_SIGNED. 21903 21903 - */ 21904 21904 - #define MC_CMD_PREPARE_SIGNED 0x10d 21905 21905 - #undef MC_CMD_0x10d_PRIVILEGE_CTG 21906 21906 - 21907 21907 - #define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21908 21908 - 21909 21909 - /* MC_CMD_PREPARE_SIGNED_IN msgrequest */ 21910 21910 - #define MC_CMD_PREPARE_SIGNED_IN_LEN 4 21911 21911 - /* the length of data area to clear */ 21912 21912 - #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0 21913 21913 - #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_LEN 4 21914 21914 - 21915 21915 - /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */ 21916 21916 - #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0 21917 21917 - 21918 21918 - 21919 22541 /* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */ 21920 22542 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4 21921 22543 /* UDP port (the standard ports are named below but any port may be used) */ ··· 21542 23046 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_OFST 0 21543 23047 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0 21544 23048 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1 21545 21545 - 21546 21546 - 21547 21547 - /***********************************/ 21548 21548 - /* MC_CMD_RX_BALANCING 21549 21549 - * Configure a port upconverter to distribute the packets on both RX engines. 21550 21550 - * Packets are distributed based on a table with the destination vFIFO. The 21551 21551 - * index of the table is a hash of source and destination of IPV4 and VLAN 21552 21552 - * priority. 21553 21553 - */ 21554 21554 - #define MC_CMD_RX_BALANCING 0x118 21555 21555 - #undef MC_CMD_0x118_PRIVILEGE_CTG 21556 21556 - 21557 21557 - #define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21558 21558 - 21559 21559 - /* MC_CMD_RX_BALANCING_IN msgrequest */ 21560 21560 - #define MC_CMD_RX_BALANCING_IN_LEN 16 21561 21561 - /* The RX port whose upconverter table will be modified */ 21562 21562 - #define MC_CMD_RX_BALANCING_IN_PORT_OFST 0 21563 21563 - #define MC_CMD_RX_BALANCING_IN_PORT_LEN 4 21564 21564 - /* The VLAN priority associated to the table index and vFIFO */ 21565 21565 - #define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4 21566 21566 - #define MC_CMD_RX_BALANCING_IN_PRIORITY_LEN 4 21567 21567 - /* The resulting bit of SRC^DST for indexing the table */ 21568 21568 - #define MC_CMD_RX_BALANCING_IN_SRC_DST_OFST 8 21569 21569 - #define MC_CMD_RX_BALANCING_IN_SRC_DST_LEN 4 21570 21570 - /* The RX engine to which the vFIFO in the table entry will point to */ 21571 21571 - #define MC_CMD_RX_BALANCING_IN_ENG_OFST 12 21572 21572 - #define MC_CMD_RX_BALANCING_IN_ENG_LEN 4 21573 21573 - 21574 21574 - /* MC_CMD_RX_BALANCING_OUT msgresponse */ 21575 21575 - #define MC_CMD_RX_BALANCING_OUT_LEN 0 21576 21576 - 21577 21577 - 21578 21578 - /***********************************/ 21579 21579 - /* MC_CMD_NVRAM_PRIVATE_APPEND 21580 21580 - * Append a single TLV to the MC_USAGE_TLV partition. Returns MC_CMD_ERR_EEXIST 21581 21581 - * if the tag is already present. 21582 21582 - */ 21583 21583 - #define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c 21584 21584 - #undef MC_CMD_0x11c_PRIVILEGE_CTG 21585 21585 - 21586 21586 - #define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21587 21587 - 21588 21588 - /* MC_CMD_NVRAM_PRIVATE_APPEND_IN msgrequest */ 21589 21589 - #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMIN 9 21590 21590 - #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX 252 21591 21591 - #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX_MCDI2 1020 21592 21592 - #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num)) 21593 21593 - #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_NUM(len) (((len)-8)/1) 21594 21594 - /* The tag to be appended */ 21595 21595 - #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0 21596 21596 - #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_LEN 4 21597 21597 - /* The length of the data */ 21598 21598 - #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4 21599 21599 - #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_LEN 4 21600 21600 - /* The data to be contained in the TLV structure */ 21601 21601 - #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_OFST 8 21602 21602 - #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1 21603 21603 - #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1 21604 21604 - #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM 244 21605 21605 - #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM_MCDI2 1012 21606 21606 - 21607 21607 - /* MC_CMD_NVRAM_PRIVATE_APPEND_OUT msgresponse */ 21608 21608 - #define MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0 21609 21609 - 21610 21610 - 21611 21611 - /***********************************/ 21612 21612 - /* MC_CMD_XPM_VERIFY_CONTENTS 21613 21613 - * Verify that the contents of the XPM memory is correct (Medford only). This 21614 21614 - * is used during manufacture to check that the XPM memory has been programmed 21615 21615 - * correctly at ATE. 21616 21616 - */ 21617 21617 - #define MC_CMD_XPM_VERIFY_CONTENTS 0x11b 21618 21618 - #undef MC_CMD_0x11b_PRIVILEGE_CTG 21619 21619 - 21620 21620 - #define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21621 21621 - 21622 21622 - /* MC_CMD_XPM_VERIFY_CONTENTS_IN msgrequest */ 21623 21623 - #define MC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4 21624 21624 - /* Data type to be checked */ 21625 21625 - #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0 21626 21626 - #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_LEN 4 21627 21627 - 21628 21628 - /* MC_CMD_XPM_VERIFY_CONTENTS_OUT msgresponse */ 21629 21629 - #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMIN 12 21630 21630 - #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX 252 21631 21631 - #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX_MCDI2 1020 21632 21632 - #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num)) 21633 21633 - #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_NUM(len) (((len)-12)/1) 21634 21634 - /* Number of sectors found (test builds only) */ 21635 21635 - #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0 21636 21636 - #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_LEN 4 21637 21637 - /* Number of bytes found (test builds only) */ 21638 21638 - #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4 21639 21639 - #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_LEN 4 21640 21640 - /* Length of signature */ 21641 21641 - #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_OFST 8 21642 21642 - #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_LEN 4 21643 21643 - /* Signature */ 21644 21644 - #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_OFST 12 21645 21645 - #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1 21646 21646 - #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0 21647 21647 - #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM 240 21648 21648 - #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM_MCDI2 1008 21649 23049 21650 23050 21651 23051 /***********************************/ ··· 21654 23262 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32 21655 23263 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_LEN 4 21656 23264 21657 21657 - 21658 21658 - /***********************************/ 21659 21659 - /* MC_CMD_ALLOCATE_TX_VFIFO_CP 21660 21660 - * When we use the TX_vFIFO_ULL mode, we can allocate common pools using the 21661 21661 - * non used switch buffers. 21662 21662 - */ 21663 21663 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d 21664 21664 - #undef MC_CMD_0x11d_PRIVILEGE_CTG 21665 21665 - 21666 21666 - #define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21667 21667 - 21668 21668 - /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */ 21669 21669 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20 21670 21670 - /* Desired instance. Must be set to a specific instance, which is a function 21671 21671 - * local queue index. The calling client must be the currently-assigned user of 21672 21672 - * this VI (see MC_CMD_SET_VI_USER). 21673 21673 - */ 21674 21674 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0 21675 21675 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4 21676 21676 - /* Will the common pool be used as TX_vFIFO_ULL (1) */ 21677 21677 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4 21678 21678 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_LEN 4 21679 21679 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */ 21680 21680 - /* enum: Using this interface without TX_vFIFO_ULL is not supported for now */ 21681 21681 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0 21682 21682 - /* Number of buffers to reserve for the common pool */ 21683 21683 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_OFST 8 21684 21684 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_LEN 4 21685 21685 - /* TX datapath to which the Common Pool is connected to. */ 21686 21686 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_OFST 12 21687 21687 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_LEN 4 21688 21688 - /* enum: Extracts information from function */ 21689 21689 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 21690 21690 - /* Network port or RX Engine to which the common pool connects. */ 21691 21691 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_OFST 16 21692 21692 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_LEN 4 21693 21693 - /* enum: Extracts information from function */ 21694 21694 - /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */ 21695 21695 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */ 21696 21696 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */ 21697 21697 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */ 21698 21698 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */ 21699 21699 - /* enum: To enable Switch loopback with Rx engine 0 */ 21700 21700 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4 21701 21701 - /* enum: To enable Switch loopback with Rx engine 1 */ 21702 21702 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5 21703 21703 - 21704 21704 - /* MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 21705 21705 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4 21706 21706 - /* ID of the common pool allocated */ 21707 21707 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0 21708 21708 - #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_LEN 4 21709 21709 - 21710 21710 - 21711 21711 - /***********************************/ 21712 21712 - /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 21713 21713 - * When we use the TX_vFIFO_ULL mode, we can allocate vFIFOs using the 21714 21714 - * previously allocated common pools. 21715 21715 - */ 21716 21716 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e 21717 21717 - #undef MC_CMD_0x11e_PRIVILEGE_CTG 21718 21718 - 21719 21719 - #define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21720 21720 - 21721 21721 - /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN msgrequest */ 21722 21722 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LEN 20 21723 21723 - /* Common pool previously allocated to which the new vFIFO will be associated 21724 21724 - */ 21725 21725 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0 21726 21726 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_LEN 4 21727 21727 - /* Port or RX engine to associate the vFIFO egress */ 21728 21728 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4 21729 21729 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_LEN 4 21730 21730 - /* enum: Extracts information from common pool */ 21731 21731 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1 21732 21732 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */ 21733 21733 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */ 21734 21734 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */ 21735 21735 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */ 21736 21736 - /* enum: To enable Switch loopback with Rx engine 0 */ 21737 21737 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4 21738 21738 - /* enum: To enable Switch loopback with Rx engine 1 */ 21739 21739 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5 21740 21740 - /* Minimum number of buffers that the pool must have */ 21741 21741 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_OFST 8 21742 21742 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_LEN 4 21743 21743 - /* enum: Do not check the space available */ 21744 21744 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0 21745 21745 - /* Will the vFIFO be used as TX_vFIFO_ULL */ 21746 21746 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_OFST 12 21747 21747 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_LEN 4 21748 21748 - /* Network priority of the vFIFO,if applicable */ 21749 21749 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_OFST 16 21750 21750 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_LEN 4 21751 21751 - /* enum: Search for the lowest unused priority */ 21752 21752 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1 21753 21753 - 21754 21754 - /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT msgresponse */ 21755 21755 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_LEN 8 21756 21756 - /* Short vFIFO ID */ 21757 21757 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0 21758 21758 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_LEN 4 21759 21759 - /* Network priority of the vFIFO */ 21760 21760 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4 21761 21761 - #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_LEN 4 21762 21762 - 21763 21763 - 21764 21764 - /***********************************/ 21765 21765 - /* MC_CMD_TEARDOWN_TX_VFIFO_VF 21766 21766 - * This interface clears the configuration of the given vFIFO and leaves it 21767 21767 - * ready to be re-used. 21768 21768 - */ 21769 21769 - #define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f 21770 21770 - #undef MC_CMD_0x11f_PRIVILEGE_CTG 21771 21771 - 21772 21772 - #define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21773 21773 - 21774 21774 - /* MC_CMD_TEARDOWN_TX_VFIFO_VF_IN msgrequest */ 21775 21775 - #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4 21776 21776 - /* Short vFIFO ID */ 21777 21777 - #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0 21778 21778 - #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_LEN 4 21779 21779 - 21780 21780 - /* MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT msgresponse */ 21781 21781 - #define MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0 21782 21782 - 21783 21783 - 21784 21784 - /***********************************/ 21785 21785 - /* MC_CMD_DEALLOCATE_TX_VFIFO_CP 21786 21786 - * This interface clears the configuration of the given common pool and leaves 21787 21787 - * it ready to be re-used. 21788 21788 - */ 21789 21789 - #define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121 21790 21790 - #undef MC_CMD_0x121_PRIVILEGE_CTG 21791 21791 - 21792 21792 - #define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21793 21793 - 21794 21794 - /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN msgrequest */ 21795 21795 - #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4 21796 21796 - /* Common pool ID given when pool allocated */ 21797 21797 - #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0 21798 21798 - #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_LEN 4 21799 21799 - 21800 21800 - /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 21801 21801 - #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0 21802 21802 - 21803 21803 - 21804 21804 - /***********************************/ 21805 21805 - /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 21806 21806 - * This interface allows the host to find out how many common pool buffers are 21807 21807 - * not yet assigned. 21808 21808 - */ 21809 21809 - #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124 21810 21810 - #undef MC_CMD_0x124_PRIVILEGE_CTG 21811 21811 - 21812 21812 - #define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21813 21813 - 21814 21814 - /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN msgrequest */ 21815 21815 - #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0 21816 21816 - 21817 21817 - /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT msgresponse */ 21818 21818 - #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_LEN 8 21819 21819 - /* Available buffers for the ENG to NET vFIFOs. */ 21820 21820 - #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0 21821 21821 - #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_LEN 4 21822 21822 - /* Available buffers for the ENG to ENG and NET to ENG vFIFOs. */ 21823 21823 - #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4 21824 21824 - #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_LEN 4 21825 21825 - 21826 21826 - 21827 21827 - /***********************************/ 21828 21828 - /* MC_CMD_SUC_VERSION 21829 21829 - * Get the version of the SUC 21830 21830 - */ 21831 21831 - #define MC_CMD_SUC_VERSION 0x134 21832 21832 - #undef MC_CMD_0x134_PRIVILEGE_CTG 21833 21833 - 21834 21834 - #define MC_CMD_0x134_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21835 21835 - 21836 21836 - /* MC_CMD_SUC_VERSION_IN msgrequest */ 21837 21837 - #define MC_CMD_SUC_VERSION_IN_LEN 0 21838 21838 - 21839 21839 - /* MC_CMD_SUC_VERSION_OUT msgresponse */ 21840 21840 - #define MC_CMD_SUC_VERSION_OUT_LEN 24 21841 21841 - /* The SUC firmware version as four numbers - a.b.c.d */ 21842 21842 - #define MC_CMD_SUC_VERSION_OUT_VERSION_OFST 0 21843 21843 - #define MC_CMD_SUC_VERSION_OUT_VERSION_LEN 4 21844 21844 - #define MC_CMD_SUC_VERSION_OUT_VERSION_NUM 4 21845 21845 - /* The date, in seconds since the Unix epoch, when the firmware image was 21846 21846 - * built. 21847 21847 - */ 21848 21848 - #define MC_CMD_SUC_VERSION_OUT_BUILD_DATE_OFST 16 21849 21849 - #define MC_CMD_SUC_VERSION_OUT_BUILD_DATE_LEN 4 21850 21850 - /* The ID of the SUC chip. This is specific to the platform but typically 21851 21851 - * indicates family, memory sizes etc. See SF-116728-SW for further details. 21852 21852 - */ 21853 21853 - #define MC_CMD_SUC_VERSION_OUT_CHIP_ID_OFST 20 21854 21854 - #define MC_CMD_SUC_VERSION_OUT_CHIP_ID_LEN 4 21855 21855 - 21856 21856 - /* MC_CMD_SUC_BOOT_VERSION_IN msgrequest: Get the version of the SUC boot 21857 21857 - * loader. 21858 21858 - */ 21859 21859 - #define MC_CMD_SUC_BOOT_VERSION_IN_LEN 4 21860 21860 - #define MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_OFST 0 21861 21861 - #define MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_LEN 4 21862 21862 - /* enum: Requests the SUC boot version. */ 21863 21863 - #define MC_CMD_SUC_VERSION_GET_BOOT_VERSION 0xb007700b 21864 21864 - 21865 21865 - /* MC_CMD_SUC_BOOT_VERSION_OUT msgresponse */ 21866 21866 - #define MC_CMD_SUC_BOOT_VERSION_OUT_LEN 4 21867 21867 - /* The SUC boot version */ 21868 21868 - #define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_OFST 0 21869 21869 - #define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_LEN 4 21870 21870 - 21871 21871 - 21872 21872 - /***********************************/ 21873 21873 - /* MC_CMD_GET_RX_PREFIX_ID 21874 21874 - * This command is part of the mechanism for configuring the format of the RX 21875 21875 - * packet prefix. It takes as input a bitmask of the fields the host would like 21876 21876 - * to be in the prefix. If the hardware supports RX prefixes with that 21877 21877 - * combination of fields, then this command returns a list of prefix-ids, 21878 21878 - * opaque identifiers suitable for use in the RX_PREFIX_ID field of a 21879 21879 - * MC_CMD_INIT_RXQ_V5_IN message. If the combination of fields is not 21880 21880 - * supported, returns ENOTSUP. If the firmware can't create any new prefix-ids 21881 21881 - * due to resource constraints, returns ENOSPC. 21882 21882 - */ 21883 21883 - #define MC_CMD_GET_RX_PREFIX_ID 0x13b 21884 21884 - #undef MC_CMD_0x13b_PRIVILEGE_CTG 21885 21885 - 21886 21886 - #define MC_CMD_0x13b_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21887 21887 - 21888 21888 - /* MC_CMD_GET_RX_PREFIX_ID_IN msgrequest */ 21889 21889 - #define MC_CMD_GET_RX_PREFIX_ID_IN_LEN 8 21890 21890 - /* Field bitmask. */ 21891 21891 - #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_OFST 0 21892 21892 - #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LEN 8 21893 21893 - #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_OFST 0 21894 21894 - #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_LEN 4 21895 21895 - #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_LBN 0 21896 21896 - #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_WIDTH 32 21897 21897 - #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_OFST 4 21898 21898 - #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_LEN 4 21899 21899 - #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_LBN 32 21900 21900 - #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_WIDTH 32 21901 21901 - #define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_OFST 0 21902 21902 - #define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_LBN 0 21903 21903 - #define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_WIDTH 1 21904 21904 - #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_OFST 0 21905 21905 - #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_LBN 1 21906 21906 - #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_WIDTH 1 21907 21907 - #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_OFST 0 21908 21908 - #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_LBN 2 21909 21909 - #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_WIDTH 1 21910 21910 - #define MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_OFST 0 21911 21911 - #define MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_LBN 3 21912 21912 - #define MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_WIDTH 1 21913 21913 - #define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_OFST 0 21914 21914 - #define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_LBN 4 21915 21915 - #define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_WIDTH 1 21916 21916 - #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_OFST 0 21917 21917 - #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_LBN 5 21918 21918 - #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_WIDTH 1 21919 21919 - #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_OFST 0 21920 21920 - #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_LBN 6 21921 21921 - #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_WIDTH 1 21922 21922 - #define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_MPORT_OFST 0 21923 21923 - #define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_MPORT_LBN 7 21924 21924 - #define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_MPORT_WIDTH 1 21925 21925 - #define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_OFST 0 21926 21926 - #define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_LBN 7 21927 21927 - #define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_WIDTH 1 21928 21928 - #define MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_OFST 0 21929 21929 - #define MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_LBN 8 21930 21930 - #define MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_WIDTH 1 21931 21931 - #define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_OFST 0 21932 21932 - #define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_LBN 9 21933 21933 - #define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_WIDTH 1 21934 21934 - #define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIPPED_OFST 0 21935 21935 - #define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIPPED_LBN 10 21936 21936 - #define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIPPED_WIDTH 1 21937 21937 - #define MC_CMD_GET_RX_PREFIX_ID_IN_VSWITCH_STATUS_OFST 0 21938 21938 - #define MC_CMD_GET_RX_PREFIX_ID_IN_VSWITCH_STATUS_LBN 11 21939 21939 - #define MC_CMD_GET_RX_PREFIX_ID_IN_VSWITCH_STATUS_WIDTH 1 21940 21940 - 21941 21941 - /* MC_CMD_GET_RX_PREFIX_ID_OUT msgresponse */ 21942 21942 - #define MC_CMD_GET_RX_PREFIX_ID_OUT_LENMIN 8 21943 21943 - #define MC_CMD_GET_RX_PREFIX_ID_OUT_LENMAX 252 21944 21944 - #define MC_CMD_GET_RX_PREFIX_ID_OUT_LENMAX_MCDI2 1020 21945 21945 - #define MC_CMD_GET_RX_PREFIX_ID_OUT_LEN(num) (4+4*(num)) 21946 21946 - #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_NUM(len) (((len)-4)/4) 21947 21947 - /* Number of prefix-ids returned */ 21948 21948 - #define MC_CMD_GET_RX_PREFIX_ID_OUT_NUM_RX_PREFIX_IDS_OFST 0 21949 21949 - #define MC_CMD_GET_RX_PREFIX_ID_OUT_NUM_RX_PREFIX_IDS_LEN 4 21950 21950 - /* Opaque prefix identifiers which can be passed into MC_CMD_INIT_RXQ_V5 or 21951 21951 - * MC_CMD_QUERY_PREFIX_ID 21952 21952 - */ 21953 21953 - #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_OFST 4 21954 21954 - #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_LEN 4 21955 21955 - #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_MINNUM 1 21956 21956 - #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_MAXNUM 62 21957 21957 - #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_MAXNUM_MCDI2 254 21958 21958 - 21959 21959 - /* RX_PREFIX_FIELD_INFO structuredef: Information about a single RX prefix 21960 21960 - * field 21961 21961 - */ 21962 21962 - #define RX_PREFIX_FIELD_INFO_LEN 4 21963 21963 - /* The offset of the field from the start of the prefix, in bits */ 21964 21964 - #define RX_PREFIX_FIELD_INFO_OFFSET_BITS_OFST 0 21965 21965 - #define RX_PREFIX_FIELD_INFO_OFFSET_BITS_LEN 2 21966 21966 - #define RX_PREFIX_FIELD_INFO_OFFSET_BITS_LBN 0 21967 21967 - #define RX_PREFIX_FIELD_INFO_OFFSET_BITS_WIDTH 16 21968 21968 - /* The width of the field, in bits */ 21969 21969 - #define RX_PREFIX_FIELD_INFO_WIDTH_BITS_OFST 2 21970 21970 - #define RX_PREFIX_FIELD_INFO_WIDTH_BITS_LEN 1 21971 21971 - #define RX_PREFIX_FIELD_INFO_WIDTH_BITS_LBN 16 21972 21972 - #define RX_PREFIX_FIELD_INFO_WIDTH_BITS_WIDTH 8 21973 21973 - /* The type of the field. These enum values are in the same order as the fields 21974 21974 - * in the MC_CMD_GET_RX_PREFIX_ID_IN bitmask 21975 21975 - */ 21976 21976 - #define RX_PREFIX_FIELD_INFO_TYPE_OFST 3 21977 21977 - #define RX_PREFIX_FIELD_INFO_TYPE_LEN 1 21978 21978 - #define RX_PREFIX_FIELD_INFO_LENGTH 0x0 /* enum */ 21979 21979 - #define RX_PREFIX_FIELD_INFO_RSS_HASH_VALID 0x1 /* enum */ 21980 21980 - #define RX_PREFIX_FIELD_INFO_USER_FLAG 0x2 /* enum */ 21981 21981 - #define RX_PREFIX_FIELD_INFO_CLASS 0x3 /* enum */ 21982 21982 - #define RX_PREFIX_FIELD_INFO_PARTIAL_TSTAMP 0x4 /* enum */ 21983 21983 - #define RX_PREFIX_FIELD_INFO_RSS_HASH 0x5 /* enum */ 21984 21984 - #define RX_PREFIX_FIELD_INFO_USER_MARK 0x6 /* enum */ 21985 21985 - #define RX_PREFIX_FIELD_INFO_INGRESS_MPORT 0x7 /* enum */ 21986 21986 - #define RX_PREFIX_FIELD_INFO_INGRESS_VPORT 0x7 /* enum */ 21987 21987 - #define RX_PREFIX_FIELD_INFO_CSUM_FRAME 0x8 /* enum */ 21988 21988 - #define RX_PREFIX_FIELD_INFO_VLAN_STRIP_TCI 0x9 /* enum */ 21989 21989 - #define RX_PREFIX_FIELD_INFO_VLAN_STRIPPED 0xa /* enum */ 21990 21990 - #define RX_PREFIX_FIELD_INFO_VSWITCH_STATUS 0xb /* enum */ 21991 21991 - #define RX_PREFIX_FIELD_INFO_TYPE_LBN 24 21992 21992 - #define RX_PREFIX_FIELD_INFO_TYPE_WIDTH 8 21993 21993 - 21994 21994 - /* RX_PREFIX_FIXED_RESPONSE structuredef: Information about an RX prefix in 21995 21995 - * which every field has a fixed offset and width 21996 21996 - */ 21997 21997 - #define RX_PREFIX_FIXED_RESPONSE_LENMIN 4 21998 21998 - #define RX_PREFIX_FIXED_RESPONSE_LENMAX 252 21999 21999 - #define RX_PREFIX_FIXED_RESPONSE_LENMAX_MCDI2 1020 22000 22000 - #define RX_PREFIX_FIXED_RESPONSE_LEN(num) (4+4*(num)) 22001 22001 - #define RX_PREFIX_FIXED_RESPONSE_FIELDS_NUM(len) (((len)-4)/4) 22002 22002 - /* Length of the RX prefix in bytes */ 22003 22003 - #define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_OFST 0 22004 22004 - #define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_LEN 1 22005 22005 - #define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_LBN 0 22006 22006 - #define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_WIDTH 8 22007 22007 - /* Number of fields present in the prefix */ 22008 22008 - #define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_OFST 1 22009 22009 - #define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_LEN 1 22010 22010 - #define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_LBN 8 22011 22011 - #define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_WIDTH 8 22012 22012 - #define RX_PREFIX_FIXED_RESPONSE_RESERVED_OFST 2 22013 22013 - #define RX_PREFIX_FIXED_RESPONSE_RESERVED_LEN 2 22014 22014 - #define RX_PREFIX_FIXED_RESPONSE_RESERVED_LBN 16 22015 22015 - #define RX_PREFIX_FIXED_RESPONSE_RESERVED_WIDTH 16 22016 22016 - /* Array of RX_PREFIX_FIELD_INFO structures, of length FIELD_COUNT */ 22017 22017 - #define RX_PREFIX_FIXED_RESPONSE_FIELDS_OFST 4 22018 22018 - #define RX_PREFIX_FIXED_RESPONSE_FIELDS_LEN 4 22019 22019 - #define RX_PREFIX_FIXED_RESPONSE_FIELDS_MINNUM 0 22020 22020 - #define RX_PREFIX_FIXED_RESPONSE_FIELDS_MAXNUM 62 22021 22021 - #define RX_PREFIX_FIXED_RESPONSE_FIELDS_MAXNUM_MCDI2 254 22022 22022 - #define RX_PREFIX_FIXED_RESPONSE_FIELDS_LBN 32 22023 22023 - #define RX_PREFIX_FIXED_RESPONSE_FIELDS_WIDTH 32 22024 22024 - 22025 22025 - 22026 22026 - /***********************************/ 22027 22027 - /* MC_CMD_QUERY_RX_PREFIX_ID 22028 22028 - * This command takes an RX prefix id (obtained from MC_CMD_GET_RX_PREFIX_ID) 22029 22029 - * and returns a description of the RX prefix of packets delievered to an RXQ 22030 22030 - * created with that prefix id 22031 22031 - */ 22032 22032 - #define MC_CMD_QUERY_RX_PREFIX_ID 0x13c 22033 22033 - #undef MC_CMD_0x13c_PRIVILEGE_CTG 22034 22034 - 22035 22035 - #define MC_CMD_0x13c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 22036 22036 - 22037 22037 - /* MC_CMD_QUERY_RX_PREFIX_ID_IN msgrequest */ 22038 22038 - #define MC_CMD_QUERY_RX_PREFIX_ID_IN_LEN 4 22039 22039 - /* Prefix id to query */ 22040 22040 - #define MC_CMD_QUERY_RX_PREFIX_ID_IN_RX_PREFIX_ID_OFST 0 22041 22041 - #define MC_CMD_QUERY_RX_PREFIX_ID_IN_RX_PREFIX_ID_LEN 4 22042 22042 - 22043 22043 - /* MC_CMD_QUERY_RX_PREFIX_ID_OUT msgresponse */ 22044 22044 - #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMIN 4 22045 22045 - #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMAX 252 22046 22046 - #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMAX_MCDI2 1020 22047 22047 - #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LEN(num) (4+1*(num)) 22048 22048 - #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_NUM(len) (((len)-4)/1) 22049 22049 - /* An enum describing the structure of this response. */ 22050 22050 - #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_OFST 0 22051 22051 - #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_LEN 1 22052 22052 - /* enum: The response is of format RX_PREFIX_FIXED_RESPONSE */ 22053 22053 - #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_FIXED 0x0 22054 22054 - #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESERVED_OFST 1 22055 22055 - #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESERVED_LEN 3 22056 22056 - /* The response. Its format is as defined by the RESPONSE_TYPE value */ 22057 22057 - #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_OFST 4 22058 22058 - #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_LEN 1 22059 22059 - #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_MINNUM 0 22060 22060 - #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_MAXNUM 248 22061 22061 - #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_MAXNUM_MCDI2 1016 22062 22062 - 22063 22063 - 22064 22064 - /***********************************/ 22065 22065 - /* MC_CMD_BUNDLE 22066 22066 - * A command to perform various bundle-related operations on insecure cards. 22067 22067 - */ 22068 22068 - #define MC_CMD_BUNDLE 0x13d 22069 22069 - #undef MC_CMD_0x13d_PRIVILEGE_CTG 22070 22070 - 22071 22071 - #define MC_CMD_0x13d_PRIVILEGE_CTG SRIOV_CTG_INSECURE 22072 22072 - 22073 22073 - /* MC_CMD_BUNDLE_IN msgrequest */ 22074 22074 - #define MC_CMD_BUNDLE_IN_LEN 4 22075 22075 - /* Sub-command code */ 22076 22076 - #define MC_CMD_BUNDLE_IN_OP_OFST 0 22077 22077 - #define MC_CMD_BUNDLE_IN_OP_LEN 4 22078 22078 - /* enum: Get the current host access mode set on component partitions. */ 22079 22079 - #define MC_CMD_BUNDLE_IN_OP_COMPONENT_ACCESS_GET 0x0 22080 22080 - /* enum: Set the host access mode set on component partitions. */ 22081 22081 - #define MC_CMD_BUNDLE_IN_OP_COMPONENT_ACCESS_SET 0x1 22082 22082 - 22083 22083 - /* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN msgrequest: Retrieve the current 22084 22084 - * access mode on component partitions such as MC_FIRMWARE, SUC_FIRMWARE and 22085 22085 - * EXPANSION_UEFI. This command only works on engineering (insecure) cards. On 22086 22086 - * secure adapters, this command returns MC_CMD_ERR_EPERM. 22087 22087 - */ 22088 22088 - #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_LEN 4 22089 22089 - /* Sub-command code. Must be OP_COMPONENT_ACCESS_GET. */ 22090 22090 - #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_OP_OFST 0 22091 22091 - #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_OP_LEN 4 22092 22092 - 22093 22093 - /* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT msgresponse: Returns the access 22094 22094 - * control mode. 22095 22095 - */ 22096 22096 - #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_LEN 4 22097 22097 - /* Access mode of component partitions. */ 22098 22098 - #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_ACCESS_MODE_OFST 0 22099 22099 - #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_ACCESS_MODE_LEN 4 22100 22100 - /* enum: Component partitions are read-only from the host. */ 22101 22101 - #define MC_CMD_BUNDLE_COMPONENTS_READ_ONLY 0x0 22102 22102 - /* enum: Component partitions can read read-from written-to by the host. */ 22103 22103 - #define MC_CMD_BUNDLE_COMPONENTS_READ_WRITE 0x1 22104 22104 - 22105 22105 - /* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN msgrequest: The component 22106 22106 - * partitions such as MC_FIRMWARE, SUC_FIRMWARE, EXPANSION_UEFI are set as 22107 22107 - * read-only on firmware built with bundle support. This command marks these 22108 22108 - * partitions as read/writeable. The access status set by this command does not 22109 22109 - * persist across MC reboots. This command only works on engineering (insecure) 22110 22110 - * cards. On secure adapters, this command returns MC_CMD_ERR_EPERM. 22111 22111 - */ 22112 22112 - #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_LEN 8 22113 22113 - /* Sub-command code. Must be OP_COMPONENT_ACCESS_SET. */ 22114 22114 - #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_OP_OFST 0 22115 22115 - #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_OP_LEN 4 22116 22116 - /* Access mode of component partitions. */ 22117 22117 - #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_ACCESS_MODE_OFST 4 22118 22118 - #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_ACCESS_MODE_LEN 4 22119 22119 - /* Enum values, see field(s): */ 22120 22120 - /* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT/ACCESS_MODE */ 22121 22121 - 22122 22122 - /* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_OUT msgresponse */ 22123 22123 - #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_OUT_LEN 0 22124 22124 - 22125 22125 - 22126 22126 - /***********************************/ 22127 22127 - /* MC_CMD_GET_VPD 22128 22128 - * Read all VPD starting from a given address 22129 22129 - */ 22130 22130 - #define MC_CMD_GET_VPD 0x165 22131 22131 - #undef MC_CMD_0x165_PRIVILEGE_CTG 22132 22132 - 22133 22133 - #define MC_CMD_0x165_PRIVILEGE_CTG SRIOV_CTG_GENERAL 22134 22134 - 22135 22135 - /* MC_CMD_GET_VPD_IN msgresponse */ 22136 22136 - #define MC_CMD_GET_VPD_IN_LEN 4 22137 22137 - /* VPD address to start from. In case VPD is longer than MCDI buffer 22138 22138 - * (unlikely), user can make multiple calls with different starting addresses. 22139 22139 - */ 22140 22140 - #define MC_CMD_GET_VPD_IN_ADDR_OFST 0 22141 22141 - #define MC_CMD_GET_VPD_IN_ADDR_LEN 4 22142 22142 - 22143 22143 - /* MC_CMD_GET_VPD_OUT msgresponse */ 22144 22144 - #define MC_CMD_GET_VPD_OUT_LENMIN 0 22145 22145 - #define MC_CMD_GET_VPD_OUT_LENMAX 252 22146 22146 - #define MC_CMD_GET_VPD_OUT_LENMAX_MCDI2 1020 22147 22147 - #define MC_CMD_GET_VPD_OUT_LEN(num) (0+1*(num)) 22148 22148 - #define MC_CMD_GET_VPD_OUT_DATA_NUM(len) (((len)-0)/1) 22149 22149 - /* VPD data returned. */ 22150 22150 - #define MC_CMD_GET_VPD_OUT_DATA_OFST 0 22151 22151 - #define MC_CMD_GET_VPD_OUT_DATA_LEN 1 22152 22152 - #define MC_CMD_GET_VPD_OUT_DATA_MINNUM 0 22153 22153 - #define MC_CMD_GET_VPD_OUT_DATA_MAXNUM 252 22154 22154 - #define MC_CMD_GET_VPD_OUT_DATA_MAXNUM_MCDI2 1020 22155 22155 - 22156 22156 - 22157 22157 - /***********************************/ 22158 22158 - /* MC_CMD_GET_NCSI_INFO 22159 22159 - * Provide information about the NC-SI stack 22160 22160 - */ 22161 22161 - #define MC_CMD_GET_NCSI_INFO 0x167 22162 22162 - #undef MC_CMD_0x167_PRIVILEGE_CTG 22163 22163 - 22164 22164 - #define MC_CMD_0x167_PRIVILEGE_CTG SRIOV_CTG_GENERAL 22165 22165 - 22166 22166 - /* MC_CMD_GET_NCSI_INFO_IN msgrequest */ 22167 22167 - #define MC_CMD_GET_NCSI_INFO_IN_LEN 8 22168 22168 - /* Operation to be performed */ 22169 22169 - #define MC_CMD_GET_NCSI_INFO_IN_OP_OFST 0 22170 22170 - #define MC_CMD_GET_NCSI_INFO_IN_OP_LEN 4 22171 22171 - /* enum: Information on the link settings. */ 22172 22172 - #define MC_CMD_GET_NCSI_INFO_IN_OP_LINK 0x0 22173 22173 - /* enum: Statistics associated with the channel */ 22174 22174 - #define MC_CMD_GET_NCSI_INFO_IN_OP_STATISTICS 0x1 22175 22175 - /* The NC-SI channel on which the operation is to be performed */ 22176 22176 - #define MC_CMD_GET_NCSI_INFO_IN_CHANNEL_OFST 4 22177 22177 - #define MC_CMD_GET_NCSI_INFO_IN_CHANNEL_LEN 4 22178 22178 - 22179 22179 - /* MC_CMD_GET_NCSI_INFO_LINK_OUT msgresponse */ 22180 22180 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_LEN 12 22181 22181 - /* Settings as received from BMC. */ 22182 22182 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_SETTINGS_OFST 0 22183 22183 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_SETTINGS_LEN 4 22184 22184 - /* Advertised capabilities applied to channel. */ 22185 22185 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ADV_CAP_OFST 4 22186 22186 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ADV_CAP_LEN 4 22187 22187 - /* General status */ 22188 22188 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATUS_OFST 8 22189 22189 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATUS_LEN 4 22190 22190 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_OFST 8 22191 22191 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_LBN 0 22192 22192 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_WIDTH 2 22193 22193 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_OFST 8 22194 22194 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_LBN 2 22195 22195 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_WIDTH 1 22196 22196 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_OFST 8 22197 22197 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_LBN 3 22198 22198 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_WIDTH 1 22199 22199 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_OFST 8 22200 22200 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_LBN 4 22201 22201 - #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_WIDTH 1 22202 22202 - 22203 22203 - /* MC_CMD_GET_NCSI_INFO_STATISTICS_OUT msgresponse */ 22204 22204 - #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_LEN 28 22205 22205 - /* The number of NC-SI commands received. */ 22206 22206 - #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMDS_RX_OFST 0 22207 22207 - #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMDS_RX_LEN 4 22208 22208 - /* The number of NC-SI commands dropped. */ 22209 22209 - #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_PKTS_DROPPED_OFST 4 22210 22210 - #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_PKTS_DROPPED_LEN 4 22211 22211 - /* The number of invalid NC-SI commands received. */ 22212 22212 - #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_TYPE_ERRS_OFST 8 22213 22213 - #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_TYPE_ERRS_LEN 4 22214 22214 - /* The number of checksum errors seen. */ 22215 22215 - #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_CSUM_ERRS_OFST 12 22216 22216 - #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_CSUM_ERRS_LEN 4 22217 22217 - /* The number of NC-SI requests received. */ 22218 22218 - #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_RX_PKTS_OFST 16 22219 22219 - #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_RX_PKTS_LEN 4 22220 22220 - /* The number of NC-SI responses sent (includes AENs) */ 22221 22221 - #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_TX_PKTS_OFST 20 22222 22222 - #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_TX_PKTS_LEN 4 22223 22223 - /* The number of NC-SI AENs sent */ 22224 22224 - #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_AENS_SENT_OFST 24 22225 22225 - #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_AENS_SENT_LEN 4 22226 22226 - 22227 23265 /* CLIENT_HANDLE structuredef: A client is an abstract entity that can make 22228 23266 * requests of the device and that can own resources managed by the device. 22229 23267 * Examples of clients include PCIe functions and dynamic clients. A client ··· 21670 23848 #define CLIENT_HANDLE_OPAQUE_LBN 0 21671 23849 #define CLIENT_HANDLE_OPAQUE_WIDTH 32 21672 23850 21673 21673 - /* CLOCK_INFO structuredef: Information about a single hardware clock */ 21674 21674 - #define CLOCK_INFO_LEN 28 21675 21675 - /* Enumeration that uniquely identifies the clock */ 21676 21676 - #define CLOCK_INFO_CLOCK_ID_OFST 0 21677 21677 - #define CLOCK_INFO_CLOCK_ID_LEN 2 21678 21678 - /* enum: The Riverhead CMC (card MC) */ 21679 21679 - #define CLOCK_INFO_CLOCK_CMC 0x0 21680 21680 - /* enum: The Riverhead NMC (network MC) */ 21681 21681 - #define CLOCK_INFO_CLOCK_NMC 0x1 21682 21682 - /* enum: The Riverhead SDNET slice main logic */ 21683 21683 - #define CLOCK_INFO_CLOCK_SDNET 0x2 21684 21684 - /* enum: The Riverhead SDNET LUT */ 21685 21685 - #define CLOCK_INFO_CLOCK_SDNET_LUT 0x3 21686 21686 - /* enum: The Riverhead SDNET control logic */ 21687 21687 - #define CLOCK_INFO_CLOCK_SDNET_CTRL 0x4 21688 21688 - /* enum: The Riverhead Streaming SubSystem */ 21689 21689 - #define CLOCK_INFO_CLOCK_SSS 0x5 21690 21690 - /* enum: The Riverhead network MAC and associated CSR registers */ 21691 21691 - #define CLOCK_INFO_CLOCK_MAC 0x6 21692 21692 - #define CLOCK_INFO_CLOCK_ID_LBN 0 21693 21693 - #define CLOCK_INFO_CLOCK_ID_WIDTH 16 21694 21694 - /* Assorted flags */ 21695 21695 - #define CLOCK_INFO_FLAGS_OFST 2 21696 21696 - #define CLOCK_INFO_FLAGS_LEN 2 21697 21697 - #define CLOCK_INFO_SETTABLE_OFST 2 21698 21698 - #define CLOCK_INFO_SETTABLE_LBN 0 21699 21699 - #define CLOCK_INFO_SETTABLE_WIDTH 1 21700 21700 - #define CLOCK_INFO_FLAGS_LBN 16 21701 21701 - #define CLOCK_INFO_FLAGS_WIDTH 16 21702 21702 - /* The frequency in HZ */ 21703 21703 - #define CLOCK_INFO_FREQUENCY_OFST 4 21704 21704 - #define CLOCK_INFO_FREQUENCY_LEN 8 21705 21705 - #define CLOCK_INFO_FREQUENCY_LO_OFST 4 21706 21706 - #define CLOCK_INFO_FREQUENCY_LO_LEN 4 21707 21707 - #define CLOCK_INFO_FREQUENCY_LO_LBN 32 21708 21708 - #define CLOCK_INFO_FREQUENCY_LO_WIDTH 32 21709 21709 - #define CLOCK_INFO_FREQUENCY_HI_OFST 8 21710 21710 - #define CLOCK_INFO_FREQUENCY_HI_LEN 4 21711 21711 - #define CLOCK_INFO_FREQUENCY_HI_LBN 64 21712 21712 - #define CLOCK_INFO_FREQUENCY_HI_WIDTH 32 21713 21713 - #define CLOCK_INFO_FREQUENCY_LBN 32 21714 21714 - #define CLOCK_INFO_FREQUENCY_WIDTH 64 21715 21715 - /* Human-readable ASCII name for clock, with NUL termination */ 21716 21716 - #define CLOCK_INFO_NAME_OFST 12 21717 21717 - #define CLOCK_INFO_NAME_LEN 1 21718 21718 - #define CLOCK_INFO_NAME_NUM 16 21719 21719 - #define CLOCK_INFO_NAME_LBN 96 21720 21720 - #define CLOCK_INFO_NAME_WIDTH 8 21721 21721 - 21722 23851 /* SCHED_CREDIT_CHECK_RESULT structuredef */ 21723 23852 #define SCHED_CREDIT_CHECK_RESULT_LEN 16 21724 21724 - /* The instance of the scheduler. Refer to XN-200389-AW for the location of 21725 21725 - * these schedulers in the hardware. 23853 23853 + /* The instance of the scheduler. Refer to XN-200389-AW (snic/hnic) and 23854 23854 + * XN-200425-TC (cdx) for the location of these schedulers in the hardware. 21726 23855 */ 21727 23856 #define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_OFST 0 21728 23857 #define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LEN 1 ··· 21687 23914 #define SCHED_CREDIT_CHECK_RESULT_DMAC_H2C 0x7 /* enum */ 21688 23915 #define SCHED_CREDIT_CHECK_RESULT_HUB_NET_B 0x8 /* enum */ 21689 23916 #define SCHED_CREDIT_CHECK_RESULT_HUB_NET_REPLAY 0x9 /* enum */ 23917 23917 + #define SCHED_CREDIT_CHECK_RESULT_ADAPTER_C2H_C 0xa /* enum */ 23918 23918 + #define SCHED_CREDIT_CHECK_RESULT_A2_H2C_C 0xb /* enum */ 23919 23919 + #define SCHED_CREDIT_CHECK_RESULT_A3_SOFT_ADAPTOR_C 0xc /* enum */ 23920 23920 + #define SCHED_CREDIT_CHECK_RESULT_A4_DPU_WRITE_C 0xd /* enum */ 23921 23921 + #define SCHED_CREDIT_CHECK_RESULT_JRC_RRU 0xe /* enum */ 23922 23922 + #define SCHED_CREDIT_CHECK_RESULT_CDM_SINK 0xf /* enum */ 23923 23923 + #define SCHED_CREDIT_CHECK_RESULT_PCIE_SINK 0x10 /* enum */ 23924 23924 + #define SCHED_CREDIT_CHECK_RESULT_UPORT_SINK 0x11 /* enum */ 23925 23925 + #define SCHED_CREDIT_CHECK_RESULT_PSX_SINK 0x12 /* enum */ 23926 23926 + #define SCHED_CREDIT_CHECK_RESULT_A5_DPU_READ_C 0x13 /* enum */ 21690 23927 #define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LBN 0 21691 23928 #define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_WIDTH 8 21692 23929 /* The type of node that this result refers to. */ ··· 21706 23923 #define SCHED_CREDIT_CHECK_RESULT_DEST 0x0 21707 23924 /* enum: Source node */ 21708 23925 #define SCHED_CREDIT_CHECK_RESULT_SOURCE 0x1 23926 23926 + /* enum: Destination node credit type 1 (new to the Keystone schedulers, see 23927 23927 + * SF-120268-TC) 23928 23928 + */ 23929 23929 + #define SCHED_CREDIT_CHECK_RESULT_DEST_CREDIT1 0x2 21709 23930 #define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_LBN 8 21710 23931 #define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_WIDTH 8 21711 23932 /* Level of node in scheduler hierarchy (level 0 is the bottom of the ··· 21734 23947 #define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_LEN 4 21735 23948 #define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_LBN 96 21736 23949 #define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_WIDTH 32 21737 21737 - 21738 21738 - 21739 21739 - /***********************************/ 21740 21740 - /* MC_CMD_GET_CLOCKS_INFO 21741 21741 - * Get information about the device clocks 21742 21742 - */ 21743 21743 - #define MC_CMD_GET_CLOCKS_INFO 0x166 21744 21744 - #undef MC_CMD_0x166_PRIVILEGE_CTG 21745 21745 - 21746 21746 - #define MC_CMD_0x166_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21747 21747 - 21748 21748 - /* MC_CMD_GET_CLOCKS_INFO_IN msgrequest */ 21749 21749 - #define MC_CMD_GET_CLOCKS_INFO_IN_LEN 0 21750 21750 - 21751 21751 - /* MC_CMD_GET_CLOCKS_INFO_OUT msgresponse */ 21752 21752 - #define MC_CMD_GET_CLOCKS_INFO_OUT_LENMIN 0 21753 21753 - #define MC_CMD_GET_CLOCKS_INFO_OUT_LENMAX 252 21754 21754 - #define MC_CMD_GET_CLOCKS_INFO_OUT_LENMAX_MCDI2 1008 21755 21755 - #define MC_CMD_GET_CLOCKS_INFO_OUT_LEN(num) (0+28*(num)) 21756 21756 - #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_NUM(len) (((len)-0)/28) 21757 21757 - /* An array of CLOCK_INFO structures. */ 21758 21758 - #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_OFST 0 21759 21759 - #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_LEN 28 21760 21760 - #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MINNUM 0 21761 21761 - #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MAXNUM 9 21762 21762 - #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MAXNUM_MCDI2 36 21763 21763 - 21764 21764 - 21765 21765 - /***********************************/ 21766 21766 - /* MC_CMD_VNIC_ENCAP_RULE_ADD 21767 21767 - * Add a rule for detecting encapsulations in the VNIC stage. Currently this 21768 21768 - * only affects checksum validation in VNIC RX - on TX the send descriptor 21769 21769 - * explicitly specifies encapsulation. These rules are per-VNIC, i.e. only 21770 21770 - * apply to the current driver. If a rule matches, then the packet is 21771 21771 - * considered to have the corresponding encapsulation type, and the inner 21772 21772 - * packet is parsed. It is up to the driver to ensure that overlapping rules 21773 21773 - * are not inserted. (If a packet would match multiple rules, a random one of 21774 21774 - * them will be used.) A rule with the exact same match criteria may not be 21775 21775 - * inserted twice (EALREADY). Only a limited number MATCH_FLAGS values are 21776 21776 - * supported, use MC_CMD_GET_PARSER_DISP_INFO with OP 21777 21777 - * OP_GET_SUPPORTED_VNIC_ENCAP_RULE_MATCHES to get a list of supported 21778 21778 - * combinations. Each driver may only have a limited set of active rules - 21779 21779 - * returns ENOSPC if the caller's table is full. 21780 21780 - */ 21781 21781 - #define MC_CMD_VNIC_ENCAP_RULE_ADD 0x16d 21782 21782 - #undef MC_CMD_0x16d_PRIVILEGE_CTG 21783 21783 - 21784 21784 - #define MC_CMD_0x16d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21785 21785 - 21786 21786 - /* MC_CMD_VNIC_ENCAP_RULE_ADD_IN msgrequest */ 21787 21787 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_LEN 36 21788 21788 - /* Set to MAE_MPORT_SELECTOR_ASSIGNED. In the future this may be relaxed. */ 21789 21789 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_OFST 0 21790 21790 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_LEN 4 21791 21791 - /* Any non-zero bits other than the ones named below or an unsupported 21792 21792 - * combination will cause the NIC to return EOPNOTSUPP. In the future more 21793 21793 - * flags may be added. 21794 21794 - */ 21795 21795 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_OFST 4 21796 21796 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_LEN 4 21797 21797 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_OFST 4 21798 21798 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_LBN 0 21799 21799 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_WIDTH 1 21800 21800 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_OFST 4 21801 21801 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_LBN 1 21802 21802 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_WIDTH 1 21803 21803 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_OFST 4 21804 21804 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_LBN 2 21805 21805 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_WIDTH 1 21806 21806 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_OFST 4 21807 21807 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_LBN 3 21808 21808 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_WIDTH 1 21809 21809 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_OFST 4 21810 21810 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_LBN 4 21811 21811 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_WIDTH 1 21812 21812 - /* Only if MATCH_ETHER_TYPE is set. Ethertype value as bytes in network order. 21813 21813 - * Currently only IPv4 (0x0800) and IPv6 (0x86DD) ethertypes may be used. 21814 21814 - */ 21815 21815 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ETHER_TYPE_OFST 8 21816 21816 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ETHER_TYPE_LEN 2 21817 21817 - /* Only if MATCH_OUTER_VLAN is set. VID value as bytes in network order. 21818 21818 - * (Deprecated) 21819 21819 - */ 21820 21820 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_LBN 80 21821 21821 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WIDTH 12 21822 21822 - /* Only if MATCH_OUTER_VLAN is set. Aligned wrapper for OUTER_VLAN_VID. */ 21823 21823 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WORD_OFST 10 21824 21824 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WORD_LEN 2 21825 21825 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_OFST 10 21826 21826 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_LBN 0 21827 21827 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_WIDTH 12 21828 21828 - /* Only if MATCH_DST_IP is set. IP address as bytes in network order. In the 21829 21829 - * case of IPv4, the IP should be in the first 4 bytes and all other bytes 21830 21830 - * should be zero. 21831 21831 - */ 21832 21832 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_IP_OFST 12 21833 21833 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_IP_LEN 16 21834 21834 - /* Only if MATCH_IP_PROTO is set. Currently only UDP proto (17) may be used. */ 21835 21835 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_IP_PROTO_OFST 28 21836 21836 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_IP_PROTO_LEN 1 21837 21837 - /* Actions that should be applied to packets match the rule. */ 21838 21838 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ACTION_FLAGS_OFST 29 21839 21839 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ACTION_FLAGS_LEN 1 21840 21840 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_OFST 29 21841 21841 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_LBN 0 21842 21842 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_WIDTH 1 21843 21843 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_RSS_ON_OUTER_OFST 29 21844 21844 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_RSS_ON_OUTER_LBN 1 21845 21845 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_RSS_ON_OUTER_WIDTH 1 21846 21846 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STEER_ON_OUTER_OFST 29 21847 21847 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STEER_ON_OUTER_LBN 2 21848 21848 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STEER_ON_OUTER_WIDTH 1 21849 21849 - /* Only if MATCH_DST_PORT is set. Port number as bytes in network order. */ 21850 21850 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_PORT_OFST 30 21851 21851 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_PORT_LEN 2 21852 21852 - /* Resulting encapsulation type, as per MAE_MCDI_ENCAP_TYPE enumeration. */ 21853 21853 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_OFST 32 21854 21854 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_LEN 4 21855 21855 - 21856 21856 - /* MC_CMD_VNIC_ENCAP_RULE_ADD_OUT msgresponse */ 21857 21857 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_LEN 4 21858 21858 - /* Handle to inserted rule. Used for removing the rule. */ 21859 21859 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_OFST 0 21860 21860 - #define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_LEN 4 21861 21861 - 21862 21862 - 21863 21863 - /***********************************/ 21864 21864 - /* MC_CMD_VNIC_ENCAP_RULE_REMOVE 21865 21865 - * Remove a VNIC encapsulation rule. Packets which would have previously 21866 21866 - * matched the rule will then be considered as unencapsulated. Returns EALREADY 21867 21867 - * if the input HANDLE doesn't correspond to an existing rule. 21868 21868 - */ 21869 21869 - #define MC_CMD_VNIC_ENCAP_RULE_REMOVE 0x16e 21870 21870 - #undef MC_CMD_0x16e_PRIVILEGE_CTG 21871 21871 - 21872 21872 - #define MC_CMD_0x16e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21873 21873 - 21874 21874 - /* MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN msgrequest */ 21875 21875 - #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_LEN 4 21876 21876 - /* Handle which was returned by MC_CMD_VNIC_ENCAP_RULE_ADD. */ 21877 21877 - #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_OFST 0 21878 21878 - #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_LEN 4 21879 21879 - 21880 21880 - /* MC_CMD_VNIC_ENCAP_RULE_REMOVE_OUT msgresponse */ 21881 21881 - #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_OUT_LEN 0 21882 21882 - 21883 21883 - /* UUID structuredef: An RFC4122 standard UUID. The values here are stored in 21884 21884 - * the endianness specified by the RFC; users should ignore the broken-out 21885 21885 - * fields and instead do straight memory copies to ensure correct ordering. 21886 21886 - */ 21887 21887 - #define UUID_LEN 16 21888 21888 - #define UUID_TIME_LOW_OFST 0 21889 21889 - #define UUID_TIME_LOW_LEN 4 21890 21890 - #define UUID_TIME_LOW_LBN 0 21891 21891 - #define UUID_TIME_LOW_WIDTH 32 21892 21892 - #define UUID_TIME_MID_OFST 4 21893 21893 - #define UUID_TIME_MID_LEN 2 21894 21894 - #define UUID_TIME_MID_LBN 32 21895 21895 - #define UUID_TIME_MID_WIDTH 16 21896 21896 - #define UUID_TIME_HI_LBN 52 21897 21897 - #define UUID_TIME_HI_WIDTH 12 21898 21898 - #define UUID_VERSION_LBN 48 21899 21899 - #define UUID_VERSION_WIDTH 4 21900 21900 - #define UUID_RESERVED_LBN 64 21901 21901 - #define UUID_RESERVED_WIDTH 2 21902 21902 - #define UUID_CLK_SEQ_LBN 66 21903 21903 - #define UUID_CLK_SEQ_WIDTH 14 21904 21904 - #define UUID_NODE_OFST 10 21905 21905 - #define UUID_NODE_LEN 6 21906 21906 - #define UUID_NODE_LBN 80 21907 21907 - #define UUID_NODE_WIDTH 48 21908 21908 - 21909 21909 - 21910 21910 - /***********************************/ 21911 21911 - /* MC_CMD_PLUGIN_ALLOC 21912 21912 - * Create a handle to a datapath plugin's extension. This involves finding a 21913 21913 - * currently-loaded plugin offering the given functionality (as identified by 21914 21914 - * the UUID) and allocating a handle to track the usage of it. Plugin 21915 21915 - * functionality is identified by 'extension' rather than any other identifier 21916 21916 - * so that a single plugin bitfile may offer more than one piece of independent 21917 21917 - * functionality. If two bitfiles are loaded which both offer the same 21918 21918 - * extension, then the metadata is interrogated further to determine which is 21919 21919 - * the newest and that is the one opened. See SF-123625-SW for architectural 21920 21920 - * detail on datapath plugins. 21921 21921 - */ 21922 21922 - #define MC_CMD_PLUGIN_ALLOC 0x1ad 21923 21923 - #undef MC_CMD_0x1ad_PRIVILEGE_CTG 21924 21924 - 21925 21925 - #define MC_CMD_0x1ad_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21926 21926 - 21927 21927 - /* MC_CMD_PLUGIN_ALLOC_IN msgrequest */ 21928 21928 - #define MC_CMD_PLUGIN_ALLOC_IN_LEN 24 21929 21929 - /* The functionality requested of the plugin, as a UUID structure */ 21930 21930 - #define MC_CMD_PLUGIN_ALLOC_IN_UUID_OFST 0 21931 21931 - #define MC_CMD_PLUGIN_ALLOC_IN_UUID_LEN 16 21932 21932 - /* Additional options for opening the handle */ 21933 21933 - #define MC_CMD_PLUGIN_ALLOC_IN_FLAGS_OFST 16 21934 21934 - #define MC_CMD_PLUGIN_ALLOC_IN_FLAGS_LEN 4 21935 21935 - #define MC_CMD_PLUGIN_ALLOC_IN_FLAG_INFO_ONLY_OFST 16 21936 21936 - #define MC_CMD_PLUGIN_ALLOC_IN_FLAG_INFO_ONLY_LBN 0 21937 21937 - #define MC_CMD_PLUGIN_ALLOC_IN_FLAG_INFO_ONLY_WIDTH 1 21938 21938 - #define MC_CMD_PLUGIN_ALLOC_IN_FLAG_ALLOW_DISABLED_OFST 16 21939 21939 - #define MC_CMD_PLUGIN_ALLOC_IN_FLAG_ALLOW_DISABLED_LBN 1 21940 21940 - #define MC_CMD_PLUGIN_ALLOC_IN_FLAG_ALLOW_DISABLED_WIDTH 1 21941 21941 - /* Load the extension only if it is in the specified administrative group. 21942 21942 - * Specify ANY to load the extension wherever it is found (if there are 21943 21943 - * multiple choices then the extension with the highest MINOR_VER/PATCH_VER 21944 21944 - * will be loaded). See MC_CMD_PLUGIN_GET_META_GLOBAL for a description of 21945 21945 - * administrative groups. 21946 21946 - */ 21947 21947 - #define MC_CMD_PLUGIN_ALLOC_IN_ADMIN_GROUP_OFST 20 21948 21948 - #define MC_CMD_PLUGIN_ALLOC_IN_ADMIN_GROUP_LEN 2 21949 21949 - /* enum: Load the extension from any ADMIN_GROUP. */ 21950 21950 - #define MC_CMD_PLUGIN_ALLOC_IN_ANY 0xffff 21951 21951 - /* Reserved */ 21952 21952 - #define MC_CMD_PLUGIN_ALLOC_IN_RESERVED_OFST 22 21953 21953 - #define MC_CMD_PLUGIN_ALLOC_IN_RESERVED_LEN 2 21954 21954 - 21955 21955 - /* MC_CMD_PLUGIN_ALLOC_OUT msgresponse */ 21956 21956 - #define MC_CMD_PLUGIN_ALLOC_OUT_LEN 4 21957 21957 - /* Unique identifier of this usage */ 21958 21958 - #define MC_CMD_PLUGIN_ALLOC_OUT_HANDLE_OFST 0 21959 21959 - #define MC_CMD_PLUGIN_ALLOC_OUT_HANDLE_LEN 4 21960 21960 - 21961 21961 - 21962 21962 - /***********************************/ 21963 21963 - /* MC_CMD_PLUGIN_FREE 21964 21964 - * Delete a handle to a plugin's extension. 21965 21965 - */ 21966 21966 - #define MC_CMD_PLUGIN_FREE 0x1ae 21967 21967 - #undef MC_CMD_0x1ae_PRIVILEGE_CTG 21968 21968 - 21969 21969 - #define MC_CMD_0x1ae_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21970 21970 - 21971 21971 - /* MC_CMD_PLUGIN_FREE_IN msgrequest */ 21972 21972 - #define MC_CMD_PLUGIN_FREE_IN_LEN 4 21973 21973 - /* Handle returned by MC_CMD_PLUGIN_ALLOC_OUT */ 21974 21974 - #define MC_CMD_PLUGIN_FREE_IN_HANDLE_OFST 0 21975 21975 - #define MC_CMD_PLUGIN_FREE_IN_HANDLE_LEN 4 21976 21976 - 21977 21977 - /* MC_CMD_PLUGIN_FREE_OUT msgresponse */ 21978 21978 - #define MC_CMD_PLUGIN_FREE_OUT_LEN 0 21979 21979 - 21980 21980 - 21981 21981 - /***********************************/ 21982 21982 - /* MC_CMD_PLUGIN_GET_META_GLOBAL 21983 21983 - * Returns the global metadata applying to the whole plugin extension. See the 21984 21984 - * other metadata calls for subtypes of data. 21985 21985 - */ 21986 21986 - #define MC_CMD_PLUGIN_GET_META_GLOBAL 0x1af 21987 21987 - #undef MC_CMD_0x1af_PRIVILEGE_CTG 21988 21988 - 21989 21989 - #define MC_CMD_0x1af_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21990 21990 - 21991 21991 - /* MC_CMD_PLUGIN_GET_META_GLOBAL_IN msgrequest */ 21992 21992 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_IN_LEN 4 21993 21993 - /* Handle returned by MC_CMD_PLUGIN_ALLOC_OUT */ 21994 21994 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_IN_HANDLE_OFST 0 21995 21995 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_IN_HANDLE_LEN 4 21996 21996 - 21997 21997 - /* MC_CMD_PLUGIN_GET_META_GLOBAL_OUT msgresponse */ 21998 21998 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_LEN 36 21999 21999 - /* Unique identifier of this plugin extension. This is identical to the value 22000 22000 - * which was requested when the handle was allocated. 22001 22001 - */ 22002 22002 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_UUID_OFST 0 22003 22003 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_UUID_LEN 16 22004 22004 - /* semver sub-version of this plugin extension */ 22005 22005 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MINOR_VER_OFST 16 22006 22006 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MINOR_VER_LEN 2 22007 22007 - /* semver micro-version of this plugin extension */ 22008 22008 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_PATCH_VER_OFST 18 22009 22009 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_PATCH_VER_LEN 2 22010 22010 - /* Number of different messages which can be sent to this extension */ 22011 22011 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_NUM_MSGS_OFST 20 22012 22012 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_NUM_MSGS_LEN 4 22013 22013 - /* Byte offset within the VI window of the plugin's mapped CSR window. */ 22014 22014 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_OFFSET_OFST 24 22015 22015 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_OFFSET_LEN 2 22016 22016 - /* Number of bytes mapped through to the plugin's CSRs. 0 if that feature was 22017 22017 - * not requested by the plugin (in which case MAPPED_CSR_OFFSET and 22018 22018 - * MAPPED_CSR_FLAGS are ignored). 22019 22019 - */ 22020 22020 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_SIZE_OFST 26 22021 22021 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_SIZE_LEN 2 22022 22022 - /* Flags indicating how to perform the CSR window mapping. */ 22023 22023 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAGS_OFST 28 22024 22024 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAGS_LEN 4 22025 22025 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAG_READ_OFST 28 22026 22026 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAG_READ_LBN 0 22027 22027 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAG_READ_WIDTH 1 22028 22028 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAG_WRITE_OFST 28 22029 22029 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAG_WRITE_LBN 1 22030 22030 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAG_WRITE_WIDTH 1 22031 22031 - /* Identifier of the set of extensions which all change state together. 22032 22032 - * Extensions having the same ADMIN_GROUP will always load and unload at the 22033 22033 - * same time. ADMIN_GROUP values themselves are arbitrary (but they contain a 22034 22034 - * generation number as an implementation detail to ensure that they're not 22035 22035 - * reused rapidly). 22036 22036 - */ 22037 22037 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_ADMIN_GROUP_OFST 32 22038 22038 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_ADMIN_GROUP_LEN 1 22039 22039 - /* Bitshift in MC_CMD_DEVEL_CLIENT_PRIVILEGE_MODIFY's MASK parameters 22040 22040 - * corresponding to this extension, i.e. set the bit 1<<PRIVILEGE_BIT to permit 22041 22041 - * access to this extension. 22042 22042 - */ 22043 22043 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_PRIVILEGE_BIT_OFST 33 22044 22044 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_PRIVILEGE_BIT_LEN 1 22045 22045 - /* Reserved */ 22046 22046 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_RESERVED_OFST 34 22047 22047 - #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_RESERVED_LEN 2 22048 22048 - 22049 22049 - 22050 22050 - /***********************************/ 22051 22051 - /* MC_CMD_PLUGIN_GET_META_PUBLISHER 22052 22052 - * Returns metadata supplied by the plugin author which describes this 22053 22053 - * extension in a human-readable way. Contrast with 22054 22054 - * MC_CMD_PLUGIN_GET_META_GLOBAL, which returns information needed for software 22055 22055 - * to operate. 22056 22056 - */ 22057 22057 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER 0x1b0 22058 22058 - #undef MC_CMD_0x1b0_PRIVILEGE_CTG 22059 22059 - 22060 22060 - #define MC_CMD_0x1b0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 22061 22061 - 22062 22062 - /* MC_CMD_PLUGIN_GET_META_PUBLISHER_IN msgrequest */ 22063 22063 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_LEN 12 22064 22064 - /* Handle returned by MC_CMD_PLUGIN_ALLOC_OUT */ 22065 22065 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_HANDLE_OFST 0 22066 22066 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_HANDLE_LEN 4 22067 22067 - /* Category of data to return */ 22068 22068 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_SUBTYPE_OFST 4 22069 22069 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_SUBTYPE_LEN 4 22070 22070 - /* enum: Top-level information about the extension. The returned data is an 22071 22071 - * array of key/value pairs using the keys in RFC5013 (Dublin Core) to describe 22072 22072 - * the extension. The data is a back-to-back list of zero-terminated strings; 22073 22073 - * the even-numbered fields (0,2,4,...) are keys and their following odd- 22074 22074 - * numbered fields are the corresponding values. Both keys and values are 22075 22075 - * nominally UTF-8. Per RFC5013, the same key may be repeated any number of 22076 22076 - * times. Note that all information (including the key/value structure itself 22077 22077 - * and the UTF-8 encoding) may have been provided by the plugin author, so 22078 22078 - * callers must be cautious about parsing it. Callers should parse only the 22079 22079 - * top-level structure to separate out the keys and values; the contents of the 22080 22080 - * values is not expected to be machine-readable. 22081 22081 - */ 22082 22082 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_EXTENSION_KVS 0x0 22083 22083 - /* Byte position of the data to be returned within the full data block of the 22084 22084 - * given SUBTYPE. 22085 22085 - */ 22086 22086 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_OFFSET_OFST 8 22087 22087 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_OFFSET_LEN 4 22088 22088 - 22089 22089 - /* MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT msgresponse */ 22090 22090 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_LENMIN 4 22091 22091 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_LENMAX 252 22092 22092 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_LENMAX_MCDI2 1020 22093 22093 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_LEN(num) (4+1*(num)) 22094 22094 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_NUM(len) (((len)-4)/1) 22095 22095 - /* Full length of the data block of the requested SUBTYPE, in bytes. */ 22096 22096 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_TOTAL_SIZE_OFST 0 22097 22097 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_TOTAL_SIZE_LEN 4 22098 22098 - /* The information requested by SUBTYPE. */ 22099 22099 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_OFST 4 22100 22100 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_LEN 1 22101 22101 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_MINNUM 0 22102 22102 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_MAXNUM 248 22103 22103 - #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_MAXNUM_MCDI2 1016 22104 22104 - 22105 22105 - 22106 22106 - /***********************************/ 22107 22107 - /* MC_CMD_PLUGIN_GET_META_MSG 22108 22108 - * Returns the simple metadata for a specific plugin request message. This 22109 22109 - * supplies information necessary for the host to know how to build an 22110 22110 - * MC_CMD_PLUGIN_REQ request. 22111 22111 - */ 22112 22112 - #define MC_CMD_PLUGIN_GET_META_MSG 0x1b1 22113 22113 - #undef MC_CMD_0x1b1_PRIVILEGE_CTG 22114 22114 - 22115 22115 - #define MC_CMD_0x1b1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 22116 22116 - 22117 22117 - /* MC_CMD_PLUGIN_GET_META_MSG_IN msgrequest */ 22118 22118 - #define MC_CMD_PLUGIN_GET_META_MSG_IN_LEN 8 22119 22119 - /* Handle returned by MC_CMD_PLUGIN_ALLOC_OUT */ 22120 22120 - #define MC_CMD_PLUGIN_GET_META_MSG_IN_HANDLE_OFST 0 22121 22121 - #define MC_CMD_PLUGIN_GET_META_MSG_IN_HANDLE_LEN 4 22122 22122 - /* Unique message ID to obtain */ 22123 22123 - #define MC_CMD_PLUGIN_GET_META_MSG_IN_ID_OFST 4 22124 22124 - #define MC_CMD_PLUGIN_GET_META_MSG_IN_ID_LEN 4 22125 22125 - 22126 22126 - /* MC_CMD_PLUGIN_GET_META_MSG_OUT msgresponse */ 22127 22127 - #define MC_CMD_PLUGIN_GET_META_MSG_OUT_LEN 44 22128 22128 - /* Unique message ID. This is the same value as the input parameter; it exists 22129 22129 - * to allow future MCDI extensions which enumerate all messages. 22130 22130 - */ 22131 22131 - #define MC_CMD_PLUGIN_GET_META_MSG_OUT_ID_OFST 0 22132 22132 - #define MC_CMD_PLUGIN_GET_META_MSG_OUT_ID_LEN 4 22133 22133 - /* Packed index number of this message, assigned by the MC to give each message 22134 22134 - * a unique ID in an array to allow for more efficient storage/management. 22135 22135 - */ 22136 22136 - #define MC_CMD_PLUGIN_GET_META_MSG_OUT_INDEX_OFST 4 22137 22137 - #define MC_CMD_PLUGIN_GET_META_MSG_OUT_INDEX_LEN 4 22138 22138 - /* Short human-readable codename for this message. This is conventionally 22139 22139 - * formatted as a C identifier in the basic ASCII character set with any spare 22140 22140 - * bytes at the end set to 0, however this convention is not enforced by the MC 22141 22141 - * so consumers must check for all potential malformations before using it for 22142 22142 - * a trusted purpose. 22143 22143 - */ 22144 22144 - #define MC_CMD_PLUGIN_GET_META_MSG_OUT_NAME_OFST 8 22145 22145 - #define MC_CMD_PLUGIN_GET_META_MSG_OUT_NAME_LEN 32 22146 22146 - /* Number of bytes of data which must be passed from the host kernel to the MC 22147 22147 - * for this message's payload, and which are passed back again in the response. 22148 22148 - * The MC's plugin metadata loader will have validated that the number of bytes 22149 22149 - * specified here will fit in to MC_CMD_PLUGIN_REQ_IN_DATA in a single MCDI 22150 22150 - * message. 22151 22151 - */ 22152 22152 - #define MC_CMD_PLUGIN_GET_META_MSG_OUT_DATA_SIZE_OFST 40 22153 22153 - #define MC_CMD_PLUGIN_GET_META_MSG_OUT_DATA_SIZE_LEN 4 22154 22154 - 22155 22155 - /* PLUGIN_EXTENSION structuredef: Used within MC_CMD_PLUGIN_GET_ALL to describe 22156 22156 - * an individual extension. 22157 22157 - */ 22158 22158 - #define PLUGIN_EXTENSION_LEN 20 22159 22159 - #define PLUGIN_EXTENSION_UUID_OFST 0 22160 22160 - #define PLUGIN_EXTENSION_UUID_LEN 16 22161 22161 - #define PLUGIN_EXTENSION_UUID_LBN 0 22162 22162 - #define PLUGIN_EXTENSION_UUID_WIDTH 128 22163 22163 - #define PLUGIN_EXTENSION_ADMIN_GROUP_OFST 16 22164 22164 - #define PLUGIN_EXTENSION_ADMIN_GROUP_LEN 1 22165 22165 - #define PLUGIN_EXTENSION_ADMIN_GROUP_LBN 128 22166 22166 - #define PLUGIN_EXTENSION_ADMIN_GROUP_WIDTH 8 22167 22167 - #define PLUGIN_EXTENSION_FLAG_ENABLED_LBN 136 22168 22168 - #define PLUGIN_EXTENSION_FLAG_ENABLED_WIDTH 1 22169 22169 - #define PLUGIN_EXTENSION_RESERVED_LBN 137 22170 22170 - #define PLUGIN_EXTENSION_RESERVED_WIDTH 23 22171 22171 - 22172 22172 - 22173 22173 - /***********************************/ 22174 22174 - /* MC_CMD_PLUGIN_GET_ALL 22175 22175 - * Returns a list of all plugin extensions currently loaded and available. The 22176 22176 - * UUIDs returned can be passed to MC_CMD_PLUGIN_ALLOC in order to obtain more 22177 22177 - * detailed metadata via the MC_CMD_PLUGIN_GET_META_* family of requests. The 22178 22178 - * ADMIN_GROUP field collects how extensions are grouped in to units which are 22179 22179 - * loaded/unloaded together; extensions with the same value are in the same 22180 22180 - * group. 22181 22181 - */ 22182 22182 - #define MC_CMD_PLUGIN_GET_ALL 0x1b2 22183 22183 - #undef MC_CMD_0x1b2_PRIVILEGE_CTG 22184 22184 - 22185 22185 - #define MC_CMD_0x1b2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 22186 22186 - 22187 22187 - /* MC_CMD_PLUGIN_GET_ALL_IN msgrequest */ 22188 22188 - #define MC_CMD_PLUGIN_GET_ALL_IN_LEN 4 22189 22189 - /* Additional options for querying. Note that if neither FLAG_INCLUDE_ENABLED 22190 22190 - * nor FLAG_INCLUDE_DISABLED are specified then the result set will be empty. 22191 22191 - */ 22192 22192 - #define MC_CMD_PLUGIN_GET_ALL_IN_FLAGS_OFST 0 22193 22193 - #define MC_CMD_PLUGIN_GET_ALL_IN_FLAGS_LEN 4 22194 22194 - #define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_ENABLED_OFST 0 22195 22195 - #define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_ENABLED_LBN 0 22196 22196 - #define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_ENABLED_WIDTH 1 22197 22197 - #define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_DISABLED_OFST 0 22198 22198 - #define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_DISABLED_LBN 1 22199 22199 - #define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_DISABLED_WIDTH 1 22200 22200 - 22201 22201 - /* MC_CMD_PLUGIN_GET_ALL_OUT msgresponse */ 22202 22202 - #define MC_CMD_PLUGIN_GET_ALL_OUT_LENMIN 0 22203 22203 - #define MC_CMD_PLUGIN_GET_ALL_OUT_LENMAX 240 22204 22204 - #define MC_CMD_PLUGIN_GET_ALL_OUT_LENMAX_MCDI2 1020 22205 22205 - #define MC_CMD_PLUGIN_GET_ALL_OUT_LEN(num) (0+20*(num)) 22206 22206 - #define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_NUM(len) (((len)-0)/20) 22207 22207 - /* The list of available plugin extensions, as an array of PLUGIN_EXTENSION 22208 22208 - * structs. 22209 22209 - */ 22210 22210 - #define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_OFST 0 22211 22211 - #define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_LEN 20 22212 22212 - #define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_MINNUM 0 22213 22213 - #define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_MAXNUM 12 22214 22214 - #define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_MAXNUM_MCDI2 51 22215 22215 - 22216 22216 - 22217 22217 - /***********************************/ 22218 22218 - /* MC_CMD_PLUGIN_REQ 22219 22219 - * Send a command to a plugin. A plugin may define an arbitrary number of 22220 22220 - * 'messages' which it allows applications on the host system to send, each 22221 22221 - * identified by a 32-bit ID. 22222 22222 - */ 22223 22223 - #define MC_CMD_PLUGIN_REQ 0x1b3 22224 22224 - #undef MC_CMD_0x1b3_PRIVILEGE_CTG 22225 22225 - 22226 22226 - #define MC_CMD_0x1b3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 22227 22227 - 22228 22228 - /* MC_CMD_PLUGIN_REQ_IN msgrequest */ 22229 22229 - #define MC_CMD_PLUGIN_REQ_IN_LENMIN 8 22230 22230 - #define MC_CMD_PLUGIN_REQ_IN_LENMAX 252 22231 22231 - #define MC_CMD_PLUGIN_REQ_IN_LENMAX_MCDI2 1020 22232 22232 - #define MC_CMD_PLUGIN_REQ_IN_LEN(num) (8+1*(num)) 22233 22233 - #define MC_CMD_PLUGIN_REQ_IN_DATA_NUM(len) (((len)-8)/1) 22234 22234 - /* Handle returned by MC_CMD_PLUGIN_ALLOC_OUT */ 22235 22235 - #define MC_CMD_PLUGIN_REQ_IN_HANDLE_OFST 0 22236 22236 - #define MC_CMD_PLUGIN_REQ_IN_HANDLE_LEN 4 22237 22237 - /* Message ID defined by the plugin author */ 22238 22238 - #define MC_CMD_PLUGIN_REQ_IN_ID_OFST 4 22239 22239 - #define MC_CMD_PLUGIN_REQ_IN_ID_LEN 4 22240 22240 - /* Data blob being the parameter to the message. This must be of the length 22241 22241 - * specified by MC_CMD_PLUGIN_GET_META_MSG_IN_MCDI_PARAM_SIZE. 22242 22242 - */ 22243 22243 - #define MC_CMD_PLUGIN_REQ_IN_DATA_OFST 8 22244 22244 - #define MC_CMD_PLUGIN_REQ_IN_DATA_LEN 1 22245 22245 - #define MC_CMD_PLUGIN_REQ_IN_DATA_MINNUM 0 22246 22246 - #define MC_CMD_PLUGIN_REQ_IN_DATA_MAXNUM 244 22247 22247 - #define MC_CMD_PLUGIN_REQ_IN_DATA_MAXNUM_MCDI2 1012 22248 22248 - 22249 22249 - /* MC_CMD_PLUGIN_REQ_OUT msgresponse */ 22250 22250 - #define MC_CMD_PLUGIN_REQ_OUT_LENMIN 0 22251 22251 - #define MC_CMD_PLUGIN_REQ_OUT_LENMAX 252 22252 22252 - #define MC_CMD_PLUGIN_REQ_OUT_LENMAX_MCDI2 1020 22253 22253 - #define MC_CMD_PLUGIN_REQ_OUT_LEN(num) (0+1*(num)) 22254 22254 - #define MC_CMD_PLUGIN_REQ_OUT_DATA_NUM(len) (((len)-0)/1) 22255 22255 - /* The input data, as transformed and/or updated by the plugin's eBPF. Will be 22256 22256 - * the same size as the input DATA parameter. 22257 22257 - */ 22258 22258 - #define MC_CMD_PLUGIN_REQ_OUT_DATA_OFST 0 22259 22259 - #define MC_CMD_PLUGIN_REQ_OUT_DATA_LEN 1 22260 22260 - #define MC_CMD_PLUGIN_REQ_OUT_DATA_MINNUM 0 22261 22261 - #define MC_CMD_PLUGIN_REQ_OUT_DATA_MAXNUM 252 22262 22262 - #define MC_CMD_PLUGIN_REQ_OUT_DATA_MAXNUM_MCDI2 1020 22263 22263 - 22264 22264 - /* DESC_ADDR_REGION structuredef: Describes a contiguous region of DESC_ADDR 22265 22265 - * space that maps to a contiguous region of TRGT_ADDR space. Addresses 22266 22266 - * DESC_ADDR in the range [DESC_ADDR_BASE:DESC_ADDR_BASE + 1 << 22267 22267 - * WINDOW_SIZE_LOG2) map to TRGT_ADDR = DESC_ADDR - DESC_ADDR_BASE + 22268 22268 - * TRGT_ADDR_BASE. 22269 22269 - */ 22270 22270 - #define DESC_ADDR_REGION_LEN 32 22271 22271 - /* The start of the region in DESC_ADDR space. */ 22272 22272 - #define DESC_ADDR_REGION_DESC_ADDR_BASE_OFST 0 22273 22273 - #define DESC_ADDR_REGION_DESC_ADDR_BASE_LEN 8 22274 22274 - #define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_OFST 0 22275 22275 - #define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_LEN 4 22276 22276 - #define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_LBN 0 22277 22277 - #define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_WIDTH 32 22278 22278 - #define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_OFST 4 22279 22279 - #define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_LEN 4 22280 22280 - #define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_LBN 32 22281 22281 - #define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_WIDTH 32 22282 22282 - #define DESC_ADDR_REGION_DESC_ADDR_BASE_LBN 0 22283 22283 - #define DESC_ADDR_REGION_DESC_ADDR_BASE_WIDTH 64 22284 22284 - /* The start of the region in TRGT_ADDR space. Drivers can set this via 22285 22285 - * MC_CMD_SET_DESC_ADDR_REGIONS. 22286 22286 - */ 22287 22287 - #define DESC_ADDR_REGION_TRGT_ADDR_BASE_OFST 8 22288 22288 - #define DESC_ADDR_REGION_TRGT_ADDR_BASE_LEN 8 22289 22289 - #define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_OFST 8 22290 22290 - #define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_LEN 4 22291 22291 - #define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_LBN 64 22292 22292 - #define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_WIDTH 32 22293 22293 - #define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_OFST 12 22294 22294 - #define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_LEN 4 22295 22295 - #define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_LBN 96 22296 22296 - #define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_WIDTH 32 22297 22297 - #define DESC_ADDR_REGION_TRGT_ADDR_BASE_LBN 64 22298 22298 - #define DESC_ADDR_REGION_TRGT_ADDR_BASE_WIDTH 64 22299 22299 - /* The size of the region. */ 22300 22300 - #define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_OFST 16 22301 22301 - #define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_LEN 4 22302 22302 - #define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_LBN 128 22303 22303 - #define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_WIDTH 32 22304 22304 - /* The alignment restriction on TRGT_ADDR. TRGT_ADDR values set by the driver 22305 22305 - * must be a multiple of 1 << TRGT_ADDR_ALIGN_LOG2. 22306 22306 - */ 22307 22307 - #define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_OFST 20 22308 22308 - #define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_LEN 4 22309 22309 - #define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_LBN 160 22310 22310 - #define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_WIDTH 32 22311 22311 - #define DESC_ADDR_REGION_RSVD_OFST 24 22312 22312 - #define DESC_ADDR_REGION_RSVD_LEN 8 22313 22313 - #define DESC_ADDR_REGION_RSVD_LO_OFST 24 22314 22314 - #define DESC_ADDR_REGION_RSVD_LO_LEN 4 22315 22315 - #define DESC_ADDR_REGION_RSVD_LO_LBN 192 22316 22316 - #define DESC_ADDR_REGION_RSVD_LO_WIDTH 32 22317 22317 - #define DESC_ADDR_REGION_RSVD_HI_OFST 28 22318 22318 - #define DESC_ADDR_REGION_RSVD_HI_LEN 4 22319 22319 - #define DESC_ADDR_REGION_RSVD_HI_LBN 224 22320 22320 - #define DESC_ADDR_REGION_RSVD_HI_WIDTH 32 22321 22321 - #define DESC_ADDR_REGION_RSVD_LBN 192 22322 22322 - #define DESC_ADDR_REGION_RSVD_WIDTH 64 22323 23950 22324 23951 22325 23952 /***********************************/ ··· 22037 24836 22038 24837 22039 24838 /***********************************/ 22040 22040 - /* MC_CMD_GET_BOARD_ATTR 22041 22041 - * Retrieve physical build-level board attributes as configured at 22042 22042 - * manufacturing stage. Fields originate from EEPROM and per-platform constants 22043 22043 - * in firmware. Fields are used in development to identify/ differentiate 22044 22044 - * boards based on build levels/parameters, and also in manufacturing to cross 22045 22045 - * check "what was programmed in manufacturing" is same as "what firmware 22046 22046 - * thinks has been programmed" as there are two layers to translation within 22047 22047 - * firmware before the attributes reach this MCDI handler. Some parameters are 22048 22048 - * retrieved as part of other commands and therefore not replicated here. See 22049 22049 - * GET_VERSION_OUT. 22050 22050 - */ 22051 22051 - #define MC_CMD_GET_BOARD_ATTR 0x1c6 22052 22052 - #undef MC_CMD_0x1c6_PRIVILEGE_CTG 22053 22053 - 22054 22054 - #define MC_CMD_0x1c6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 22055 22055 - 22056 22056 - /* MC_CMD_GET_BOARD_ATTR_IN msgrequest */ 22057 22057 - #define MC_CMD_GET_BOARD_ATTR_IN_LEN 0 22058 22058 - 22059 22059 - /* MC_CMD_GET_BOARD_ATTR_OUT msgresponse */ 22060 22060 - #define MC_CMD_GET_BOARD_ATTR_OUT_LEN 16 22061 22061 - /* Defines board capabilities and validity of attributes returned in this 22062 22062 - * response-message. 22063 22063 - */ 22064 22064 - #define MC_CMD_GET_BOARD_ATTR_OUT_FLAGS_OFST 0 22065 22065 - #define MC_CMD_GET_BOARD_ATTR_OUT_FLAGS_LEN 4 22066 22066 - #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_OFST 0 22067 22067 - #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_LBN 0 22068 22068 - #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_WIDTH 1 22069 22069 - #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_OFST 0 22070 22070 - #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_LBN 1 22071 22071 - #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_WIDTH 1 22072 22072 - #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_OFST 0 22073 22073 - #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_LBN 2 22074 22074 - #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_WIDTH 1 22075 22075 - #define MC_CMD_GET_BOARD_ATTR_OUT_ATTRIBUTES_OFST 4 22076 22076 - #define MC_CMD_GET_BOARD_ATTR_OUT_ATTRIBUTES_LEN 4 22077 22077 - #define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_OFST 4 22078 22078 - #define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_LBN 0 22079 22079 - #define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_WIDTH 1 22080 22080 - #define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_OFST 4 22081 22081 - #define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_LBN 1 22082 22082 - #define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_WIDTH 1 22083 22083 - #define MC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_OFST 4 22084 22084 - #define MC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_LBN 16 22085 22085 - #define MC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_WIDTH 8 22086 22086 - /* enum: The FPGA voltage on the adapter can be set to low */ 22087 22087 - #define MC_CMD_FPGA_VOLTAGE_LOW 0x0 22088 22088 - /* enum: The FPGA voltage on the adapter can be set to regular */ 22089 22089 - #define MC_CMD_FPGA_VOLTAGE_REG 0x1 22090 22090 - /* enum: The FPGA voltage on the adapter can be set to high */ 22091 22091 - #define MC_CMD_FPGA_VOLTAGE_HIGH 0x2 22092 22092 - #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_OFST 4 22093 22093 - #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_LBN 24 22094 22094 - #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_WIDTH 8 22095 22095 - /* An array of cage types on the board */ 22096 22096 - #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_OFST 8 22097 22097 - #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_LEN 1 22098 22098 - #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_NUM 8 22099 22099 - /* enum: The cages are not known */ 22100 22100 - #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_UNKNOWN 0x0 22101 22101 - /* enum: The cages are SFP/SFP+ */ 22102 22102 - #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_SFP 0x1 22103 22103 - /* enum: The cages are QSFP/QSFP+ */ 22104 22104 - #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_QSFP 0x2 22105 22105 - 22106 22106 - 22107 22107 - /***********************************/ 22108 22108 - /* MC_CMD_GET_SOC_STATE 22109 22109 - * Retrieve current state of the System-on-Chip. This command is valid when 22110 22110 - * MC_CMD_GET_BOARD_ATTR:HAS_SOC is set. 22111 22111 - */ 22112 22112 - #define MC_CMD_GET_SOC_STATE 0x1c7 22113 22113 - #undef MC_CMD_0x1c7_PRIVILEGE_CTG 22114 22114 - 22115 22115 - #define MC_CMD_0x1c7_PRIVILEGE_CTG SRIOV_CTG_GENERAL 22116 22116 - 22117 22117 - /* MC_CMD_GET_SOC_STATE_IN msgrequest */ 22118 22118 - #define MC_CMD_GET_SOC_STATE_IN_LEN 0 22119 22119 - 22120 22120 - /* MC_CMD_GET_SOC_STATE_OUT msgresponse */ 22121 22121 - #define MC_CMD_GET_SOC_STATE_OUT_LEN 12 22122 22122 - /* Status flags for the SoC */ 22123 22123 - #define MC_CMD_GET_SOC_STATE_OUT_FLAGS_OFST 0 22124 22124 - #define MC_CMD_GET_SOC_STATE_OUT_FLAGS_LEN 4 22125 22125 - #define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_OFST 0 22126 22126 - #define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_LBN 0 22127 22127 - #define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_WIDTH 1 22128 22128 - #define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_OFST 0 22129 22129 - #define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_LBN 1 22130 22130 - #define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_WIDTH 1 22131 22131 - #define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_OFST 0 22132 22132 - #define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_LBN 2 22133 22133 - #define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_WIDTH 1 22134 22134 - /* Status fields for the SoC */ 22135 22135 - #define MC_CMD_GET_SOC_STATE_OUT_ATTRIBUTES_OFST 4 22136 22136 - #define MC_CMD_GET_SOC_STATE_OUT_ATTRIBUTES_LEN 4 22137 22137 - #define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_OFST 4 22138 22138 - #define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_LBN 0 22139 22139 - #define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_WIDTH 8 22140 22140 - /* enum: Power on (set by SUC on power up) */ 22141 22141 - #define MC_CMD_GET_SOC_STATE_OUT_SOC_BOOT 0x0 22142 22142 - /* enum: Running bootloader */ 22143 22143 - #define MC_CMD_GET_SOC_STATE_OUT_SOC_BOOTLOADER 0x1 22144 22144 - /* enum: Bootloader has started OS. OS is booting */ 22145 22145 - #define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_START 0x2 22146 22146 - /* enum: OS is running */ 22147 22147 - #define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_RUNNING 0x3 22148 22148 - /* enum: Maintenance OS is running */ 22149 22149 - #define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_MAINTENANCE 0x4 22150 22150 - /* Number of SoC resets since power on */ 22151 22151 - #define MC_CMD_GET_SOC_STATE_OUT_RESET_COUNT_OFST 8 22152 22152 - #define MC_CMD_GET_SOC_STATE_OUT_RESET_COUNT_LEN 4 22153 22153 - 22154 22154 - 22155 22155 - /***********************************/ 22156 24839 /* MC_CMD_CHECK_SCHEDULER_CREDITS 22157 24840 * For debugging purposes. For each source and destination node in the hardware 22158 24841 * schedulers, check whether the number of credits is as it should be. This ··· 22092 25007 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MINNUM 0 22093 25008 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MAXNUM 14 22094 25009 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MAXNUM_MCDI2 62 22095 22095 - 22096 22096 - 22097 22097 - /***********************************/ 22098 22098 - /* MC_CMD_TXQ_STATS 22099 22099 - * Query per-TXQ statistics. 22100 22100 - */ 22101 22101 - #define MC_CMD_TXQ_STATS 0x1d5 22102 22102 - #undef MC_CMD_0x1d5_PRIVILEGE_CTG 22103 22103 - 22104 22104 - #define MC_CMD_0x1d5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 22105 22105 - 22106 22106 - /* MC_CMD_TXQ_STATS_IN msgrequest */ 22107 22107 - #define MC_CMD_TXQ_STATS_IN_LEN 8 22108 22108 - /* Instance of TXQ to retrieve statistics for */ 22109 22109 - #define MC_CMD_TXQ_STATS_IN_INSTANCE_OFST 0 22110 22110 - #define MC_CMD_TXQ_STATS_IN_INSTANCE_LEN 4 22111 22111 - /* Flags for the request */ 22112 22112 - #define MC_CMD_TXQ_STATS_IN_FLAGS_OFST 4 22113 22113 - #define MC_CMD_TXQ_STATS_IN_FLAGS_LEN 4 22114 22114 - #define MC_CMD_TXQ_STATS_IN_CLEAR_OFST 4 22115 22115 - #define MC_CMD_TXQ_STATS_IN_CLEAR_LBN 0 22116 22116 - #define MC_CMD_TXQ_STATS_IN_CLEAR_WIDTH 1 22117 22117 - 22118 22118 - /* MC_CMD_TXQ_STATS_OUT msgresponse */ 22119 22119 - #define MC_CMD_TXQ_STATS_OUT_LENMIN 0 22120 22120 - #define MC_CMD_TXQ_STATS_OUT_LENMAX 248 22121 22121 - #define MC_CMD_TXQ_STATS_OUT_LENMAX_MCDI2 1016 22122 22122 - #define MC_CMD_TXQ_STATS_OUT_LEN(num) (0+8*(num)) 22123 22123 - #define MC_CMD_TXQ_STATS_OUT_STATISTICS_NUM(len) (((len)-0)/8) 22124 22124 - #define MC_CMD_TXQ_STATS_OUT_STATISTICS_OFST 0 22125 22125 - #define MC_CMD_TXQ_STATS_OUT_STATISTICS_LEN 8 22126 22126 - #define MC_CMD_TXQ_STATS_OUT_STATISTICS_LO_OFST 0 22127 22127 - #define MC_CMD_TXQ_STATS_OUT_STATISTICS_LO_LEN 4 22128 22128 - #define MC_CMD_TXQ_STATS_OUT_STATISTICS_LO_LBN 0 22129 22129 - #define MC_CMD_TXQ_STATS_OUT_STATISTICS_LO_WIDTH 32 22130 22130 - #define MC_CMD_TXQ_STATS_OUT_STATISTICS_HI_OFST 4 22131 22131 - #define MC_CMD_TXQ_STATS_OUT_STATISTICS_HI_LEN 4 22132 22132 - #define MC_CMD_TXQ_STATS_OUT_STATISTICS_HI_LBN 32 22133 22133 - #define MC_CMD_TXQ_STATS_OUT_STATISTICS_HI_WIDTH 32 22134 22134 - #define MC_CMD_TXQ_STATS_OUT_STATISTICS_MINNUM 0 22135 22135 - #define MC_CMD_TXQ_STATS_OUT_STATISTICS_MAXNUM 31 22136 22136 - #define MC_CMD_TXQ_STATS_OUT_STATISTICS_MAXNUM_MCDI2 127 22137 22137 - #define MC_CMD_TXQ_STATS_CTPIO_MAX_FILL 0x0 /* enum */ 22138 22138 - 22139 22139 - /* FUNCTION_PERSONALITY structuredef: The meanings of the personalities are 22140 22140 - * defined in SF-120734-TC with more information in SF-122717-TC. 22141 22141 - */ 22142 22142 - #define FUNCTION_PERSONALITY_LEN 4 22143 22143 - #define FUNCTION_PERSONALITY_ID_OFST 0 22144 22144 - #define FUNCTION_PERSONALITY_ID_LEN 4 22145 22145 - /* enum: Function has no assigned personality */ 22146 22146 - #define FUNCTION_PERSONALITY_NULL 0x0 22147 22147 - /* enum: Function has an EF100-style function control window and VI windows 22148 22148 - * with both EF100 and vDPA doorbells. 22149 22149 - */ 22150 22150 - #define FUNCTION_PERSONALITY_EF100 0x1 22151 22151 - /* enum: Function has virtio net device configuration registers and doorbells 22152 22152 - * for virtio queue pairs. 22153 22153 - */ 22154 22154 - #define FUNCTION_PERSONALITY_VIRTIO_NET 0x2 22155 22155 - /* enum: Function has virtio block device configuration registers and a 22156 22156 - * doorbell for a single virtqueue. 22157 22157 - */ 22158 22158 - #define FUNCTION_PERSONALITY_VIRTIO_BLK 0x3 22159 22159 - /* enum: Function is a Xilinx acceleration device - management function */ 22160 22160 - #define FUNCTION_PERSONALITY_ACCEL_MGMT 0x4 22161 22161 - /* enum: Function is a Xilinx acceleration device - user function */ 22162 22162 - #define FUNCTION_PERSONALITY_ACCEL_USR 0x5 22163 22163 - #define FUNCTION_PERSONALITY_ID_LBN 0 22164 22164 - #define FUNCTION_PERSONALITY_ID_WIDTH 32 22165 25010 22166 25011 22167 25012 /***********************************/ ··· 22174 25159 22175 25160 /* MC_CMD_VIRTIO_TEST_FEATURES_OUT msgresponse */ 22176 25161 #define MC_CMD_VIRTIO_TEST_FEATURES_OUT_LEN 0 22177 22177 - 22178 22178 - 22179 22179 - /***********************************/ 22180 22180 - /* MC_CMD_VIRTIO_GET_CAPABILITIES 22181 22181 - * Get virtio capabilities supported by the device. Returns general virtio 22182 22182 - * capabilities and limitations of the hardware / firmware implementation 22183 22183 - * (hardware device as a whole), rather than that of individual configured 22184 22184 - * virtio devices. At present, only the absolute maximum number of queues 22185 22185 - * allowed on multi-queue devices is returned. Response is expected to be 22186 22186 - * extended as necessary in the future. 22187 22187 - */ 22188 22188 - #define MC_CMD_VIRTIO_GET_CAPABILITIES 0x1d3 22189 22189 - #undef MC_CMD_0x1d3_PRIVILEGE_CTG 22190 22190 - 22191 22191 - #define MC_CMD_0x1d3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 22192 22192 - 22193 22193 - /* MC_CMD_VIRTIO_GET_CAPABILITIES_IN msgrequest */ 22194 22194 - #define MC_CMD_VIRTIO_GET_CAPABILITIES_IN_LEN 4 22195 22195 - /* Type of device to get capabilities for. Matches the device id as defined by 22196 22196 - * the virtio spec. 22197 22197 - */ 22198 22198 - #define MC_CMD_VIRTIO_GET_CAPABILITIES_IN_DEVICE_ID_OFST 0 22199 22199 - #define MC_CMD_VIRTIO_GET_CAPABILITIES_IN_DEVICE_ID_LEN 4 22200 22200 - /* Enum values, see field(s): */ 22201 22201 - /* MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_IN/DEVICE_ID */ 22202 22202 - 22203 22203 - /* MC_CMD_VIRTIO_GET_CAPABILITIES_OUT msgresponse */ 22204 22204 - #define MC_CMD_VIRTIO_GET_CAPABILITIES_OUT_LEN 4 22205 22205 - /* Maximum number of queues supported for a single device instance */ 22206 22206 - #define MC_CMD_VIRTIO_GET_CAPABILITIES_OUT_MAX_QUEUES_OFST 0 22207 22207 - #define MC_CMD_VIRTIO_GET_CAPABILITIES_OUT_MAX_QUEUES_LEN 4 22208 25162 22209 25163 22210 25164 /***********************************/ ··· 22458 25474 #define PCIE_FUNCTION_INTF_LBN 32 22459 25475 #define PCIE_FUNCTION_INTF_WIDTH 32 22460 25476 22461 22461 - /* QUEUE_ID structuredef: Structure representing an absolute queue identifier 22462 22462 - * (absolute VI number + VI relative queue number). On Keystone, a VI can 22463 22463 - * contain multiple queues (at present, up to 2), each with separate controls 22464 22464 - * for direction. This structure is required to uniquely identify the absolute 22465 22465 - * source queue for descriptor proxy functions. 22466 22466 - */ 22467 22467 - #define QUEUE_ID_LEN 4 22468 22468 - /* Absolute VI number */ 22469 22469 - #define QUEUE_ID_ABS_VI_OFST 0 22470 22470 - #define QUEUE_ID_ABS_VI_LEN 2 22471 22471 - #define QUEUE_ID_ABS_VI_LBN 0 22472 22472 - #define QUEUE_ID_ABS_VI_WIDTH 16 22473 22473 - /* Relative queue number within the VI */ 22474 22474 - #define QUEUE_ID_REL_QUEUE_LBN 16 22475 22475 - #define QUEUE_ID_REL_QUEUE_WIDTH 1 22476 22476 - #define QUEUE_ID_RESERVED_LBN 17 22477 22477 - #define QUEUE_ID_RESERVED_WIDTH 15 22478 22478 - 22479 22479 - 22480 22480 - /***********************************/ 22481 22481 - /* MC_CMD_DESC_PROXY_FUNC_CREATE 22482 22482 - * Descriptor proxy functions are abstract devices that forward all request 22483 22483 - * submitted to the host PCIe function (descriptors submitted to Virtio or 22484 22484 - * EF100 queues) to be handled on another function (most commonly on the 22485 22485 - * embedded Application Processor), via EF100 descriptor proxy, memory-to- 22486 22486 - * memory and descriptor-to-completion mechanisms. Primary user is Virtio-blk 22487 22487 - * subsystem, see SF-122927-TC. This function allocates a new descriptor proxy 22488 22488 - * function on the host and assigns a user-defined label. The actual function 22489 22489 - * configuration is not persisted until the caller configures it with 22490 22490 - * MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN and commits with 22491 22491 - * MC_CMD_DESC_PROXY_FUNC_COMMIT_IN. 22492 22492 - */ 22493 22493 - #define MC_CMD_DESC_PROXY_FUNC_CREATE 0x172 22494 22494 - #undef MC_CMD_0x172_PRIVILEGE_CTG 22495 22495 - 22496 22496 - #define MC_CMD_0x172_PRIVILEGE_CTG SRIOV_CTG_ADMIN 22497 22497 - 22498 22498 - /* MC_CMD_DESC_PROXY_FUNC_CREATE_IN msgrequest */ 22499 22499 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_LEN 52 22500 22500 - /* PCIe Function ID to allocate (as struct PCIE_FUNCTION). Set to 22501 22501 - * {PF_ANY,VF_ANY,interface} for "any available function" Set to 22502 22502 - * {PF_ANY,VF_NULL,interface} for "any available PF" 22503 22503 - */ 22504 22504 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_OFST 0 22505 22505 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LEN 8 22506 22506 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_OFST 0 22507 22507 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_LEN 4 22508 22508 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_LBN 0 22509 22509 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_WIDTH 32 22510 22510 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_OFST 4 22511 22511 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_LEN 4 22512 22512 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_LBN 32 22513 22513 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_WIDTH 32 22514 22514 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_PF_OFST 0 22515 22515 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_PF_LEN 2 22516 22516 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_VF_OFST 2 22517 22517 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_VF_LEN 2 22518 22518 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_INTF_OFST 4 22519 22519 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_INTF_LEN 4 22520 22520 - /* The personality to set. The meanings of the personalities are defined in 22521 22521 - * SF-120734-TC with more information in SF-122717-TC. At present, we only 22522 22522 - * support proxying for VIRTIO_BLK 22523 22523 - */ 22524 22524 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_PERSONALITY_OFST 8 22525 22525 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_PERSONALITY_LEN 4 22526 22526 - /* Enum values, see field(s): */ 22527 22527 - /* FUNCTION_PERSONALITY/ID */ 22528 22528 - /* User-defined label (zero-terminated ASCII string) to uniquely identify the 22529 22529 - * function 22530 22530 - */ 22531 22531 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_LABEL_OFST 12 22532 22532 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_LABEL_LEN 40 22533 22533 - 22534 22534 - /* MC_CMD_DESC_PROXY_FUNC_CREATE_OUT msgresponse */ 22535 22535 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_LEN 12 22536 22536 - /* Handle to the descriptor proxy function */ 22537 22537 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_HANDLE_OFST 0 22538 22538 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_HANDLE_LEN 4 22539 22539 - /* Allocated function ID (as struct PCIE_FUNCTION) */ 22540 22540 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_OFST 4 22541 22541 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LEN 8 22542 22542 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_OFST 4 22543 22543 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_LEN 4 22544 22544 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_LBN 32 22545 22545 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_WIDTH 32 22546 22546 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_OFST 8 22547 22547 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_LEN 4 22548 22548 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_LBN 64 22549 22549 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_WIDTH 32 22550 22550 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_PF_OFST 4 22551 22551 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_PF_LEN 2 22552 22552 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_VF_OFST 6 22553 22553 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_VF_LEN 2 22554 22554 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_INTF_OFST 8 22555 22555 - #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_INTF_LEN 4 22556 22556 - 22557 22557 - 22558 22558 - /***********************************/ 22559 22559 - /* MC_CMD_DESC_PROXY_FUNC_DESTROY 22560 22560 - * Remove an existing descriptor proxy function. Underlying function 22561 22561 - * personality and configuration reverts back to factory default. Function 22562 22562 - * configuration is committed immediately to specified store and any function 22563 22563 - * ownership is released. 22564 22564 - */ 22565 22565 - #define MC_CMD_DESC_PROXY_FUNC_DESTROY 0x173 22566 22566 - #undef MC_CMD_0x173_PRIVILEGE_CTG 22567 22567 - 22568 22568 - #define MC_CMD_0x173_PRIVILEGE_CTG SRIOV_CTG_ADMIN 22569 22569 - 22570 22570 - /* MC_CMD_DESC_PROXY_FUNC_DESTROY_IN msgrequest */ 22571 22571 - #define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_LEN 44 22572 22572 - /* User-defined label (zero-terminated ASCII string) to uniquely identify the 22573 22573 - * function 22574 22574 - */ 22575 22575 - #define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_LABEL_OFST 0 22576 22576 - #define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_LABEL_LEN 40 22577 22577 - /* Store from which to remove function configuration */ 22578 22578 - #define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_STORE_OFST 40 22579 22579 - #define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_STORE_LEN 4 22580 22580 - /* Enum values, see field(s): */ 22581 22581 - /* MC_CMD_DESC_PROXY_FUNC_COMMIT/MC_CMD_DESC_PROXY_FUNC_COMMIT_IN/STORE */ 22582 22582 - 22583 22583 - /* MC_CMD_DESC_PROXY_FUNC_DESTROY_OUT msgresponse */ 22584 22584 - #define MC_CMD_DESC_PROXY_FUNC_DESTROY_OUT_LEN 0 22585 22585 - 22586 22586 - /* VIRTIO_BLK_CONFIG structuredef: Virtio block device configuration. See 22587 22587 - * Virtio specification v1.1, Sections 5.2.3 and 6 for definition of feature 22588 22588 - * bits. See Virtio specification v1.1, Section 5.2.4 (struct 22589 22589 - * virtio_blk_config) for definition of remaining configuration fields 22590 22590 - */ 22591 22591 - #define VIRTIO_BLK_CONFIG_LEN 68 22592 22592 - /* Virtio block device features to advertise, per Virtio 1.1, 5.2.3 and 6 */ 22593 22593 - #define VIRTIO_BLK_CONFIG_FEATURES_OFST 0 22594 22594 - #define VIRTIO_BLK_CONFIG_FEATURES_LEN 8 22595 22595 - #define VIRTIO_BLK_CONFIG_FEATURES_LO_OFST 0 22596 22596 - #define VIRTIO_BLK_CONFIG_FEATURES_LO_LEN 4 22597 22597 - #define VIRTIO_BLK_CONFIG_FEATURES_LO_LBN 0 22598 22598 - #define VIRTIO_BLK_CONFIG_FEATURES_LO_WIDTH 32 22599 22599 - #define VIRTIO_BLK_CONFIG_FEATURES_HI_OFST 4 22600 22600 - #define VIRTIO_BLK_CONFIG_FEATURES_HI_LEN 4 22601 22601 - #define VIRTIO_BLK_CONFIG_FEATURES_HI_LBN 32 22602 22602 - #define VIRTIO_BLK_CONFIG_FEATURES_HI_WIDTH 32 22603 22603 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_OFST 0 22604 22604 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_LBN 0 22605 22605 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_WIDTH 1 22606 22606 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_OFST 0 22607 22607 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_LBN 1 22608 22608 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_WIDTH 1 22609 22609 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_OFST 0 22610 22610 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_LBN 2 22611 22611 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_WIDTH 1 22612 22612 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_OFST 0 22613 22613 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_LBN 4 22614 22614 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_WIDTH 1 22615 22615 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_OFST 0 22616 22616 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_LBN 5 22617 22617 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_WIDTH 1 22618 22618 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_OFST 0 22619 22619 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_LBN 6 22620 22620 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_WIDTH 1 22621 22621 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_OFST 0 22622 22622 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_LBN 7 22623 22623 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_WIDTH 1 22624 22624 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_OFST 0 22625 22625 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_LBN 9 22626 22626 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_WIDTH 1 22627 22627 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_OFST 0 22628 22628 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_LBN 10 22629 22629 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_WIDTH 1 22630 22630 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_OFST 0 22631 22631 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_LBN 11 22632 22632 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_WIDTH 1 22633 22633 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_OFST 0 22634 22634 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_LBN 12 22635 22635 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_WIDTH 1 22636 22636 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_OFST 0 22637 22637 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_LBN 13 22638 22638 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_WIDTH 1 22639 22639 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_OFST 0 22640 22640 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_LBN 14 22641 22641 - #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_WIDTH 1 22642 22642 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_OFST 0 22643 22643 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_LBN 28 22644 22644 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_WIDTH 1 22645 22645 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_OFST 0 22646 22646 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_LBN 29 22647 22647 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_WIDTH 1 22648 22648 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_OFST 0 22649 22649 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_LBN 32 22650 22650 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_WIDTH 1 22651 22651 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_OFST 0 22652 22652 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_LBN 33 22653 22653 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_WIDTH 1 22654 22654 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_OFST 0 22655 22655 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_LBN 34 22656 22656 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_WIDTH 1 22657 22657 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_OFST 0 22658 22658 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_LBN 35 22659 22659 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_WIDTH 1 22660 22660 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_OFST 0 22661 22661 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_LBN 36 22662 22662 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_WIDTH 1 22663 22663 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_OFST 0 22664 22664 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_LBN 37 22665 22665 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_WIDTH 1 22666 22666 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_OFST 0 22667 22667 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_LBN 38 22668 22668 - #define VIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_WIDTH 1 22669 22669 - #define VIRTIO_BLK_CONFIG_FEATURES_LBN 0 22670 22670 - #define VIRTIO_BLK_CONFIG_FEATURES_WIDTH 64 22671 22671 - /* The capacity of the device (expressed in 512-byte sectors) */ 22672 22672 - #define VIRTIO_BLK_CONFIG_CAPACITY_OFST 8 22673 22673 - #define VIRTIO_BLK_CONFIG_CAPACITY_LEN 8 22674 22674 - #define VIRTIO_BLK_CONFIG_CAPACITY_LO_OFST 8 22675 22675 - #define VIRTIO_BLK_CONFIG_CAPACITY_LO_LEN 4 22676 22676 - #define VIRTIO_BLK_CONFIG_CAPACITY_LO_LBN 64 22677 22677 - #define VIRTIO_BLK_CONFIG_CAPACITY_LO_WIDTH 32 22678 22678 - #define VIRTIO_BLK_CONFIG_CAPACITY_HI_OFST 12 22679 22679 - #define VIRTIO_BLK_CONFIG_CAPACITY_HI_LEN 4 22680 22680 - #define VIRTIO_BLK_CONFIG_CAPACITY_HI_LBN 96 22681 22681 - #define VIRTIO_BLK_CONFIG_CAPACITY_HI_WIDTH 32 22682 22682 - #define VIRTIO_BLK_CONFIG_CAPACITY_LBN 64 22683 22683 - #define VIRTIO_BLK_CONFIG_CAPACITY_WIDTH 64 22684 22684 - /* Maximum size of any single segment. Only valid when VIRTIO_BLK_F_SIZE_MAX is 22685 22685 - * set. 22686 22686 - */ 22687 22687 - #define VIRTIO_BLK_CONFIG_SIZE_MAX_OFST 16 22688 22688 - #define VIRTIO_BLK_CONFIG_SIZE_MAX_LEN 4 22689 22689 - #define VIRTIO_BLK_CONFIG_SIZE_MAX_LBN 128 22690 22690 - #define VIRTIO_BLK_CONFIG_SIZE_MAX_WIDTH 32 22691 22691 - /* Maximum number of segments in a request. Only valid when 22692 22692 - * VIRTIO_BLK_F_SEG_MAX is set. 22693 22693 - */ 22694 22694 - #define VIRTIO_BLK_CONFIG_SEG_MAX_OFST 20 22695 22695 - #define VIRTIO_BLK_CONFIG_SEG_MAX_LEN 4 22696 22696 - #define VIRTIO_BLK_CONFIG_SEG_MAX_LBN 160 22697 22697 - #define VIRTIO_BLK_CONFIG_SEG_MAX_WIDTH 32 22698 22698 - /* Disk-style geometry - cylinders. Only valid when VIRTIO_BLK_F_GEOMETRY is 22699 22699 - * set. 22700 22700 - */ 22701 22701 - #define VIRTIO_BLK_CONFIG_CYLINDERS_OFST 24 22702 22702 - #define VIRTIO_BLK_CONFIG_CYLINDERS_LEN 2 22703 22703 - #define VIRTIO_BLK_CONFIG_CYLINDERS_LBN 192 22704 22704 - #define VIRTIO_BLK_CONFIG_CYLINDERS_WIDTH 16 22705 22705 - /* Disk-style geometry - heads. Only valid when VIRTIO_BLK_F_GEOMETRY is set. 22706 22706 - */ 22707 22707 - #define VIRTIO_BLK_CONFIG_HEADS_OFST 26 22708 22708 - #define VIRTIO_BLK_CONFIG_HEADS_LEN 1 22709 22709 - #define VIRTIO_BLK_CONFIG_HEADS_LBN 208 22710 22710 - #define VIRTIO_BLK_CONFIG_HEADS_WIDTH 8 22711 22711 - /* Disk-style geometry - sectors. Only valid when VIRTIO_BLK_F_GEOMETRY is set. 22712 22712 - */ 22713 22713 - #define VIRTIO_BLK_CONFIG_SECTORS_OFST 27 22714 22714 - #define VIRTIO_BLK_CONFIG_SECTORS_LEN 1 22715 22715 - #define VIRTIO_BLK_CONFIG_SECTORS_LBN 216 22716 22716 - #define VIRTIO_BLK_CONFIG_SECTORS_WIDTH 8 22717 22717 - /* Block size of disk. Only valid when VIRTIO_BLK_F_BLK_SIZE is set. */ 22718 22718 - #define VIRTIO_BLK_CONFIG_BLK_SIZE_OFST 28 22719 22719 - #define VIRTIO_BLK_CONFIG_BLK_SIZE_LEN 4 22720 22720 - #define VIRTIO_BLK_CONFIG_BLK_SIZE_LBN 224 22721 22721 - #define VIRTIO_BLK_CONFIG_BLK_SIZE_WIDTH 32 22722 22722 - /* Block topology - number of logical blocks per physical block (log2). Only 22723 22723 - * valid when VIRTIO_BLK_F_TOPOLOGY is set. 22724 22724 - */ 22725 22725 - #define VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_OFST 32 22726 22726 - #define VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_LEN 1 22727 22727 - #define VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_LBN 256 22728 22728 - #define VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_WIDTH 8 22729 22729 - /* Block topology - offset of first aligned logical block. Only valid when 22730 22730 - * VIRTIO_BLK_F_TOPOLOGY is set. 22731 22731 - */ 22732 22732 - #define VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_OFST 33 22733 22733 - #define VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_LEN 1 22734 22734 - #define VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_LBN 264 22735 22735 - #define VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_WIDTH 8 22736 22736 - /* Block topology - suggested minimum I/O size in blocks. Only valid when 22737 22737 - * VIRTIO_BLK_F_TOPOLOGY is set. 22738 22738 - */ 22739 22739 - #define VIRTIO_BLK_CONFIG_MIN_IO_SIZE_OFST 34 22740 22740 - #define VIRTIO_BLK_CONFIG_MIN_IO_SIZE_LEN 2 22741 22741 - #define VIRTIO_BLK_CONFIG_MIN_IO_SIZE_LBN 272 22742 22742 - #define VIRTIO_BLK_CONFIG_MIN_IO_SIZE_WIDTH 16 22743 22743 - /* Block topology - optimal (suggested maximum) I/O size in blocks. Only valid 22744 22744 - * when VIRTIO_BLK_F_TOPOLOGY is set. 22745 22745 - */ 22746 22746 - #define VIRTIO_BLK_CONFIG_OPT_IO_SIZE_OFST 36 22747 22747 - #define VIRTIO_BLK_CONFIG_OPT_IO_SIZE_LEN 4 22748 22748 - #define VIRTIO_BLK_CONFIG_OPT_IO_SIZE_LBN 288 22749 22749 - #define VIRTIO_BLK_CONFIG_OPT_IO_SIZE_WIDTH 32 22750 22750 - /* Unused, set to zero. Note that virtio_blk_config.writeback is volatile and 22751 22751 - * not carried in config data. 22752 22752 - */ 22753 22753 - #define VIRTIO_BLK_CONFIG_UNUSED0_OFST 40 22754 22754 - #define VIRTIO_BLK_CONFIG_UNUSED0_LEN 2 22755 22755 - #define VIRTIO_BLK_CONFIG_UNUSED0_LBN 320 22756 22756 - #define VIRTIO_BLK_CONFIG_UNUSED0_WIDTH 16 22757 22757 - /* Number of queues. Only valid if the VIRTIO_BLK_F_MQ feature is negotiated. 22758 22758 - */ 22759 22759 - #define VIRTIO_BLK_CONFIG_NUM_QUEUES_OFST 42 22760 22760 - #define VIRTIO_BLK_CONFIG_NUM_QUEUES_LEN 2 22761 22761 - #define VIRTIO_BLK_CONFIG_NUM_QUEUES_LBN 336 22762 22762 - #define VIRTIO_BLK_CONFIG_NUM_QUEUES_WIDTH 16 22763 22763 - /* Maximum discard sectors size, in 512-byte units. Only valid if 22764 22764 - * VIRTIO_BLK_F_DISCARD is set. 22765 22765 - */ 22766 22766 - #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_OFST 44 22767 22767 - #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_LEN 4 22768 22768 - #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_LBN 352 22769 22769 - #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_WIDTH 32 22770 22770 - /* Maximum discard segment number. Only valid if VIRTIO_BLK_F_DISCARD is set. 22771 22771 - */ 22772 22772 - #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_OFST 48 22773 22773 - #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_LEN 4 22774 22774 - #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_LBN 384 22775 22775 - #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_WIDTH 32 22776 22776 - /* Discard sector alignment, in 512-byte units. Only valid if 22777 22777 - * VIRTIO_BLK_F_DISCARD is set. 22778 22778 - */ 22779 22779 - #define VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_OFST 52 22780 22780 - #define VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_LEN 4 22781 22781 - #define VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_LBN 416 22782 22782 - #define VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_WIDTH 32 22783 22783 - /* Maximum write zeroes sectors size, in 512-byte units. Only valid if 22784 22784 - * VIRTIO_BLK_F_WRITE_ZEROES is set. 22785 22785 - */ 22786 22786 - #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_OFST 56 22787 22787 - #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_LEN 4 22788 22788 - #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_LBN 448 22789 22789 - #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_WIDTH 32 22790 22790 - /* Maximum write zeroes segment number. Only valid if VIRTIO_BLK_F_WRITE_ZEROES 22791 22791 - * is set. 22792 22792 - */ 22793 22793 - #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_OFST 60 22794 22794 - #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_LEN 4 22795 22795 - #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_LBN 480 22796 22796 - #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_WIDTH 32 22797 22797 - /* Write zeroes request can result in deallocating one or more sectors. Only 22798 22798 - * valid if VIRTIO_BLK_F_WRITE_ZEROES is set. 22799 22799 - */ 22800 22800 - #define VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_OFST 64 22801 22801 - #define VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_LEN 1 22802 22802 - #define VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_LBN 512 22803 22803 - #define VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_WIDTH 8 22804 22804 - /* Unused, set to zero. */ 22805 22805 - #define VIRTIO_BLK_CONFIG_UNUSED1_OFST 65 22806 22806 - #define VIRTIO_BLK_CONFIG_UNUSED1_LEN 3 22807 22807 - #define VIRTIO_BLK_CONFIG_UNUSED1_LBN 520 22808 22808 - #define VIRTIO_BLK_CONFIG_UNUSED1_WIDTH 24 22809 22809 - 22810 22810 - 22811 22811 - /***********************************/ 22812 22812 - /* MC_CMD_DESC_PROXY_FUNC_CONFIG_SET 22813 22813 - * Set configuration for an existing descriptor proxy function. Configuration 22814 22814 - * data must match function personality. The actual function configuration is 22815 22815 - * not persisted until the caller commits with MC_CMD_DESC_PROXY_FUNC_COMMIT_IN 22816 22816 - */ 22817 22817 - #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET 0x174 22818 22818 - #undef MC_CMD_0x174_PRIVILEGE_CTG 22819 22819 - 22820 22820 - #define MC_CMD_0x174_PRIVILEGE_CTG SRIOV_CTG_ADMIN 22821 22821 - 22822 22822 - /* MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN msgrequest */ 22823 22823 - #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LENMIN 20 22824 22824 - #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LENMAX 252 22825 22825 - #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LENMAX_MCDI2 1020 22826 22826 - #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LEN(num) (20+1*(num)) 22827 22827 - #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_NUM(len) (((len)-20)/1) 22828 22828 - /* Handle to descriptor proxy function (as returned by 22829 22829 - * MC_CMD_DESC_PROXY_FUNC_OPEN) 22830 22830 - */ 22831 22831 - #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_HANDLE_OFST 0 22832 22832 - #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_HANDLE_LEN 4 22833 22833 - /* Reserved for future extension, set to zero. */ 22834 22834 - #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_RESERVED_OFST 4 22835 22835 - #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_RESERVED_LEN 16 22836 22836 - /* Configuration data. Format of configuration data is determined implicitly 22837 22837 - * from function personality referred to by HANDLE. Currently, only supported 22838 22838 - * format is VIRTIO_BLK_CONFIG. 22839 22839 - */ 22840 22840 - #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_OFST 20 22841 22841 - #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_LEN 1 22842 22842 - #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_MINNUM 0 22843 22843 - #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_MAXNUM 232 22844 22844 - #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_MAXNUM_MCDI2 1000 22845 22845 - 22846 22846 - /* MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_OUT msgresponse */ 22847 22847 - #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_OUT_LEN 0 22848 22848 - 22849 22849 - 22850 22850 - /***********************************/ 22851 22851 - /* MC_CMD_DESC_PROXY_FUNC_COMMIT 22852 22852 - * Commit function configuration to non-volatile or volatile store. Once 22853 22853 - * configuration is applied to hardware (which may happen immediately or on 22854 22854 - * next function/device reset) a DESC_PROXY_FUNC_CONFIG_SET MCDI event will be 22855 22855 - * delivered to callers MCDI event queue. 22856 22856 - */ 22857 22857 - #define MC_CMD_DESC_PROXY_FUNC_COMMIT 0x175 22858 22858 - #undef MC_CMD_0x175_PRIVILEGE_CTG 22859 22859 - 22860 22860 - #define MC_CMD_0x175_PRIVILEGE_CTG SRIOV_CTG_ADMIN 22861 22861 - 22862 22862 - /* MC_CMD_DESC_PROXY_FUNC_COMMIT_IN msgrequest */ 22863 22863 - #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_LEN 8 22864 22864 - /* Handle to descriptor proxy function (as returned by 22865 22865 - * MC_CMD_DESC_PROXY_FUNC_OPEN) 22866 22866 - */ 22867 22867 - #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_HANDLE_OFST 0 22868 22868 - #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_HANDLE_LEN 4 22869 22869 - #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_STORE_OFST 4 22870 22870 - #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_STORE_LEN 4 22871 22871 - /* enum: Store into non-volatile (dynamic) config */ 22872 22872 - #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_NON_VOLATILE 0x0 22873 22873 - /* enum: Store into volatile (ephemeral) config */ 22874 22874 - #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_VOLATILE 0x1 22875 22875 - 22876 22876 - /* MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT msgresponse */ 22877 22877 - #define MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_LEN 4 22878 22878 - /* Generation count to be delivered in an event once configuration becomes live 22879 22879 - */ 22880 22880 - #define MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_CONFIG_GENERATION_OFST 0 22881 22881 - #define MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_CONFIG_GENERATION_LEN 4 22882 22882 - 22883 22883 - 22884 22884 - /***********************************/ 22885 22885 - /* MC_CMD_DESC_PROXY_FUNC_OPEN 22886 22886 - * Retrieve a handle for an existing descriptor proxy function. Returns an 22887 22887 - * integer handle, valid until function is deallocated, MC rebooted or power- 22888 22888 - * cycle. Returns ENODEV if no function with given label exists. 22889 22889 - */ 22890 22890 - #define MC_CMD_DESC_PROXY_FUNC_OPEN 0x176 22891 22891 - #undef MC_CMD_0x176_PRIVILEGE_CTG 22892 22892 - 22893 22893 - #define MC_CMD_0x176_PRIVILEGE_CTG SRIOV_CTG_ADMIN 22894 22894 - 22895 22895 - /* MC_CMD_DESC_PROXY_FUNC_OPEN_IN msgrequest */ 22896 22896 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_IN_LEN 40 22897 22897 - /* User-defined label (zero-terminated ASCII string) to uniquely identify the 22898 22898 - * function 22899 22899 - */ 22900 22900 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_IN_LABEL_OFST 0 22901 22901 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_IN_LABEL_LEN 40 22902 22902 - 22903 22903 - /* MC_CMD_DESC_PROXY_FUNC_OPEN_OUT msgresponse */ 22904 22904 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LENMIN 40 22905 22905 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LENMAX 252 22906 22906 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LENMAX_MCDI2 1020 22907 22907 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LEN(num) (40+1*(num)) 22908 22908 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_NUM(len) (((len)-40)/1) 22909 22909 - /* Handle to the descriptor proxy function */ 22910 22910 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_HANDLE_OFST 0 22911 22911 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_HANDLE_LEN 4 22912 22912 - /* PCIe Function ID (as struct PCIE_FUNCTION) */ 22913 22913 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_OFST 4 22914 22914 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LEN 8 22915 22915 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_OFST 4 22916 22916 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_LEN 4 22917 22917 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_LBN 32 22918 22918 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_WIDTH 32 22919 22919 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_OFST 8 22920 22920 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_LEN 4 22921 22921 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_LBN 64 22922 22922 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_WIDTH 32 22923 22923 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_PF_OFST 4 22924 22924 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_PF_LEN 2 22925 22925 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_VF_OFST 6 22926 22926 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_VF_LEN 2 22927 22927 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_INTF_OFST 8 22928 22928 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_INTF_LEN 4 22929 22929 - /* Function personality */ 22930 22930 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_OFST 12 22931 22931 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_LEN 4 22932 22932 - /* Enum values, see field(s): */ 22933 22933 - /* FUNCTION_PERSONALITY/ID */ 22934 22934 - /* Function configuration state */ 22935 22935 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_STATUS_OFST 16 22936 22936 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_STATUS_LEN 4 22937 22937 - /* enum: Function configuration is visible to the host (live) */ 22938 22938 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LIVE 0x0 22939 22939 - /* enum: Function configuration is pending reset */ 22940 22940 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PENDING 0x1 22941 22941 - /* enum: Function configuration is missing (created, but no configuration 22942 22942 - * committed) 22943 22943 - */ 22944 22944 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_UNCONFIGURED 0x2 22945 22945 - /* Generation count to be delivered in an event once the configuration becomes 22946 22946 - * live (if status is "pending") 22947 22947 - */ 22948 22948 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_GENERATION_OFST 20 22949 22949 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_GENERATION_LEN 4 22950 22950 - /* Reserved for future extension, set to zero. */ 22951 22951 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_RESERVED_OFST 24 22952 22952 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_RESERVED_LEN 16 22953 22953 - /* Configuration data corresponding to function personality. Currently, only 22954 22954 - * supported format is VIRTIO_BLK_CONFIG. Not valid if status is UNCONFIGURED. 22955 22955 - */ 22956 22956 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_OFST 40 22957 22957 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_LEN 1 22958 22958 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_MINNUM 0 22959 22959 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_MAXNUM 212 22960 22960 - #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_MAXNUM_MCDI2 980 22961 22961 - 22962 22962 - 22963 22963 - /***********************************/ 22964 22964 - /* MC_CMD_DESC_PROXY_FUNC_CLOSE 22965 22965 - * Releases a handle for an open descriptor proxy function. If proxying was 22966 22966 - * enabled on the device, the caller is expected to gracefully stop it using 22967 22967 - * MC_CMD_DESC_PROXY_FUNC_DISABLE prior to calling this function. Closing an 22968 22968 - * active device without disabling proxying will result in forced close, which 22969 22969 - * will put the device into a failed state and signal the host driver of the 22970 22970 - * error (for virtio, DEVICE_NEEDS_RESET flag would be set on the host side) 22971 22971 - */ 22972 22972 - #define MC_CMD_DESC_PROXY_FUNC_CLOSE 0x1a1 22973 22973 - #undef MC_CMD_0x1a1_PRIVILEGE_CTG 22974 22974 - 22975 22975 - #define MC_CMD_0x1a1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 22976 22976 - 22977 22977 - /* MC_CMD_DESC_PROXY_FUNC_CLOSE_IN msgrequest */ 22978 22978 - #define MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_LEN 4 22979 22979 - /* Handle to the descriptor proxy function */ 22980 22980 - #define MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_HANDLE_OFST 0 22981 22981 - #define MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_HANDLE_LEN 4 22982 22982 - 22983 22983 - /* MC_CMD_DESC_PROXY_FUNC_CLOSE_OUT msgresponse */ 22984 22984 - #define MC_CMD_DESC_PROXY_FUNC_CLOSE_OUT_LEN 0 22985 22985 - 22986 22986 - /* DESC_PROXY_FUNC_MAP structuredef */ 22987 22987 - #define DESC_PROXY_FUNC_MAP_LEN 52 22988 22988 - /* PCIe function ID (as struct PCIE_FUNCTION) */ 22989 22989 - #define DESC_PROXY_FUNC_MAP_FUNC_OFST 0 22990 22990 - #define DESC_PROXY_FUNC_MAP_FUNC_LEN 8 22991 22991 - #define DESC_PROXY_FUNC_MAP_FUNC_LO_OFST 0 22992 22992 - #define DESC_PROXY_FUNC_MAP_FUNC_LO_LEN 4 22993 22993 - #define DESC_PROXY_FUNC_MAP_FUNC_LO_LBN 0 22994 22994 - #define DESC_PROXY_FUNC_MAP_FUNC_LO_WIDTH 32 22995 22995 - #define DESC_PROXY_FUNC_MAP_FUNC_HI_OFST 4 22996 22996 - #define DESC_PROXY_FUNC_MAP_FUNC_HI_LEN 4 22997 22997 - #define DESC_PROXY_FUNC_MAP_FUNC_HI_LBN 32 22998 22998 - #define DESC_PROXY_FUNC_MAP_FUNC_HI_WIDTH 32 22999 22999 - #define DESC_PROXY_FUNC_MAP_FUNC_LBN 0 23000 23000 - #define DESC_PROXY_FUNC_MAP_FUNC_WIDTH 64 23001 23001 - #define DESC_PROXY_FUNC_MAP_FUNC_PF_OFST 0 23002 23002 - #define DESC_PROXY_FUNC_MAP_FUNC_PF_LEN 2 23003 23003 - #define DESC_PROXY_FUNC_MAP_FUNC_PF_LBN 0 23004 23004 - #define DESC_PROXY_FUNC_MAP_FUNC_PF_WIDTH 16 23005 23005 - #define DESC_PROXY_FUNC_MAP_FUNC_VF_OFST 2 23006 23006 - #define DESC_PROXY_FUNC_MAP_FUNC_VF_LEN 2 23007 23007 - #define DESC_PROXY_FUNC_MAP_FUNC_VF_LBN 16 23008 23008 - #define DESC_PROXY_FUNC_MAP_FUNC_VF_WIDTH 16 23009 23009 - #define DESC_PROXY_FUNC_MAP_FUNC_INTF_OFST 4 23010 23010 - #define DESC_PROXY_FUNC_MAP_FUNC_INTF_LEN 4 23011 23011 - #define DESC_PROXY_FUNC_MAP_FUNC_INTF_LBN 32 23012 23012 - #define DESC_PROXY_FUNC_MAP_FUNC_INTF_WIDTH 32 23013 23013 - /* Function personality */ 23014 23014 - #define DESC_PROXY_FUNC_MAP_PERSONALITY_OFST 8 23015 23015 - #define DESC_PROXY_FUNC_MAP_PERSONALITY_LEN 4 23016 23016 - /* Enum values, see field(s): */ 23017 23017 - /* FUNCTION_PERSONALITY/ID */ 23018 23018 - #define DESC_PROXY_FUNC_MAP_PERSONALITY_LBN 64 23019 23019 - #define DESC_PROXY_FUNC_MAP_PERSONALITY_WIDTH 32 23020 23020 - /* User-defined label (zero-terminated ASCII string) to uniquely identify the 23021 23021 - * function 23022 23022 - */ 23023 23023 - #define DESC_PROXY_FUNC_MAP_LABEL_OFST 12 23024 23024 - #define DESC_PROXY_FUNC_MAP_LABEL_LEN 40 23025 23025 - #define DESC_PROXY_FUNC_MAP_LABEL_LBN 96 23026 23026 - #define DESC_PROXY_FUNC_MAP_LABEL_WIDTH 320 23027 23027 - 23028 23028 - 23029 23029 - /***********************************/ 23030 23030 - /* MC_CMD_DESC_PROXY_FUNC_ENUM 23031 23031 - * Enumerate existing descriptor proxy functions 23032 23032 - */ 23033 23033 - #define MC_CMD_DESC_PROXY_FUNC_ENUM 0x177 23034 23034 - #undef MC_CMD_0x177_PRIVILEGE_CTG 23035 23035 - 23036 23036 - #define MC_CMD_0x177_PRIVILEGE_CTG SRIOV_CTG_ADMIN 23037 23037 - 23038 23038 - /* MC_CMD_DESC_PROXY_FUNC_ENUM_IN msgrequest */ 23039 23039 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_IN_LEN 4 23040 23040 - /* Starting index, set to 0 on first request. See 23041 23041 - * MC_CMD_DESC_PROXY_FUNC_ENUM_OUT/FLAGS. 23042 23042 - */ 23043 23043 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_IN_START_IDX_OFST 0 23044 23044 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_IN_START_IDX_LEN 4 23045 23045 - 23046 23046 - /* MC_CMD_DESC_PROXY_FUNC_ENUM_OUT msgresponse */ 23047 23047 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMIN 4 23048 23048 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMAX 212 23049 23049 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMAX_MCDI2 992 23050 23050 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LEN(num) (4+52*(num)) 23051 23051 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_NUM(len) (((len)-4)/52) 23052 23052 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FLAGS_OFST 0 23053 23053 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FLAGS_LEN 4 23054 23054 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_OFST 0 23055 23055 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_LBN 0 23056 23056 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_WIDTH 1 23057 23057 - /* Function map, as array of DESC_PROXY_FUNC_MAP */ 23058 23058 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_OFST 4 23059 23059 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_LEN 52 23060 23060 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MINNUM 0 23061 23061 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MAXNUM 4 23062 23062 - #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MAXNUM_MCDI2 19 23063 23063 - 23064 23064 - 23065 23065 - /***********************************/ 23066 23066 - /* MC_CMD_DESC_PROXY_FUNC_ENABLE 23067 23067 - * Enable descriptor proxying for function into target event queue. Returns VI 23068 23068 - * allocation info for the proxy source function, so that the caller can map 23069 23069 - * absolute VI IDs from descriptor proxy events back to the originating 23070 23070 - * function. This is a legacy function that only supports single queue proxy 23071 23071 - * devices. It is also limited in that it can only be called after host driver 23072 23072 - * attach (once VI allocation is known) and will return MC_CMD_ERR_ENOTCONN 23073 23073 - * otherwise. For new code, see MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE which 23074 23074 - * supports multi-queue devices and has no dependency on host driver attach. 23075 23075 - */ 23076 23076 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE 0x178 23077 23077 - #undef MC_CMD_0x178_PRIVILEGE_CTG 23078 23078 - 23079 23079 - #define MC_CMD_0x178_PRIVILEGE_CTG SRIOV_CTG_ADMIN 23080 23080 - 23081 23081 - /* MC_CMD_DESC_PROXY_FUNC_ENABLE_IN msgrequest */ 23082 23082 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_LEN 8 23083 23083 - /* Handle to descriptor proxy function (as returned by 23084 23084 - * MC_CMD_DESC_PROXY_FUNC_OPEN) 23085 23085 - */ 23086 23086 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_HANDLE_OFST 0 23087 23087 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_HANDLE_LEN 4 23088 23088 - /* Descriptor proxy sink queue (caller function relative). Must be extended 23089 23089 - * width event queue 23090 23090 - */ 23091 23091 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_TARGET_EVQ_OFST 4 23092 23092 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_TARGET_EVQ_LEN 4 23093 23093 - 23094 23094 - /* MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT msgresponse */ 23095 23095 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_LEN 8 23096 23096 - /* The number of VIs allocated on the function */ 23097 23097 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_COUNT_OFST 0 23098 23098 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_COUNT_LEN 4 23099 23099 - /* The base absolute VI number allocated to the function. */ 23100 23100 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_BASE_OFST 4 23101 23101 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_BASE_LEN 4 23102 23102 - 23103 23103 - 23104 23104 - /***********************************/ 23105 23105 - /* MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE 23106 23106 - * Enable descriptor proxying for a source queue on a host function into target 23107 23107 - * event queue. Source queue number is a relative virtqueue number on the 23108 23108 - * source function (0 to max_virtqueues-1). For a multi-queue device, the 23109 23109 - * caller must enable all source queues individually. To retrieve absolute VI 23110 23110 - * information for the source function (so that VI IDs from descriptor proxy 23111 23111 - * events can be mapped back to source function / queue) see 23112 23112 - * MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO 23113 23113 - */ 23114 23114 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE 0x1d0 23115 23115 - #undef MC_CMD_0x1d0_PRIVILEGE_CTG 23116 23116 - 23117 23117 - #define MC_CMD_0x1d0_PRIVILEGE_CTG SRIOV_CTG_ADMIN 23118 23118 - 23119 23119 - /* MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN msgrequest */ 23120 23120 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_LEN 12 23121 23121 - /* Handle to descriptor proxy function (as returned by 23122 23122 - * MC_CMD_DESC_PROXY_FUNC_OPEN) 23123 23123 - */ 23124 23124 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_HANDLE_OFST 0 23125 23125 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_HANDLE_LEN 4 23126 23126 - /* Source relative queue number to enable proxying on */ 23127 23127 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_SOURCE_QUEUE_OFST 4 23128 23128 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_SOURCE_QUEUE_LEN 4 23129 23129 - /* Descriptor proxy sink queue (caller function relative). Must be extended 23130 23130 - * width event queue 23131 23131 - */ 23132 23132 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_TARGET_EVQ_OFST 8 23133 23133 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_TARGET_EVQ_LEN 4 23134 23134 - 23135 23135 - /* MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_OUT msgresponse */ 23136 23136 - #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_OUT_LEN 0 23137 23137 - 23138 23138 - 23139 23139 - /***********************************/ 23140 23140 - /* MC_CMD_DESC_PROXY_FUNC_DISABLE 23141 23141 - * Disable descriptor proxying for function. For multi-queue functions, 23142 23142 - * disables all queues. 23143 23143 - */ 23144 23144 - #define MC_CMD_DESC_PROXY_FUNC_DISABLE 0x179 23145 23145 - #undef MC_CMD_0x179_PRIVILEGE_CTG 23146 23146 - 23147 23147 - #define MC_CMD_0x179_PRIVILEGE_CTG SRIOV_CTG_ADMIN 23148 23148 - 23149 23149 - /* MC_CMD_DESC_PROXY_FUNC_DISABLE_IN msgrequest */ 23150 23150 - #define MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_LEN 4 23151 23151 - /* Handle to descriptor proxy function (as returned by 23152 23152 - * MC_CMD_DESC_PROXY_FUNC_OPEN) 23153 23153 - */ 23154 23154 - #define MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_HANDLE_OFST 0 23155 23155 - #define MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_HANDLE_LEN 4 23156 23156 - 23157 23157 - /* MC_CMD_DESC_PROXY_FUNC_DISABLE_OUT msgresponse */ 23158 23158 - #define MC_CMD_DESC_PROXY_FUNC_DISABLE_OUT_LEN 0 23159 23159 - 23160 23160 - 23161 23161 - /***********************************/ 23162 23162 - /* MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE 23163 23163 - * Disable descriptor proxying for a specific source queue on a function. 23164 23164 - */ 23165 23165 - #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE 0x1d1 23166 23166 - #undef MC_CMD_0x1d1_PRIVILEGE_CTG 23167 23167 - 23168 23168 - #define MC_CMD_0x1d1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 23169 23169 - 23170 23170 - /* MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN msgrequest */ 23171 23171 - #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_LEN 8 23172 23172 - /* Handle to descriptor proxy function (as returned by 23173 23173 - * MC_CMD_DESC_PROXY_FUNC_OPEN) 23174 23174 - */ 23175 23175 - #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_HANDLE_OFST 0 23176 23176 - #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_HANDLE_LEN 4 23177 23177 - /* Source relative queue number to disable proxying on */ 23178 23178 - #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_SOURCE_QUEUE_OFST 4 23179 23179 - #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_SOURCE_QUEUE_LEN 4 23180 23180 - 23181 23181 - /* MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_OUT msgresponse */ 23182 23182 - #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_OUT_LEN 0 23183 23183 - 23184 23184 - 23185 23185 - /***********************************/ 23186 23186 - /* MC_CMD_DESC_PROXY_GET_VI_INFO 23187 23187 - * Returns absolute VI allocation information for the descriptor proxy source 23188 23188 - * function referenced by HANDLE, so that the caller can map absolute VI IDs 23189 23189 - * from descriptor proxy events back to the originating function and queue. The 23190 23190 - * call is only valid after the host driver for the source function has 23191 23191 - * attached (after receiving a driver attach event for the descriptor proxy 23192 23192 - * function) and will fail with ENOTCONN otherwise. 23193 23193 - */ 23194 23194 - #define MC_CMD_DESC_PROXY_GET_VI_INFO 0x1d2 23195 23195 - #undef MC_CMD_0x1d2_PRIVILEGE_CTG 23196 23196 - 23197 23197 - #define MC_CMD_0x1d2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 23198 23198 - 23199 23199 - /* MC_CMD_DESC_PROXY_GET_VI_INFO_IN msgrequest */ 23200 23200 - #define MC_CMD_DESC_PROXY_GET_VI_INFO_IN_LEN 4 23201 23201 - /* Handle to descriptor proxy function (as returned by 23202 23202 - * MC_CMD_DESC_PROXY_FUNC_OPEN) 23203 23203 - */ 23204 23204 - #define MC_CMD_DESC_PROXY_GET_VI_INFO_IN_HANDLE_OFST 0 23205 23205 - #define MC_CMD_DESC_PROXY_GET_VI_INFO_IN_HANDLE_LEN 4 23206 23206 - 23207 23207 - /* MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT msgresponse */ 23208 23208 - #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_LENMIN 0 23209 23209 - #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_LENMAX 252 23210 23210 - #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_LENMAX_MCDI2 1020 23211 23211 - #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_LEN(num) (0+4*(num)) 23212 23212 - #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_NUM(len) (((len)-0)/4) 23213 23213 - /* VI information (VI ID + VI relative queue number) for each of the source 23214 23214 - * queues (in order from 0 to max_virtqueues-1), as array of QUEUE_ID 23215 23215 - * structures. 23216 23216 - */ 23217 23217 - #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_OFST 0 23218 23218 - #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_LEN 4 23219 23219 - #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_MINNUM 0 23220 23220 - #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_MAXNUM 63 23221 23221 - #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_MAXNUM_MCDI2 255 23222 23222 - #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_ABS_VI_OFST 0 23223 23223 - #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_ABS_VI_LEN 2 23224 23224 - #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_REL_QUEUE_LBN 16 23225 23225 - #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_REL_QUEUE_WIDTH 1 23226 23226 - #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_RESERVED_LBN 17 23227 23227 - #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_RESERVED_WIDTH 15 23228 23228 - 23229 23229 - 23230 23230 - /***********************************/ 23231 23231 - /* MC_CMD_GET_ADDR_SPC_ID 23232 23232 - * Get Address space identifier for use in mem2mem descriptors for a given 23233 23233 - * target. See SF-120734-TC for details on ADDR_SPC_IDs and mem2mem 23234 23234 - * descriptors. 23235 23235 - */ 23236 23236 - #define MC_CMD_GET_ADDR_SPC_ID 0x1a0 23237 23237 - #undef MC_CMD_0x1a0_PRIVILEGE_CTG 23238 23238 - 23239 23239 - #define MC_CMD_0x1a0_PRIVILEGE_CTG SRIOV_CTG_ADMIN 23240 23240 - 23241 23241 - /* MC_CMD_GET_ADDR_SPC_ID_IN msgrequest */ 23242 23242 - #define MC_CMD_GET_ADDR_SPC_ID_IN_LEN 16 23243 23243 - /* Resource type to get ADDR_SPC_ID for */ 23244 23244 - #define MC_CMD_GET_ADDR_SPC_ID_IN_TYPE_OFST 0 23245 23245 - #define MC_CMD_GET_ADDR_SPC_ID_IN_TYPE_LEN 4 23246 23246 - /* enum: Address space ID for host/AP memory DMA over the same interface this 23247 23247 - * MCDI was called on 23248 23248 - */ 23249 23249 - #define MC_CMD_GET_ADDR_SPC_ID_IN_SELF 0x0 23250 23250 - /* enum: Address space ID for host/AP memory DMA via PCI interface and function 23251 23251 - * specified by FUNC 23252 23252 - */ 23253 23253 - #define MC_CMD_GET_ADDR_SPC_ID_IN_PCI_FUNC 0x1 23254 23254 - /* enum: Address space ID for host/AP memory DMA via PCI interface and function 23255 23255 - * specified by FUNC with PASID value specified by PASID 23256 23256 - */ 23257 23257 - #define MC_CMD_GET_ADDR_SPC_ID_IN_PCI_FUNC_PASID 0x2 23258 23258 - /* enum: Address space ID for host/AP memory DMA via PCI interface and function 23259 23259 - * specified by FUNC with PASID value of relative VI specified by VI 23260 23260 - */ 23261 23261 - #define MC_CMD_GET_ADDR_SPC_ID_IN_REL_VI 0x3 23262 23262 - /* enum: Address space ID for host/AP memory DMA via PCI interface, function 23263 23263 - * and PASID value of absolute VI specified by VI 23264 23264 - */ 23265 23265 - #define MC_CMD_GET_ADDR_SPC_ID_IN_ABS_VI 0x4 23266 23266 - /* enum: Address space ID for host memory DMA via PCI interface and function of 23267 23267 - * descriptor proxy function specified by HANDLE 23268 23268 - */ 23269 23269 - #define MC_CMD_GET_ADDR_SPC_ID_IN_DESC_PROXY_HANDLE 0x5 23270 23270 - /* enum: Address space ID for DMA to/from MC memory */ 23271 23271 - #define MC_CMD_GET_ADDR_SPC_ID_IN_MC_MEM 0x6 23272 23272 - /* enum: Address space ID for DMA to/from other SmartNIC memory (on-chip, DDR) 23273 23273 - */ 23274 23274 - #define MC_CMD_GET_ADDR_SPC_ID_IN_NIC_MEM 0x7 23275 23275 - /* PCIe Function ID (as struct PCIE_FUNCTION). Only valid if TYPE is PCI_FUNC, 23276 23276 - * PCI_FUNC_PASID or REL_VI. 23277 23277 - */ 23278 23278 - #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_OFST 4 23279 23279 - #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LEN 8 23280 23280 - #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_OFST 4 23281 23281 - #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_LEN 4 23282 23282 - #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_LBN 32 23283 23283 - #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_WIDTH 32 23284 23284 - #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_OFST 8 23285 23285 - #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_LEN 4 23286 23286 - #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_LBN 64 23287 23287 - #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_WIDTH 32 23288 23288 - #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_PF_OFST 4 23289 23289 - #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_PF_LEN 2 23290 23290 - #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_VF_OFST 6 23291 23291 - #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_VF_LEN 2 23292 23292 - #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_INTF_OFST 8 23293 23293 - #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_INTF_LEN 4 23294 23294 - /* PASID value. Only valid if TYPE is PCI_FUNC_PASID. */ 23295 23295 - #define MC_CMD_GET_ADDR_SPC_ID_IN_PASID_OFST 12 23296 23296 - #define MC_CMD_GET_ADDR_SPC_ID_IN_PASID_LEN 4 23297 23297 - /* Relative or absolute VI number. Only valid if TYPE is REL_VI or ABS_VI */ 23298 23298 - #define MC_CMD_GET_ADDR_SPC_ID_IN_VI_OFST 12 23299 23299 - #define MC_CMD_GET_ADDR_SPC_ID_IN_VI_LEN 4 23300 23300 - /* Descriptor proxy function handle. Only valid if TYPE is DESC_PROXY_HANDLE. 23301 23301 - */ 23302 23302 - #define MC_CMD_GET_ADDR_SPC_ID_IN_HANDLE_OFST 4 23303 23303 - #define MC_CMD_GET_ADDR_SPC_ID_IN_HANDLE_LEN 4 23304 23304 - 23305 23305 - /* MC_CMD_GET_ADDR_SPC_ID_OUT msgresponse */ 23306 23306 - #define MC_CMD_GET_ADDR_SPC_ID_OUT_LEN 8 23307 23307 - /* Address Space ID for the requested target. Only the lower 36 bits are valid 23308 23308 - * in the current SmartNIC implementation. 23309 23309 - */ 23310 23310 - #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_OFST 0 23311 23311 - #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LEN 8 23312 23312 - #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_OFST 0 23313 23313 - #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_LEN 4 23314 23314 - #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_LBN 0 23315 23315 - #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_WIDTH 32 23316 23316 - #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_OFST 4 23317 23317 - #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_LEN 4 23318 23318 - #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_LBN 32 23319 23319 - #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_WIDTH 32 23320 23320 - 23321 25477 23322 25478 /***********************************/ 23323 25479 /* MC_CMD_GET_CLIENT_HANDLE ··· 22483 26359 * INTF=CALLER, PF=PF_NULL, VF=... to refer to a VF child of the calling PF or 22484 26360 * a sibling VF of the calling VF. - INTF=CALLER, PF=..., VF=VF_NULL to refer 22485 26361 * to a PF on the calling interface - INTF=CALLER, PF=..., VF=... to refer to a 22486 22486 - * VF on the calling interface - INTF=..., PF=..., VF=VF_NULL to refer to a PF 26362 26362 + * VF on the calling interface - INTF=..., PF=PF_NULL, VF=VF_NULL to refer to 26363 26363 + * the named interface itself - INTF=..., PF=..., VF=VF_NULL to refer to a PF 22487 26364 * on a named interface - INTF=..., PF=..., VF=... to refer to a VF on a named 22488 26365 * interface where ... refers to a small integer for the VF/PF fields, and to 22489 26366 * values from the PCIE_INTERFACE enum for for the INTF field. It's only ··· 22505 26380 * backwards compatibility only, callers should use PCIE_INTERFACE_CALLER. 22506 26381 */ 22507 26382 #define MC_CMD_GET_CLIENT_HANDLE_IN_PCIE_FUNCTION_INTF_NULL 0xffffffff 26383 26383 + /* See structuredef: PCIE_FUNCTION */ 22508 26384 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_PF_OFST 4 22509 26385 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_PF_LEN 2 22510 26386 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_VF_OFST 6 ··· 23476 27350 /* MAE_MPORT_SELECTOR structuredef: MPORTS are identified by an opaque unsigned 23477 27351 * integer value (mport_id) that is guaranteed to be representable within 23478 27352 * 32-bits or within any NIC interface field that needs store the value 23479 23479 - * (whichever is narrowers). This selector structure provides a stable way to 27353 27353 + * (whichever is narrower). This selector structure provides a stable way to 23480 27354 * refer to m-ports. 23481 27355 */ 23482 27356 #define MAE_MPORT_SELECTOR_LEN 4 ··· 23551 27425 #define MAE_MPORT_SELECTOR_FLAT_WIDTH 32 23552 27426 23553 27427 /* MAE_LINK_ENDPOINT_SELECTOR structuredef: Structure that identifies a real or 23554 23554 - * virtual network port by MAE port and link end 27428 27428 + * virtual network port by MAE port and link end. Intended to be used by 27429 27429 + * network port MCDI commands. Setting FLAT to MAE_LINK_ENDPOINT_COMPAT is 27430 27430 + * equivalent to using the previous version of the command. Not all possible 27431 27431 + * combinations of MPORT_END and MPORT_SELECTOR in MAE_LINK_ENDPOINT_SELECTOR 27432 27432 + * will work in all circumstances. 1. Some will always work (e.g. a VF can 27433 27433 + * always address its logical MAC using MPORT_SELECTOR=ASSIGNED,LINK_END=VNIC), 27434 27434 + * 2. Some are not meaningful and will always fail with EINVAL (e.g. attempting 27435 27435 + * to address the VNIC end of a link to a physical port), 3. Some are 27436 27436 + * meaningful but require the MCDI client to have the required permission and 27437 27437 + * fail with EPERM otherwise (e.g. trying to set the MAC on a VF the caller 27438 27438 + * cannot administer), and 4. Some could be implementation-specific and fail 27439 27439 + * with ENOTSUP if not available (no examples exist right now). See 27440 27440 + * SF-123581-TC section 4.3 for more details. 23555 27441 */ 23556 27442 #define MAE_LINK_ENDPOINT_SELECTOR_LEN 8 23557 23557 - /* The MAE MPORT of interest */ 27443 27443 + /* Identifier for the MAE MPORT of interest */ 23558 27444 #define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_OFST 0 23559 27445 #define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LEN 4 23560 27446 #define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LBN 0 ··· 23967 27829 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM_MCDI2 253 23968 27830 /* enum: A counter ID that is guaranteed never to represent a real counter */ 23969 27831 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_NULL 0xffffffff 27832 27832 + /* Other enum values, see field(s): */ 27833 27833 + /* MAE_COUNTER_ID */ 23970 27834 23971 27835 23972 27836 /***********************************/ ··· 24406 28266 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_OFST 0 24407 28267 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_LBN 14 24408 28268 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1 28269 28269 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_C_PL_OFST 0 28270 28270 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_C_PL_LBN 15 28271 28271 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_C_PL_WIDTH 1 28272 28272 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_D_PL_OFST 0 28273 28273 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_D_PL_LBN 16 28274 28274 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_D_PL_WIDTH 1 28275 28275 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_OFST 0 28276 28276 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_LBN 17 28277 28277 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_WIDTH 1 28278 28278 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_NET_CHAN_OFST 0 28279 28279 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_NET_CHAN_LBN 18 28280 28280 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_NET_CHAN_WIDTH 1 28281 28281 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_LACP_PLUGIN_OFST 0 28282 28282 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_LACP_PLUGIN_LBN 19 28283 28283 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_LACP_PLUGIN_WIDTH 1 28284 28284 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_LACP_INC_L4_OFST 0 28285 28285 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_LACP_INC_L4_LBN 20 28286 28286 + #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_LACP_INC_L4_WIDTH 1 24409 28287 /* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */ 24410 28288 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_OFST 4 24411 28289 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_LEN 2 ··· 24449 28291 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DELIVER_OFST 20 24450 28292 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DELIVER_LEN 4 24451 28293 /* Allows an action set to trigger several counter updates. Set to 24452 24452 - * COUNTER_LIST_ID_NULL to request no counter action. 28294 28294 + * MAE_COUNTER_ID_NULL to request no counter action. 24453 28295 */ 24454 28296 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID_OFST 24 24455 28297 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID_LEN 4 28298 28298 + /* Enum values, see field(s): */ 28299 28299 + /* MAE_COUNTER_ID */ 24456 28300 /* If a driver only wished to update one counter within this action set, then 24457 28301 * it can supply a COUNTER_ID instead of allocating a single-element counter 24458 28302 * list. The ID must have been allocated with COUNTER_TYPE=AR. This field 24459 24459 - * should be set to COUNTER_ID_NULL if this behaviour is not required. It is 24460 24460 - * not valid to supply a non-NULL value for both COUNTER_LIST_ID and 28303 28303 + * should be set to MAE_COUNTER_ID_NULL if this behaviour is not required. It 28304 28304 + * is not valid to supply a non-NULL value for both COUNTER_LIST_ID and 24461 28305 * COUNTER_ID. 24462 28306 */ 24463 28307 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_ID_OFST 28 24464 28308 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_ID_LEN 4 28309 28309 + /* Enum values, see field(s): */ 28310 28310 + /* MAE_COUNTER_ID */ 24465 28311 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_VALUE_OFST 32 24466 28312 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_VALUE_LEN 4 24467 28313 /* Set to MAC_ID_NULL to request no source MAC replacement. */ ··· 24509 28347 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_OFST 0 24510 28348 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_LBN 14 24511 28349 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1 28350 28350 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_C_PL_OFST 0 28351 28351 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_C_PL_LBN 15 28352 28352 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_C_PL_WIDTH 1 28353 28353 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_D_PL_OFST 0 28354 28354 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_D_PL_LBN 16 28355 28355 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_D_PL_WIDTH 1 28356 28356 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_OFST 0 28357 28357 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_LBN 17 28358 28358 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_WIDTH 1 28359 28359 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_NET_CHAN_OFST 0 28360 28360 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_NET_CHAN_LBN 18 28361 28361 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_NET_CHAN_WIDTH 1 28362 28362 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LACP_PLUGIN_OFST 0 28363 28363 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LACP_PLUGIN_LBN 19 28364 28364 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LACP_PLUGIN_WIDTH 1 28365 28365 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LACP_INC_L4_OFST 0 28366 28366 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LACP_INC_L4_LBN 20 28367 28367 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LACP_INC_L4_WIDTH 1 24512 28368 /* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */ 24513 28369 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_TCI_BE_OFST 4 24514 28370 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_TCI_BE_LEN 2 ··· 24552 28372 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DELIVER_OFST 20 24553 28373 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DELIVER_LEN 4 24554 28374 /* Allows an action set to trigger several counter updates. Set to 24555 24555 - * COUNTER_LIST_ID_NULL to request no counter action. 28375 28375 + * MAE_COUNTER_ID_NULL to request no counter action. 24556 28376 */ 24557 28377 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_LIST_ID_OFST 24 24558 28378 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_LIST_ID_LEN 4 28379 28379 + /* Enum values, see field(s): */ 28380 28380 + /* MAE_COUNTER_ID */ 24559 28381 /* If a driver only wished to update one counter within this action set, then 24560 28382 * it can supply a COUNTER_ID instead of allocating a single-element counter 24561 28383 * list. The ID must have been allocated with COUNTER_TYPE=AR. This field 24562 24562 - * should be set to COUNTER_ID_NULL if this behaviour is not required. It is 24563 24563 - * not valid to supply a non-NULL value for both COUNTER_LIST_ID and 28384 28384 + * should be set to MAE_COUNTER_ID_NULL if this behaviour is not required. It 28385 28385 + * is not valid to supply a non-NULL value for both COUNTER_LIST_ID and 24564 28386 * COUNTER_ID. 24565 28387 */ 24566 28388 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_ID_OFST 28 24567 28389 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_ID_LEN 4 28390 28390 + /* Enum values, see field(s): */ 28391 28391 + /* MAE_COUNTER_ID */ 24568 28392 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_VALUE_OFST 32 24569 28393 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_VALUE_LEN 4 24570 28394 /* Set to MAC_ID_NULL to request no source MAC replacement. */ ··· 24620 28436 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_OFST 50 24621 28437 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_LBN 6 24622 28438 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_WIDTH 1 28439 28439 + 28440 28440 + /* MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN msgrequest: Only supported if 28441 28441 + * MAE_ACTION_SET_ALLOC_V3_SUPPORTED is advertised in 28442 28442 + * MC_CMD_GET_CAPABILITIES_V10_OUT. 28443 28443 + */ 28444 28444 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_LEN 53 28445 28445 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_FLAGS_OFST 0 28446 28446 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_FLAGS_LEN 4 28447 28447 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN_PUSH_OFST 0 28448 28448 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN_PUSH_LBN 0 28449 28449 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN_PUSH_WIDTH 2 28450 28450 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN_POP_OFST 0 28451 28451 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN_POP_LBN 4 28452 28452 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN_POP_WIDTH 2 28453 28453 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DECAP_OFST 0 28454 28454 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DECAP_LBN 8 28455 28455 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DECAP_WIDTH 1 28456 28456 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_MARK_OFST 0 28457 28457 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_MARK_LBN 9 28458 28458 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_MARK_WIDTH 1 28459 28459 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_FLAG_OFST 0 28460 28460 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_FLAG_LBN 10 28461 28461 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_FLAG_WIDTH 1 28462 28462 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_NAT_OFST 0 28463 28463 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_NAT_LBN 11 28464 28464 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_NAT_WIDTH 1 28465 28465 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DECR_IP_TTL_OFST 0 28466 28466 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DECR_IP_TTL_LBN 12 28467 28467 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DECR_IP_TTL_WIDTH 1 28468 28468 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_SET_SRC_MPORT_OFST 0 28469 28469 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_SET_SRC_MPORT_LBN 13 28470 28470 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_SET_SRC_MPORT_WIDTH 1 28471 28471 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_SUPPRESS_SELF_DELIVERY_OFST 0 28472 28472 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_SUPPRESS_SELF_DELIVERY_LBN 14 28473 28473 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1 28474 28474 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_C_PL_OFST 0 28475 28475 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_C_PL_LBN 15 28476 28476 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_C_PL_WIDTH 1 28477 28477 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_D_PL_OFST 0 28478 28478 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_D_PL_LBN 16 28479 28479 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_D_PL_WIDTH 1 28480 28480 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_OFST 0 28481 28481 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_LBN 17 28482 28482 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_WIDTH 1 28483 28483 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_SET_NET_CHAN_OFST 0 28484 28484 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_SET_NET_CHAN_LBN 18 28485 28485 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_SET_NET_CHAN_WIDTH 1 28486 28486 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_LACP_PLUGIN_OFST 0 28487 28487 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_LACP_PLUGIN_LBN 19 28488 28488 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_LACP_PLUGIN_WIDTH 1 28489 28489 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_LACP_INC_L4_OFST 0 28490 28490 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_LACP_INC_L4_LBN 20 28491 28491 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_LACP_INC_L4_WIDTH 1 28492 28492 + /* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */ 28493 28493 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN0_TCI_BE_OFST 4 28494 28494 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN0_TCI_BE_LEN 2 28495 28495 + /* If VLAN_PUSH >= 1, TPID value to be inserted as outermost VLAN. */ 28496 28496 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN0_PROTO_BE_OFST 6 28497 28497 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN0_PROTO_BE_LEN 2 28498 28498 + /* If VLAN_PUSH == 2, inner TCI value to be inserted. */ 28499 28499 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN1_TCI_BE_OFST 8 28500 28500 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN1_TCI_BE_LEN 2 28501 28501 + /* If VLAN_PUSH == 2, inner TPID value to be inserted. */ 28502 28502 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN1_PROTO_BE_OFST 10 28503 28503 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN1_PROTO_BE_LEN 2 28504 28504 + /* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */ 28505 28505 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RSVD_OFST 12 28506 28506 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RSVD_LEN 4 28507 28507 + /* Set to ENCAP_HEADER_ID_NULL to request no encap action */ 28508 28508 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ENCAP_HEADER_ID_OFST 16 28509 28509 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ENCAP_HEADER_ID_LEN 4 28510 28510 + /* An m-port selector identifying the m-port that the modified packet should be 28511 28511 + * delivered to. Set to MPORT_SELECTOR_NULL to request no delivery of the 28512 28512 + * packet. 28513 28513 + */ 28514 28514 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DELIVER_OFST 20 28515 28515 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DELIVER_LEN 4 28516 28516 + /* Allows an action set to trigger several counter updates. Set to 28517 28517 + * MAE_COUNTER_ID_NULL to request no counter action. 28518 28518 + */ 28519 28519 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_COUNTER_LIST_ID_OFST 24 28520 28520 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_COUNTER_LIST_ID_LEN 4 28521 28521 + /* Enum values, see field(s): */ 28522 28522 + /* MAE_COUNTER_ID */ 28523 28523 + /* If a driver only wished to update one counter within this action set, then 28524 28524 + * it can supply a COUNTER_ID instead of allocating a single-element counter 28525 28525 + * list. The ID must have been allocated with COUNTER_TYPE=AR. This field 28526 28526 + * should be set to MAE_COUNTER_ID_NULL if this behaviour is not required. It 28527 28527 + * is not valid to supply a non-NULL value for both COUNTER_LIST_ID and 28528 28528 + * COUNTER_ID. 28529 28529 + */ 28530 28530 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_COUNTER_ID_OFST 28 28531 28531 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_COUNTER_ID_LEN 4 28532 28532 + /* Enum values, see field(s): */ 28533 28533 + /* MAE_COUNTER_ID */ 28534 28534 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_MARK_VALUE_OFST 32 28535 28535 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_MARK_VALUE_LEN 4 28536 28536 + /* Set to MAC_ID_NULL to request no source MAC replacement. */ 28537 28537 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_SRC_MAC_ID_OFST 36 28538 28538 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_SRC_MAC_ID_LEN 4 28539 28539 + /* Set to MAC_ID_NULL to request no destination MAC replacement. */ 28540 28540 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DST_MAC_ID_OFST 40 28541 28541 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DST_MAC_ID_LEN 4 28542 28542 + /* Source m-port ID to be reported for DO_SET_SRC_MPORT action. */ 28543 28543 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_REPORTED_SRC_MPORT_OFST 44 28544 28544 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_REPORTED_SRC_MPORT_LEN 4 28545 28545 + /* Actions for modifying the Differentiated Services Code-Point (DSCP) bits 28546 28546 + * within IPv4 and IPv6 headers. 28547 28547 + */ 28548 28548 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DSCP_CONTROL_OFST 48 28549 28549 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DSCP_CONTROL_LEN 2 28550 28550 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DSCP_ENCAP_COPY_OFST 48 28551 28551 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DSCP_ENCAP_COPY_LBN 0 28552 28552 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DSCP_ENCAP_COPY_WIDTH 1 28553 28553 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DSCP_DECAP_COPY_OFST 48 28554 28554 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DSCP_DECAP_COPY_LBN 1 28555 28555 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DSCP_DECAP_COPY_WIDTH 1 28556 28556 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_DSCP_OFST 48 28557 28557 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_DSCP_LBN 2 28558 28558 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_DSCP_WIDTH 1 28559 28559 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DSCP_VALUE_OFST 48 28560 28560 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DSCP_VALUE_LBN 3 28561 28561 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DSCP_VALUE_WIDTH 6 28562 28562 + /* Actions for modifying the Explicit Congestion Notification (ECN) bits within 28563 28563 + * IPv4 and IPv6 headers. 28564 28564 + */ 28565 28565 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_CONTROL_OFST 50 28566 28566 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_CONTROL_LEN 1 28567 28567 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_ECN_ENCAP_COPY_OFST 50 28568 28568 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_ECN_ENCAP_COPY_LBN 0 28569 28569 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_ECN_ENCAP_COPY_WIDTH 1 28570 28570 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_ECN_DECAP_COPY_OFST 50 28571 28571 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_ECN_DECAP_COPY_LBN 1 28572 28572 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_ECN_DECAP_COPY_WIDTH 1 28573 28573 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_ECN_OFST 50 28574 28574 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_ECN_LBN 2 28575 28575 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_ECN_WIDTH 1 28576 28576 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_VALUE_OFST 50 28577 28577 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_VALUE_LBN 3 28578 28578 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_VALUE_WIDTH 2 28579 28579 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_ECT_0_TO_CE_OFST 50 28580 28580 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_ECT_0_TO_CE_LBN 5 28581 28581 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_ECT_0_TO_CE_WIDTH 1 28582 28582 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_ECT_1_TO_CE_OFST 50 28583 28583 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_ECT_1_TO_CE_LBN 6 28584 28584 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_ECT_1_TO_CE_WIDTH 1 28585 28585 + /* Actions for overwriting CH_ROUTE subfields. */ 28586 28586 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_OVERWRITE_OFST 51 28587 28587 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_OVERWRITE_LEN 1 28588 28588 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_C_PL_OFST 51 28589 28589 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_C_PL_LBN 0 28590 28590 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_C_PL_WIDTH 1 28591 28591 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_D_PL_OFST 51 28592 28592 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_D_PL_LBN 1 28593 28593 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_D_PL_WIDTH 1 28594 28594 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_PL_CHAN_OFST 51 28595 28595 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_PL_CHAN_LBN 2 28596 28596 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_PL_CHAN_WIDTH 1 28597 28597 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_OUT_HOST_CHAN_OFST 51 28598 28598 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_OUT_HOST_CHAN_LBN 3 28599 28599 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_OUT_HOST_CHAN_WIDTH 1 28600 28600 + /* Override outgoing CH_VC to network port for DO_SET_NET_CHAN action. Cannot 28601 28601 + * be used in conjunction with DO_SET_SRC_MPORT action. 28602 28602 + */ 28603 28603 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_NET_CHAN_OFST 52 28604 28604 + #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_NET_CHAN_LEN 1 24623 28605 24624 28606 /* MC_CMD_MAE_ACTION_SET_ALLOC_OUT msgresponse */ 24625 28607 #define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN 4 ··· 25029 28679 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_MINNUM 1 25030 28680 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_MAXNUM 32 25031 28681 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_MAXNUM_MCDI2 32 25032 25032 - 25033 25033 - 25034 25034 - /***********************************/ 25035 25035 - /* MC_CMD_MAE_OUTER_RULE_UPDATE 25036 25036 - * Atomically change the response of an Outer Rule. 25037 25037 - */ 25038 25038 - #define MC_CMD_MAE_OUTER_RULE_UPDATE 0x17d 25039 25039 - #undef MC_CMD_0x17d_PRIVILEGE_CTG 25040 25040 - 25041 25041 - #define MC_CMD_0x17d_PRIVILEGE_CTG SRIOV_CTG_MAE 25042 25042 - 25043 25043 - /* MC_CMD_MAE_OUTER_RULE_UPDATE_IN msgrequest */ 25044 25044 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_LEN 16 25045 25045 - /* ID of outer rule to update */ 25046 25046 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_OR_ID_OFST 0 25047 25047 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_OR_ID_LEN 4 25048 25048 - /* Packets matching the rule will be parsed with this encapsulation. */ 25049 25049 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_ENCAP_TYPE_OFST 4 25050 25050 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_ENCAP_TYPE_LEN 4 25051 25051 - /* Enum values, see field(s): */ 25052 25052 - /* MAE_MCDI_ENCAP_TYPE */ 25053 25053 - /* This field controls the actions that are performed when a rule is hit. */ 25054 25054 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_ACTION_CONTROL_OFST 8 25055 25055 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_ACTION_CONTROL_LEN 4 25056 25056 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_DO_CT_OFST 8 25057 25057 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_DO_CT_LBN 0 25058 25058 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_DO_CT_WIDTH 1 25059 25059 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_VNI_MODE_OFST 8 25060 25060 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_VNI_MODE_LBN 1 25061 25061 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_VNI_MODE_WIDTH 2 25062 25062 - /* Enum values, see field(s): */ 25063 25063 - /* MAE_CT_VNI_MODE */ 25064 25064 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_DO_COUNT_OFST 8 25065 25065 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_DO_COUNT_LBN 3 25066 25066 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_DO_COUNT_WIDTH 1 25067 25067 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_TCP_FLAGS_INHIBIT_OFST 8 25068 25068 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_TCP_FLAGS_INHIBIT_LBN 4 25069 25069 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_TCP_FLAGS_INHIBIT_WIDTH 1 25070 25070 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_RECIRC_ID_OFST 8 25071 25071 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_RECIRC_ID_LBN 8 25072 25072 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_RECIRC_ID_WIDTH 8 25073 25073 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_DOMAIN_OFST 8 25074 25074 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_DOMAIN_LBN 16 25075 25075 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_DOMAIN_WIDTH 16 25076 25076 - /* ID of counter to increment when the rule is hit. Only used if the DO_COUNT 25077 25077 - * flag is set. The ID must have been allocated with COUNTER_TYPE=OR. 25078 25078 - */ 25079 25079 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_COUNTER_ID_OFST 12 25080 25080 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_COUNTER_ID_LEN 4 25081 25081 - 25082 25082 - /* MC_CMD_MAE_OUTER_RULE_UPDATE_OUT msgresponse */ 25083 25083 - #define MC_CMD_MAE_OUTER_RULE_UPDATE_OUT_LEN 0 25084 28682 25085 28683 /* MAE_ACTION_RULE_RESPONSE structuredef */ 25086 28684 #define MAE_ACTION_RULE_RESPONSE_LEN 16 ··· 25420 29122 #define MAE_MPORT_DESC_VNIC_PLUGIN_TBD_LBN 352 25421 29123 #define MAE_MPORT_DESC_VNIC_PLUGIN_TBD_WIDTH 32 25422 29124 25423 25423 - /* MAE_MPORT_DESC_V2 structuredef */ 25424 25424 - #define MAE_MPORT_DESC_V2_LEN 56 25425 25425 - #define MAE_MPORT_DESC_V2_MPORT_ID_OFST 0 25426 25426 - #define MAE_MPORT_DESC_V2_MPORT_ID_LEN 4 25427 25427 - #define MAE_MPORT_DESC_V2_MPORT_ID_LBN 0 25428 25428 - #define MAE_MPORT_DESC_V2_MPORT_ID_WIDTH 32 25429 25429 - /* Reserved for future purposes, contains information independent of caller */ 25430 25430 - #define MAE_MPORT_DESC_V2_FLAGS_OFST 4 25431 25431 - #define MAE_MPORT_DESC_V2_FLAGS_LEN 4 25432 25432 - #define MAE_MPORT_DESC_V2_FLAGS_LBN 32 25433 25433 - #define MAE_MPORT_DESC_V2_FLAGS_WIDTH 32 25434 25434 - #define MAE_MPORT_DESC_V2_CALLER_FLAGS_OFST 8 25435 25435 - #define MAE_MPORT_DESC_V2_CALLER_FLAGS_LEN 4 25436 25436 - #define MAE_MPORT_DESC_V2_CAN_RECEIVE_ON_OFST 8 25437 25437 - #define MAE_MPORT_DESC_V2_CAN_RECEIVE_ON_LBN 0 25438 25438 - #define MAE_MPORT_DESC_V2_CAN_RECEIVE_ON_WIDTH 1 25439 25439 - #define MAE_MPORT_DESC_V2_CAN_DELIVER_TO_OFST 8 25440 25440 - #define MAE_MPORT_DESC_V2_CAN_DELIVER_TO_LBN 1 25441 25441 - #define MAE_MPORT_DESC_V2_CAN_DELIVER_TO_WIDTH 1 25442 25442 - #define MAE_MPORT_DESC_V2_CAN_DELETE_OFST 8 25443 25443 - #define MAE_MPORT_DESC_V2_CAN_DELETE_LBN 2 25444 25444 - #define MAE_MPORT_DESC_V2_CAN_DELETE_WIDTH 1 25445 25445 - #define MAE_MPORT_DESC_V2_IS_ZOMBIE_OFST 8 25446 25446 - #define MAE_MPORT_DESC_V2_IS_ZOMBIE_LBN 3 25447 25447 - #define MAE_MPORT_DESC_V2_IS_ZOMBIE_WIDTH 1 25448 25448 - #define MAE_MPORT_DESC_V2_CALLER_FLAGS_LBN 64 25449 25449 - #define MAE_MPORT_DESC_V2_CALLER_FLAGS_WIDTH 32 25450 25450 - /* Not the ideal name; it's really the type of thing connected to the m-port */ 25451 25451 - #define MAE_MPORT_DESC_V2_MPORT_TYPE_OFST 12 25452 25452 - #define MAE_MPORT_DESC_V2_MPORT_TYPE_LEN 4 25453 25453 - /* enum: Connected to a MAC... */ 25454 25454 - #define MAE_MPORT_DESC_V2_MPORT_TYPE_NET_PORT 0x0 25455 25455 - /* enum: Adds metadata and delivers to another m-port */ 25456 25456 - #define MAE_MPORT_DESC_V2_MPORT_TYPE_ALIAS 0x1 25457 25457 - /* enum: Connected to a VNIC. */ 25458 25458 - #define MAE_MPORT_DESC_V2_MPORT_TYPE_VNIC 0x2 25459 25459 - #define MAE_MPORT_DESC_V2_MPORT_TYPE_LBN 96 25460 25460 - #define MAE_MPORT_DESC_V2_MPORT_TYPE_WIDTH 32 25461 25461 - /* 128-bit value available to drivers for m-port identification. */ 25462 25462 - #define MAE_MPORT_DESC_V2_UUID_OFST 16 25463 25463 - #define MAE_MPORT_DESC_V2_UUID_LEN 16 25464 25464 - #define MAE_MPORT_DESC_V2_UUID_LBN 128 25465 25465 - #define MAE_MPORT_DESC_V2_UUID_WIDTH 128 25466 25466 - /* Big wadge of space reserved for other common properties */ 25467 25467 - #define MAE_MPORT_DESC_V2_RESERVED_OFST 32 25468 25468 - #define MAE_MPORT_DESC_V2_RESERVED_LEN 8 25469 25469 - #define MAE_MPORT_DESC_V2_RESERVED_LO_OFST 32 25470 25470 - #define MAE_MPORT_DESC_V2_RESERVED_LO_LEN 4 25471 25471 - #define MAE_MPORT_DESC_V2_RESERVED_LO_LBN 256 25472 25472 - #define MAE_MPORT_DESC_V2_RESERVED_LO_WIDTH 32 25473 25473 - #define MAE_MPORT_DESC_V2_RESERVED_HI_OFST 36 25474 25474 - #define MAE_MPORT_DESC_V2_RESERVED_HI_LEN 4 25475 25475 - #define MAE_MPORT_DESC_V2_RESERVED_HI_LBN 288 25476 25476 - #define MAE_MPORT_DESC_V2_RESERVED_HI_WIDTH 32 25477 25477 - #define MAE_MPORT_DESC_V2_RESERVED_LBN 256 25478 25478 - #define MAE_MPORT_DESC_V2_RESERVED_WIDTH 64 25479 25479 - /* Logical port index. Only valid when type NET Port. */ 25480 25480 - #define MAE_MPORT_DESC_V2_NET_PORT_IDX_OFST 40 25481 25481 - #define MAE_MPORT_DESC_V2_NET_PORT_IDX_LEN 4 25482 25482 - #define MAE_MPORT_DESC_V2_NET_PORT_IDX_LBN 320 25483 25483 - #define MAE_MPORT_DESC_V2_NET_PORT_IDX_WIDTH 32 25484 25484 - /* The m-port delivered to */ 25485 25485 - #define MAE_MPORT_DESC_V2_ALIAS_DELIVER_MPORT_ID_OFST 40 25486 25486 - #define MAE_MPORT_DESC_V2_ALIAS_DELIVER_MPORT_ID_LEN 4 25487 25487 - #define MAE_MPORT_DESC_V2_ALIAS_DELIVER_MPORT_ID_LBN 320 25488 25488 - #define MAE_MPORT_DESC_V2_ALIAS_DELIVER_MPORT_ID_WIDTH 32 25489 25489 - /* The type of thing that owns the VNIC */ 25490 25490 - #define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_OFST 40 25491 25491 - #define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_LEN 4 25492 25492 - #define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_FUNCTION 0x1 /* enum */ 25493 25493 - #define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_PLUGIN 0x2 /* enum */ 25494 25494 - #define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_LBN 320 25495 25495 - #define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_WIDTH 32 25496 25496 - /* The PCIe interface on which the function lives. CJK: We need an enumeration 25497 25497 - * of interfaces that we extend as new interface (types) appear. This belongs 25498 25498 - * elsewhere and should be referenced from here 25499 25499 - */ 25500 25500 - #define MAE_MPORT_DESC_V2_VNIC_FUNCTION_INTERFACE_OFST 44 25501 25501 - #define MAE_MPORT_DESC_V2_VNIC_FUNCTION_INTERFACE_LEN 4 25502 25502 - #define MAE_MPORT_DESC_V2_VNIC_FUNCTION_INTERFACE_LBN 352 25503 25503 - #define MAE_MPORT_DESC_V2_VNIC_FUNCTION_INTERFACE_WIDTH 32 25504 25504 - #define MAE_MPORT_DESC_V2_VNIC_FUNCTION_PF_IDX_OFST 48 25505 25505 - #define MAE_MPORT_DESC_V2_VNIC_FUNCTION_PF_IDX_LEN 2 25506 25506 - #define MAE_MPORT_DESC_V2_VNIC_FUNCTION_PF_IDX_LBN 384 25507 25507 - #define MAE_MPORT_DESC_V2_VNIC_FUNCTION_PF_IDX_WIDTH 16 25508 25508 - #define MAE_MPORT_DESC_V2_VNIC_FUNCTION_VF_IDX_OFST 50 25509 25509 - #define MAE_MPORT_DESC_V2_VNIC_FUNCTION_VF_IDX_LEN 2 25510 25510 - /* enum: Indicates that the function is a PF */ 25511 25511 - #define MAE_MPORT_DESC_V2_VF_IDX_NULL 0xffff 25512 25512 - #define MAE_MPORT_DESC_V2_VNIC_FUNCTION_VF_IDX_LBN 400 25513 25513 - #define MAE_MPORT_DESC_V2_VNIC_FUNCTION_VF_IDX_WIDTH 16 25514 25514 - /* Reserved. Should be ignored for now. */ 25515 25515 - #define MAE_MPORT_DESC_V2_VNIC_PLUGIN_TBD_OFST 44 25516 25516 - #define MAE_MPORT_DESC_V2_VNIC_PLUGIN_TBD_LEN 4 25517 25517 - #define MAE_MPORT_DESC_V2_VNIC_PLUGIN_TBD_LBN 352 25518 25518 - #define MAE_MPORT_DESC_V2_VNIC_PLUGIN_TBD_WIDTH 32 25519 25519 - /* A client handle for the VNIC's owner. Only valid for type VNIC. */ 25520 25520 - #define MAE_MPORT_DESC_V2_VNIC_CLIENT_HANDLE_OFST 52 25521 25521 - #define MAE_MPORT_DESC_V2_VNIC_CLIENT_HANDLE_LEN 4 25522 25522 - #define MAE_MPORT_DESC_V2_VNIC_CLIENT_HANDLE_LBN 416 25523 25523 - #define MAE_MPORT_DESC_V2_VNIC_CLIENT_HANDLE_WIDTH 32 25524 25524 - 25525 25525 - 25526 25526 - /***********************************/ 25527 25527 - /* MC_CMD_MAE_MPORT_ENUMERATE 25528 25528 - * Deprecated in favour of MAE_MPORT_READ_JOURNAL. Support for this command 25529 25529 - * will be removed at some future point. 25530 25530 - */ 25531 25531 - #define MC_CMD_MAE_MPORT_ENUMERATE 0x17c 25532 25532 - #undef MC_CMD_0x17c_PRIVILEGE_CTG 25533 25533 - 25534 25534 - #define MC_CMD_0x17c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 25535 25535 - 25536 25536 - /* MC_CMD_MAE_MPORT_ENUMERATE_IN msgrequest */ 25537 25537 - #define MC_CMD_MAE_MPORT_ENUMERATE_IN_LEN 0 25538 25538 - 25539 25539 - /* MC_CMD_MAE_MPORT_ENUMERATE_OUT msgresponse */ 25540 25540 - #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_LENMIN 8 25541 25541 - #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_LENMAX 252 25542 25542 - #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_LENMAX_MCDI2 1020 25543 25543 - #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_LEN(num) (8+1*(num)) 25544 25544 - #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_NUM(len) (((len)-8)/1) 25545 25545 - #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_COUNT_OFST 0 25546 25546 - #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_COUNT_LEN 4 25547 25547 - #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_SIZEOF_MPORT_DESC_OFST 4 25548 25548 - #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_SIZEOF_MPORT_DESC_LEN 4 25549 25549 - /* Any array of MAE_MPORT_DESC structures. The MAE_MPORT_DESC structure may 25550 25550 - * grow in future version of this command. Drivers should use a stride of 25551 25551 - * SIZEOF_MPORT_DESC. Fields beyond SIZEOF_MPORT_DESC are not present. 25552 25552 - */ 25553 25553 - #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_OFST 8 25554 25554 - #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_LEN 1 25555 25555 - #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MINNUM 0 25556 25556 - #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MAXNUM 244 25557 25557 - #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MAXNUM_MCDI2 1012 25558 25558 - 25559 29125 25560 29126 /***********************************/ 25561 29127 /* MC_CMD_MAE_MPORT_READ_JOURNAL ··· 25732 29570 25733 29571 25734 29572 /***********************************/ 25735 25735 - /* MC_CMD_TABLE_UPDATE 25736 25736 - * Update an existing entry in a table with a new response value. May return 25737 25737 - * EINVAL for unknown table ID or other bad request parameters, ENOENT if the 25738 25738 - * entry does not already exist, or EPERM if the operation is not permitted. In 25739 25739 - * case of an error, the additional MCDI error argument field returns the raw 25740 25740 - * error code from the underlying CAM driver. 25741 25741 - */ 25742 25742 - #define MC_CMD_TABLE_UPDATE 0x1ce 25743 25743 - #undef MC_CMD_0x1ce_PRIVILEGE_CTG 25744 25744 - 25745 25745 - #define MC_CMD_0x1ce_PRIVILEGE_CTG SRIOV_CTG_GENERAL 25746 25746 - 25747 25747 - /* MC_CMD_TABLE_UPDATE_IN msgrequest */ 25748 25748 - #define MC_CMD_TABLE_UPDATE_IN_LENMIN 16 25749 25749 - #define MC_CMD_TABLE_UPDATE_IN_LENMAX 252 25750 25750 - #define MC_CMD_TABLE_UPDATE_IN_LENMAX_MCDI2 1020 25751 25751 - #define MC_CMD_TABLE_UPDATE_IN_LEN(num) (12+4*(num)) 25752 25752 - #define MC_CMD_TABLE_UPDATE_IN_DATA_NUM(len) (((len)-12)/4) 25753 25753 - /* Table identifier. */ 25754 25754 - #define MC_CMD_TABLE_UPDATE_IN_TABLE_ID_OFST 0 25755 25755 - #define MC_CMD_TABLE_UPDATE_IN_TABLE_ID_LEN 4 25756 25756 - /* Enum values, see field(s): */ 25757 25757 - /* TABLE_ID */ 25758 25758 - /* Width in bits of supplied key data (must match table properties). */ 25759 25759 - #define MC_CMD_TABLE_UPDATE_IN_KEY_WIDTH_OFST 4 25760 25760 - #define MC_CMD_TABLE_UPDATE_IN_KEY_WIDTH_LEN 2 25761 25761 - /* Width in bits of supplied mask data (0 for direct/BCAM tables, or for STCAM 25762 25762 - * when allocated MASK_ID is used instead). 25763 25763 - */ 25764 25764 - #define MC_CMD_TABLE_UPDATE_IN_MASK_WIDTH_OFST 6 25765 25765 - #define MC_CMD_TABLE_UPDATE_IN_MASK_WIDTH_LEN 2 25766 25766 - /* Width in bits of supplied response data (for INSERT and UPDATE operations 25767 25767 - * this must match the table properties; for DELETE operations, no response 25768 25768 - * data is required and this must be 0). 25769 25769 - */ 25770 25770 - #define MC_CMD_TABLE_UPDATE_IN_RESP_WIDTH_OFST 8 25771 25771 - #define MC_CMD_TABLE_UPDATE_IN_RESP_WIDTH_LEN 2 25772 25772 - /* Mask ID for STCAM table - used instead of mask data if the table descriptor 25773 25773 - * reports ALLOC_MASKS==1. Otherwise set to 0. 25774 25774 - */ 25775 25775 - #define MC_CMD_TABLE_UPDATE_IN_MASK_ID_OFST 6 25776 25776 - #define MC_CMD_TABLE_UPDATE_IN_MASK_ID_LEN 2 25777 25777 - /* Priority for TCAM or STCAM, in range 0..N_PRIORITIES-1, otherwise 0. */ 25778 25778 - #define MC_CMD_TABLE_UPDATE_IN_PRIORITY_OFST 8 25779 25779 - #define MC_CMD_TABLE_UPDATE_IN_PRIORITY_LEN 2 25780 25780 - /* (32-bit alignment padding - set to 0) */ 25781 25781 - #define MC_CMD_TABLE_UPDATE_IN_RESERVED_OFST 10 25782 25782 - #define MC_CMD_TABLE_UPDATE_IN_RESERVED_LEN 2 25783 25783 - /* Sequence of key, mask (if MASK_WIDTH > 0), and response (if RESP_WIDTH > 0) 25784 25784 - * data values. Each of these items is logically treated as a single wide N-bit 25785 25785 - * value, in which the individual fields have been placed within that value per 25786 25786 - * the LBN and WIDTH information from the table field descriptors. The wide 25787 25787 - * N-bit value is padded with 0 bits at the MSB end if necessary to make a 25788 25788 - * multiple of 32 bits. The value is then packed into this command as a 25789 25789 - * sequence of 32-bit words, bits [31:0] first, then bits [63:32], etc. 25790 25790 - */ 25791 25791 - #define MC_CMD_TABLE_UPDATE_IN_DATA_OFST 12 25792 25792 - #define MC_CMD_TABLE_UPDATE_IN_DATA_LEN 4 25793 25793 - #define MC_CMD_TABLE_UPDATE_IN_DATA_MINNUM 1 25794 25794 - #define MC_CMD_TABLE_UPDATE_IN_DATA_MAXNUM 60 25795 25795 - #define MC_CMD_TABLE_UPDATE_IN_DATA_MAXNUM_MCDI2 252 25796 25796 - 25797 25797 - /* MC_CMD_TABLE_UPDATE_OUT msgresponse */ 25798 25798 - #define MC_CMD_TABLE_UPDATE_OUT_LEN 0 25799 25799 - 25800 25800 - 25801 25801 - /***********************************/ 25802 29573 /* MC_CMD_TABLE_DELETE 25803 29574 * Delete an existing entry in a table. May return EINVAL for unknown table ID 25804 29575 * or other bad request parameters, ENOENT if the entry does not exist, or ··· 25796 29701 25797 29702 /* MC_CMD_TABLE_DELETE_OUT msgresponse */ 25798 29703 #define MC_CMD_TABLE_DELETE_OUT_LEN 0 29704 29704 + 29705 29705 + /* MC_CMD_QUEUE_HANDLE structuredef: On X4, to distinguish between full- 29706 29706 + * featured (X2-style) VIs and low-latency (X3-style) queues, we use the top 29707 29707 + * bits of the queue handle to specify the queue type in all MCDI calls which 29708 29708 + * refer to VIs/queues. These bits should be masked off when indexing into a 29709 29709 + * queue in the BAR. 29710 29710 + */ 29711 29711 + #define MC_CMD_QUEUE_HANDLE_LEN 4 29712 29712 + /* Combined queue number and type. This is the ID returned by and passed into 29713 29713 + * MCDI calls that use queues. 29714 29714 + */ 29715 29715 + #define MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_OFST 0 29716 29716 + #define MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_LEN 4 29717 29717 + #define MC_CMD_QUEUE_HANDLE_QUEUE_NUM_OFST 0 29718 29718 + #define MC_CMD_QUEUE_HANDLE_QUEUE_NUM_LBN 0 29719 29719 + #define MC_CMD_QUEUE_HANDLE_QUEUE_NUM_WIDTH 24 29720 29720 + #define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_OFST 0 29721 29721 + #define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LBN 24 29722 29722 + #define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_WIDTH 8 29723 29723 + /* enum: Indicates that the queue instance is a full-featured VI */ 29724 29724 + #define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_FF_VI 0x0 29725 29725 + /* enum: Indicates that the queue instance is a LL TXQ */ 29726 29726 + #define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LL_TXQ 0x1 29727 29727 + /* enum: Indicates that the queue instance is a LL RXQ */ 29728 29728 + #define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LL_RXQ 0x2 29729 29729 + /* enum: Indicates that the queue instance is a LL EVQ */ 29730 29730 + #define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LL_EVQ 0x3 29731 29731 + #define MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_LBN 0 29732 29732 + #define MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_WIDTH 32 29733 29733 + 29734 29734 + 29735 29735 + /***********************************/ 29736 29736 + /* MC_CMD_ALLOC_LL_QUEUES 29737 29737 + * Allocate low latency (X3-style) queues for current PCI function. Can be 29738 29738 + * called more than once if desired to allocate more queues. 29739 29739 + */ 29740 29740 + #define MC_CMD_ALLOC_LL_QUEUES 0x1dd 29741 29741 + #undef MC_CMD_0x1dd_PRIVILEGE_CTG 29742 29742 + 29743 29743 + #define MC_CMD_0x1dd_PRIVILEGE_CTG SRIOV_CTG_GENERAL 29744 29744 + 29745 29745 + /* MC_CMD_ALLOC_LL_QUEUES_IN msgrequest */ 29746 29746 + #define MC_CMD_ALLOC_LL_QUEUES_IN_LEN 24 29747 29747 + /* The minimum number of TXQs that is acceptable */ 29748 29748 + #define MC_CMD_ALLOC_LL_QUEUES_IN_MIN_TXQ_COUNT_OFST 0 29749 29749 + #define MC_CMD_ALLOC_LL_QUEUES_IN_MIN_TXQ_COUNT_LEN 4 29750 29750 + /* The maximum number of TXQs that would be useful */ 29751 29751 + #define MC_CMD_ALLOC_LL_QUEUES_IN_MAX_TXQ_COUNT_OFST 4 29752 29752 + #define MC_CMD_ALLOC_LL_QUEUES_IN_MAX_TXQ_COUNT_LEN 4 29753 29753 + /* The minimum number of RXQs that is acceptable */ 29754 29754 + #define MC_CMD_ALLOC_LL_QUEUES_IN_MIN_RXQ_COUNT_OFST 8 29755 29755 + #define MC_CMD_ALLOC_LL_QUEUES_IN_MIN_RXQ_COUNT_LEN 4 29756 29756 + /* The maximum number of RXQs that would be useful */ 29757 29757 + #define MC_CMD_ALLOC_LL_QUEUES_IN_MAX_RXQ_COUNT_OFST 12 29758 29758 + #define MC_CMD_ALLOC_LL_QUEUES_IN_MAX_RXQ_COUNT_LEN 4 29759 29759 + /* The minimum number of EVQs that is acceptable */ 29760 29760 + #define MC_CMD_ALLOC_LL_QUEUES_IN_MIN_EVQ_COUNT_OFST 16 29761 29761 + #define MC_CMD_ALLOC_LL_QUEUES_IN_MIN_EVQ_COUNT_LEN 4 29762 29762 + /* The maximum number of EVQs that would be useful */ 29763 29763 + #define MC_CMD_ALLOC_LL_QUEUES_IN_MAX_EVQ_COUNT_OFST 20 29764 29764 + #define MC_CMD_ALLOC_LL_QUEUES_IN_MAX_EVQ_COUNT_LEN 4 29765 29765 + 29766 29766 + /* MC_CMD_ALLOC_LL_QUEUES_OUT msgresponse */ 29767 29767 + #define MC_CMD_ALLOC_LL_QUEUES_OUT_LENMIN 16 29768 29768 + #define MC_CMD_ALLOC_LL_QUEUES_OUT_LENMAX 252 29769 29769 + #define MC_CMD_ALLOC_LL_QUEUES_OUT_LENMAX_MCDI2 1020 29770 29770 + #define MC_CMD_ALLOC_LL_QUEUES_OUT_LEN(num) (12+4*(num)) 29771 29771 + #define MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_NUM(len) (((len)-12)/4) 29772 29772 + /* The number of TXQs allocated in this request */ 29773 29773 + #define MC_CMD_ALLOC_LL_QUEUES_OUT_TXQ_COUNT_OFST 0 29774 29774 + #define MC_CMD_ALLOC_LL_QUEUES_OUT_TXQ_COUNT_LEN 4 29775 29775 + /* The number of RXQs allocated in this request */ 29776 29776 + #define MC_CMD_ALLOC_LL_QUEUES_OUT_RXQ_COUNT_OFST 4 29777 29777 + #define MC_CMD_ALLOC_LL_QUEUES_OUT_RXQ_COUNT_LEN 4 29778 29778 + /* The number of EVQs allocated in this request */ 29779 29779 + #define MC_CMD_ALLOC_LL_QUEUES_OUT_EVQ_COUNT_OFST 8 29780 29780 + #define MC_CMD_ALLOC_LL_QUEUES_OUT_EVQ_COUNT_LEN 4 29781 29781 + /* A list of allocated queues, returned as MC_CMD_QUEUE_HANDLEs, not 29782 29782 + * necessarily contiguous. TXQs are first in the list, followed by RXQs then 29783 29783 + * EVQs. The type of each queue is indicated by the top bits (see the 29784 29784 + * QUEUE_TYPE enum) 29785 29785 + */ 29786 29786 + #define MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_OFST 12 29787 29787 + #define MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_LEN 4 29788 29788 + #define MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_MINNUM 1 29789 29789 + #define MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_MAXNUM 60 29790 29790 + #define MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_MAXNUM_MCDI2 252 29791 29791 + 29792 29792 + 29793 29793 + /***********************************/ 29794 29794 + /* MC_CMD_FREE_LL_QUEUES 29795 29795 + * Free low latency (X3-style) queues for current PCI function. 29796 29796 + */ 29797 29797 + #define MC_CMD_FREE_LL_QUEUES 0x1de 29798 29798 + #undef MC_CMD_0x1de_PRIVILEGE_CTG 29799 29799 + 29800 29800 + #define MC_CMD_0x1de_PRIVILEGE_CTG SRIOV_CTG_GENERAL 29801 29801 + 29802 29802 + /* MC_CMD_FREE_LL_QUEUES_IN msgrequest */ 29803 29803 + #define MC_CMD_FREE_LL_QUEUES_IN_LENMIN 8 29804 29804 + #define MC_CMD_FREE_LL_QUEUES_IN_LENMAX 252 29805 29805 + #define MC_CMD_FREE_LL_QUEUES_IN_LENMAX_MCDI2 1020 29806 29806 + #define MC_CMD_FREE_LL_QUEUES_IN_LEN(num) (4+4*(num)) 29807 29807 + #define MC_CMD_FREE_LL_QUEUES_IN_QUEUES_NUM(len) (((len)-4)/4) 29808 29808 + /* The number of queues to free. */ 29809 29809 + #define MC_CMD_FREE_LL_QUEUES_IN_QUEUE_COUNT_OFST 0 29810 29810 + #define MC_CMD_FREE_LL_QUEUES_IN_QUEUE_COUNT_LEN 4 29811 29811 + /* A list of queues to free, as a list of MC_CMD_QUEUE_HANDLEs. They must have 29812 29812 + * all been previously allocated by MC_CMD_ALLOC_LL_QUEUES. The type of each 29813 29813 + * queue should be indicated by the top bits. 29814 29814 + */ 29815 29815 + #define MC_CMD_FREE_LL_QUEUES_IN_QUEUES_OFST 4 29816 29816 + #define MC_CMD_FREE_LL_QUEUES_IN_QUEUES_LEN 4 29817 29817 + #define MC_CMD_FREE_LL_QUEUES_IN_QUEUES_MINNUM 1 29818 29818 + #define MC_CMD_FREE_LL_QUEUES_IN_QUEUES_MAXNUM 62 29819 29819 + #define MC_CMD_FREE_LL_QUEUES_IN_QUEUES_MAXNUM_MCDI2 254 29820 29820 + 29821 29821 + /* MC_CMD_FREE_LL_QUEUES_OUT msgresponse */ 29822 29822 + #define MC_CMD_FREE_LL_QUEUES_OUT_LEN 0 25799 29823 25800 29824 25801 29825 #endif /* MCDI_PCOL_H */

+1 -58

drivers/net/ethernet/sfc/mcdi_port.c

reviewed

··· 17 17 #include "selftest.h" 18 18 #include "mcdi_port_common.h" 19 19 20 20 - static int efx_mcdi_mdio_read(struct net_device *net_dev, 21 21 - int prtad, int devad, u16 addr) 22 22 - { 23 23 - struct efx_nic *efx = efx_netdev_priv(net_dev); 24 24 - MCDI_DECLARE_BUF(inbuf, MC_CMD_MDIO_READ_IN_LEN); 25 25 - MCDI_DECLARE_BUF(outbuf, MC_CMD_MDIO_READ_OUT_LEN); 26 26 - size_t outlen; 27 27 - int rc; 28 28 - 29 29 - MCDI_SET_DWORD(inbuf, MDIO_READ_IN_BUS, efx->mdio_bus); 30 30 - MCDI_SET_DWORD(inbuf, MDIO_READ_IN_PRTAD, prtad); 31 31 - MCDI_SET_DWORD(inbuf, MDIO_READ_IN_DEVAD, devad); 32 32 - MCDI_SET_DWORD(inbuf, MDIO_READ_IN_ADDR, addr); 33 33 - 34 34 - rc = efx_mcdi_rpc(efx, MC_CMD_MDIO_READ, inbuf, sizeof(inbuf), 35 35 - outbuf, sizeof(outbuf), &outlen); 36 36 - if (rc) 37 37 - return rc; 38 38 - 39 39 - if (MCDI_DWORD(outbuf, MDIO_READ_OUT_STATUS) != 40 40 - MC_CMD_MDIO_STATUS_GOOD) 41 41 - return -EIO; 42 42 - 43 43 - return (u16)MCDI_DWORD(outbuf, MDIO_READ_OUT_VALUE); 44 44 - } 45 45 - 46 46 - static int efx_mcdi_mdio_write(struct net_device *net_dev, 47 47 - int prtad, int devad, u16 addr, u16 value) 48 48 - { 49 49 - struct efx_nic *efx = efx_netdev_priv(net_dev); 50 50 - MCDI_DECLARE_BUF(inbuf, MC_CMD_MDIO_WRITE_IN_LEN); 51 51 - MCDI_DECLARE_BUF(outbuf, MC_CMD_MDIO_WRITE_OUT_LEN); 52 52 - size_t outlen; 53 53 - int rc; 54 54 - 55 55 - MCDI_SET_DWORD(inbuf, MDIO_WRITE_IN_BUS, efx->mdio_bus); 56 56 - MCDI_SET_DWORD(inbuf, MDIO_WRITE_IN_PRTAD, prtad); 57 57 - MCDI_SET_DWORD(inbuf, MDIO_WRITE_IN_DEVAD, devad); 58 58 - MCDI_SET_DWORD(inbuf, MDIO_WRITE_IN_ADDR, addr); 59 59 - MCDI_SET_DWORD(inbuf, MDIO_WRITE_IN_VALUE, value); 60 60 - 61 61 - rc = efx_mcdi_rpc(efx, MC_CMD_MDIO_WRITE, inbuf, sizeof(inbuf), 62 62 - outbuf, sizeof(outbuf), &outlen); 63 63 - if (rc) 64 64 - return rc; 65 65 - 66 66 - if (MCDI_DWORD(outbuf, MDIO_WRITE_OUT_STATUS) != 67 67 - MC_CMD_MDIO_STATUS_GOOD) 68 68 - return -EIO; 69 69 - 70 70 - return 0; 71 71 - } 72 20 73 21 u32 efx_mcdi_phy_get_caps(struct efx_nic *efx) 74 22 { ··· 45 97 { 46 98 int rc; 47 99 48 48 - /* Set up MDIO structure for PHY */ 49 49 - efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 50 50 - efx->mdio.mdio_read = efx_mcdi_mdio_read; 51 51 - efx->mdio.mdio_write = efx_mcdi_mdio_write; 52 52 - 53 53 - /* Fill out MDIO structure, loopback modes, and initial link state */ 100 100 + /* Fill out loopback modes and initial link state */ 54 101 rc = efx_mcdi_phy_probe(efx); 55 102 if (rc != 0) 56 103 return rc;

-11

drivers/net/ethernet/sfc/mcdi_port_common.c

reviewed

··· 448 448 efx->phy_data = phy_data; 449 449 efx->phy_type = phy_data->type; 450 450 451 451 - efx->mdio_bus = phy_data->channel; 452 452 - efx->mdio.prtad = phy_data->port; 453 453 - efx->mdio.mmds = phy_data->mmd_mask & ~(1 << MC_CMD_MMD_CLAUSE22); 454 454 - efx->mdio.mode_support = 0; 455 455 - if (phy_data->mmd_mask & (1 << MC_CMD_MMD_CLAUSE22)) 456 456 - efx->mdio.mode_support |= MDIO_SUPPORTS_C22; 457 457 - if (phy_data->mmd_mask & ~(1 << MC_CMD_MMD_CLAUSE22)) 458 458 - efx->mdio.mode_support |= MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 459 459 - 460 451 caps = MCDI_DWORD(outbuf, GET_LINK_OUT_CAP); 461 452 if (caps & (1 << MC_CMD_PHY_CAP_AN_LBN)) 462 453 mcdi_to_ethtool_linkset(phy_data->media, caps, ··· 537 546 cmd->base.port = mcdi_to_ethtool_media(phy_cfg->media); 538 547 cmd->base.phy_address = phy_cfg->port; 539 548 cmd->base.autoneg = !!(efx->link_advertising[0] & ADVERTISED_Autoneg); 540 540 - cmd->base.mdio_support = (efx->mdio.mode_support & 541 541 - (MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22)); 542 549 543 550 mcdi_to_ethtool_linkset(phy_cfg->media, phy_cfg->supported_cap, 544 551 cmd->link_modes.supported);

+4 -5

drivers/net/ethernet/sfc/net_driver.h

reviewed

··· 15 15 #include <linux/ethtool.h> 16 16 #include <linux/if_vlan.h> 17 17 #include <linux/timer.h> 18 18 - #include <linux/mdio.h> 18 18 + #include <linux/mii.h> 19 19 #include <linux/list.h> 20 20 #include <linux/pci.h> 21 21 #include <linux/device.h> ··· 956 956 * @stats_buffer: DMA buffer for statistics 957 957 * @phy_type: PHY type 958 958 * @phy_data: PHY private data (including PHY-specific stats) 959 959 - * @mdio: PHY MDIO interface 960 960 - * @mdio_bus: PHY MDIO bus ID (only used by Siena) 961 959 * @phy_mode: PHY operating mode. Serialised by @mac_lock. 962 960 * @link_advertising: Autonegotiation advertising flags 963 961 * @fec_config: Forward Error Correction configuration flags. For bit positions ··· 1130 1132 1131 1133 unsigned int phy_type; 1132 1134 void *phy_data; 1133 1133 - struct mdio_if_info mdio; 1134 1134 - unsigned int mdio_bus; 1135 1135 enum efx_phy_mode phy_mode; 1136 1136 1137 1137 __ETHTOOL_DECLARE_LINK_MODE_MASK(link_advertising); ··· 1381 1385 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers 1382 1386 * @always_rx_scatter: NIC will always scatter packets to multiple buffers 1383 1387 * @option_descriptors: NIC supports TX option descriptors 1388 1388 + * @flash_auto_partition: firmware flash uses AUTO partition, driver does 1389 1389 + * not need to perform image parsing 1384 1390 * @min_interrupt_mode: Lowest capability interrupt mode supported 1385 1391 * from &enum efx_int_mode. 1386 1392 * @timer_period_max: Maximum period of interrupt timer (in ticks) ··· 1559 1561 bool can_rx_scatter; 1560 1562 bool always_rx_scatter; 1561 1563 bool option_descriptors; 1564 1564 + bool flash_auto_partition; 1562 1565 unsigned int min_interrupt_mode; 1563 1566 unsigned int timer_period_max; 1564 1567 netdev_features_t offload_features;