Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
iio: adc: Add support for the Renesas RZ/N1 ADC
The Renesas RZ/N1 ADC controller is the ADC controller available in the
Renesas RZ/N1 SoCs family. It can use up to two internal ADC cores (ADC1
and ADC2) those internal cores are not directly accessed but are handled
through ADC controller virtual channels.
Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
Reviewed-by: Nuno Sá <nuno.sa@analog.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
Herve Codina (Schneider Electric)
and committed by
Jonathan Cameron
2387a7d6
77538d11
+501
+10
drivers/iio/adc/Kconfig
+10
drivers/iio/adc/Kconfig
···
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To compile this driver as a module, choose M here: the
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module will be called rzg2l_adc.
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config RZN1_ADC
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tristate "Renesas RZ/N1 ADC driver"
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depends on ARCH_RZN1 || COMPILE_TEST
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help
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Say yes here to build support for the ADC found in Renesas
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RZ/N1 family.
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To compile this driver as a module, choose M here: the
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module will be called rzn1-adc.
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config RZT2H_ADC
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tristate "Renesas RZ/T2H / RZ/N2H ADC driver"
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depends on ARCH_RENESAS || COMPILE_TEST
+1
drivers/iio/adc/Makefile
+1
drivers/iio/adc/Makefile
···
124
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obj-$(CONFIG_ROHM_BD79124) += rohm-bd79124.o
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obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
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obj-$(CONFIG_RZG2L_ADC) += rzg2l_adc.o
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obj-$(CONFIG_RZN1_ADC) += rzn1-adc.o
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obj-$(CONFIG_RZT2H_ADC) += rzt2h_adc.o
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obj-$(CONFIG_SC27XX_ADC) += sc27xx_adc.o
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obj-$(CONFIG_SD_ADC_MODULATOR) += sd_adc_modulator.o
+490
drivers/iio/adc/rzn1-adc.c
+490
drivers/iio/adc/rzn1-adc.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
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* Renesas RZ/N1 ADC driver
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*
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* Copyright (C) 2025 Schneider-Electric
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*
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* Author: Herve Codina <herve.codina@bootlin.com>
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*
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* The RZ/N1 ADC controller can handle channels from its internal ADC1 and/or
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* ADC2 cores. The driver use ADC1 and/or ADC2 cores depending on the presence
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* of the related power supplies (AVDD and VREF) description in the device-tree.
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*/
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+
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#include <linux/array_size.h>
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/cleanup.h>
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#include <linux/clk.h>
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#include <linux/dev_printk.h>
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#include <linux/err.h>
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#include <linux/iio/iio.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/types.h>
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+
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#define RZN1_ADC_CONTROL_REG 0x02c
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#define RZN1_ADC_CONTROL_ADC_BUSY BIT(6)
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+
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#define RZN1_ADC_FORCE_REG 0x030
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#define RZN1_ADC_SET_FORCE_REG 0x034
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#define RZN1_ADC_CLEAR_FORCE_REG 0x038
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#define RZN1_ADC_FORCE_VC(_n) BIT(_n)
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+
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#define RZN1_ADC_CONFIG_REG 0x040
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#define RZN1_ADC_CONFIG_ADC_POWER_DOWN BIT(3)
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+
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#define RZN1_ADC_VC_REG(_n) (0x0c0 + 4 * (_n))
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#define RZN1_ADC_VC_ADC2_ENABLE BIT(16)
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#define RZN1_ADC_VC_ADC1_ENABLE BIT(15)
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#define RZN1_ADC_VC_ADC2_CHANNEL_SEL_MASK GENMASK(5, 3)
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#define RZN1_ADC_VC_ADC1_CHANNEL_SEL_MASK GENMASK(2, 0)
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+
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#define RZN1_ADC_ADC1_DATA_REG(_n) (0x100 + 4 * (_n))
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#define RZN1_ADC_ADC2_DATA_REG(_n) (0x140 + 4 * (_n))
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#define RZN1_ADC_ADCX_DATA_DATA_MASK GENMASK(11, 0)
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+
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#define RZN1_ADC_NO_CHANNEL -1
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+
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#define RZN1_ADC_CHANNEL_SHARED_SCALE(_ch, _ds_name) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = (_ch), \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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.datasheet_name = (_ds_name), \
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}
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+
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#define RZN1_ADC_CHANNEL_SEPARATED_SCALE(_ch, _ds_name) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = (_ch), \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_SCALE), \
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.datasheet_name = (_ds_name), \
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}
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+
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/*
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* 8 ADC1_IN signals existed numbered 0..4, 6..8
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* ADCx_IN5 doesn't exist in RZ/N1 datasheet
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*/
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static struct iio_chan_spec rzn1_adc1_channels[] = {
78
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RZN1_ADC_CHANNEL_SHARED_SCALE(0, "ADC1_IN0"),
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RZN1_ADC_CHANNEL_SHARED_SCALE(1, "ADC1_IN1"),
80
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RZN1_ADC_CHANNEL_SHARED_SCALE(2, "ADC1_IN2"),
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RZN1_ADC_CHANNEL_SHARED_SCALE(3, "ADC1_IN3"),
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RZN1_ADC_CHANNEL_SHARED_SCALE(4, "ADC1_IN4"),
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RZN1_ADC_CHANNEL_SHARED_SCALE(5, "ADC1_IN6"),
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RZN1_ADC_CHANNEL_SHARED_SCALE(6, "ADC1_IN7"),
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RZN1_ADC_CHANNEL_SHARED_SCALE(7, "ADC1_IN8"),
86
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};
87
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static struct iio_chan_spec rzn1_adc2_channels[] = {
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RZN1_ADC_CHANNEL_SHARED_SCALE(8, "ADC2_IN0"),
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RZN1_ADC_CHANNEL_SHARED_SCALE(9, "ADC2_IN1"),
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RZN1_ADC_CHANNEL_SHARED_SCALE(10, "ADC2_IN2"),
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RZN1_ADC_CHANNEL_SHARED_SCALE(11, "ADC2_IN3"),
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RZN1_ADC_CHANNEL_SHARED_SCALE(12, "ADC2_IN4"),
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RZN1_ADC_CHANNEL_SHARED_SCALE(13, "ADC2_IN6"),
95
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RZN1_ADC_CHANNEL_SHARED_SCALE(14, "ADC2_IN7"),
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RZN1_ADC_CHANNEL_SHARED_SCALE(15, "ADC2_IN8"),
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};
98
+
99
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/*
100
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* If both ADCs core are used, scale cannot be common. Indeed, scale is
101
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* based on Vref connected on each ADC core.
102
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*/
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static struct iio_chan_spec rzn1_adc1_adc2_channels[] = {
104
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RZN1_ADC_CHANNEL_SEPARATED_SCALE(0, "ADC1_IN0"),
105
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RZN1_ADC_CHANNEL_SEPARATED_SCALE(1, "ADC1_IN1"),
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RZN1_ADC_CHANNEL_SEPARATED_SCALE(2, "ADC1_IN2"),
107
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RZN1_ADC_CHANNEL_SEPARATED_SCALE(3, "ADC1_IN3"),
108
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RZN1_ADC_CHANNEL_SEPARATED_SCALE(4, "ADC1_IN4"),
109
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RZN1_ADC_CHANNEL_SEPARATED_SCALE(5, "ADC1_IN6"),
110
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RZN1_ADC_CHANNEL_SEPARATED_SCALE(6, "ADC1_IN7"),
111
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RZN1_ADC_CHANNEL_SEPARATED_SCALE(7, "ADC1_IN8"),
112
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RZN1_ADC_CHANNEL_SEPARATED_SCALE(8, "ADC2_IN0"),
113
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RZN1_ADC_CHANNEL_SEPARATED_SCALE(9, "ADC2_IN1"),
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RZN1_ADC_CHANNEL_SEPARATED_SCALE(10, "ADC2_IN2"),
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RZN1_ADC_CHANNEL_SEPARATED_SCALE(11, "ADC2_IN3"),
116
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RZN1_ADC_CHANNEL_SEPARATED_SCALE(12, "ADC2_IN4"),
117
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RZN1_ADC_CHANNEL_SEPARATED_SCALE(13, "ADC2_IN6"),
118
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RZN1_ADC_CHANNEL_SEPARATED_SCALE(14, "ADC2_IN7"),
119
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RZN1_ADC_CHANNEL_SEPARATED_SCALE(15, "ADC2_IN8"),
120
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};
121
+
122
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struct rzn1_adc {
123
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struct device *dev;
124
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void __iomem *regs;
125
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struct mutex lock; /* ADC lock */
126
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int adc1_vref_mV; /* ADC1 Vref in mV. Negative if ADC1 is not used */
127
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int adc2_vref_mV; /* ADC2 Vref in mV. Negative if ADC2 is not used */
128
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};
129
+
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static int rzn1_adc_power(struct rzn1_adc *rzn1_adc, bool power)
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{
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u32 v;
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+
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writel(power ? 0 : RZN1_ADC_CONFIG_ADC_POWER_DOWN,
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rzn1_adc->regs + RZN1_ADC_CONFIG_REG);
136
+
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/* Wait for the ADC_BUSY to clear */
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return readl_poll_timeout_atomic(rzn1_adc->regs + RZN1_ADC_CONTROL_REG,
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v, !(v & RZN1_ADC_CONTROL_ADC_BUSY),
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0, 500);
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}
142
+
143
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static void rzn1_adc_vc_setup_conversion(struct rzn1_adc *rzn1_adc, u32 ch,
144
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int adc1_ch, int adc2_ch)
145
+
{
146
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u32 vc = 0;
147
+
148
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if (adc1_ch != RZN1_ADC_NO_CHANNEL)
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vc |= RZN1_ADC_VC_ADC1_ENABLE |
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FIELD_PREP(RZN1_ADC_VC_ADC1_CHANNEL_SEL_MASK, adc1_ch);
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+
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if (adc2_ch != RZN1_ADC_NO_CHANNEL)
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vc |= RZN1_ADC_VC_ADC2_ENABLE |
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FIELD_PREP(RZN1_ADC_VC_ADC2_CHANNEL_SEL_MASK, adc2_ch);
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writel(vc, rzn1_adc->regs + RZN1_ADC_VC_REG(ch));
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}
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+
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static int rzn1_adc_vc_start_conversion(struct rzn1_adc *rzn1_adc, u32 ch)
160
+
{
161
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u32 val;
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+
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val = readl(rzn1_adc->regs + RZN1_ADC_FORCE_REG);
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if (val & RZN1_ADC_FORCE_VC(ch))
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return -EBUSY;
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writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_SET_FORCE_REG);
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return 0;
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}
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static void rzn1_adc_vc_stop_conversion(struct rzn1_adc *rzn1_adc, u32 ch)
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{
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writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_CLEAR_FORCE_REG);
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}
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static int rzn1_adc_vc_wait_conversion(struct rzn1_adc *rzn1_adc, u32 ch,
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u32 *adc1_data, u32 *adc2_data)
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{
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u32 data_reg;
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int ret;
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u32 v;
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+
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/*
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* When a VC is selected, it needs 20 ADC clocks to perform the
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* conversion.
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*
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* The worst case is when the 16 VCs need to perform a conversion and
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* our VC is the lowest in term of priority.
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*
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* In that case, the conversion is performed in 16 * 20 ADC clocks.
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*
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* The ADC clock can be set from 4MHz to 20MHz. This leads to a worst
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* case of 16 * 20 * 1/4Mhz = 80us.
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*
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* Round it up to 100us.
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*/
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/* Wait for the ADC_FORCE_VC(n) to clear */
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ret = readl_poll_timeout_atomic(rzn1_adc->regs + RZN1_ADC_FORCE_REG,
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v, !(v & RZN1_ADC_FORCE_VC(ch)),
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0, 100);
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if (ret)
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return ret;
205
+
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if (adc1_data) {
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data_reg = readl(rzn1_adc->regs + RZN1_ADC_ADC1_DATA_REG(ch));
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*adc1_data = FIELD_GET(RZN1_ADC_ADCX_DATA_DATA_MASK, data_reg);
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}
210
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if (adc2_data) {
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data_reg = readl(rzn1_adc->regs + RZN1_ADC_ADC2_DATA_REG(ch));
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*adc2_data = FIELD_GET(RZN1_ADC_ADCX_DATA_DATA_MASK, data_reg);
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}
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return 0;
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}
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static int rzn1_adc_read_raw_ch(struct rzn1_adc *rzn1_adc, unsigned int chan, int *val)
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{
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u32 *adc1_data, *adc2_data;
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int adc1_ch, adc2_ch;
223
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u32 adc_data;
224
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int ret;
225
+
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/*
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* IIO chan are decoupled from chans used in rzn1_adc_vc_*() functions.
228
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* The RZ/N1 ADC VC controller can handle on a single VC chan one
229
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* channel from the ADC1 core and one channel from the ADC2 core.
230
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*
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* Even if IIO chans are mapped 1:1 to ADC core chans and so uses only
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* a chan from ADC1 or a chan from ADC2, future improvements can define
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* an IIO chan that uses one chan from ADC1 and one chan from ADC2.
234
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*/
235
+
236
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if (chan < 8) {
237
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/* chan 0..7 used to get ADC1 ch 0..7 */
238
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adc1_ch = chan;
239
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adc1_data = &adc_data;
240
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adc2_ch = RZN1_ADC_NO_CHANNEL;
241
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adc2_data = NULL;
242
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} else if (chan < 16) {
243
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/* chan 8..15 used to get ADC2 ch 0..7 */
244
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adc1_ch = RZN1_ADC_NO_CHANNEL;
245
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adc1_data = NULL;
246
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adc2_ch = chan - 8;
247
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adc2_data = &adc_data;
248
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} else {
249
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return -EINVAL;
250
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}
251
+
252
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ACQUIRE(pm_runtime_active_auto_try_enabled, pm)(rzn1_adc->dev);
253
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ret = ACQUIRE_ERR(pm_runtime_active_auto_try_enabled, &pm);
254
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if (ret < 0)
255
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return ret;
256
+
257
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scoped_guard(mutex, &rzn1_adc->lock) {
258
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rzn1_adc_vc_setup_conversion(rzn1_adc, chan, adc1_ch, adc2_ch);
259
+
260
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ret = rzn1_adc_vc_start_conversion(rzn1_adc, chan);
261
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if (ret)
262
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return ret;
263
+
264
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ret = rzn1_adc_vc_wait_conversion(rzn1_adc, chan, adc1_data, adc2_data);
265
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if (ret) {
266
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rzn1_adc_vc_stop_conversion(rzn1_adc, chan);
267
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return ret;
268
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}
269
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}
270
+
271
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*val = adc_data;
272
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ret = IIO_VAL_INT;
273
+
274
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return 0;
275
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}
276
+
277
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static int rzn1_adc_get_vref_mV(struct rzn1_adc *rzn1_adc, unsigned int chan)
278
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{
279
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/* chan 0..7 use ADC1 ch 0..7. Vref related to ADC1 core */
280
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if (chan < 8)
281
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return rzn1_adc->adc1_vref_mV;
282
+
283
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/* chan 8..15 use ADC2 ch 0..7. Vref related to ADC2 core */
284
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if (chan < 16)
285
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return rzn1_adc->adc2_vref_mV;
286
+
287
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return -EINVAL;
288
+
}
289
+
290
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static int rzn1_adc_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
291
+
int *val, int *val2, long mask)
292
+
{
293
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struct rzn1_adc *rzn1_adc = iio_priv(indio_dev);
294
+
int ret;
295
+
296
+
switch (mask) {
297
+
case IIO_CHAN_INFO_RAW:
298
+
ret = rzn1_adc_read_raw_ch(rzn1_adc, chan->channel, val);
299
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if (ret)
300
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return ret;
301
+
return IIO_VAL_INT;
302
+
303
+
case IIO_CHAN_INFO_SCALE:
304
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ret = rzn1_adc_get_vref_mV(rzn1_adc, chan->channel);
305
+
if (ret < 0)
306
+
return ret;
307
+
*val = ret;
308
+
*val2 = 12;
309
+
return IIO_VAL_FRACTIONAL_LOG2;
310
+
311
+
default:
312
+
return -EINVAL;
313
+
}
314
+
}
315
+
316
+
static const struct iio_info rzn1_adc_info = {
317
+
.read_raw = &rzn1_adc_read_raw,
318
+
};
319
+
320
+
static int rzn1_adc_set_iio_dev_channels(struct rzn1_adc *rzn1_adc,
321
+
struct iio_dev *indio_dev)
322
+
{
323
+
/*
324
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* When an ADC core is not used, its related vref_mV is set to a
325
+
* negative error code. Use the correct IIO channels table based on
326
+
* those vref_mV values.
327
+
*/
328
+
if (rzn1_adc->adc1_vref_mV >= 0) {
329
+
if (rzn1_adc->adc2_vref_mV >= 0) {
330
+
indio_dev->channels = rzn1_adc1_adc2_channels;
331
+
indio_dev->num_channels = ARRAY_SIZE(rzn1_adc1_adc2_channels);
332
+
} else {
333
+
indio_dev->channels = rzn1_adc1_channels;
334
+
indio_dev->num_channels = ARRAY_SIZE(rzn1_adc1_channels);
335
+
}
336
+
return 0;
337
+
}
338
+
339
+
if (rzn1_adc->adc2_vref_mV >= 0) {
340
+
indio_dev->channels = rzn1_adc2_channels;
341
+
indio_dev->num_channels = ARRAY_SIZE(rzn1_adc2_channels);
342
+
return 0;
343
+
}
344
+
345
+
return dev_err_probe(rzn1_adc->dev, -ENODEV,
346
+
"Failed to set IIO channels, no ADC core used\n");
347
+
}
348
+
349
+
static int rzn1_adc_core_get_regulators(struct rzn1_adc *rzn1_adc,
350
+
int *adc_vref_mV,
351
+
const char *avdd_name, const char *vref_name)
352
+
{
353
+
struct device *dev = rzn1_adc->dev;
354
+
int ret;
355
+
356
+
/*
357
+
* For a given ADC core (ADC1 or ADC2), both regulators (AVDD and VREF)
358
+
* must be available in order to have the ADC core used.
359
+
*
360
+
* We use the regulators presence to check the usage of the related
361
+
* ADC core. If both regulators are available, the ADC core is used.
362
+
* Otherwise, the ADC core is not used.
363
+
*
364
+
* The adc_vref_mV value is set to a negative error code (-ENODEV) when
365
+
* the ADC core is not used. Otherwise it is set to the VRef mV value.
366
+
*/
367
+
368
+
*adc_vref_mV = -ENODEV;
369
+
370
+
ret = devm_regulator_get_enable_optional(dev, avdd_name);
371
+
if (ret == -ENODEV)
372
+
return 0;
373
+
if (ret < 0)
374
+
return dev_err_probe(dev, ret, "Failed to get '%s' regulator\n",
375
+
avdd_name);
376
+
377
+
ret = devm_regulator_get_enable_read_voltage(dev, vref_name);
378
+
if (ret == -ENODEV)
379
+
return 0;
380
+
if (ret < 0)
381
+
return dev_err_probe(dev, ret, "Failed to get '%s' regulator\n",
382
+
vref_name);
383
+
384
+
/*
385
+
* Both regulators are available.
386
+
* Set adc_vref_mV to the Vref value in mV. This, as the value set is
387
+
* positive, also signals that the ADC is used.
388
+
*/
389
+
*adc_vref_mV = ret / 1000;
390
+
391
+
return 0;
392
+
}
393
+
394
+
static int rzn1_adc_probe(struct platform_device *pdev)
395
+
{
396
+
struct device *dev = &pdev->dev;
397
+
struct iio_dev *indio_dev;
398
+
struct rzn1_adc *rzn1_adc;
399
+
struct clk *clk;
400
+
int ret;
401
+
402
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*rzn1_adc));
403
+
if (!indio_dev)
404
+
return -ENOMEM;
405
+
406
+
rzn1_adc = iio_priv(indio_dev);
407
+
rzn1_adc->dev = dev;
408
+
409
+
ret = devm_mutex_init(dev, &rzn1_adc->lock);
410
+
if (ret)
411
+
return ret;
412
+
413
+
rzn1_adc->regs = devm_platform_ioremap_resource(pdev, 0);
414
+
if (IS_ERR(rzn1_adc->regs))
415
+
return PTR_ERR(rzn1_adc->regs);
416
+
417
+
clk = devm_clk_get_enabled(dev, "pclk");
418
+
if (IS_ERR(clk))
419
+
return dev_err_probe(dev, PTR_ERR(clk), "Failed to get pclk\n");
420
+
421
+
clk = devm_clk_get_enabled(dev, "adc");
422
+
if (IS_ERR(clk))
423
+
return dev_err_probe(dev, PTR_ERR(clk), "Failed to get adc clk\n");
424
+
425
+
ret = rzn1_adc_core_get_regulators(rzn1_adc, &rzn1_adc->adc1_vref_mV,
426
+
"adc1-avdd", "adc1-vref");
427
+
if (ret)
428
+
return ret;
429
+
430
+
ret = rzn1_adc_core_get_regulators(rzn1_adc, &rzn1_adc->adc2_vref_mV,
431
+
"adc2-avdd", "adc2-vref");
432
+
if (ret)
433
+
return ret;
434
+
435
+
platform_set_drvdata(pdev, rzn1_adc);
436
+
437
+
indio_dev->name = "rzn1-adc";
438
+
indio_dev->info = &rzn1_adc_info;
439
+
indio_dev->modes = INDIO_DIRECT_MODE;
440
+
ret = rzn1_adc_set_iio_dev_channels(rzn1_adc, indio_dev);
441
+
if (ret)
442
+
return ret;
443
+
444
+
pm_runtime_set_autosuspend_delay(dev, 500);
445
+
pm_runtime_use_autosuspend(dev);
446
+
ret = devm_pm_runtime_enable(dev);
447
+
if (ret)
448
+
return dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
449
+
450
+
return devm_iio_device_register(dev, indio_dev);
451
+
}
452
+
453
+
static int rzn1_adc_pm_runtime_suspend(struct device *dev)
454
+
{
455
+
struct rzn1_adc *rzn1_adc = dev_get_drvdata(dev);
456
+
457
+
return rzn1_adc_power(rzn1_adc, false);
458
+
}
459
+
460
+
static int rzn1_adc_pm_runtime_resume(struct device *dev)
461
+
{
462
+
struct rzn1_adc *rzn1_adc = dev_get_drvdata(dev);
463
+
464
+
return rzn1_adc_power(rzn1_adc, true);
465
+
}
466
+
467
+
static DEFINE_RUNTIME_DEV_PM_OPS(rzn1_adc_pm_ops,
468
+
rzn1_adc_pm_runtime_suspend,
469
+
rzn1_adc_pm_runtime_resume,
470
+
NULL);
471
+
472
+
static const struct of_device_id rzn1_adc_of_match[] = {
473
+
{ .compatible = "renesas,rzn1-adc" },
474
+
{ }
475
+
};
476
+
MODULE_DEVICE_TABLE(of, rzn1_adc_of_match);
477
+
478
+
static struct platform_driver rzn1_adc_driver = {
479
+
.probe = rzn1_adc_probe,
480
+
.driver = {
481
+
.name = "rzn1-adc",
482
+
.of_match_table = rzn1_adc_of_match,
483
+
.pm = pm_ptr(&rzn1_adc_pm_ops),
484
+
},
485
+
};
486
+
module_platform_driver(rzn1_adc_driver);
487
+
488
+
MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>");
489
+
MODULE_DESCRIPTION("Renesas RZ/N1 ADC Driver");
490
+
MODULE_LICENSE("GPL");