Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
iio: adc: ad4062: Add IIO Trigger support
Adds support for IIO Trigger. Optionally, gp1 is assigned as Data Ready
signal, if not present, fallback to an I3C IBI with the same role.
The software trigger is allocated by the device, but must be attached by
the user before enabling the buffer. The purpose is to not impede
removing the driver due to the increased reference count when
iio_trigger_set_immutable() or iio_trigger_get() is used.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
Jorge Marques
and committed by
Jonathan Cameron
23cc9228
c31721dc
+268
-6
+2
drivers/iio/adc/Kconfig
+2
drivers/iio/adc/Kconfig
+266
-6
drivers/iio/adc/ad4062.c
+266
-6
drivers/iio/adc/ad4062.c
···
9
9
#include <linux/bitops.h>
10
10
#include <linux/completion.h>
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#include <linux/delay.h>
12
+
#include <linux/devm-helpers.h>
12
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#include <linux/err.h>
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#include <linux/i3c/device.h>
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#include <linux/i3c/master.h>
16
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#include <linux/iio/buffer.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/trigger.h>
19
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/interrupt.h>
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#include <linux/jiffies.h>
18
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#include <linux/math.h>
···
64
59
#define AD4062_REG_DEVICE_STATUS_DEVICE_RESET BIT(6)
65
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#define AD4062_REG_IBI_STATUS 0x48
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#define AD4062_REG_CONV_READ_LSB 0x50
62
+
#define AD4062_REG_CONV_READ_16BITS 0x51
63
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#define AD4062_REG_CONV_READ_32BITS 0x53
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#define AD4062_REG_CONV_TRIGGER_16BITS 0x57
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#define AD4062_REG_CONV_TRIGGER_32BITS 0x59
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#define AD4062_REG_CONV_AUTO 0x61
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#define AD4062_MAX_REG AD4062_REG_CONV_AUTO
···
102
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AD4062_SCAN_TYPE_BURST_AVG,
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};
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+
static const struct iio_scan_type ad4062_scan_type_12_s[] = {
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[AD4062_SCAN_TYPE_SAMPLE] = {
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.sign = 's',
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.realbits = 12,
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.storagebits = 16,
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.endianness = IIO_BE,
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},
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[AD4062_SCAN_TYPE_BURST_AVG] = {
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.sign = 's',
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.realbits = 14,
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.storagebits = 16,
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.endianness = IIO_BE,
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},
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};
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+
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static const struct iio_scan_type ad4062_scan_type_16_s[] = {
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[AD4062_SCAN_TYPE_SAMPLE] = {
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.sign = 's',
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.realbits = 16,
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.storagebits = 16,
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.endianness = IIO_BE,
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},
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[AD4062_SCAN_TYPE_BURST_AVG] = {
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.sign = 's',
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.realbits = 20,
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.storagebits = 32,
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.endianness = IIO_BE,
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},
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};
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+
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static const unsigned int ad4062_conversion_freqs[] = {
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2000000, 1000000, 300000, 100000, /* 0 - 3 */
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33300, 10000, 3000, 500, /* 4 - 7 */
···
143
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const struct ad4062_chip_info *chip;
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const struct ad4062_bus_ops *ops;
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enum ad4062_operation_mode mode;
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+
struct work_struct trig_conv;
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struct completion completion;
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struct iio_trigger *trigger;
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struct iio_dev *indio_dev;
···
151
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struct regmap *regmap;
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int vref_uV;
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unsigned int samp_freqs[ARRAY_SIZE(ad4062_conversion_freqs)];
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+
bool gpo_irq[2];
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u16 sampling_frequency;
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u8 oversamp_ratio;
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u8 conv_sizeof;
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u8 conv_addr;
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union {
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__be32 be32;
···
188
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.n_yes_ranges = ARRAY_SIZE(ad4062_regmap_wr_ranges),
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};
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-
#define AD4062_CHAN { \
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#define AD4062_CHAN(bits) { \
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.type = IIO_VOLTAGE, \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) | \
194
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BIT(IIO_CHAN_INFO_SCALE) | \
···
199
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.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
200
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.indexed = 1, \
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.channel = 0, \
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.has_ext_scan_type = 1, \
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+
.ext_scan_type = ad4062_scan_type_##bits##_s, \
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+
.num_ext_scan_type = ARRAY_SIZE(ad4062_scan_type_##bits##_s), \
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}
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static const struct ad4062_chip_info ad4060_chip_info = {
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.name = "ad4060",
206
-
.channels = { AD4062_CHAN },
168
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.channels = { AD4062_CHAN(12) },
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.prod_id = AD4060_PROD_ID,
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.avg_max = 256,
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};
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static const struct ad4062_chip_info ad4062_chip_info = {
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.name = "ad4062",
213
-
.channels = { AD4062_CHAN },
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+
.channels = { AD4062_CHAN(16) },
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.prod_id = AD4062_PROD_ID,
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.avg_max = 4096,
216
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};
···
378
334
const bool *ref_sel)
379
335
{
380
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struct ad4062_state *st = iio_priv(indio_dev);
337
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const struct iio_scan_type *scan_type;
381
338
int ret;
339
+
340
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scan_type = iio_get_current_scan_type(indio_dev, chan);
341
+
if (IS_ERR(scan_type))
342
+
return PTR_ERR(scan_type);
382
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383
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ret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF,
384
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AD4062_REG_GP_CONF_MODE_MSK_1,
···
421
372
struct iio_dev *indio_dev = private;
422
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struct ad4062_state *st = iio_priv(indio_dev);
423
374
424
-
complete(&st->completion);
375
+
if (iio_buffer_enabled(indio_dev) && iio_trigger_using_own(indio_dev))
376
+
iio_trigger_poll(st->trigger);
377
+
else
378
+
complete(&st->completion);
425
379
426
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return IRQ_HANDLED;
427
381
}
···
434
382
{
435
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struct ad4062_state *st = i3cdev_get_drvdata(i3cdev);
436
384
437
-
complete(&st->completion);
385
+
if (iio_buffer_enabled(st->indio_dev))
386
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iio_trigger_poll_nested(st->trigger);
387
+
else
388
+
complete(&st->completion);
389
+
}
390
+
391
+
static void ad4062_trigger_work(struct work_struct *work)
392
+
{
393
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struct ad4062_state *st =
394
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container_of(work, struct ad4062_state, trig_conv);
395
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int ret;
396
+
397
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/*
398
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* Read current conversion, if at reg CONV_READ, stop bit triggers
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* next sample and does not need writing the address.
400
+
*/
401
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struct i3c_priv_xfer xfer_sample = {
402
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.data.in = &st->buf.be32,
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.len = st->conv_sizeof,
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.rnw = true,
405
+
};
406
+
struct i3c_priv_xfer xfer_trigger = {
407
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.data.out = &st->conv_addr,
408
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.len = sizeof(st->conv_addr),
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.rnw = false,
410
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};
411
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412
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ret = i3c_device_do_priv_xfers(st->i3cdev, &xfer_sample, 1);
413
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if (ret)
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return;
415
+
416
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iio_push_to_buffers_with_ts(st->indio_dev, &st->buf.be32, st->conv_sizeof,
417
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iio_get_time_ns(st->indio_dev));
418
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if (st->gpo_irq[1])
419
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return;
420
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i3c_device_do_priv_xfers(st->i3cdev, &xfer_trigger, 1);
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}
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+
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static irqreturn_t ad4062_poll_handler(int irq, void *p)
425
+
{
426
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struct iio_poll_func *pf = p;
427
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struct iio_dev *indio_dev = pf->indio_dev;
428
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struct ad4062_state *st = iio_priv(indio_dev);
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+
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iio_trigger_notify_done(indio_dev->trig);
431
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schedule_work(&st->trig_conv);
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+
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return IRQ_HANDLED;
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}
439
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static void ad4062_disable_ibi(void *data)
···
533
433
if (ret == -EPROBE_DEFER)
534
434
return ret;
535
435
536
-
if (ret < 0)
436
+
if (ret < 0) {
437
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st->gpo_irq[1] = false;
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return regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN,
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AD4062_REG_ADC_IBI_EN_CONV_TRIGGER,
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AD4062_REG_ADC_IBI_EN_CONV_TRIGGER);
441
+
}
442
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st->gpo_irq[1] = true;
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541
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return devm_request_threaded_irq(dev, ret,
542
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ad4062_irq_handler_drdy,
543
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NULL, IRQF_ONESHOT, indio_dev->name,
544
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indio_dev);
448
+
}
449
+
450
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static const struct iio_trigger_ops ad4062_trigger_ops = {
451
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.validate_device = &iio_trigger_validate_own_device,
452
+
};
453
+
454
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static int ad4062_request_trigger(struct iio_dev *indio_dev)
455
+
{
456
+
struct ad4062_state *st = iio_priv(indio_dev);
457
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struct device *dev = &st->i3cdev->dev;
458
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int ret;
459
+
460
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st->trigger = devm_iio_trigger_alloc(dev, "%s-dev%d",
461
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indio_dev->name,
462
+
iio_device_id(indio_dev));
463
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if (!st->trigger)
464
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return -ENOMEM;
465
+
466
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st->trigger->ops = &ad4062_trigger_ops;
467
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iio_trigger_set_drvdata(st->trigger, indio_dev);
468
+
469
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ret = devm_iio_trigger_register(dev, st->trigger);
470
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if (ret)
471
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return ret;
472
+
473
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indio_dev->trig = iio_trigger_get(st->trigger);
474
+
475
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return 0;
545
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}
546
477
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static const int ad4062_oversampling_avail[] = {
···
607
476
default:
608
477
return -EINVAL;
609
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}
479
+
}
480
+
481
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static int ad4062_get_chan_scale(struct iio_dev *indio_dev, int *val, int *val2)
482
+
{
483
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struct ad4062_state *st = iio_priv(indio_dev);
484
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const struct iio_scan_type *scan_type;
485
+
486
+
/*
487
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* In burst averaging mode the averaging filter accumulates resulting
488
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* in a sample with increased precision.
489
+
*/
490
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scan_type = iio_get_current_scan_type(indio_dev, st->chip->channels);
491
+
if (IS_ERR(scan_type))
492
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return PTR_ERR(scan_type);
493
+
494
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*val = (st->vref_uV * 2) / (MICRO / MILLI); /* signed */
495
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*val2 = scan_type->realbits - 1;
496
+
497
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return IIO_VAL_FRACTIONAL_LOG2;
610
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}
611
499
612
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static int ad4062_get_chan_calibscale(struct ad4062_state *st, int *val, int *val2)
···
743
593
int ret;
744
594
745
595
switch (info) {
596
+
case IIO_CHAN_INFO_SCALE:
597
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return ad4062_get_chan_scale(indio_dev, val, val2);
598
+
746
599
case IIO_CHAN_INFO_SAMP_FREQ:
747
600
return ad4062_get_sampling_frequency(st, val);
748
601
}
···
794
641
return ret;
795
642
}
796
643
644
+
/*
645
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* The AD4062 in burst averaging mode increases realbits from 16-bits to
646
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* 20-bits, increasing the storagebits from 16-bits to 32-bits.
647
+
*/
648
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static inline size_t ad4062_sizeof_storagebits(struct ad4062_state *st)
649
+
{
650
+
const struct iio_scan_type *scan_type =
651
+
iio_get_current_scan_type(st->indio_dev, st->chip->channels);
652
+
653
+
return BITS_TO_BYTES(scan_type->storagebits);
654
+
}
655
+
656
+
/* Read registers only with realbits (no sign extension bytes) */
657
+
static inline size_t ad4062_get_conv_addr(struct ad4062_state *st, size_t _sizeof)
658
+
{
659
+
if (st->gpo_irq[1])
660
+
return _sizeof == sizeof(u32) ? AD4062_REG_CONV_READ_32BITS :
661
+
AD4062_REG_CONV_READ_16BITS;
662
+
return _sizeof == sizeof(u32) ? AD4062_REG_CONV_TRIGGER_32BITS :
663
+
AD4062_REG_CONV_TRIGGER_16BITS;
664
+
}
665
+
666
+
static int pm_ad4062_triggered_buffer_postenable(struct ad4062_state *st)
667
+
{
668
+
int ret;
669
+
670
+
PM_RUNTIME_ACQUIRE(&st->i3cdev->dev, pm);
671
+
ret = PM_RUNTIME_ACQUIRE_ERR(&pm);
672
+
if (ret)
673
+
return ret;
674
+
675
+
ret = ad4062_set_operation_mode(st, st->mode);
676
+
if (ret)
677
+
return ret;
678
+
679
+
st->conv_sizeof = ad4062_sizeof_storagebits(st);
680
+
st->conv_addr = ad4062_get_conv_addr(st, st->conv_sizeof);
681
+
/* CONV_READ requires read to trigger first sample. */
682
+
struct i3c_priv_xfer xfer_sample[2] = {
683
+
{
684
+
.data.out = &st->conv_addr,
685
+
.len = sizeof(st->conv_addr),
686
+
.rnw = false,
687
+
},
688
+
{
689
+
.data.in = &st->buf.be32,
690
+
.len = sizeof(st->buf.be32),
691
+
.rnw = true,
692
+
}
693
+
};
694
+
695
+
return i3c_device_do_priv_xfers(st->i3cdev, xfer_sample,
696
+
st->gpo_irq[1] ? 2 : 1);
697
+
}
698
+
699
+
static int ad4062_triggered_buffer_postenable(struct iio_dev *indio_dev)
700
+
{
701
+
struct ad4062_state *st = iio_priv(indio_dev);
702
+
int ret;
703
+
704
+
ret = pm_ad4062_triggered_buffer_postenable(st);
705
+
if (ret)
706
+
return ret;
707
+
708
+
pm_runtime_get_noresume(&st->i3cdev->dev);
709
+
return 0;
710
+
}
711
+
712
+
static int ad4062_triggered_buffer_predisable(struct iio_dev *indio_dev)
713
+
{
714
+
struct ad4062_state *st = iio_priv(indio_dev);
715
+
716
+
pm_runtime_put_autosuspend(&st->i3cdev->dev);
717
+
return 0;
718
+
}
719
+
720
+
static const struct iio_buffer_setup_ops ad4062_triggered_buffer_setup_ops = {
721
+
.postenable = &ad4062_triggered_buffer_postenable,
722
+
.predisable = &ad4062_triggered_buffer_predisable,
723
+
};
724
+
797
725
static int ad4062_debugfs_reg_access(struct iio_dev *indio_dev, unsigned int reg,
798
726
unsigned int writeval, unsigned int *readval)
799
727
{
···
886
652
return regmap_write(st->regmap, reg, writeval);
887
653
}
888
654
655
+
static int ad4062_get_current_scan_type(const struct iio_dev *indio_dev,
656
+
const struct iio_chan_spec *chan)
657
+
{
658
+
struct ad4062_state *st = iio_priv(indio_dev);
659
+
660
+
return st->mode == AD4062_BURST_AVERAGING_MODE ?
661
+
AD4062_SCAN_TYPE_BURST_AVG :
662
+
AD4062_SCAN_TYPE_SAMPLE;
663
+
}
664
+
889
665
static const struct iio_info ad4062_info = {
890
666
.read_raw = ad4062_read_raw,
891
667
.write_raw = ad4062_write_raw,
892
668
.read_avail = ad4062_read_avail,
669
+
.get_current_scan_type = ad4062_get_current_scan_type,
893
670
.debugfs_reg_access = ad4062_debugfs_reg_access,
894
671
};
895
672
···
1007
762
if (ret)
1008
763
return ret;
1009
764
765
+
ret = ad4062_request_trigger(indio_dev);
766
+
if (ret)
767
+
return ret;
768
+
769
+
ret = devm_iio_triggered_buffer_setup(&i3cdev->dev, indio_dev,
770
+
iio_pollfunc_store_time,
771
+
ad4062_poll_handler,
772
+
&ad4062_triggered_buffer_setup_ops);
773
+
if (ret)
774
+
return ret;
775
+
1010
776
pm_runtime_set_active(dev);
1011
777
ret = devm_pm_runtime_enable(dev);
1012
778
if (ret)
···
1029
773
ret = ad4062_request_ibi(i3cdev);
1030
774
if (ret)
1031
775
return dev_err_probe(dev, ret, "Failed to request i3c ibi\n");
776
+
777
+
ret = devm_work_autocancel(dev, &st->trig_conv, ad4062_trigger_work);
778
+
if (ret)
779
+
return ret;
1032
780
1033
781
return devm_iio_device_register(dev, indio_dev);
1034
782
}