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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
perf jevents: Add support for Yitian 710 DDR PMU (arm64) aliasing
Add alias support for T-HEAD Yitian 710 SoC DDR PMU events.
Reviewed-by: John Garry <john.g.garry@oracle.com>
Reviewed-by: Shuai Xue <xueshuai@linux.alibaba.com>
Signed-off-by: Jing Zhang <renyu.zj@linux.alibaba.com>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Zhuo Song <zhuo.song@linux.alibaba.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-doc@vger.kernel.org
Link: https://lore.kernel.org/r/1690528175-2499-2-git-send-email-renyu.zj@linux.alibaba.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
authored by
Jing Zhang
and committed by
Arnaldo Carvalho de Melo
24069d81
404e077a
+374
+373
tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/ali_drw.json
+373
tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/ali_drw.json
···
1
+
[
2
+
{
3
+
"BriefDescription": "A Write or Read Op at HIF interface. The unit is 64B.",
4
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"ConfigCode": "0x0",
5
+
"EventName": "hif_rd_or_wr",
6
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"Unit": "ali_drw",
7
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"Compat": "ali_drw_pmu"
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},
9
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{
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"BriefDescription": "A Write Op at HIF interface. The unit is 64B.",
11
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"ConfigCode": "0x1",
12
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"EventName": "hif_wr",
13
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"Unit": "ali_drw",
14
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"Compat": "ali_drw_pmu"
15
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},
16
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{
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"BriefDescription": "A Read Op at HIF interface. The unit is 64B.",
18
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"ConfigCode": "0x2",
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"EventName": "hif_rd",
20
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"Unit": "ali_drw",
21
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"Compat": "ali_drw_pmu"
22
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},
23
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{
24
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"BriefDescription": "A Read-Modify-Write Op at HIF interface. The unit is 64B.",
25
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"ConfigCode": "0x3",
26
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"EventName": "hif_rmw",
27
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"Unit": "ali_drw",
28
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"Compat": "ali_drw_pmu"
29
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},
30
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{
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"BriefDescription": "A high priority Read at HIF interface. The unit is 64B.",
32
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"ConfigCode": "0x4",
33
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"EventName": "hif_hi_pri_rd",
34
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"Unit": "ali_drw",
35
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"Compat": "ali_drw_pmu"
36
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},
37
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{
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"BriefDescription": "A write data cycle at DFI interface (to DRAM).",
39
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"ConfigCode": "0x7",
40
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"EventName": "dfi_wr_data_cycles",
41
+
"Unit": "ali_drw",
42
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"Compat": "ali_drw_pmu"
43
+
},
44
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{
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+
"BriefDescription": "A read data cycle at DFI interface (to DRAM).",
46
+
"ConfigCode": "0x8",
47
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"EventName": "dfi_rd_data_cycles",
48
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"Unit": "ali_drw",
49
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"Compat": "ali_drw_pmu"
50
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},
51
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{
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+
"BriefDescription": "A high priority read becomes critical.",
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"ConfigCode": "0x9",
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"EventName": "hpr_xact_when_critical",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A low priority read becomes critical.",
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"ConfigCode": "0xA",
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"EventName": "lpr_xact_when_critical",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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+
"BriefDescription": "A write becomes critical.",
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"ConfigCode": "0xB",
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"EventName": "wr_xact_when_critical",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "An Activate(ACT) command to DRAM.",
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"ConfigCode": "0xC",
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+
"EventName": "op_is_activate",
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"Unit": "ali_drw",
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+
"Compat": "ali_drw_pmu"
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},
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{
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+
"BriefDescription": "A Read or Write CAS command to DRAM.",
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+
"ConfigCode": "0xD",
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+
"EventName": "op_is_rd_or_wr",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "An Activate(ACT) command for read to DRAM.",
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"ConfigCode": "0xE",
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+
"EventName": "op_is_rd_activate",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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+
"BriefDescription": "A Read CAS command to DRAM.",
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+
"ConfigCode": "0xF",
96
+
"EventName": "op_is_rd",
97
+
"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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+
"BriefDescription": "A Write CAS command to DRAM.",
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+
"ConfigCode": "0x10",
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+
"EventName": "op_is_wr",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A Masked Write command to DRAM.",
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"ConfigCode": "0x11",
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+
"EventName": "op_is_mwr",
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+
"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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+
"BriefDescription": "A Precharge(PRE) command to DRAM.",
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"ConfigCode": "0x12",
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"EventName": "op_is_precharge",
118
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A Precharge(PRE) required by read or write.",
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"ConfigCode": "0x13",
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"EventName": "precharge_for_rdwr",
125
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A Precharge(PRE) required by other conditions.",
130
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"ConfigCode": "0x14",
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"EventName": "precharge_for_other",
132
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"Unit": "ali_drw",
133
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A read-write turnaround.",
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"ConfigCode": "0x15",
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"EventName": "rdwr_transitions",
139
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
141
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},
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{
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"BriefDescription": "A write combine(merge) in write data buffer.",
144
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"ConfigCode": "0x16",
145
+
"EventName": "write_combine",
146
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"Unit": "ali_drw",
147
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"Compat": "ali_drw_pmu"
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+
},
149
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{
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"BriefDescription": "A Write-After-Read hazard.",
151
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"ConfigCode": "0x17",
152
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"EventName": "war_hazard",
153
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"Unit": "ali_drw",
154
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"Compat": "ali_drw_pmu"
155
+
},
156
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{
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"BriefDescription": "A Read-After-Write hazard.",
158
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"ConfigCode": "0x18",
159
+
"EventName": "raw_hazard",
160
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"Unit": "ali_drw",
161
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"Compat": "ali_drw_pmu"
162
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},
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{
164
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"BriefDescription": "A Write-After-Write hazard.",
165
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"ConfigCode": "0x19",
166
+
"EventName": "waw_hazard",
167
+
"Unit": "ali_drw",
168
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"Compat": "ali_drw_pmu"
169
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},
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{
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+
"BriefDescription": "Rank0 enters self-refresh(SRE).",
172
+
"ConfigCode": "0x1A",
173
+
"EventName": "op_is_enter_selfref_rk0",
174
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "Rank1 enters self-refresh(SRE).",
179
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"ConfigCode": "0x1B",
180
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"EventName": "op_is_enter_selfref_rk1",
181
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"Unit": "ali_drw",
182
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"Compat": "ali_drw_pmu"
183
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},
184
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{
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"BriefDescription": "Rank2 enters self-refresh(SRE).",
186
+
"ConfigCode": "0x1C",
187
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"EventName": "op_is_enter_selfref_rk2",
188
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"Unit": "ali_drw",
189
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "Rank3 enters self-refresh(SRE).",
193
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"ConfigCode": "0x1D",
194
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"EventName": "op_is_enter_selfref_rk3",
195
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"Unit": "ali_drw",
196
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"Compat": "ali_drw_pmu"
197
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},
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{
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"BriefDescription": "Rank0 enters power-down(PDE).",
200
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"ConfigCode": "0x1E",
201
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"EventName": "op_is_enter_powerdown_rk0",
202
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"Unit": "ali_drw",
203
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"Compat": "ali_drw_pmu"
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},
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{
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+
"BriefDescription": "Rank1 enters power-down(PDE).",
207
+
"ConfigCode": "0x1F",
208
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"EventName": "op_is_enter_powerdown_rk1",
209
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"Unit": "ali_drw",
210
+
"Compat": "ali_drw_pmu"
211
+
},
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{
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+
"BriefDescription": "Rank2 enters power-down(PDE).",
214
+
"ConfigCode": "0x20",
215
+
"EventName": "op_is_enter_powerdown_rk2",
216
+
"Unit": "ali_drw",
217
+
"Compat": "ali_drw_pmu"
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},
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{
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+
"BriefDescription": "Rank3 enters power-down(PDE).",
221
+
"ConfigCode": "0x21",
222
+
"EventName": "op_is_enter_powerdown_rk3",
223
+
"Unit": "ali_drw",
224
+
"Compat": "ali_drw_pmu"
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+
},
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+
{
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+
"BriefDescription": "A cycle that Rank0 stays in self-refresh mode.",
228
+
"ConfigCode": "0x26",
229
+
"EventName": "selfref_mode_rk0",
230
+
"Unit": "ali_drw",
231
+
"Compat": "ali_drw_pmu"
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+
},
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+
{
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+
"BriefDescription": "A cycle that Rank1 stays in self-refresh mode.",
235
+
"ConfigCode": "0x27",
236
+
"EventName": "selfref_mode_rk1",
237
+
"Unit": "ali_drw",
238
+
"Compat": "ali_drw_pmu"
239
+
},
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+
{
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+
"BriefDescription": "A cycle that Rank2 stays in self-refresh mode.",
242
+
"ConfigCode": "0x28",
243
+
"EventName": "selfref_mode_rk2",
244
+
"Unit": "ali_drw",
245
+
"Compat": "ali_drw_pmu"
246
+
},
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+
{
248
+
"BriefDescription": "A cycle that Rank3 stays in self-refresh mode.",
249
+
"ConfigCode": "0x29",
250
+
"EventName": "selfref_mode_rk3",
251
+
"Unit": "ali_drw",
252
+
"Compat": "ali_drw_pmu"
253
+
},
254
+
{
255
+
"BriefDescription": "An auto-refresh(REF) command to DRAM.",
256
+
"ConfigCode": "0x2A",
257
+
"EventName": "op_is_refresh",
258
+
"Unit": "ali_drw",
259
+
"Compat": "ali_drw_pmu"
260
+
},
261
+
{
262
+
"BriefDescription": "A critical auto-refresh(REF) command to DRAM.",
263
+
"ConfigCode": "0x2B",
264
+
"EventName": "op_is_crit_ref",
265
+
"Unit": "ali_drw",
266
+
"Compat": "ali_drw_pmu"
267
+
},
268
+
{
269
+
"BriefDescription": "An MRR or MRW command to DRAM.",
270
+
"ConfigCode": "0x2D",
271
+
"EventName": "op_is_load_mode",
272
+
"Unit": "ali_drw",
273
+
"Compat": "ali_drw_pmu"
274
+
},
275
+
{
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+
"BriefDescription": "A ZQCal command to DRAM.",
277
+
"ConfigCode": "0x2E",
278
+
"EventName": "op_is_zqcl",
279
+
"Unit": "ali_drw",
280
+
"Compat": "ali_drw_pmu"
281
+
},
282
+
{
283
+
"BriefDescription": "At least one entry in read queue reaches the visible window limit.",
284
+
"ConfigCode": "0x30",
285
+
"EventName": "visible_window_limit_reached_rd",
286
+
"Unit": "ali_drw",
287
+
"Compat": "ali_drw_pmu"
288
+
},
289
+
{
290
+
"BriefDescription": "At least one entry in write queue reaches the visible window limit.",
291
+
"ConfigCode": "0x31",
292
+
"EventName": "visible_window_limit_reached_wr",
293
+
"Unit": "ali_drw",
294
+
"Compat": "ali_drw_pmu"
295
+
},
296
+
{
297
+
"BriefDescription": "A DQS Oscillator MPC command to DRAM.",
298
+
"ConfigCode": "0x34",
299
+
"EventName": "op_is_dqsosc_mpc",
300
+
"Unit": "ali_drw",
301
+
"Compat": "ali_drw_pmu"
302
+
},
303
+
{
304
+
"BriefDescription": "A DQS Oscillator MRR command to DRAM.",
305
+
"ConfigCode": "0x35",
306
+
"EventName": "op_is_dqsosc_mrr",
307
+
"Unit": "ali_drw",
308
+
"Compat": "ali_drw_pmu"
309
+
},
310
+
{
311
+
"BriefDescription": "A Temperature Compensated Refresh(TCR) MRR command to DRAM.",
312
+
"ConfigCode": "0x36",
313
+
"EventName": "op_is_tcr_mrr",
314
+
"Unit": "ali_drw",
315
+
"Compat": "ali_drw_pmu"
316
+
},
317
+
{
318
+
"BriefDescription": "A ZQCal Start command to DRAM.",
319
+
"ConfigCode": "0x37",
320
+
"EventName": "op_is_zqstart",
321
+
"Unit": "ali_drw",
322
+
"Compat": "ali_drw_pmu"
323
+
},
324
+
{
325
+
"BriefDescription": "A ZQCal Latch command to DRAM.",
326
+
"ConfigCode": "0x38",
327
+
"EventName": "op_is_zqlatch",
328
+
"Unit": "ali_drw",
329
+
"Compat": "ali_drw_pmu"
330
+
},
331
+
{
332
+
"BriefDescription": "A packet at CHI TXREQ interface (request).",
333
+
"ConfigCode": "0x39",
334
+
"EventName": "chi_txreq",
335
+
"Unit": "ali_drw",
336
+
"Compat": "ali_drw_pmu"
337
+
},
338
+
{
339
+
"BriefDescription": "A packet at CHI TXDAT interface (read data).",
340
+
"ConfigCode": "0x3A",
341
+
"EventName": "chi_txdat",
342
+
"Unit": "ali_drw",
343
+
"Compat": "ali_drw_pmu"
344
+
},
345
+
{
346
+
"BriefDescription": "A packet at CHI RXDAT interface (write data).",
347
+
"ConfigCode": "0x3B",
348
+
"EventName": "chi_rxdat",
349
+
"Unit": "ali_drw",
350
+
"Compat": "ali_drw_pmu"
351
+
},
352
+
{
353
+
"BriefDescription": "A packet at CHI RXRSP interface.",
354
+
"ConfigCode": "0x3C",
355
+
"EventName": "chi_rxrsp",
356
+
"Unit": "ali_drw",
357
+
"Compat": "ali_drw_pmu"
358
+
},
359
+
{
360
+
"BriefDescription": "A violation detected in TZC.",
361
+
"ConfigCode": "0x3D",
362
+
"EventName": "tsz_vio",
363
+
"Unit": "ali_drw",
364
+
"Compat": "ali_drw_pmu"
365
+
},
366
+
{
367
+
"BriefDescription": "The ddr cycles.",
368
+
"ConfigCode": "0x80",
369
+
"EventName": "ddr_cycles",
370
+
"Unit": "ali_drw",
371
+
"Compat": "ali_drw_pmu"
372
+
}
373
+
]