Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/intel: add reg_bits.h for the various register content helpers
Add a shared header that's used by i915, xe, and i915 display.
Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/e641fe6dcecef92367471f3e0d150f9f47ae4edc.1772042022.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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drivers/gpu/drm/i915/i915_reg_defs.h
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drivers/gpu/drm/i915/i915_reg_defs.h
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#ifndef __I915_REG_DEFS__
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#define __I915_REG_DEFS__
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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/*
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* Wrappers over the generic fixed width BIT_U*() and GENMASK_U*()
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* implementations, for compatibility reasons with previous implementation.
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*/
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#define REG_GENMASK(high, low) GENMASK_U32(high, low)
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#define REG_GENMASK64(high, low) GENMASK_U64(high, low)
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#define REG_GENMASK16(high, low) GENMASK_U16(high, low)
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#define REG_GENMASK8(high, low) GENMASK_U8(high, low)
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#define REG_BIT(n) BIT_U32(n)
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#define REG_BIT64(n) BIT_U64(n)
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#define REG_BIT16(n) BIT_U16(n)
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#define REG_BIT8(n) BIT_U8(n)
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/*
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* Local integer constant expression version of is_power_of_2().
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*/
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#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
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/**
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* REG_FIELD_PREP() - Prepare a u32 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to put in the field
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*
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* Local copy of FIELD_PREP() to generate an integer constant expression, force
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* u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
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*
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* @return: @__val masked and shifted into the field defined by @__mask.
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*/
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#define REG_FIELD_PREP(__mask, __val) \
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((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
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BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
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BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
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BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
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BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
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/**
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* REG_FIELD_PREP8() - Prepare a u8 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to put in the field
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*
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* Local copy of FIELD_PREP() to generate an integer constant expression, force
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* u8 and for consistency with REG_FIELD_GET8(), REG_BIT8() and REG_GENMASK8().
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*
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* @return: @__val masked and shifted into the field defined by @__mask.
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*/
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#define REG_FIELD_PREP8(__mask, __val) \
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((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
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BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
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BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \
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BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
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BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
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/**
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* REG_FIELD_GET() - Extract a u32 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to extract the bitfield value from
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*
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* Local wrapper for FIELD_GET() to force u32 and for consistency with
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* REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
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*
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* @return: Masked and shifted value of the field defined by @__mask in @__val.
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*/
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#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
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/**
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* REG_FIELD_GET64() - Extract a u64 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to extract the bitfield value from
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*
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* Local wrapper for FIELD_GET() to force u64 and for consistency with
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* REG_GENMASK64().
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*
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* @return: Masked and shifted value of the field defined by @__mask in @__val.
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*/
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#define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val))
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/**
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* REG_FIELD_PREP16() - Prepare a u16 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to put in the field
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*
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* Local copy of FIELD_PREP16() to generate an integer constant
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* expression, force u8 and for consistency with
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* REG_FIELD_GET16(), REG_BIT16() and REG_GENMASK16().
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*
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* @return: @__val masked and shifted into the field defined by @__mask.
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*/
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#define REG_FIELD_PREP16(__mask, __val) \
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((u16)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
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BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
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BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U16_MAX) + \
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BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
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BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
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#define REG_MASKED_FIELD(mask, value) \
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(BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \
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BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \
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BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \
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((mask) << 16 | (value)))
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#define REG_MASKED_FIELD_ENABLE(a) \
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(__builtin_choose_expr(__builtin_constant_p(a), REG_MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); REG_MASKED_FIELD(_a, _a); })))
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#define REG_MASKED_FIELD_DISABLE(a) \
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(REG_MASKED_FIELD((a), 0))
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#include <drm/intel/reg_bits.h>
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/*
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* Given the first two numbers __a and __b of arbitrarily many evenly spaced
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* Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
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*/
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#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
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/**
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* REG_FIELD_GET8() - Extract a u8 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to extract the bitfield value from
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*
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* Local wrapper for FIELD_GET() to force u8 and for consistency with
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* REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
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*
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* @return: Masked and shifted value of the field defined by @__mask in @__val.
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*/
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#define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val))
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/**
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* REG_FIELD_MAX() - produce the maximum value representable by a field
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* @__mask: shifted mask defining the field's length and position
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*
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* Local wrapper for FIELD_MAX() to return the maximum bit value that can
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* be held in the field specified by @_mask, cast to u32 for consistency
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* with other macros.
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*/
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#define REG_FIELD_MAX(__mask) ((u32)FIELD_MAX(__mask))
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typedef struct {
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u32 reg;
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include/drm/intel/reg_bits.h
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include/drm/intel/reg_bits.h
···
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/* SPDX-License-Identifier: MIT */
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/* Copyright © 2026 Intel Corporation */
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#ifndef _REG_BITS_H_
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#define _REG_BITS_H_
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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/*
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* Wrappers over the generic fixed width BIT_U*() and GENMASK_U*()
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* implementations, for compatibility reasons with previous implementation.
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*/
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#define REG_GENMASK(high, low) GENMASK_U32(high, low)
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#define REG_GENMASK64(high, low) GENMASK_U64(high, low)
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#define REG_GENMASK16(high, low) GENMASK_U16(high, low)
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#define REG_GENMASK8(high, low) GENMASK_U8(high, low)
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#define REG_BIT(n) BIT_U32(n)
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#define REG_BIT64(n) BIT_U64(n)
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#define REG_BIT16(n) BIT_U16(n)
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#define REG_BIT8(n) BIT_U8(n)
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/*
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* Local integer constant expression version of is_power_of_2().
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*/
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#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
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/**
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* REG_FIELD_PREP8() - Prepare a u8 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to put in the field
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*
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* Local copy of FIELD_PREP() to generate an integer constant expression, force
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* u8 and for consistency with REG_FIELD_GET8(), REG_BIT8() and REG_GENMASK8().
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*
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* @return: @__val masked and shifted into the field defined by @__mask.
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*/
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#define REG_FIELD_PREP8(__mask, __val) \
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((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
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BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
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BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \
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BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
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BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
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/**
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* REG_FIELD_PREP16() - Prepare a u16 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to put in the field
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*
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* Local copy of FIELD_PREP16() to generate an integer constant
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* expression, force u8 and for consistency with
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* REG_FIELD_GET16(), REG_BIT16() and REG_GENMASK16().
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*
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* @return: @__val masked and shifted into the field defined by @__mask.
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*/
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#define REG_FIELD_PREP16(__mask, __val) \
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((u16)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
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BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
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BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U16_MAX) + \
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BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
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BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
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/**
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* REG_FIELD_PREP() - Prepare a u32 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to put in the field
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*
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* Local copy of FIELD_PREP() to generate an integer constant expression, force
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* u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
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*
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* @return: @__val masked and shifted into the field defined by @__mask.
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*/
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#define REG_FIELD_PREP(__mask, __val) \
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((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
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BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
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BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
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BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
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BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
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+
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/**
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* REG_FIELD_GET8() - Extract a u8 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to extract the bitfield value from
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*
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* Local wrapper for FIELD_GET() to force u8 and for consistency with
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* REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
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*
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* @return: Masked and shifted value of the field defined by @__mask in @__val.
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*/
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#define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val))
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+
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/**
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* REG_FIELD_GET() - Extract a u32 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to extract the bitfield value from
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*
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* Local wrapper for FIELD_GET() to force u32 and for consistency with
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* REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
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*
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* @return: Masked and shifted value of the field defined by @__mask in @__val.
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*/
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#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
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/**
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* REG_FIELD_GET64() - Extract a u64 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to extract the bitfield value from
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*
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* Local wrapper for FIELD_GET() to force u64 and for consistency with
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* REG_GENMASK64().
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*
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* @return: Masked and shifted value of the field defined by @__mask in @__val.
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*/
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#define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val))
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+
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/**
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* REG_FIELD_MAX() - produce the maximum value representable by a field
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* @__mask: shifted mask defining the field's length and position
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*
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* Local wrapper for FIELD_MAX() to return the maximum bit value that can
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* be held in the field specified by @_mask, cast to u32 for consistency
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* with other macros.
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*/
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#define REG_FIELD_MAX(__mask) ((u32)FIELD_MAX(__mask))
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+
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#define REG_MASKED_FIELD(mask, value) \
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(BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask), (mask) & 0xffff0000, 0)) + \
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BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(value), (value) & 0xffff0000, 0)) + \
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BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(mask) && __builtin_constant_p(value), (value) & ~(mask), 0)) + \
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((mask) << 16 | (value)))
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+
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#define REG_MASKED_FIELD_ENABLE(a) \
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(__builtin_choose_expr(__builtin_constant_p(a), REG_MASKED_FIELD((a), (a)), ({ typeof(a) _a = (a); REG_MASKED_FIELD(_a, _a); })))
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#define REG_MASKED_FIELD_DISABLE(a) \
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(REG_MASKED_FIELD((a), 0))
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+
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#endif