Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle:
"Random fixes across the MIPS tree. The two hotspots are several bugs
in the module loader and the ath79 SOC support; also noteworthy is the
restructuring of the code to synchronize CPU timers across CPUs on
startup; the old code recently ceased to work due to unrelated
changes.
All except one of these patches have sat for a significant time in
linux-next for testing."
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: pci-ar724x: avoid data bus error due to a missing PCIe module
MIPS: Malta: Delete duplicate PCI fixup.
MIPS: ath79: don't hardcode the unavailability of the DSP ASE
MIPS: Synchronize MIPS count one CPU at a time
MIPS: BCM63xx: Fix SPI message control register handling for BCM6338/6348.
MIPS: Module: Deal with malformed HI16/LO16 relocation sequences.
MIPS: Fix race condition in module relocation code.
MIPS: Fix memory leak in error path of HI16/LO16 relocation handling.
MIPS: MTX-1: Add udelay to mtx1_pci_idsel
MIPS: ath79: select HAVE_CLK
MIPS: ath79: Use correct IRQ number for the OHCI controller on AR7240
MIPS: ath79: Fix number of GPIO lines for AR724[12]
MIPS: Octeon: Fix broken interrupt controller code.
+170
-109
+1
arch/mips/Kconfig
+1
arch/mips/Kconfig
+2
arch/mips/alchemy/board-mtx1.c
+2
arch/mips/alchemy/board-mtx1.c
···
228
228
* adapter on the mtx-1 "singleboard" variant. It triggers a custom
229
229
* logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
230
230
*/
231
+
udelay(1);
232
+
231
233
if (assert && devsel != 0)
232
234
/* Suppress signal to Cardbus */
233
235
alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
+2
arch/mips/ath79/dev-usb.c
+2
arch/mips/ath79/dev-usb.c
···
145
145
146
146
ath79_ohci_resources[0].start = AR7240_OHCI_BASE;
147
147
ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1;
148
+
ath79_ohci_resources[1].start = ATH79_CPU_IRQ_USB;
149
+
ath79_ohci_resources[1].end = ATH79_CPU_IRQ_USB;
148
150
platform_device_register(&ath79_ohci_device);
149
151
}
150
152
+4
-2
arch/mips/ath79/gpio.c
+4
-2
arch/mips/ath79/gpio.c
···
188
188
189
189
if (soc_is_ar71xx())
190
190
ath79_gpio_count = AR71XX_GPIO_COUNT;
191
-
else if (soc_is_ar724x())
192
-
ath79_gpio_count = AR724X_GPIO_COUNT;
191
+
else if (soc_is_ar7240())
192
+
ath79_gpio_count = AR7240_GPIO_COUNT;
193
+
else if (soc_is_ar7241() || soc_is_ar7242())
194
+
ath79_gpio_count = AR7241_GPIO_COUNT;
193
195
else if (soc_is_ar913x())
194
196
ath79_gpio_count = AR913X_GPIO_COUNT;
195
197
else if (soc_is_ar933x())
+4
arch/mips/bcm63xx/dev-spi.c
+4
arch/mips/bcm63xx/dev-spi.c
···
106
106
if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
107
107
spi_resources[0].end += BCM_6338_RSET_SPI_SIZE - 1;
108
108
spi_pdata.fifo_size = SPI_6338_MSG_DATA_SIZE;
109
+
spi_pdata.msg_type_shift = SPI_6338_MSG_TYPE_SHIFT;
110
+
spi_pdata.msg_ctl_width = SPI_6338_MSG_CTL_WIDTH;
109
111
}
110
112
111
113
if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
112
114
spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
113
115
spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
116
+
spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
117
+
spi_pdata.msg_ctl_width = SPI_6358_MSG_CTL_WIDTH;
114
118
}
115
119
116
120
bcm63xx_spi_regs_init();
+43
-46
arch/mips/cavium-octeon/octeon-irq.c
+43
-46
arch/mips/cavium-octeon/octeon-irq.c
···
61
61
octeon_irq_ciu_to_irq[line][bit] = irq;
62
62
}
63
63
64
+
static void octeon_irq_force_ciu_mapping(struct irq_domain *domain,
65
+
int irq, int line, int bit)
66
+
{
67
+
irq_domain_associate(domain, irq, line << 6 | bit);
68
+
}
69
+
64
70
static int octeon_coreid_for_cpu(int cpu)
65
71
{
66
72
#ifdef CONFIG_SMP
···
189
183
mutex_init(&cd->core_irq_mutex);
190
184
191
185
irq = OCTEON_IRQ_SW0 + i;
192
-
switch (irq) {
193
-
case OCTEON_IRQ_TIMER:
194
-
case OCTEON_IRQ_SW0:
195
-
case OCTEON_IRQ_SW1:
196
-
case OCTEON_IRQ_5:
197
-
case OCTEON_IRQ_PERF:
198
-
irq_set_chip_data(irq, cd);
199
-
irq_set_chip_and_handler(irq, &octeon_irq_chip_core,
200
-
handle_percpu_irq);
201
-
break;
202
-
default:
203
-
break;
204
-
}
186
+
irq_set_chip_data(irq, cd);
187
+
irq_set_chip_and_handler(irq, &octeon_irq_chip_core,
188
+
handle_percpu_irq);
205
189
}
206
190
}
207
191
···
886
890
unsigned int type;
887
891
unsigned int pin;
888
892
unsigned int trigger;
889
-
struct octeon_irq_gpio_domain_data *gpiod;
890
893
891
894
if (d->of_node != node)
892
895
return -EINVAL;
···
920
925
break;
921
926
}
922
927
*out_type = type;
923
-
gpiod = d->host_data;
924
-
*out_hwirq = gpiod->base_hwirq + pin;
928
+
*out_hwirq = pin;
925
929
926
930
return 0;
927
931
}
···
990
996
static int octeon_irq_gpio_map(struct irq_domain *d,
991
997
unsigned int virq, irq_hw_number_t hw)
992
998
{
993
-
unsigned int line = hw >> 6;
994
-
unsigned int bit = hw & 63;
999
+
struct octeon_irq_gpio_domain_data *gpiod = d->host_data;
1000
+
unsigned int line, bit;
995
1001
996
1002
if (!octeon_irq_virq_in_range(virq))
997
1003
return -EINVAL;
998
1004
1005
+
hw += gpiod->base_hwirq;
1006
+
line = hw >> 6;
1007
+
bit = hw & 63;
999
1008
if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0)
1000
1009
return -EINVAL;
1001
1010
1002
1011
octeon_irq_set_ciu_mapping(virq, line, bit,
1003
1012
octeon_irq_gpio_chip,
1004
1013
octeon_irq_handle_gpio);
1005
-
1006
1014
return 0;
1007
1015
}
1008
1016
···
1145
1149
struct irq_chip *chip_wd;
1146
1150
struct device_node *gpio_node;
1147
1151
struct device_node *ciu_node;
1152
+
struct irq_domain *ciu_domain = NULL;
1148
1153
1149
1154
octeon_irq_init_ciu_percpu();
1150
1155
octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu;
···
1174
1177
/* Mips internal */
1175
1178
octeon_irq_init_core();
1176
1179
1177
-
/* CIU_0 */
1178
-
for (i = 0; i < 16; i++)
1179
-
octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq);
1180
-
1181
-
octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq);
1182
-
octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq);
1183
-
1184
-
for (i = 0; i < 4; i++)
1185
-
octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq);
1186
-
for (i = 0; i < 4; i++)
1187
-
octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq);
1188
-
1189
-
octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq);
1190
-
for (i = 0; i < 4; i++)
1191
-
octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip, handle_edge_irq);
1192
-
1193
-
octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq);
1194
-
octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq);
1195
-
1196
-
/* CIU_1 */
1197
-
for (i = 0; i < 16; i++)
1198
-
octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq);
1199
-
1200
-
octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq);
1201
-
1202
1180
gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio");
1203
1181
if (gpio_node) {
1204
1182
struct octeon_irq_gpio_domain_data *gpiod;
···
1191
1219
1192
1220
ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu");
1193
1221
if (ciu_node) {
1194
-
irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL);
1222
+
ciu_domain = irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL);
1195
1223
of_node_put(ciu_node);
1196
1224
} else
1197
-
pr_warn("Cannot find device node for cavium,octeon-3860-ciu.\n");
1225
+
panic("Cannot find device node for cavium,octeon-3860-ciu.");
1226
+
1227
+
/* CIU_0 */
1228
+
for (i = 0; i < 16; i++)
1229
+
octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i + 0);
1230
+
1231
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq);
1232
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq);
1233
+
1234
+
for (i = 0; i < 4; i++)
1235
+
octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_INT0, 0, i + 36);
1236
+
for (i = 0; i < 4; i++)
1237
+
octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 0, i + 40);
1238
+
1239
+
octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_RML, 0, 46);
1240
+
for (i = 0; i < 4; i++)
1241
+
octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52);
1242
+
1243
+
octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 0, 56);
1244
+
octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_BOOTDMA, 0, 63);
1245
+
1246
+
/* CIU_1 */
1247
+
for (i = 0; i < 16; i++)
1248
+
octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq);
1249
+
1250
+
octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB1, 1, 17);
1198
1251
1199
1252
/* Enable the CIU lines */
1200
1253
set_c0_status(STATUSF_IP3 | STATUSF_IP2);
+2
-1
arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+2
-1
arch/mips/include/asm/mach-ath79/ar71xx_regs.h
···
393
393
#define AR71XX_GPIO_REG_FUNC 0x28
394
394
395
395
#define AR71XX_GPIO_COUNT 16
396
-
#define AR724X_GPIO_COUNT 18
396
+
#define AR7240_GPIO_COUNT 18
397
+
#define AR7241_GPIO_COUNT 20
397
398
#define AR913X_GPIO_COUNT 22
398
399
#define AR933X_GPIO_COUNT 30
399
400
#define AR934X_GPIO_COUNT 23
-1
arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
-1
arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
+2
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
+2
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
+10
-3
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+10
-3
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
···
1054
1054
#define SPI_6338_FILL_BYTE 0x07
1055
1055
#define SPI_6338_MSG_TAIL 0x09
1056
1056
#define SPI_6338_RX_TAIL 0x0b
1057
-
#define SPI_6338_MSG_CTL 0x40
1057
+
#define SPI_6338_MSG_CTL 0x40 /* 8-bits register */
1058
+
#define SPI_6338_MSG_CTL_WIDTH 8
1058
1059
#define SPI_6338_MSG_DATA 0x41
1059
1060
#define SPI_6338_MSG_DATA_SIZE 0x3f
1060
1061
#define SPI_6338_RX_DATA 0x80
···
1071
1070
#define SPI_6348_FILL_BYTE 0x07
1072
1071
#define SPI_6348_MSG_TAIL 0x09
1073
1072
#define SPI_6348_RX_TAIL 0x0b
1074
-
#define SPI_6348_MSG_CTL 0x40
1073
+
#define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
1074
+
#define SPI_6348_MSG_CTL_WIDTH 8
1075
1075
#define SPI_6348_MSG_DATA 0x41
1076
1076
#define SPI_6348_MSG_DATA_SIZE 0x3f
1077
1077
#define SPI_6348_RX_DATA 0x80
···
1080
1078
1081
1079
/* BCM 6358 SPI core */
1082
1080
#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
1081
+
#define SPI_6358_MSG_CTL_WIDTH 16
1083
1082
#define SPI_6358_MSG_DATA 0x02
1084
1083
#define SPI_6358_MSG_DATA_SIZE 0x21e
1085
1084
#define SPI_6358_RX_DATA 0x400
···
1097
1094
1098
1095
/* BCM 6358 SPI core */
1099
1096
#define SPI_6368_MSG_CTL 0x00 /* 16-bits register */
1097
+
#define SPI_6368_MSG_CTL_WIDTH 16
1100
1098
#define SPI_6368_MSG_DATA 0x02
1101
1099
#define SPI_6368_MSG_DATA_SIZE 0x21e
1102
1100
#define SPI_6368_RX_DATA 0x400
···
1119
1115
#define SPI_HD_W 0x01
1120
1116
#define SPI_HD_R 0x02
1121
1117
#define SPI_BYTE_CNT_SHIFT 0
1122
-
#define SPI_MSG_TYPE_SHIFT 14
1118
+
#define SPI_6338_MSG_TYPE_SHIFT 6
1119
+
#define SPI_6348_MSG_TYPE_SHIFT 6
1120
+
#define SPI_6358_MSG_TYPE_SHIFT 14
1121
+
#define SPI_6368_MSG_TYPE_SHIFT 14
1123
1122
1124
1123
/* Command */
1125
1124
#define SPI_CMD_NOOP 0x00
+1
-9
arch/mips/include/asm/mach-cavium-octeon/irq.h
+1
-9
arch/mips/include/asm/mach-cavium-octeon/irq.h
···
21
21
OCTEON_IRQ_TIMER,
22
22
/* sources in CIU_INTX_EN0 */
23
23
OCTEON_IRQ_WORKQ0,
24
-
OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16,
25
-
OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16,
24
+
OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 16,
26
25
OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
27
26
OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
28
27
OCTEON_IRQ_MBOX1,
29
-
OCTEON_IRQ_UART0,
30
-
OCTEON_IRQ_UART1,
31
-
OCTEON_IRQ_UART2,
32
28
OCTEON_IRQ_PCI_INT0,
33
29
OCTEON_IRQ_PCI_INT1,
34
30
OCTEON_IRQ_PCI_INT2,
···
34
38
OCTEON_IRQ_PCI_MSI2,
35
39
OCTEON_IRQ_PCI_MSI3,
36
40
37
-
OCTEON_IRQ_TWSI,
38
-
OCTEON_IRQ_TWSI2,
39
41
OCTEON_IRQ_RML,
40
42
OCTEON_IRQ_TIMER0,
41
43
OCTEON_IRQ_TIMER1,
···
41
47
OCTEON_IRQ_TIMER3,
42
48
OCTEON_IRQ_USB0,
43
49
OCTEON_IRQ_USB1,
44
-
OCTEON_IRQ_MII0,
45
-
OCTEON_IRQ_MII1,
46
50
OCTEON_IRQ_BOOTDMA,
47
51
#ifndef CONFIG_PCI_MSI
48
52
OCTEON_IRQ_LAST = 127
+1
arch/mips/include/asm/module.h
+1
arch/mips/include/asm/module.h
+4
-4
arch/mips/include/asm/r4k-timer.h
+4
-4
arch/mips/include/asm/r4k-timer.h
···
12
12
13
13
#ifdef CONFIG_SYNC_R4K
14
14
15
-
extern void synchronise_count_master(void);
16
-
extern void synchronise_count_slave(void);
15
+
extern void synchronise_count_master(int cpu);
16
+
extern void synchronise_count_slave(int cpu);
17
17
18
18
#else
19
19
20
-
static inline void synchronise_count_master(void)
20
+
static inline void synchronise_count_master(int cpu)
21
21
{
22
22
}
23
23
24
-
static inline void synchronise_count_slave(void)
24
+
static inline void synchronise_count_slave(int cpu)
25
25
{
26
26
}
27
27
+34
-9
arch/mips/kernel/module.c
+34
-9
arch/mips/kernel/module.c
···
39
39
Elf_Addr value;
40
40
};
41
41
42
-
static struct mips_hi16 *mips_hi16_list;
43
-
44
42
static LIST_HEAD(dbe_list);
45
43
static DEFINE_SPINLOCK(dbe_lock);
46
44
···
126
128
127
129
n->addr = (Elf_Addr *)location;
128
130
n->value = v;
129
-
n->next = mips_hi16_list;
130
-
mips_hi16_list = n;
131
+
n->next = me->arch.r_mips_hi16_list;
132
+
me->arch.r_mips_hi16_list = n;
131
133
132
134
return 0;
133
135
}
···
140
142
return 0;
141
143
}
142
144
145
+
static void free_relocation_chain(struct mips_hi16 *l)
146
+
{
147
+
struct mips_hi16 *next;
148
+
149
+
while (l) {
150
+
next = l->next;
151
+
kfree(l);
152
+
l = next;
153
+
}
154
+
}
155
+
143
156
static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v)
144
157
{
145
158
unsigned long insnlo = *location;
159
+
struct mips_hi16 *l;
146
160
Elf_Addr val, vallo;
147
161
148
162
/* Sign extend the addend we extract from the lo insn. */
149
163
vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
150
164
151
-
if (mips_hi16_list != NULL) {
152
-
struct mips_hi16 *l;
153
-
154
-
l = mips_hi16_list;
165
+
if (me->arch.r_mips_hi16_list != NULL) {
166
+
l = me->arch.r_mips_hi16_list;
155
167
while (l != NULL) {
156
168
struct mips_hi16 *next;
157
169
unsigned long insn;
···
196
188
l = next;
197
189
}
198
190
199
-
mips_hi16_list = NULL;
191
+
me->arch.r_mips_hi16_list = NULL;
200
192
}
201
193
202
194
/*
···
209
201
return 0;
210
202
211
203
out_danger:
204
+
free_relocation_chain(l);
205
+
me->arch.r_mips_hi16_list = NULL;
206
+
212
207
pr_err("module %s: dangerous R_MIPS_LO16 REL relocation\n", me->name);
213
208
214
209
return -ENOEXEC;
···
284
273
pr_debug("Applying relocate section %u to %u\n", relsec,
285
274
sechdrs[relsec].sh_info);
286
275
276
+
me->arch.r_mips_hi16_list = NULL;
287
277
for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
288
278
/* This is where to make the change */
289
279
location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
···
306
294
res = reloc_handlers_rel[ELF_MIPS_R_TYPE(rel[i])](me, location, v);
307
295
if (res)
308
296
return res;
297
+
}
298
+
299
+
/*
300
+
* Normally the hi16 list should be deallocated at this point. A
301
+
* malformed binary however could contain a series of R_MIPS_HI16
302
+
* relocations not followed by a R_MIPS_LO16 relocation. In that
303
+
* case, free up the list and return an error.
304
+
*/
305
+
if (me->arch.r_mips_hi16_list) {
306
+
free_relocation_chain(me->arch.r_mips_hi16_list);
307
+
me->arch.r_mips_hi16_list = NULL;
308
+
309
+
return -ENOEXEC;
309
310
}
310
311
311
312
return 0;
+2
-2
arch/mips/kernel/smp.c
+2
-2
arch/mips/kernel/smp.c
···
130
130
131
131
cpu_set(cpu, cpu_callin_map);
132
132
133
-
synchronise_count_slave();
133
+
synchronise_count_slave(cpu);
134
134
135
135
/*
136
136
* irq will be enabled in ->smp_finish(), enabling it too early
···
173
173
void __init smp_cpus_done(unsigned int max_cpus)
174
174
{
175
175
mp_ops->cpus_done();
176
-
synchronise_count_master();
177
176
}
178
177
179
178
/* called from main before smp_init() */
···
205
206
while (!cpu_isset(cpu, cpu_callin_map))
206
207
udelay(100);
207
208
209
+
synchronise_count_master(cpu);
208
210
return 0;
209
211
}
210
212
+11
-15
arch/mips/kernel/sync-r4k.c
+11
-15
arch/mips/kernel/sync-r4k.c
···
28
28
#define COUNTON 100
29
29
#define NR_LOOPS 5
30
30
31
-
void __cpuinit synchronise_count_master(void)
31
+
void __cpuinit synchronise_count_master(int cpu)
32
32
{
33
33
int i;
34
34
unsigned long flags;
35
35
unsigned int initcount;
36
-
int nslaves;
37
36
38
37
#ifdef CONFIG_MIPS_MT_SMTC
39
38
/*
···
42
43
return;
43
44
#endif
44
45
45
-
printk(KERN_INFO "Synchronize counters across %u CPUs: ",
46
-
num_online_cpus());
46
+
printk(KERN_INFO "Synchronize counters for CPU %u: ", cpu);
47
47
48
48
local_irq_save(flags);
49
49
···
50
52
* Notify the slaves that it's time to start
51
53
*/
52
54
atomic_set(&count_reference, read_c0_count());
53
-
atomic_set(&count_start_flag, 1);
55
+
atomic_set(&count_start_flag, cpu);
54
56
smp_wmb();
55
57
56
58
/* Count will be initialised to current timer for all CPU's */
···
67
69
* two CPUs.
68
70
*/
69
71
70
-
nslaves = num_online_cpus()-1;
71
72
for (i = 0; i < NR_LOOPS; i++) {
72
-
/* slaves loop on '!= ncpus' */
73
-
while (atomic_read(&count_count_start) != nslaves)
73
+
/* slaves loop on '!= 2' */
74
+
while (atomic_read(&count_count_start) != 1)
74
75
mb();
75
76
atomic_set(&count_count_stop, 0);
76
77
smp_wmb();
···
86
89
/*
87
90
* Wait for all slaves to leave the synchronization point:
88
91
*/
89
-
while (atomic_read(&count_count_stop) != nslaves)
92
+
while (atomic_read(&count_count_stop) != 1)
90
93
mb();
91
94
atomic_set(&count_count_start, 0);
92
95
smp_wmb();
···
94
97
}
95
98
/* Arrange for an interrupt in a short while */
96
99
write_c0_compare(read_c0_count() + COUNTON);
100
+
atomic_set(&count_start_flag, 0);
97
101
98
102
local_irq_restore(flags);
99
103
···
106
108
printk("done.\n");
107
109
}
108
110
109
-
void __cpuinit synchronise_count_slave(void)
111
+
void __cpuinit synchronise_count_slave(int cpu)
110
112
{
111
113
int i;
112
114
unsigned int initcount;
113
-
int ncpus;
114
115
115
116
#ifdef CONFIG_MIPS_MT_SMTC
116
117
/*
···
124
127
* so we first wait for the master to say everyone is ready
125
128
*/
126
129
127
-
while (!atomic_read(&count_start_flag))
130
+
while (atomic_read(&count_start_flag) != cpu)
128
131
mb();
129
132
130
133
/* Count will be initialised to next expire for all CPU's */
131
134
initcount = atomic_read(&count_reference);
132
135
133
-
ncpus = num_online_cpus();
134
136
for (i = 0; i < NR_LOOPS; i++) {
135
137
atomic_inc(&count_count_start);
136
-
while (atomic_read(&count_count_start) != ncpus)
138
+
while (atomic_read(&count_count_start) != 2)
137
139
mb();
138
140
139
141
/*
···
142
146
write_c0_count(initcount);
143
147
144
148
atomic_inc(&count_count_stop);
145
-
while (atomic_read(&count_count_stop) != ncpus)
149
+
while (atomic_read(&count_count_stop) != 2)
146
150
mb();
147
151
}
148
152
/* Arrange for an interrupt in a short while */
-13
arch/mips/mti-malta/malta-pci.c
-13
arch/mips/mti-malta/malta-pci.c
···
252
252
253
253
register_pci_controller(controller);
254
254
}
255
-
256
-
/* Enable PCI 2.1 compatibility in PIIX4 */
257
-
static void __devinit quirk_dlcsetup(struct pci_dev *dev)
258
-
{
259
-
u8 odlc, ndlc;
260
-
(void) pci_read_config_byte(dev, 0x82, &odlc);
261
-
/* Enable passive releases and delayed transaction */
262
-
ndlc = odlc | 7;
263
-
(void) pci_write_config_byte(dev, 0x82, ndlc);
264
-
}
265
-
266
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
267
-
quirk_dlcsetup);
+22
arch/mips/pci/pci-ar724x.c
+22
arch/mips/pci/pci-ar724x.c
···
23
23
#define AR724X_PCI_MEM_BASE 0x10000000
24
24
#define AR724X_PCI_MEM_SIZE 0x08000000
25
25
26
+
#define AR724X_PCI_REG_RESET 0x18
26
27
#define AR724X_PCI_REG_INT_STATUS 0x4c
27
28
#define AR724X_PCI_REG_INT_MASK 0x50
29
+
30
+
#define AR724X_PCI_RESET_LINK_UP BIT(0)
28
31
29
32
#define AR724X_PCI_INT_DEV0 BIT(14)
30
33
···
41
38
42
39
static u32 ar724x_pci_bar0_value;
43
40
static bool ar724x_pci_bar0_is_cached;
41
+
static bool ar724x_pci_link_up;
42
+
43
+
static inline bool ar724x_pci_check_link(void)
44
+
{
45
+
u32 reset;
46
+
47
+
reset = __raw_readl(ar724x_pci_ctrl_base + AR724X_PCI_REG_RESET);
48
+
return reset & AR724X_PCI_RESET_LINK_UP;
49
+
}
44
50
45
51
static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
46
52
int size, uint32_t *value)
···
57
45
unsigned long flags;
58
46
void __iomem *base;
59
47
u32 data;
48
+
49
+
if (!ar724x_pci_link_up)
50
+
return PCIBIOS_DEVICE_NOT_FOUND;
60
51
61
52
if (devfn)
62
53
return PCIBIOS_DEVICE_NOT_FOUND;
···
110
95
void __iomem *base;
111
96
u32 data;
112
97
int s;
98
+
99
+
if (!ar724x_pci_link_up)
100
+
return PCIBIOS_DEVICE_NOT_FOUND;
113
101
114
102
if (devfn)
115
103
return PCIBIOS_DEVICE_NOT_FOUND;
···
297
279
AR724X_PCI_CTRL_SIZE);
298
280
if (ar724x_pci_ctrl_base == NULL)
299
281
goto err_unmap_devcfg;
282
+
283
+
ar724x_pci_link_up = ar724x_pci_check_link();
284
+
if (!ar724x_pci_link_up)
285
+
pr_warn("ar724x: PCIe link is down\n");
300
286
301
287
ar724x_pci_irq_init(irq);
302
288
register_pci_controller(&ar724x_pci_controller);
+25
-4
drivers/spi/spi-bcm63xx.c
+25
-4
drivers/spi/spi-bcm63xx.c
···
47
47
/* Platform data */
48
48
u32 speed_hz;
49
49
unsigned fifo_size;
50
+
unsigned int msg_type_shift;
51
+
unsigned int msg_ctl_width;
50
52
51
53
/* Data buffers */
52
54
const unsigned char *tx_ptr;
···
223
221
msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
224
222
225
223
if (t->rx_buf && t->tx_buf)
226
-
msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
224
+
msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
227
225
else if (t->rx_buf)
228
-
msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
226
+
msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
229
227
else if (t->tx_buf)
230
-
msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
228
+
msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
231
229
232
-
bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
230
+
switch (bs->msg_ctl_width) {
231
+
case 8:
232
+
bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
233
+
break;
234
+
case 16:
235
+
bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
236
+
break;
237
+
}
233
238
234
239
/* Issue the transfer */
235
240
cmd = SPI_CMD_START_IMMEDIATE;
···
415
406
master->transfer_one_message = bcm63xx_spi_transfer_one;
416
407
master->mode_bits = MODEBITS;
417
408
bs->speed_hz = pdata->speed_hz;
409
+
bs->msg_type_shift = pdata->msg_type_shift;
410
+
bs->msg_ctl_width = pdata->msg_ctl_width;
418
411
bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
419
412
bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
413
+
414
+
switch (bs->msg_ctl_width) {
415
+
case 8:
416
+
case 16:
417
+
break;
418
+
default:
419
+
dev_err(dev, "unsupported MSG_CTL width: %d\n",
420
+
bs->msg_ctl_width);
421
+
goto out_clk_disable;
422
+
}
420
423
421
424
/* Initialize hardware */
422
425
clk_enable(bs->clk);