Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: rework common ucode handling for vega10
Handle ucode differences in vega10.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Huang Rui
and committed by
Alex Deucher
2445b227
9079ac76
+52
-22
+1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
+1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
+46
-22
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+46
-22
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
···
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return AMDGPU_FW_LOAD_DIRECT;
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}
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-
static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode,
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uint64_t mc_addr, void *kptr)
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static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
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struct amdgpu_firmware_info *ucode,
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uint64_t mc_addr, void *kptr)
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{
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const struct common_firmware_header *header = NULL;
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const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
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if (NULL == ucode->fw)
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return 0;
···
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header = (const struct common_firmware_header *)ucode->fw->data;
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-
ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
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cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
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memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
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le32_to_cpu(header->ucode_array_offset_bytes)),
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ucode->ucode_size);
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if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
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(ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
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ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
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ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
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ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT)) {
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ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
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+
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memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
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le32_to_cpu(header->ucode_array_offset_bytes)),
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ucode->ucode_size);
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} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 ||
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ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) {
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ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
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le32_to_cpu(cp_hdr->jt_size) * 4;
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+
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memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
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le32_to_cpu(header->ucode_array_offset_bytes)),
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ucode->ucode_size);
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} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
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ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) {
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ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
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+
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memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
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le32_to_cpu(header->ucode_array_offset_bytes) +
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le32_to_cpu(cp_hdr->jt_offset) * 4),
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ucode->ucode_size);
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}
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return 0;
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}
···
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(le32_to_cpu(header->jt_offset) * 4);
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memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
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ucode->ucode_size += le32_to_cpu(header->jt_size) * 4;
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return 0;
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}
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-
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int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
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{
···
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uint64_t fw_mc_addr;
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void *fw_buf_ptr = NULL;
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uint64_t fw_offset = 0;
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int i, err, max;
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int i, err;
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struct amdgpu_firmware_info *ucode = NULL;
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const struct common_firmware_header *header = NULL;
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···
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amdgpu_bo_unreserve(*bo);
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memset(fw_buf_ptr, 0, adev->firmware.fw_size);
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/*
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* if SMU loaded firmware, it needn't add SMC, UVD, and VCE
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* ucode info here
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*/
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if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
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max = AMDGPU_UCODE_ID_MAXIMUM - 3;
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adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
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else
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max = AMDGPU_UCODE_ID_MAXIMUM;
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adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
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for (i = 0; i < max; i++) {
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for (i = 0; i < adev->firmware.max_ucodes; i++) {
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ucode = &adev->firmware.ucode[i];
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if (ucode->fw) {
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header = (const struct common_firmware_header *)ucode->fw->data;
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amdgpu_ucode_init_single_fw(ucode, fw_mc_addr + fw_offset,
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fw_buf_ptr + fw_offset);
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if (i == AMDGPU_UCODE_ID_CP_MEC1) {
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amdgpu_ucode_init_single_fw(adev, ucode, fw_mc_addr + fw_offset,
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(void *)((uint8_t *)fw_buf_ptr + fw_offset));
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if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
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adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
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const struct gfx_firmware_header_v1_0 *cp_hdr;
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cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
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amdgpu_ucode_patch_jt(ucode, fw_mc_addr + fw_offset,
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fw_buf_ptr + fw_offset);
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fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
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}
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fw_offset += ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
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fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
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}
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}
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return 0;
···
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{
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int i;
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struct amdgpu_firmware_info *ucode = NULL;
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int max;
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if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
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max = AMDGPU_UCODE_ID_MAXIMUM - 3;
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else
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max = AMDGPU_UCODE_ID_MAXIMUM;
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for (i = 0; i < max; i++) {
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for (i = 0; i < adev->firmware.max_ucodes; i++) {
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ucode = &adev->firmware.ucode[i];
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if (ucode->fw) {
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ucode->mc_addr = 0;
+5
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+5
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
···
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AMDGPU_UCODE_ID_CP_PFP,
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AMDGPU_UCODE_ID_CP_ME,
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AMDGPU_UCODE_ID_CP_MEC1,
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AMDGPU_UCODE_ID_CP_MEC1_JT,
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AMDGPU_UCODE_ID_CP_MEC2,
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AMDGPU_UCODE_ID_CP_MEC2_JT,
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AMDGPU_UCODE_ID_RLC_G,
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AMDGPU_UCODE_ID_STORAGE,
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AMDGPU_UCODE_ID_SMC,
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AMDGPU_UCODE_ID_UVD,
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AMDGPU_UCODE_ID_VCE,
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AMDGPU_UCODE_ID_MAXIMUM,
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};
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