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Revert "drm/amd/display: Rework YCbCr422 DSC policy"

Revert commit 19b79e4f2182 ("drm/amd/display: Rework YCbCr422 DSC policy")

Reason for Revert:
This commit is causing compliance failures

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Relja Vojvodic and committed by
Alex Deucher
246808e7 4d55784b

+18 -22
+1 -1
drivers/gpu/drm/amd/display/dc/dc.h
··· 563 563 bool frame_update_cmd_version2; 564 564 struct spl_sharpness_range dcn_sharpness_range; 565 565 struct spl_sharpness_range dcn_override_sharpness_range; 566 - bool no_native422_support; 567 566 }; 568 567 569 568 enum visual_confirm { ··· 987 988 * causing an issue or not. 988 989 */ 989 990 struct dc_debug_options { 991 + bool native422_support; 990 992 bool disable_dsc; 991 993 enum visual_confirm visual_confirm; 992 994 int visual_confirm_rect_height;
-1
drivers/gpu/drm/amd/display/dc/dc_dsc.h
··· 52 52 uint32_t max_target_bpp; 53 53 uint32_t min_target_bpp; 54 54 bool enable_dsc_when_not_needed; 55 - bool ycbcr422_simple; 56 55 }; 57 56 58 57 struct dc_dsc_config_options {
+7 -6
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
··· 680 680 } else { 681 681 build_dsc_enc_caps(dsc, dsc_enc_caps); 682 682 } 683 + 684 + if (dsc->ctx->dc->debug.native422_support) 685 + dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; 683 686 } 684 687 685 688 /* Returns 'false' if no intersection was found for at least one capability. ··· 1100 1097 branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_0_mps; 1101 1098 break; 1102 1099 case PIXEL_ENCODING_YCBCR422: 1103 - if (policy.ycbcr422_simple) { 1100 + is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_NATIVE_422; 1101 + sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_1_mps; 1102 + branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_1_mps; 1103 + if (!is_dsc_possible) { 1104 1104 is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_SIMPLE_422; 1105 1105 dsc_cfg->ycbcr422_simple = is_dsc_possible; 1106 1106 sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_0_mps; 1107 - } else { 1108 - is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_NATIVE_422; 1109 - sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_1_mps; 1110 - branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_1_mps; 1111 1107 } 1112 1108 break; 1113 1109 case PIXEL_ENCODING_YCBCR420: ··· 1406 1404 policy->min_target_bpp = 8; 1407 1405 /* DP specs limits to 3 x bpc */ 1408 1406 policy->max_target_bpp = 3 * bpc; 1409 - policy->ycbcr422_simple = true; 1410 1407 break; 1411 1408 case PIXEL_ENCODING_YCBCR420: 1412 1409 /* DP specs limits to 6 */
+1 -1
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
··· 100 100 dsc_enc_caps->color_formats.bits.RGB = 1; 101 101 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; 102 102 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; 103 - dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; 103 + dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; 104 104 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; 105 105 106 106 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
+1 -1
drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
··· 128 128 dsc_enc_caps->color_formats.bits.RGB = 1; 129 129 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; 130 130 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; 131 - dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; 131 + dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; 132 132 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; 133 133 134 134 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
+1 -1
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
··· 78 78 dsc_enc_caps->color_formats.bits.RGB = 1; 79 79 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; 80 80 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; 81 - dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; 81 + dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; 82 82 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; 83 83 84 84 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
-2
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
··· 1963 1963 dc->config.use_pipe_ctx_sync_logic = true; 1964 1964 dc->config.disable_hbr_audio_dp2 = true; 1965 1965 1966 - dc->config.no_native422_support = true; 1967 - 1968 1966 /* read VBIOS LTTPR caps */ 1969 1967 { 1970 1968 if (ctx->dc_bios->funcs->get_lttpr_caps) {
-2
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
··· 1926 1926 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1927 1927 dc->caps.color.mpc.ocsc = 1; 1928 1928 1929 - dc->config.no_native422_support = true; 1930 - 1931 1929 /* read VBIOS LTTPR caps */ 1932 1930 { 1933 1931 if (ctx->dc_bios->funcs->get_lttpr_caps) {