Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mtd/for-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull MTD updates from Miquel Raynal:
"MTD changes:
- No particularly important patchset this cycle, but we have a few
usual improvements: like using a better/more recent helper or
checking a return value.
Raw NAND changes:
- The use of for_each_child_of_node_scoped() has been spread into the
subsystem drivers
- a couple of exit path have been fixed (mtk, denali)
- TI GPMC bindings have been enhanced to comply with up-to-date
partition descriptions
- a load of small and misc fixes
SPI-NAND changes:
- The most impacting series this cycle is bringing support for
continuous reads in the SPI-NAND subsystem.
This is a feature already merged in the raw NAND subsystem which
allows optimizing the internal fetch times in the chip while
reading sequential pages within an eraseblock.
For now only Macronix NANDs benefit from this feature. While we are
talking about Macronix, some of their chip need an explicit action
for selecting a different plane, and support for it has also been
brought.
- The bitflip threshold has also been set to the same arbitrary level
as in the raw NAND subsystem to optimize wear leveling decisions
- Add upport for a new Winbond chip
SPI NOR changes:
- Add Write Protect support for N25Q064A.
- New flash support for Zetta ZD25Q128C and Spansion S28HS256T.
- Fix a NULL dereference in probe path for flashes without a name.
The probe path tries to access the name without checking its
existence first. S28HS256T is the first flash to define its entry
without a name, uncovering this issue"
* tag 'mtd/for-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (41 commits)
mtd: spi-nor: fix flash probing
mtd: spi-nor: spansion: Add support for S28HS256T
mtd: spi-nor: winbond: add Zetta ZD25Q128C support
mtd: spi-nor: micron-st: Add n25q064a WP support
mtd: spi-nor: sst: Factor out common write operation to `sst_nor_write_data()`
mtd: spinand: macronix: Flag parts needing explicit plane select
mtd: spinand: Add support for setting plane select bits
dt-bindings: mtd: ti, gpmc-nand: support partitions node
mtd: rawnand: mtk: Fix init error path
mtd: powernv: Add check devm_kasprintf() returned value
mtd: rawnand: mtk: Factorize out the logic cleaning mtk chips
mtd: rawnand: atmel: Add message on DMA usage
mtd: rawnand: meson: Fix typo in function name
mtd: spi-nand: macronix: Continuous read support
mtd: spi-nand: macronix: Add a possible bitflip status flag
mtd: spi-nand: macronix: Extract the bitflip retrieval logic
mtd: spi-nand: macronix: Fix helper name
mtd: spi-nand: Expose spinand_write_reg_op()
mtd: spi-nand: Add continuous read support
mtd: spi-nand: Isolate the MTD read logic in a helper
...
+621
-314
+1
-4
Documentation/devicetree/bindings/mtd/ti,gpmc-nand.yaml
+1
-4
Documentation/devicetree/bindings/mtd/ti,gpmc-nand.yaml
···
61
61
GPIO connection to R/B signal from NAND chip
62
62
maxItems: 1
63
63
64
-
patternProperties:
65
-
"@[0-9a-f]+$":
66
-
$ref: /schemas/mtd/partitions/partition.yaml
67
-
68
64
allOf:
69
65
- $ref: /schemas/memory-controllers/ti,gpmc-child.yaml
66
+
- $ref: mtd.yaml#
70
67
71
68
required:
72
69
- compatible
+3
drivers/mtd/devices/powernv_flash.c
+3
drivers/mtd/devices/powernv_flash.c
+2
drivers/mtd/devices/slram.c
+2
drivers/mtd/devices/slram.c
···
296
296
T("slram: devname = %s\n", devname);
297
297
if ((!map) || (!(devstart = strsep(&map, ",")))) {
298
298
E("slram: No devicestart specified.\n");
299
+
break;
299
300
}
300
301
T("slram: devstart = %s\n", devstart);
301
302
if ((!map) || (!(devlength = strsep(&map, ",")))) {
302
303
E("slram: No devicelength / -end specified.\n");
304
+
break;
303
305
}
304
306
T("slram: devlength = %s\n", devlength);
305
307
if (parse_cmdline(devname, devstart, devlength) != 0) {
+1
-1
drivers/mtd/mtdconcat.c
+1
-1
drivers/mtd/mtdconcat.c
+2
-3
drivers/mtd/nand/raw/arasan-nand-controller.c
+2
-3
drivers/mtd/nand/raw/arasan-nand-controller.c
···
1360
1360
1361
1361
static int anfc_chips_init(struct arasan_nfc *nfc)
1362
1362
{
1363
-
struct device_node *np = nfc->dev->of_node, *nand_np;
1363
+
struct device_node *np = nfc->dev->of_node;
1364
1364
int nchips = of_get_child_count(np);
1365
1365
int ret;
1366
1366
···
1370
1370
return -EINVAL;
1371
1371
}
1372
1372
1373
-
for_each_child_of_node(np, nand_np) {
1373
+
for_each_child_of_node_scoped(np, nand_np) {
1374
1374
ret = anfc_chip_init(nfc, nand_np);
1375
1375
if (ret) {
1376
-
of_node_put(nand_np);
1377
1376
anfc_chips_cleanup(nfc);
1378
1377
break;
1379
1378
}
+4
-1
drivers/mtd/nand/raw/atmel/nand-controller.c
+4
-1
drivers/mtd/nand/raw/atmel/nand-controller.c
···
2049
2049
dma_cap_set(DMA_MEMCPY, mask);
2050
2050
2051
2051
nc->dmac = dma_request_channel(mask, NULL, NULL);
2052
-
if (!nc->dmac)
2052
+
if (nc->dmac)
2053
+
dev_info(nc->dev, "using %s for DMA transfers\n",
2054
+
dma_chan_name(nc->dmac));
2055
+
else
2053
2056
dev_err(nc->dev, "Failed to request DMA channel\n");
2054
2057
}
2055
2058
+1
-3
drivers/mtd/nand/raw/cadence-nand-controller.c
+1
-3
drivers/mtd/nand/raw/cadence-nand-controller.c
···
2836
2836
static int cadence_nand_chips_init(struct cdns_nand_ctrl *cdns_ctrl)
2837
2837
{
2838
2838
struct device_node *np = cdns_ctrl->dev->of_node;
2839
-
struct device_node *nand_np;
2840
2839
int max_cs = cdns_ctrl->caps2.max_banks;
2841
2840
int nchips, ret;
2842
2841
···
2848
2849
return -EINVAL;
2849
2850
}
2850
2851
2851
-
for_each_child_of_node(np, nand_np) {
2852
+
for_each_child_of_node_scoped(np, nand_np) {
2852
2853
ret = cadence_nand_chip_init(cdns_ctrl, nand_np);
2853
2854
if (ret) {
2854
-
of_node_put(nand_np);
2855
2855
cadence_nand_chips_cleanup(cdns_ctrl);
2856
2856
return ret;
2857
2857
}
+65
-5
drivers/mtd/nand/raw/davinci_nand.c
+65
-5
drivers/mtd/nand/raw/davinci_nand.c
···
20
20
#include <linux/slab.h>
21
21
#include <linux/of.h>
22
22
23
-
#include <linux/platform_data/mtd-davinci.h>
24
-
#include <linux/platform_data/mtd-davinci-aemif.h>
23
+
#define NRCSR_OFFSET 0x00
24
+
#define NANDFCR_OFFSET 0x60
25
+
#define NANDFSR_OFFSET 0x64
26
+
#define NANDF1ECC_OFFSET 0x70
27
+
28
+
/* 4-bit ECC syndrome registers */
29
+
#define NAND_4BIT_ECC_LOAD_OFFSET 0xbc
30
+
#define NAND_4BIT_ECC1_OFFSET 0xc0
31
+
#define NAND_4BIT_ECC2_OFFSET 0xc4
32
+
#define NAND_4BIT_ECC3_OFFSET 0xc8
33
+
#define NAND_4BIT_ECC4_OFFSET 0xcc
34
+
#define NAND_ERR_ADD1_OFFSET 0xd0
35
+
#define NAND_ERR_ADD2_OFFSET 0xd4
36
+
#define NAND_ERR_ERRVAL1_OFFSET 0xd8
37
+
#define NAND_ERR_ERRVAL2_OFFSET 0xdc
38
+
39
+
/* NOTE: boards don't need to use these address bits
40
+
* for ALE/CLE unless they support booting from NAND.
41
+
* They're used unless platform data overrides them.
42
+
*/
43
+
#define MASK_ALE 0x08
44
+
#define MASK_CLE 0x10
45
+
46
+
struct davinci_nand_pdata {
47
+
uint32_t mask_ale;
48
+
uint32_t mask_cle;
49
+
50
+
/*
51
+
* 0-indexed chip-select number of the asynchronous
52
+
* interface to which the NAND device has been connected.
53
+
*
54
+
* So, if you have NAND connected to CS3 of DA850, you
55
+
* will pass '1' here. Since the asynchronous interface
56
+
* on DA850 starts from CS2.
57
+
*/
58
+
uint32_t core_chipsel;
59
+
60
+
/* for packages using two chipselects */
61
+
uint32_t mask_chipsel;
62
+
63
+
/* board's default static partition info */
64
+
struct mtd_partition *parts;
65
+
unsigned int nr_parts;
66
+
67
+
/* none == NAND_ECC_ENGINE_TYPE_NONE (strongly *not* advised!!)
68
+
* soft == NAND_ECC_ENGINE_TYPE_SOFT
69
+
* else == NAND_ECC_ENGINE_TYPE_ON_HOST, according to ecc_bits
70
+
*
71
+
* All DaVinci-family chips support 1-bit hardware ECC.
72
+
* Newer ones also support 4-bit ECC, but are awkward
73
+
* using it with large page chips.
74
+
*/
75
+
enum nand_ecc_engine_type engine_type;
76
+
enum nand_ecc_placement ecc_placement;
77
+
u8 ecc_bits;
78
+
79
+
/* e.g. NAND_BUSWIDTH_16 */
80
+
unsigned int options;
81
+
/* e.g. NAND_BBT_USE_FLASH */
82
+
unsigned int bbt_options;
83
+
84
+
/* Main and mirror bbt descriptor overrides */
85
+
struct nand_bbt_descr *bbt_td;
86
+
struct nand_bbt_descr *bbt_md;
87
+
};
25
88
26
89
/*
27
90
* This is a device driver for the NAND flash controller found on the
···
117
54
uint32_t mask_cle;
118
55
119
56
uint32_t core_chipsel;
120
-
121
-
struct davinci_aemif_timing *timing;
122
57
};
123
58
124
59
static DEFINE_SPINLOCK(davinci_nand_lock);
···
836
775
info->chip.options = pdata->options;
837
776
info->chip.bbt_td = pdata->bbt_td;
838
777
info->chip.bbt_md = pdata->bbt_md;
839
-
info->timing = pdata->timing;
840
778
841
779
info->current_cs = info->vaddr;
842
780
info->core_chipsel = pdata->core_chipsel;
+4
-25
drivers/mtd/nand/raw/denali_dt.c
+4
-25
drivers/mtd/nand/raw/denali_dt.c
···
145
145
if (IS_ERR(denali->host))
146
146
return PTR_ERR(denali->host);
147
147
148
-
dt->clk = devm_clk_get(dev, "nand");
148
+
dt->clk = devm_clk_get_enabled(dev, "nand");
149
149
if (IS_ERR(dt->clk))
150
150
return PTR_ERR(dt->clk);
151
151
152
-
dt->clk_x = devm_clk_get(dev, "nand_x");
152
+
dt->clk_x = devm_clk_get_enabled(dev, "nand_x");
153
153
if (IS_ERR(dt->clk_x))
154
154
return PTR_ERR(dt->clk_x);
155
155
156
-
dt->clk_ecc = devm_clk_get(dev, "ecc");
156
+
dt->clk_ecc = devm_clk_get_enabled(dev, "ecc");
157
157
if (IS_ERR(dt->clk_ecc))
158
158
return PTR_ERR(dt->clk_ecc);
159
159
···
165
165
if (IS_ERR(dt->rst_reg))
166
166
return PTR_ERR(dt->rst_reg);
167
167
168
-
ret = clk_prepare_enable(dt->clk);
169
-
if (ret)
170
-
return ret;
171
-
172
-
ret = clk_prepare_enable(dt->clk_x);
173
-
if (ret)
174
-
goto out_disable_clk;
175
-
176
-
ret = clk_prepare_enable(dt->clk_ecc);
177
-
if (ret)
178
-
goto out_disable_clk_x;
179
-
180
168
denali->clk_rate = clk_get_rate(dt->clk);
181
169
denali->clk_x_rate = clk_get_rate(dt->clk_x);
182
170
···
175
187
*/
176
188
ret = reset_control_deassert(dt->rst_reg);
177
189
if (ret)
178
-
goto out_disable_clk_ecc;
190
+
return ret;
179
191
180
192
ret = reset_control_deassert(dt->rst);
181
193
if (ret)
···
210
222
reset_control_assert(dt->rst);
211
223
out_assert_rst_reg:
212
224
reset_control_assert(dt->rst_reg);
213
-
out_disable_clk_ecc:
214
-
clk_disable_unprepare(dt->clk_ecc);
215
-
out_disable_clk_x:
216
-
clk_disable_unprepare(dt->clk_x);
217
-
out_disable_clk:
218
-
clk_disable_unprepare(dt->clk);
219
225
220
226
return ret;
221
227
}
···
221
239
denali_remove(&dt->controller);
222
240
reset_control_assert(dt->rst);
223
241
reset_control_assert(dt->rst_reg);
224
-
clk_disable_unprepare(dt->clk_ecc);
225
-
clk_disable_unprepare(dt->clk_x);
226
-
clk_disable_unprepare(dt->clk);
227
242
}
228
243
229
244
static struct platform_driver denali_dt_driver = {
+8
-3
drivers/mtd/nand/raw/denali_pci.c
+8
-3
drivers/mtd/nand/raw/denali_pci.c
···
77
77
denali->reg = devm_ioremap(denali->dev, csr_base, csr_len);
78
78
if (!denali->reg) {
79
79
dev_err(&dev->dev, "Spectra: Unable to remap memory region\n");
80
-
return -ENOMEM;
80
+
ret = -ENOMEM;
81
+
goto regions_release;
81
82
}
82
83
83
84
denali->host = devm_ioremap(denali->dev, mem_base, mem_len);
84
85
if (!denali->host) {
85
86
dev_err(&dev->dev, "Spectra: ioremap failed!");
86
-
return -ENOMEM;
87
+
ret = -ENOMEM;
88
+
goto regions_release;
87
89
}
88
90
89
91
ret = denali_init(denali);
90
92
if (ret)
91
-
return ret;
93
+
goto regions_release;
92
94
93
95
nsels = denali->nbanks;
94
96
···
118
116
119
117
out_remove_denali:
120
118
denali_remove(denali);
119
+
regions_release:
120
+
pci_release_regions(dev);
121
121
return ret;
122
122
}
123
123
···
127
123
{
128
124
struct denali_controller *denali = pci_get_drvdata(dev);
129
125
126
+
pci_release_regions(dev);
130
127
denali_remove(denali);
131
128
}
132
129
+3
-9
drivers/mtd/nand/raw/marvell_nand.c
+3
-9
drivers/mtd/nand/raw/marvell_nand.c
···
2771
2771
static int marvell_nand_chips_init(struct device *dev, struct marvell_nfc *nfc)
2772
2772
{
2773
2773
struct device_node *np = dev->of_node;
2774
-
struct device_node *nand_np;
2775
2774
int max_cs = nfc->caps->max_cs_nb;
2776
2775
int nchips;
2777
2776
int ret;
···
2797
2798
return ret;
2798
2799
}
2799
2800
2800
-
for_each_child_of_node(np, nand_np) {
2801
+
for_each_child_of_node_scoped(np, nand_np) {
2801
2802
ret = marvell_nand_chip_init(dev, nfc, nand_np);
2802
2803
if (ret) {
2803
-
of_node_put(nand_np);
2804
-
goto cleanup_chips;
2804
+
marvell_nand_chips_cleanup(nfc);
2805
+
return ret;
2805
2806
}
2806
2807
}
2807
2808
2808
2809
return 0;
2809
-
2810
-
cleanup_chips:
2811
-
marvell_nand_chips_cleanup(nfc);
2812
-
2813
-
return ret;
2814
2810
}
2815
2811
2816
2812
static int marvell_nfc_init_dma(struct marvell_nfc *nfc)
+4
-6
drivers/mtd/nand/raw/meson_nand.c
+4
-6
drivers/mtd/nand/raw/meson_nand.c
···
1475
1475
return 0;
1476
1476
}
1477
1477
1478
-
static void meson_nfc_nand_chip_cleanup(struct meson_nfc *nfc)
1478
+
static void meson_nfc_nand_chips_cleanup(struct meson_nfc *nfc)
1479
1479
{
1480
1480
struct meson_nfc_nand_chip *meson_chip;
1481
1481
struct mtd_info *mtd;
···
1495
1495
struct meson_nfc *nfc)
1496
1496
{
1497
1497
struct device_node *np = dev->of_node;
1498
-
struct device_node *nand_np;
1499
1498
int ret;
1500
1499
1501
-
for_each_child_of_node(np, nand_np) {
1500
+
for_each_child_of_node_scoped(np, nand_np) {
1502
1501
ret = meson_nfc_nand_chip_init(dev, nfc, nand_np);
1503
1502
if (ret) {
1504
-
meson_nfc_nand_chip_cleanup(nfc);
1505
-
of_node_put(nand_np);
1503
+
meson_nfc_nand_chips_cleanup(nfc);
1506
1504
return ret;
1507
1505
}
1508
1506
}
···
1614
1616
{
1615
1617
struct meson_nfc *nfc = platform_get_drvdata(pdev);
1616
1618
1617
-
meson_nfc_nand_chip_cleanup(nfc);
1619
+
meson_nfc_nand_chips_cleanup(nfc);
1618
1620
1619
1621
meson_nfc_disable_clk(nfc);
1620
1622
}
+20
-16
drivers/mtd/nand/raw/mtk_nand.c
+20
-16
drivers/mtd/nand/raw/mtk_nand.c
···
1429
1429
return 0;
1430
1430
}
1431
1431
1432
+
static void mtk_nfc_nand_chips_cleanup(struct mtk_nfc *nfc)
1433
+
{
1434
+
struct mtk_nfc_nand_chip *mtk_chip;
1435
+
struct nand_chip *chip;
1436
+
int ret;
1437
+
1438
+
while (!list_empty(&nfc->chips)) {
1439
+
mtk_chip = list_first_entry(&nfc->chips,
1440
+
struct mtk_nfc_nand_chip, node);
1441
+
chip = &mtk_chip->nand;
1442
+
ret = mtd_device_unregister(nand_to_mtd(chip));
1443
+
WARN_ON(ret);
1444
+
nand_cleanup(chip);
1445
+
list_del(&mtk_chip->node);
1446
+
}
1447
+
}
1448
+
1432
1449
static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
1433
1450
{
1434
1451
struct device_node *np = dev->of_node;
1435
-
struct device_node *nand_np;
1436
1452
int ret;
1437
1453
1438
-
for_each_child_of_node(np, nand_np) {
1454
+
for_each_child_of_node_scoped(np, nand_np) {
1439
1455
ret = mtk_nfc_nand_chip_init(dev, nfc, nand_np);
1440
1456
if (ret) {
1441
-
of_node_put(nand_np);
1457
+
mtk_nfc_nand_chips_cleanup(nfc);
1442
1458
return ret;
1443
1459
}
1444
1460
}
···
1586
1570
static void mtk_nfc_remove(struct platform_device *pdev)
1587
1571
{
1588
1572
struct mtk_nfc *nfc = platform_get_drvdata(pdev);
1589
-
struct mtk_nfc_nand_chip *mtk_chip;
1590
-
struct nand_chip *chip;
1591
-
int ret;
1592
1573
1593
-
while (!list_empty(&nfc->chips)) {
1594
-
mtk_chip = list_first_entry(&nfc->chips,
1595
-
struct mtk_nfc_nand_chip, node);
1596
-
chip = &mtk_chip->nand;
1597
-
ret = mtd_device_unregister(nand_to_mtd(chip));
1598
-
WARN_ON(ret);
1599
-
nand_cleanup(chip);
1600
-
list_del(&mtk_chip->node);
1601
-
}
1602
-
1574
+
mtk_nfc_nand_chips_cleanup(nfc);
1603
1575
mtk_ecc_release(nfc->ecc);
1604
1576
}
1605
1577
+2
-3
drivers/mtd/nand/raw/pl35x-nand-controller.c
+2
-3
drivers/mtd/nand/raw/pl35x-nand-controller.c
···
1111
1111
1112
1112
static int pl35x_nand_chips_init(struct pl35x_nandc *nfc)
1113
1113
{
1114
-
struct device_node *np = nfc->dev->of_node, *nand_np;
1114
+
struct device_node *np = nfc->dev->of_node;
1115
1115
int nchips = of_get_child_count(np);
1116
1116
int ret;
1117
1117
···
1121
1121
return -EINVAL;
1122
1122
}
1123
1123
1124
-
for_each_child_of_node(np, nand_np) {
1124
+
for_each_child_of_node_scoped(np, nand_np) {
1125
1125
ret = pl35x_nand_chip_init(nfc, nand_np);
1126
1126
if (ret) {
1127
-
of_node_put(nand_np);
1128
1127
pl35x_nand_chips_cleanup(nfc);
1129
1128
break;
1130
1129
}
+3
-9
drivers/mtd/nand/raw/renesas-nand-controller.c
+3
-9
drivers/mtd/nand/raw/renesas-nand-controller.c
···
1297
1297
1298
1298
static int rnandc_chips_init(struct rnandc *rnandc)
1299
1299
{
1300
-
struct device_node *np;
1301
1300
int ret;
1302
1301
1303
-
for_each_child_of_node(rnandc->dev->of_node, np) {
1302
+
for_each_child_of_node_scoped(rnandc->dev->of_node, np) {
1304
1303
ret = rnandc_chip_init(rnandc, np);
1305
1304
if (ret) {
1306
-
of_node_put(np);
1307
-
goto cleanup_chips;
1305
+
rnandc_chips_cleanup(rnandc);
1306
+
return ret;
1308
1307
}
1309
1308
}
1310
1309
1311
1310
return 0;
1312
-
1313
-
cleanup_chips:
1314
-
rnandc_chips_cleanup(rnandc);
1315
-
1316
-
return ret;
1317
1311
}
1318
1312
1319
1313
static int rnandc_probe(struct platform_device *pdev)
+2
-3
drivers/mtd/nand/raw/rockchip-nand-controller.c
+2
-3
drivers/mtd/nand/raw/rockchip-nand-controller.c
···
1211
1211
1212
1212
static int rk_nfc_nand_chips_init(struct device *dev, struct rk_nfc *nfc)
1213
1213
{
1214
-
struct device_node *np = dev->of_node, *nand_np;
1214
+
struct device_node *np = dev->of_node;
1215
1215
int nchips = of_get_child_count(np);
1216
1216
int ret;
1217
1217
···
1221
1221
return -EINVAL;
1222
1222
}
1223
1223
1224
-
for_each_child_of_node(np, nand_np) {
1224
+
for_each_child_of_node_scoped(np, nand_np) {
1225
1225
ret = rk_nfc_nand_chip_init(dev, nfc, nand_np);
1226
1226
if (ret) {
1227
-
of_node_put(nand_np);
1228
1227
rk_nfc_chips_cleanup(nfc);
1229
1228
return ret;
1230
1229
}
+2
-5
drivers/mtd/nand/raw/stm32_fmc2_nand.c
+2
-5
drivers/mtd/nand/raw/stm32_fmc2_nand.c
···
1851
1851
static int stm32_fmc2_nfc_parse_dt(struct stm32_fmc2_nfc *nfc)
1852
1852
{
1853
1853
struct device_node *dn = nfc->dev->of_node;
1854
-
struct device_node *child;
1855
1854
int nchips = of_get_child_count(dn);
1856
1855
int ret = 0;
1857
1856
···
1864
1865
return -EINVAL;
1865
1866
}
1866
1867
1867
-
for_each_child_of_node(dn, child) {
1868
+
for_each_child_of_node_scoped(dn, child) {
1868
1869
ret = stm32_fmc2_nfc_parse_child(nfc, child);
1869
-
if (ret < 0) {
1870
-
of_node_put(child);
1870
+
if (ret < 0)
1871
1871
return ret;
1872
-
}
1873
1872
}
1874
1873
1875
1874
return ret;
+1
-3
drivers/mtd/nand/raw/sunxi_nand.c
+1
-3
drivers/mtd/nand/raw/sunxi_nand.c
···
2025
2025
static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
2026
2026
{
2027
2027
struct device_node *np = dev->of_node;
2028
-
struct device_node *nand_np;
2029
2028
int ret;
2030
2029
2031
-
for_each_child_of_node(np, nand_np) {
2030
+
for_each_child_of_node_scoped(np, nand_np) {
2032
2031
ret = sunxi_nand_chip_init(dev, nfc, nand_np);
2033
2032
if (ret) {
2034
-
of_node_put(nand_np);
2035
2033
sunxi_nand_chips_cleanup(nfc);
2036
2034
return ret;
2037
2035
}
+201
-22
drivers/mtd/nand/spi/core.c
+201
-22
drivers/mtd/nand/spi/core.c
···
34
34
return 0;
35
35
}
36
36
37
-
static int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val)
37
+
int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val)
38
38
{
39
39
struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg,
40
40
spinand->scratchbuf);
···
200
200
enable ? CFG_ECC_ENABLE : 0);
201
201
}
202
202
203
+
static int spinand_cont_read_enable(struct spinand_device *spinand,
204
+
bool enable)
205
+
{
206
+
return spinand->set_cont_read(spinand, enable);
207
+
}
208
+
203
209
static int spinand_check_ecc_status(struct spinand_device *spinand, u8 status)
204
210
{
205
211
struct nand_device *nand = spinand_to_nand(spinand);
···
317
311
318
312
/* Finish a page read: check the status, report errors/bitflips */
319
313
ret = spinand_check_ecc_status(spinand, engine_conf->status);
320
-
if (ret == -EBADMSG)
314
+
if (ret == -EBADMSG) {
321
315
mtd->ecc_stats.failed++;
322
-
else if (ret > 0)
323
-
mtd->ecc_stats.corrected += ret;
316
+
} else if (ret > 0) {
317
+
unsigned int pages;
318
+
319
+
/*
320
+
* Continuous reads don't allow us to get the detail,
321
+
* so we may exagerate the actual number of corrected bitflips.
322
+
*/
323
+
if (!req->continuous)
324
+
pages = 1;
325
+
else
326
+
pages = req->datalen / nanddev_page_size(nand);
327
+
328
+
mtd->ecc_stats.corrected += ret * pages;
329
+
}
324
330
325
331
return ret;
326
332
}
···
387
369
388
370
if (req->datalen) {
389
371
buf = spinand->databuf;
390
-
nbytes = nanddev_page_size(nand);
372
+
if (!req->continuous)
373
+
nbytes = nanddev_page_size(nand);
374
+
else
375
+
nbytes = round_up(req->dataoffs + req->datalen,
376
+
nanddev_page_size(nand));
391
377
column = 0;
392
378
}
393
379
···
408
386
else
409
387
rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc;
410
388
389
+
if (spinand->flags & SPINAND_HAS_READ_PLANE_SELECT_BIT)
390
+
column |= req->pos.plane << fls(nanddev_page_size(nand));
391
+
411
392
while (nbytes) {
412
393
ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf);
413
394
if (ret < 0)
···
422
397
nbytes -= ret;
423
398
column += ret;
424
399
buf += ret;
400
+
401
+
/*
402
+
* Dirmap accesses are allowed to toggle the CS.
403
+
* Toggling the CS during a continuous read is forbidden.
404
+
*/
405
+
if (nbytes && req->continuous)
406
+
return -EIO;
425
407
}
426
408
427
409
if (req->datalen)
···
491
459
wdesc = spinand->dirmaps[req->pos.plane].wdesc;
492
460
else
493
461
wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc;
462
+
463
+
if (spinand->flags & SPINAND_HAS_PROG_PLANE_SELECT_BIT)
464
+
column |= req->pos.plane << fls(nanddev_page_size(nand));
494
465
495
466
while (nbytes) {
496
467
ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf);
···
665
630
return nand_ecc_finish_io_req(nand, (struct nand_page_io_req *)req);
666
631
}
667
632
668
-
static int spinand_mtd_read(struct mtd_info *mtd, loff_t from,
669
-
struct mtd_oob_ops *ops)
633
+
static int spinand_mtd_regular_page_read(struct mtd_info *mtd, loff_t from,
634
+
struct mtd_oob_ops *ops,
635
+
unsigned int *max_bitflips)
670
636
{
671
637
struct spinand_device *spinand = mtd_to_spinand(mtd);
672
638
struct nand_device *nand = mtd_to_nanddev(mtd);
673
-
struct mtd_ecc_stats old_stats;
674
-
unsigned int max_bitflips = 0;
675
639
struct nand_io_iter iter;
676
640
bool disable_ecc = false;
677
641
bool ecc_failed = false;
678
-
int ret = 0;
642
+
int ret;
679
643
680
-
if (ops->mode == MTD_OPS_RAW || !spinand->eccinfo.ooblayout)
644
+
if (ops->mode == MTD_OPS_RAW || !mtd->ooblayout)
681
645
disable_ecc = true;
682
-
683
-
mutex_lock(&spinand->lock);
684
-
685
-
old_stats = mtd->ecc_stats;
686
646
687
647
nanddev_io_for_each_page(nand, NAND_PAGE_READ, from, ops, &iter) {
688
648
if (disable_ecc)
···
694
664
if (ret == -EBADMSG)
695
665
ecc_failed = true;
696
666
else
697
-
max_bitflips = max_t(unsigned int, max_bitflips, ret);
667
+
*max_bitflips = max_t(unsigned int, *max_bitflips, ret);
698
668
699
669
ret = 0;
700
670
ops->retlen += iter.req.datalen;
701
671
ops->oobretlen += iter.req.ooblen;
702
672
}
673
+
674
+
if (ecc_failed && !ret)
675
+
ret = -EBADMSG;
676
+
677
+
return ret;
678
+
}
679
+
680
+
static int spinand_mtd_continuous_page_read(struct mtd_info *mtd, loff_t from,
681
+
struct mtd_oob_ops *ops,
682
+
unsigned int *max_bitflips)
683
+
{
684
+
struct spinand_device *spinand = mtd_to_spinand(mtd);
685
+
struct nand_device *nand = mtd_to_nanddev(mtd);
686
+
struct nand_io_iter iter;
687
+
u8 status;
688
+
int ret;
689
+
690
+
ret = spinand_cont_read_enable(spinand, true);
691
+
if (ret)
692
+
return ret;
693
+
694
+
/*
695
+
* The cache is divided into two halves. While one half of the cache has
696
+
* the requested data, the other half is loaded with the next chunk of data.
697
+
* Therefore, the host can read out the data continuously from page to page.
698
+
* Each data read must be a multiple of 4-bytes and full pages should be read;
699
+
* otherwise, the data output might get out of sequence from one read command
700
+
* to another.
701
+
*/
702
+
nanddev_io_for_each_block(nand, NAND_PAGE_READ, from, ops, &iter) {
703
+
ret = spinand_select_target(spinand, iter.req.pos.target);
704
+
if (ret)
705
+
goto end_cont_read;
706
+
707
+
ret = nand_ecc_prepare_io_req(nand, &iter.req);
708
+
if (ret)
709
+
goto end_cont_read;
710
+
711
+
ret = spinand_load_page_op(spinand, &iter.req);
712
+
if (ret)
713
+
goto end_cont_read;
714
+
715
+
ret = spinand_wait(spinand, SPINAND_READ_INITIAL_DELAY_US,
716
+
SPINAND_READ_POLL_DELAY_US, NULL);
717
+
if (ret < 0)
718
+
goto end_cont_read;
719
+
720
+
ret = spinand_read_from_cache_op(spinand, &iter.req);
721
+
if (ret)
722
+
goto end_cont_read;
723
+
724
+
ops->retlen += iter.req.datalen;
725
+
726
+
ret = spinand_read_status(spinand, &status);
727
+
if (ret)
728
+
goto end_cont_read;
729
+
730
+
spinand_ondie_ecc_save_status(nand, status);
731
+
732
+
ret = nand_ecc_finish_io_req(nand, &iter.req);
733
+
if (ret < 0)
734
+
goto end_cont_read;
735
+
736
+
*max_bitflips = max_t(unsigned int, *max_bitflips, ret);
737
+
ret = 0;
738
+
}
739
+
740
+
end_cont_read:
741
+
/*
742
+
* Once all the data has been read out, the host can either pull CS#
743
+
* high and wait for tRST or manually clear the bit in the configuration
744
+
* register to terminate the continuous read operation. We have no
745
+
* guarantee the SPI controller drivers will effectively deassert the CS
746
+
* when we expect them to, so take the register based approach.
747
+
*/
748
+
spinand_cont_read_enable(spinand, false);
749
+
750
+
return ret;
751
+
}
752
+
753
+
static void spinand_cont_read_init(struct spinand_device *spinand)
754
+
{
755
+
struct nand_device *nand = spinand_to_nand(spinand);
756
+
enum nand_ecc_engine_type engine_type = nand->ecc.ctx.conf.engine_type;
757
+
758
+
/* OOBs cannot be retrieved so external/on-host ECC engine won't work */
759
+
if (spinand->set_cont_read &&
760
+
(engine_type == NAND_ECC_ENGINE_TYPE_ON_DIE ||
761
+
engine_type == NAND_ECC_ENGINE_TYPE_NONE)) {
762
+
spinand->cont_read_possible = true;
763
+
}
764
+
}
765
+
766
+
static bool spinand_use_cont_read(struct mtd_info *mtd, loff_t from,
767
+
struct mtd_oob_ops *ops)
768
+
{
769
+
struct nand_device *nand = mtd_to_nanddev(mtd);
770
+
struct spinand_device *spinand = nand_to_spinand(nand);
771
+
struct nand_pos start_pos, end_pos;
772
+
773
+
if (!spinand->cont_read_possible)
774
+
return false;
775
+
776
+
/* OOBs won't be retrieved */
777
+
if (ops->ooblen || ops->oobbuf)
778
+
return false;
779
+
780
+
nanddev_offs_to_pos(nand, from, &start_pos);
781
+
nanddev_offs_to_pos(nand, from + ops->len - 1, &end_pos);
782
+
783
+
/*
784
+
* Continuous reads never cross LUN boundaries. Some devices don't
785
+
* support crossing planes boundaries. Some devices don't even support
786
+
* crossing blocks boundaries. The common case being to read through UBI,
787
+
* we will very rarely read two consequent blocks or more, so it is safer
788
+
* and easier (can be improved) to only enable continuous reads when
789
+
* reading within the same erase block.
790
+
*/
791
+
if (start_pos.target != end_pos.target ||
792
+
start_pos.plane != end_pos.plane ||
793
+
start_pos.eraseblock != end_pos.eraseblock)
794
+
return false;
795
+
796
+
return start_pos.page < end_pos.page;
797
+
}
798
+
799
+
static int spinand_mtd_read(struct mtd_info *mtd, loff_t from,
800
+
struct mtd_oob_ops *ops)
801
+
{
802
+
struct spinand_device *spinand = mtd_to_spinand(mtd);
803
+
struct mtd_ecc_stats old_stats;
804
+
unsigned int max_bitflips = 0;
805
+
int ret;
806
+
807
+
mutex_lock(&spinand->lock);
808
+
809
+
old_stats = mtd->ecc_stats;
810
+
811
+
if (spinand_use_cont_read(mtd, from, ops))
812
+
ret = spinand_mtd_continuous_page_read(mtd, from, ops, &max_bitflips);
813
+
else
814
+
ret = spinand_mtd_regular_page_read(mtd, from, ops, &max_bitflips);
703
815
704
816
if (ops->stats) {
705
817
ops->stats->uncorrectable_errors +=
···
851
679
}
852
680
853
681
mutex_unlock(&spinand->lock);
854
-
855
-
if (ecc_failed && !ret)
856
-
ret = -EBADMSG;
857
682
858
683
return ret ? ret : max_bitflips;
859
684
}
···
1030
861
nanddev_per_page_oobsize(nand),
1031
862
};
1032
863
struct spi_mem_dirmap_desc *desc;
864
+
865
+
if (spinand->cont_read_possible)
866
+
info.length = nanddev_eraseblock_size(nand);
1033
867
1034
868
/* The plane number is passed in MSB just above the column address */
1035
869
info.offset = plane << fls(nand->memorg.pagesize);
···
1267
1095
spinand->flags = table[i].flags;
1268
1096
spinand->id.len = 1 + table[i].devid.len;
1269
1097
spinand->select_target = table[i].select_target;
1098
+
spinand->set_cont_read = table[i].set_cont_read;
1270
1099
1271
1100
op = spinand_select_op_variant(spinand,
1272
1101
info->op_variants.read_cache);
···
1409
1236
* may use this buffer for DMA access.
1410
1237
* Memory allocated by devm_ does not guarantee DMA-safe alignment.
1411
1238
*/
1412
-
spinand->databuf = kzalloc(nanddev_page_size(nand) +
1413
-
nanddev_per_page_oobsize(nand),
1414
-
GFP_KERNEL);
1239
+
spinand->databuf = kzalloc(nanddev_eraseblock_size(nand),
1240
+
GFP_KERNEL);
1415
1241
if (!spinand->databuf) {
1416
1242
ret = -ENOMEM;
1417
1243
goto err_free_bufs;
···
1439
1267
if (ret)
1440
1268
goto err_cleanup_nanddev;
1441
1269
1270
+
/*
1271
+
* Continuous read can only be enabled with an on-die ECC engine, so the
1272
+
* ECC initialization must have happened previously.
1273
+
*/
1274
+
spinand_cont_read_init(spinand);
1275
+
1442
1276
mtd->_read_oob = spinand_mtd_read;
1443
1277
mtd->_write_oob = spinand_mtd_write;
1444
1278
mtd->_block_isbad = spinand_mtd_block_isbad;
···
1465
1287
/* Propagate ECC information to mtd_info */
1466
1288
mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength;
1467
1289
mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size;
1290
+
mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
1468
1291
1469
1292
ret = spinand_create_dirmaps(spinand);
1470
1293
if (ret) {
+109
-37
drivers/mtd/nand/spi/macronix.c
+109
-37
drivers/mtd/nand/spi/macronix.c
···
5
5
* Author: Boris Brezillon <boris.brezillon@bootlin.com>
6
6
*/
7
7
8
+
#include <linux/bitfield.h>
8
9
#include <linux/device.h>
9
10
#include <linux/kernel.h>
10
11
#include <linux/mtd/spinand.h>
11
12
12
13
#define SPINAND_MFR_MACRONIX 0xC2
13
-
#define MACRONIX_ECCSR_MASK 0x0F
14
+
#define MACRONIX_ECCSR_BF_LAST_PAGE(eccsr) FIELD_GET(GENMASK(3, 0), eccsr)
15
+
#define MACRONIX_ECCSR_BF_ACCUMULATED_PAGES(eccsr) FIELD_GET(GENMASK(7, 4), eccsr)
16
+
#define MACRONIX_CFG_CONT_READ BIT(2)
17
+
18
+
#define STATUS_ECC_HAS_BITFLIPS_THRESHOLD (3 << 4)
19
+
20
+
/* Bitflip theshold configuration register */
21
+
#define REG_CFG_BFT 0x10
22
+
#define CFG_BFT(x) FIELD_PREP(GENMASK(7, 4), (x))
23
+
24
+
struct macronix_priv {
25
+
bool cont_read;
26
+
};
14
27
15
28
static SPINAND_OP_VARIANTS(read_cache_variants,
16
29
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
···
62
49
.free = mx35lfxge4ab_ooblayout_free,
63
50
};
64
51
65
-
static int mx35lf1ge4ab_get_eccsr(struct spinand_device *spinand, u8 *eccsr)
52
+
static int macronix_get_eccsr(struct spinand_device *spinand, u8 *eccsr)
66
53
{
54
+
struct macronix_priv *priv = spinand->priv;
67
55
struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x7c, 1),
68
56
SPI_MEM_OP_NO_ADDR,
69
57
SPI_MEM_OP_DUMMY(1, 1),
···
74
60
if (ret)
75
61
return ret;
76
62
77
-
*eccsr &= MACRONIX_ECCSR_MASK;
63
+
/*
64
+
* ECCSR exposes the number of bitflips for the last read page in bits [3:0].
65
+
* Continuous read compatible chips also expose the maximum number of
66
+
* bitflips for the whole (continuous) read operation in bits [7:4].
67
+
*/
68
+
if (!priv->cont_read)
69
+
*eccsr = MACRONIX_ECCSR_BF_LAST_PAGE(*eccsr);
70
+
else
71
+
*eccsr = MACRONIX_ECCSR_BF_ACCUMULATED_PAGES(*eccsr);
72
+
78
73
return 0;
79
74
}
80
75
81
-
static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand,
82
-
u8 status)
76
+
static int macronix_ecc_get_status(struct spinand_device *spinand,
77
+
u8 status)
83
78
{
84
79
struct nand_device *nand = spinand_to_nand(spinand);
85
80
u8 eccsr;
···
106
83
* in order to avoid forcing the wear-leveling layer to move
107
84
* data around if it's not necessary.
108
85
*/
109
-
if (mx35lf1ge4ab_get_eccsr(spinand, spinand->scratchbuf))
86
+
if (macronix_get_eccsr(spinand, spinand->scratchbuf))
110
87
return nanddev_get_ecc_conf(nand)->strength;
111
88
112
89
eccsr = *spinand->scratchbuf;
113
-
if (WARN_ON(eccsr > nanddev_get_ecc_conf(nand)->strength ||
114
-
!eccsr))
90
+
if (WARN_ON(eccsr > nanddev_get_ecc_conf(nand)->strength || !eccsr))
115
91
return nanddev_get_ecc_conf(nand)->strength;
116
92
117
93
return eccsr;
118
-
119
94
default:
120
95
break;
121
96
}
122
97
123
98
return -EINVAL;
99
+
}
100
+
101
+
static int macronix_set_cont_read(struct spinand_device *spinand, bool enable)
102
+
{
103
+
struct macronix_priv *priv = spinand->priv;
104
+
int ret;
105
+
106
+
ret = spinand_upd_cfg(spinand, MACRONIX_CFG_CONT_READ,
107
+
enable ? MACRONIX_CFG_CONT_READ : 0);
108
+
if (ret)
109
+
return ret;
110
+
111
+
priv->cont_read = enable;
112
+
113
+
return 0;
124
114
}
125
115
126
116
static const struct spinand_info macronix_spinand_table[] = {
···
146
110
&update_cache_variants),
147
111
SPINAND_HAS_QE_BIT,
148
112
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
149
-
mx35lf1ge4ab_ecc_get_status)),
113
+
macronix_ecc_get_status)),
150
114
SPINAND_INFO("MX35LF2GE4AB",
151
115
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22),
152
116
NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
···
154
118
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
155
119
&write_cache_variants,
156
120
&update_cache_variants),
157
-
SPINAND_HAS_QE_BIT,
121
+
SPINAND_HAS_QE_BIT |
122
+
SPINAND_HAS_PROG_PLANE_SELECT_BIT |
123
+
SPINAND_HAS_READ_PLANE_SELECT_BIT,
158
124
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
159
125
SPINAND_INFO("MX35LF2GE4AD",
160
126
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x26, 0x03),
···
167
129
&update_cache_variants),
168
130
SPINAND_HAS_QE_BIT,
169
131
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
170
-
mx35lf1ge4ab_ecc_get_status)),
132
+
macronix_ecc_get_status),
133
+
SPINAND_CONT_READ(macronix_set_cont_read)),
171
134
SPINAND_INFO("MX35LF4GE4AD",
172
135
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x37, 0x03),
173
136
NAND_MEMORG(1, 4096, 128, 64, 2048, 40, 1, 1, 1),
···
178
139
&update_cache_variants),
179
140
SPINAND_HAS_QE_BIT,
180
141
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
181
-
mx35lf1ge4ab_ecc_get_status)),
142
+
macronix_ecc_get_status),
143
+
SPINAND_CONT_READ(macronix_set_cont_read)),
182
144
SPINAND_INFO("MX35LF1G24AD",
183
145
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14, 0x03),
184
146
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
···
196
156
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
197
157
&write_cache_variants,
198
158
&update_cache_variants),
199
-
SPINAND_HAS_QE_BIT,
159
+
SPINAND_HAS_QE_BIT |
160
+
SPINAND_HAS_PROG_PLANE_SELECT_BIT,
200
161
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
201
162
SPINAND_INFO("MX35LF2G24AD-Z4I8",
202
163
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x64, 0x03),
···
215
174
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
216
175
&write_cache_variants,
217
176
&update_cache_variants),
218
-
SPINAND_HAS_QE_BIT,
177
+
SPINAND_HAS_QE_BIT |
178
+
SPINAND_HAS_PROG_PLANE_SELECT_BIT,
219
179
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
220
180
SPINAND_INFO("MX35LF4G24AD-Z4I8",
221
181
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x75, 0x03),
···
236
194
&update_cache_variants),
237
195
SPINAND_HAS_QE_BIT,
238
196
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
239
-
mx35lf1ge4ab_ecc_get_status)),
197
+
macronix_ecc_get_status)),
240
198
SPINAND_INFO("MX31UF1GE4BC",
241
199
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9e),
242
200
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
···
246
204
&update_cache_variants),
247
205
SPINAND_HAS_QE_BIT,
248
206
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
249
-
mx35lf1ge4ab_ecc_get_status)),
207
+
macronix_ecc_get_status)),
250
208
251
209
SPINAND_INFO("MX35LF2G14AC",
252
210
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x20),
···
255
213
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
256
214
&write_cache_variants,
257
215
&update_cache_variants),
258
-
SPINAND_HAS_QE_BIT,
216
+
SPINAND_HAS_QE_BIT |
217
+
SPINAND_HAS_PROG_PLANE_SELECT_BIT |
218
+
SPINAND_HAS_READ_PLANE_SELECT_BIT,
259
219
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
260
-
mx35lf1ge4ab_ecc_get_status)),
220
+
macronix_ecc_get_status)),
261
221
SPINAND_INFO("MX35UF4G24AD",
262
222
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5, 0x03),
263
223
NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1),
···
267
223
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
268
224
&write_cache_variants,
269
225
&update_cache_variants),
270
-
SPINAND_HAS_QE_BIT,
226
+
SPINAND_HAS_QE_BIT |
227
+
SPINAND_HAS_PROG_PLANE_SELECT_BIT,
271
228
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
272
-
mx35lf1ge4ab_ecc_get_status)),
229
+
macronix_ecc_get_status)),
273
230
SPINAND_INFO("MX35UF4G24AD-Z4I8",
274
231
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xf5, 0x03),
275
232
NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
···
280
235
&update_cache_variants),
281
236
SPINAND_HAS_QE_BIT,
282
237
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
283
-
mx35lf1ge4ab_ecc_get_status)),
238
+
macronix_ecc_get_status)),
284
239
SPINAND_INFO("MX35UF4GE4AD",
285
240
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb7, 0x03),
286
241
NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
···
290
245
&update_cache_variants),
291
246
SPINAND_HAS_QE_BIT,
292
247
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
293
-
mx35lf1ge4ab_ecc_get_status)),
248
+
macronix_ecc_get_status),
249
+
SPINAND_CONT_READ(macronix_set_cont_read)),
294
250
SPINAND_INFO("MX35UF2G14AC",
295
251
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa0),
296
252
NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
···
299
253
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
300
254
&write_cache_variants,
301
255
&update_cache_variants),
302
-
SPINAND_HAS_QE_BIT,
256
+
SPINAND_HAS_QE_BIT |
257
+
SPINAND_HAS_PROG_PLANE_SELECT_BIT |
258
+
SPINAND_HAS_READ_PLANE_SELECT_BIT,
303
259
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
304
-
mx35lf1ge4ab_ecc_get_status)),
260
+
macronix_ecc_get_status)),
305
261
SPINAND_INFO("MX35UF2G24AD",
306
262
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4, 0x03),
307
263
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
···
311
263
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
312
264
&write_cache_variants,
313
265
&update_cache_variants),
314
-
SPINAND_HAS_QE_BIT,
266
+
SPINAND_HAS_QE_BIT |
267
+
SPINAND_HAS_PROG_PLANE_SELECT_BIT,
315
268
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
316
-
mx35lf1ge4ab_ecc_get_status)),
269
+
macronix_ecc_get_status)),
317
270
SPINAND_INFO("MX35UF2G24AD-Z4I8",
318
271
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe4, 0x03),
319
272
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
···
324
275
&update_cache_variants),
325
276
SPINAND_HAS_QE_BIT,
326
277
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
327
-
mx35lf1ge4ab_ecc_get_status)),
278
+
macronix_ecc_get_status)),
328
279
SPINAND_INFO("MX35UF2GE4AD",
329
280
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa6, 0x03),
330
281
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
···
334
285
&update_cache_variants),
335
286
SPINAND_HAS_QE_BIT,
336
287
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
337
-
mx35lf1ge4ab_ecc_get_status)),
288
+
macronix_ecc_get_status),
289
+
SPINAND_CONT_READ(macronix_set_cont_read)),
338
290
SPINAND_INFO("MX35UF2GE4AC",
339
291
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa2, 0x01),
340
292
NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
···
345
295
&update_cache_variants),
346
296
SPINAND_HAS_QE_BIT,
347
297
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
348
-
mx35lf1ge4ab_ecc_get_status)),
298
+
macronix_ecc_get_status),
299
+
SPINAND_CONT_READ(macronix_set_cont_read)),
349
300
SPINAND_INFO("MX35UF1G14AC",
350
301
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x90),
351
302
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
···
356
305
&update_cache_variants),
357
306
SPINAND_HAS_QE_BIT,
358
307
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
359
-
mx35lf1ge4ab_ecc_get_status)),
308
+
macronix_ecc_get_status)),
360
309
SPINAND_INFO("MX35UF1G24AD",
361
310
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x94, 0x03),
362
311
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
···
366
315
&update_cache_variants),
367
316
SPINAND_HAS_QE_BIT,
368
317
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
369
-
mx35lf1ge4ab_ecc_get_status)),
318
+
macronix_ecc_get_status)),
370
319
SPINAND_INFO("MX35UF1GE4AD",
371
320
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x96, 0x03),
372
321
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
···
376
325
&update_cache_variants),
377
326
SPINAND_HAS_QE_BIT,
378
327
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
379
-
mx35lf1ge4ab_ecc_get_status)),
328
+
macronix_ecc_get_status),
329
+
SPINAND_CONT_READ(macronix_set_cont_read)),
380
330
SPINAND_INFO("MX35UF1GE4AC",
381
331
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92, 0x01),
382
332
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
···
387
335
&update_cache_variants),
388
336
SPINAND_HAS_QE_BIT,
389
337
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
390
-
mx35lf1ge4ab_ecc_get_status)),
391
-
338
+
macronix_ecc_get_status),
339
+
SPINAND_CONT_READ(macronix_set_cont_read)),
392
340
SPINAND_INFO("MX31LF2GE4BC",
393
341
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x2e),
394
342
NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
···
398
346
&update_cache_variants),
399
347
SPINAND_HAS_QE_BIT,
400
348
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
401
-
mx35lf1ge4ab_ecc_get_status)),
349
+
macronix_ecc_get_status)),
402
350
SPINAND_INFO("MX3UF2GE4BC",
403
351
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae),
404
352
NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
···
408
356
&update_cache_variants),
409
357
SPINAND_HAS_QE_BIT,
410
358
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
411
-
mx35lf1ge4ab_ecc_get_status)),
359
+
macronix_ecc_get_status)),
412
360
};
413
361
362
+
static int macronix_spinand_init(struct spinand_device *spinand)
363
+
{
364
+
struct macronix_priv *priv;
365
+
366
+
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
367
+
if (!priv)
368
+
return -ENOMEM;
369
+
370
+
spinand->priv = priv;
371
+
372
+
return 0;
373
+
}
374
+
375
+
static void macronix_spinand_cleanup(struct spinand_device *spinand)
376
+
{
377
+
kfree(spinand->priv);
378
+
}
379
+
414
380
static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = {
381
+
.init = macronix_spinand_init,
382
+
.cleanup = macronix_spinand_cleanup,
415
383
};
416
384
417
385
const struct spinand_manufacturer macronix_spinand_manufacturer = {
+26
drivers/mtd/nand/spi/winbond.c
+26
drivers/mtd/nand/spi/winbond.c
···
76
76
return spi_mem_exec_op(spinand->spimem, &op);
77
77
}
78
78
79
+
static int w25n01kv_ooblayout_ecc(struct mtd_info *mtd, int section,
80
+
struct mtd_oob_region *region)
81
+
{
82
+
if (section > 3)
83
+
return -ERANGE;
84
+
85
+
region->offset = 64 + (8 * section);
86
+
region->length = 7;
87
+
88
+
return 0;
89
+
}
90
+
79
91
static int w25n02kv_ooblayout_ecc(struct mtd_info *mtd, int section,
80
92
struct mtd_oob_region *region)
81
93
{
···
111
99
112
100
return 0;
113
101
}
102
+
103
+
static const struct mtd_ooblayout_ops w25n01kv_ooblayout = {
104
+
.ecc = w25n01kv_ooblayout_ecc,
105
+
.free = w25n02kv_ooblayout_free,
106
+
};
114
107
115
108
static const struct mtd_ooblayout_ops w25n02kv_ooblayout = {
116
109
.ecc = w25n02kv_ooblayout_ecc,
···
180
163
&update_cache_variants),
181
164
0,
182
165
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
166
+
SPINAND_INFO("W25N01KV",
167
+
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
168
+
NAND_MEMORG(1, 2048, 96, 64, 1024, 20, 1, 1, 1),
169
+
NAND_ECCREQ(4, 512),
170
+
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
171
+
&write_cache_variants,
172
+
&update_cache_variants),
173
+
0,
174
+
SPINAND_ECCINFO(&w25n01kv_ooblayout, w25n02kv_ecc_get_status)),
183
175
SPINAND_INFO("W25N02KV",
184
176
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
185
177
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+1
-1
drivers/mtd/parsers/bcm47xxpart.c
+1
-1
drivers/mtd/parsers/bcm47xxpart.c
···
95
95
uint32_t blocksize = master->erasesize;
96
96
int trx_parts[2]; /* Array with indexes of TRX partitions */
97
97
int trx_num = 0; /* Number of found TRX partitions */
98
-
int possible_nvram_sizes[] = { 0x8000, 0xF000, 0x10000, };
98
+
static const int possible_nvram_sizes[] = { 0x8000, 0xF000, 0x10000, };
99
99
int err;
100
100
101
101
/*
+2
-2
drivers/mtd/parsers/ofpart_core.c
+2
-2
drivers/mtd/parsers/ofpart_core.c
···
157
157
partname = of_get_property(pp, "name", &len);
158
158
parts[i].name = partname;
159
159
160
-
if (of_get_property(pp, "read-only", &len))
160
+
if (of_property_read_bool(pp, "read-only"))
161
161
parts[i].mask_flags |= MTD_WRITEABLE;
162
162
163
-
if (of_get_property(pp, "lock", &len))
163
+
if (of_property_read_bool(pp, "lock"))
164
164
parts[i].mask_flags |= MTD_POWERUP_LOCK;
165
165
166
166
if (of_property_read_bool(pp, "slc-mode"))
+2
-1
drivers/mtd/spi-nor/core.c
+2
-1
drivers/mtd/spi-nor/core.c
···
3281
3281
3282
3282
for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {
3283
3283
for (j = 0; j < manufacturers[i]->nparts; j++) {
3284
-
if (!strcmp(name, manufacturers[i]->parts[j].name)) {
3284
+
if (manufacturers[i]->parts[j].name &&
3285
+
!strcmp(name, manufacturers[i]->parts[j].name)) {
3285
3286
nor->manufacturer = manufacturers[i];
3286
3287
return &manufacturers[i]->parts[j];
3287
3288
}
+2
drivers/mtd/spi-nor/micron-st.c
+2
drivers/mtd/spi-nor/micron-st.c
+4
drivers/mtd/spi-nor/spansion.c
+4
drivers/mtd/spi-nor/spansion.c
+19
-20
drivers/mtd/spi-nor/sst.c
+19
-20
drivers/mtd/spi-nor/sst.c
···
167
167
}
168
168
};
169
169
170
+
static int sst_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
171
+
const u_char *buf)
172
+
{
173
+
u8 op = (len == 1) ? SPINOR_OP_BP : SPINOR_OP_AAI_WP;
174
+
int ret;
175
+
176
+
nor->program_opcode = op;
177
+
ret = spi_nor_write_data(nor, to, 1, buf);
178
+
if (ret < 0)
179
+
return ret;
180
+
WARN(ret != len, "While writing %zu byte written %i bytes\n", len, ret);
181
+
182
+
return spi_nor_wait_till_ready(nor);
183
+
}
184
+
170
185
static int sst_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
171
186
size_t *retlen, const u_char *buf)
172
187
{
···
203
188
204
189
/* Start write from odd address. */
205
190
if (to % 2) {
206
-
nor->program_opcode = SPINOR_OP_BP;
207
-
208
191
/* write one byte. */
209
-
ret = spi_nor_write_data(nor, to, 1, buf);
192
+
ret = sst_nor_write_data(nor, to, 1, buf);
210
193
if (ret < 0)
211
-
goto out;
212
-
WARN(ret != 1, "While writing 1 byte written %i bytes\n", ret);
213
-
ret = spi_nor_wait_till_ready(nor);
214
-
if (ret)
215
194
goto out;
216
195
217
196
to++;
···
214
205
215
206
/* Write out most of the data here. */
216
207
for (; actual < len - 1; actual += 2) {
217
-
nor->program_opcode = SPINOR_OP_AAI_WP;
218
-
219
208
/* write two bytes. */
220
-
ret = spi_nor_write_data(nor, to, 2, buf + actual);
209
+
ret = sst_nor_write_data(nor, to, 2, buf + actual);
221
210
if (ret < 0)
222
211
goto out;
223
-
WARN(ret != 2, "While writing 2 bytes written %i bytes\n", ret);
224
-
ret = spi_nor_wait_till_ready(nor);
225
-
if (ret)
226
-
goto out;
212
+
227
213
to += 2;
228
214
nor->sst_write_second = true;
229
215
}
···
238
234
if (ret)
239
235
goto out;
240
236
241
-
nor->program_opcode = SPINOR_OP_BP;
242
-
ret = spi_nor_write_data(nor, to, 1, buf + actual);
237
+
ret = sst_nor_write_data(nor, to, 1, buf + actual);
243
238
if (ret < 0)
244
-
goto out;
245
-
WARN(ret != 1, "While writing 1 byte written %i bytes\n", ret);
246
-
ret = spi_nor_wait_till_ready(nor);
247
-
if (ret)
248
239
goto out;
249
240
250
241
actual += 1;
+26
drivers/mtd/spi-nor/winbond.c
+26
drivers/mtd/spi-nor/winbond.c
···
18
18
SPI_MEM_OP_DATA_OUT(1, buf, 0))
19
19
20
20
static int
21
+
w25q128_post_bfpt_fixups(struct spi_nor *nor,
22
+
const struct sfdp_parameter_header *bfpt_header,
23
+
const struct sfdp_bfpt *bfpt)
24
+
{
25
+
/*
26
+
* Zetta ZD25Q128C is a clone of the Winbond device. But the encoded
27
+
* size is really wrong. It seems that they confused Mbit with MiB.
28
+
* Thus the flash is discovered as a 2MiB device.
29
+
*/
30
+
if (bfpt_header->major == SFDP_JESD216_MAJOR &&
31
+
bfpt_header->minor == SFDP_JESD216_MINOR &&
32
+
nor->params->size == SZ_2M &&
33
+
nor->params->erase_map.regions[0].size == SZ_2M) {
34
+
nor->params->size = SZ_16M;
35
+
nor->params->erase_map.regions[0].size = SZ_16M;
36
+
}
37
+
38
+
return 0;
39
+
}
40
+
41
+
static const struct spi_nor_fixups w25q128_fixups = {
42
+
.post_bfpt = w25q128_post_bfpt_fixups,
43
+
};
44
+
45
+
static int
21
46
w25q256_post_bfpt_fixups(struct spi_nor *nor,
22
47
const struct sfdp_parameter_header *bfpt_header,
23
48
const struct sfdp_bfpt *bfpt)
···
133
108
.size = SZ_16M,
134
109
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
135
110
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
111
+
.fixups = &w25q128_fixups,
136
112
}, {
137
113
.id = SNOR_ID(0xef, 0x40, 0x19),
138
114
.name = "w25q256",
+82
-8
include/linux/mtd/nand.h
+82
-8
include/linux/mtd/nand.h
···
103
103
* @ooblen: the number of OOB bytes to read from/write to this page
104
104
* @oobbuf: buffer to store OOB data in or get OOB data from
105
105
* @mode: one of the %MTD_OPS_XXX mode
106
+
* @continuous: no need to start over the operation at the end of each page, the
107
+
* NAND device will automatically prepare the next one
106
108
*
107
109
* This object is used to pass per-page I/O requests to NAND sub-layers. This
108
110
* way all useful information are already formatted in a useful way and
···
127
125
void *in;
128
126
} oobbuf;
129
127
int mode;
128
+
bool continuous;
130
129
};
131
130
132
131
const struct mtd_ooblayout_ops *nand_get_small_page_ooblayout(void);
···
909
906
}
910
907
911
908
/**
912
-
* nand_io_iter_init - Initialize a NAND I/O iterator
909
+
* nand_io_page_iter_init - Initialize a NAND I/O iterator
913
910
* @nand: NAND device
914
911
* @offs: absolute offset
915
912
* @req: MTD request
916
913
* @iter: NAND I/O iterator
917
914
*
918
915
* Initializes a NAND iterator based on the information passed by the MTD
919
-
* layer.
916
+
* layer for page jumps.
920
917
*/
921
-
static inline void nanddev_io_iter_init(struct nand_device *nand,
922
-
enum nand_page_io_req_type reqtype,
923
-
loff_t offs, struct mtd_oob_ops *req,
924
-
struct nand_io_iter *iter)
918
+
static inline void nanddev_io_page_iter_init(struct nand_device *nand,
919
+
enum nand_page_io_req_type reqtype,
920
+
loff_t offs, struct mtd_oob_ops *req,
921
+
struct nand_io_iter *iter)
925
922
{
926
923
struct mtd_info *mtd = nanddev_to_mtd(nand);
927
924
···
940
937
iter->req.ooblen = min_t(unsigned int,
941
938
iter->oobbytes_per_page - iter->req.ooboffs,
942
939
iter->oobleft);
940
+
iter->req.continuous = false;
941
+
}
942
+
943
+
/**
944
+
* nand_io_block_iter_init - Initialize a NAND I/O iterator
945
+
* @nand: NAND device
946
+
* @offs: absolute offset
947
+
* @req: MTD request
948
+
* @iter: NAND I/O iterator
949
+
*
950
+
* Initializes a NAND iterator based on the information passed by the MTD
951
+
* layer for block jumps (no OOB)
952
+
*
953
+
* In practice only reads may leverage this iterator.
954
+
*/
955
+
static inline void nanddev_io_block_iter_init(struct nand_device *nand,
956
+
enum nand_page_io_req_type reqtype,
957
+
loff_t offs, struct mtd_oob_ops *req,
958
+
struct nand_io_iter *iter)
959
+
{
960
+
unsigned int offs_in_eb;
961
+
962
+
iter->req.type = reqtype;
963
+
iter->req.mode = req->mode;
964
+
iter->req.dataoffs = nanddev_offs_to_pos(nand, offs, &iter->req.pos);
965
+
iter->req.ooboffs = 0;
966
+
iter->oobbytes_per_page = 0;
967
+
iter->dataleft = req->len;
968
+
iter->oobleft = 0;
969
+
iter->req.databuf.in = req->datbuf;
970
+
offs_in_eb = (nand->memorg.pagesize * iter->req.pos.page) + iter->req.dataoffs;
971
+
iter->req.datalen = min_t(unsigned int,
972
+
nanddev_eraseblock_size(nand) - offs_in_eb,
973
+
iter->dataleft);
974
+
iter->req.oobbuf.in = NULL;
975
+
iter->req.ooblen = 0;
976
+
iter->req.continuous = true;
943
977
}
944
978
945
979
/**
···
1000
960
iter->dataleft);
1001
961
iter->req.ooblen = min_t(unsigned int, iter->oobbytes_per_page,
1002
962
iter->oobleft);
963
+
}
964
+
965
+
/**
966
+
* nand_io_iter_next_block - Move to the next block
967
+
* @nand: NAND device
968
+
* @iter: NAND I/O iterator
969
+
*
970
+
* Updates the @iter to point to the next block.
971
+
* No OOB handling available.
972
+
*/
973
+
static inline void nanddev_io_iter_next_block(struct nand_device *nand,
974
+
struct nand_io_iter *iter)
975
+
{
976
+
nanddev_pos_next_eraseblock(nand, &iter->req.pos);
977
+
iter->dataleft -= iter->req.datalen;
978
+
iter->req.databuf.in += iter->req.datalen;
979
+
iter->req.dataoffs = 0;
980
+
iter->req.datalen = min_t(unsigned int, nanddev_eraseblock_size(nand),
981
+
iter->dataleft);
1003
982
}
1004
983
1005
984
/**
···
1049
990
* @req: MTD I/O request
1050
991
* @iter: NAND I/O iterator
1051
992
*
1052
-
* Should be used for iterate over pages that are contained in an MTD request.
993
+
* Should be used for iterating over pages that are contained in an MTD request.
1053
994
*/
1054
995
#define nanddev_io_for_each_page(nand, type, start, req, iter) \
1055
-
for (nanddev_io_iter_init(nand, type, start, req, iter); \
996
+
for (nanddev_io_page_iter_init(nand, type, start, req, iter); \
1056
997
!nanddev_io_iter_end(nand, iter); \
1057
998
nanddev_io_iter_next_page(nand, iter))
999
+
1000
+
/**
1001
+
* nand_io_for_each_block - Iterate over all NAND pages contained in an MTD I/O
1002
+
* request, one block at a time
1003
+
* @nand: NAND device
1004
+
* @start: start address to read/write from
1005
+
* @req: MTD I/O request
1006
+
* @iter: NAND I/O iterator
1007
+
*
1008
+
* Should be used for iterating over blocks that are contained in an MTD request.
1009
+
*/
1010
+
#define nanddev_io_for_each_block(nand, type, start, req, iter) \
1011
+
for (nanddev_io_block_iter_init(nand, type, start, req, iter); \
1012
+
!nanddev_io_iter_end(nand, iter); \
1013
+
nanddev_io_iter_next_block(nand, iter))
1058
1014
1059
1015
bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos);
1060
1016
bool nanddev_isreserved(struct nand_device *nand, const struct nand_pos *pos);
+19
include/linux/mtd/spinand.h
+19
include/linux/mtd/spinand.h
···
312
312
313
313
#define SPINAND_HAS_QE_BIT BIT(0)
314
314
#define SPINAND_HAS_CR_FEAT_BIT BIT(1)
315
+
#define SPINAND_HAS_PROG_PLANE_SELECT_BIT BIT(2)
316
+
#define SPINAND_HAS_READ_PLANE_SELECT_BIT BIT(3)
315
317
316
318
/**
317
319
* struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure
···
338
336
* @op_variants.update_cache: variants of the update-cache operation
339
337
* @select_target: function used to select a target/die. Required only for
340
338
* multi-die chips
339
+
* @set_cont_read: enable/disable continuous cached reads
341
340
*
342
341
* Each SPI NAND manufacturer driver should have a spinand_info table
343
342
* describing all the chips supported by the driver.
···
357
354
} op_variants;
358
355
int (*select_target)(struct spinand_device *spinand,
359
356
unsigned int target);
357
+
int (*set_cont_read)(struct spinand_device *spinand,
358
+
bool enable);
360
359
};
361
360
362
361
#define SPINAND_ID(__method, ...) \
···
383
378
384
379
#define SPINAND_SELECT_TARGET(__func) \
385
380
.select_target = __func,
381
+
382
+
#define SPINAND_CONT_READ(__set_cont_read) \
383
+
.set_cont_read = __set_cont_read,
386
384
387
385
#define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \
388
386
__flags, ...) \
···
430
422
* passed in spi_mem_op be DMA-able, so we can't based the bufs on
431
423
* the stack
432
424
* @manufacturer: SPI NAND manufacturer information
425
+
* @cont_read_possible: Field filled by the core once the whole system
426
+
* configuration is known to tell whether continuous reads are
427
+
* suitable to use or not in general with this chip/configuration.
428
+
* A per-transfer check must of course be done to ensure it is
429
+
* actually relevant to enable this feature.
430
+
* @set_cont_read: Enable/disable the continuous read feature
433
431
* @priv: manufacturer private data
434
432
*/
435
433
struct spinand_device {
···
465
451
u8 *scratchbuf;
466
452
const struct spinand_manufacturer *manufacturer;
467
453
void *priv;
454
+
455
+
bool cont_read_possible;
456
+
int (*set_cont_read)(struct spinand_device *spinand,
457
+
bool enable);
468
458
};
469
459
470
460
/**
···
535
517
enum spinand_readid_method rdid_method);
536
518
537
519
int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
520
+
int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val);
538
521
int spinand_select_target(struct spinand_device *spinand, unsigned int target);
539
522
540
523
#endif /* __LINUX_MTD_SPINAND_H */
-36
include/linux/platform_data/mtd-davinci-aemif.h
-36
include/linux/platform_data/mtd-davinci-aemif.h
···
1
-
/*
2
-
* TI DaVinci AEMIF support
3
-
*
4
-
* Copyright 2010 (C) Texas Instruments, Inc. https://www.ti.com/
5
-
*
6
-
* This file is licensed under the terms of the GNU General Public License
7
-
* version 2. This program is licensed "as is" without any warranty of any
8
-
* kind, whether express or implied.
9
-
*/
10
-
#ifndef _MACH_DAVINCI_AEMIF_H
11
-
#define _MACH_DAVINCI_AEMIF_H
12
-
13
-
#include <linux/platform_device.h>
14
-
15
-
#define NRCSR_OFFSET 0x00
16
-
#define AWCCR_OFFSET 0x04
17
-
#define A1CR_OFFSET 0x10
18
-
19
-
#define ACR_ASIZE_MASK 0x3
20
-
#define ACR_EW_MASK BIT(30)
21
-
#define ACR_SS_MASK BIT(31)
22
-
23
-
/* All timings in nanoseconds */
24
-
struct davinci_aemif_timing {
25
-
u8 wsetup;
26
-
u8 wstrobe;
27
-
u8 whold;
28
-
29
-
u8 rsetup;
30
-
u8 rstrobe;
31
-
u8 rhold;
32
-
33
-
u8 ta;
34
-
};
35
-
36
-
#endif
-88
include/linux/platform_data/mtd-davinci.h
-88
include/linux/platform_data/mtd-davinci.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0-or-later */
2
-
/*
3
-
* mach-davinci/nand.h
4
-
*
5
-
* Copyright © 2006 Texas Instruments.
6
-
*
7
-
* Ported to 2.6.23 Copyright © 2008 by
8
-
* Sander Huijsen <Shuijsen@optelecom-nkf.com>
9
-
* Troy Kisky <troy.kisky@boundarydevices.com>
10
-
* Dirk Behme <Dirk.Behme@gmail.com>
11
-
*
12
-
* --------------------------------------------------------------------------
13
-
*/
14
-
15
-
#ifndef __ARCH_ARM_DAVINCI_NAND_H
16
-
#define __ARCH_ARM_DAVINCI_NAND_H
17
-
18
-
#include <linux/mtd/rawnand.h>
19
-
20
-
#define NANDFCR_OFFSET 0x60
21
-
#define NANDFSR_OFFSET 0x64
22
-
#define NANDF1ECC_OFFSET 0x70
23
-
24
-
/* 4-bit ECC syndrome registers */
25
-
#define NAND_4BIT_ECC_LOAD_OFFSET 0xbc
26
-
#define NAND_4BIT_ECC1_OFFSET 0xc0
27
-
#define NAND_4BIT_ECC2_OFFSET 0xc4
28
-
#define NAND_4BIT_ECC3_OFFSET 0xc8
29
-
#define NAND_4BIT_ECC4_OFFSET 0xcc
30
-
#define NAND_ERR_ADD1_OFFSET 0xd0
31
-
#define NAND_ERR_ADD2_OFFSET 0xd4
32
-
#define NAND_ERR_ERRVAL1_OFFSET 0xd8
33
-
#define NAND_ERR_ERRVAL2_OFFSET 0xdc
34
-
35
-
/* NOTE: boards don't need to use these address bits
36
-
* for ALE/CLE unless they support booting from NAND.
37
-
* They're used unless platform data overrides them.
38
-
*/
39
-
#define MASK_ALE 0x08
40
-
#define MASK_CLE 0x10
41
-
42
-
struct davinci_nand_pdata { /* platform_data */
43
-
uint32_t mask_ale;
44
-
uint32_t mask_cle;
45
-
46
-
/*
47
-
* 0-indexed chip-select number of the asynchronous
48
-
* interface to which the NAND device has been connected.
49
-
*
50
-
* So, if you have NAND connected to CS3 of DA850, you
51
-
* will pass '1' here. Since the asynchronous interface
52
-
* on DA850 starts from CS2.
53
-
*/
54
-
uint32_t core_chipsel;
55
-
56
-
/* for packages using two chipselects */
57
-
uint32_t mask_chipsel;
58
-
59
-
/* board's default static partition info */
60
-
struct mtd_partition *parts;
61
-
unsigned nr_parts;
62
-
63
-
/* none == NAND_ECC_ENGINE_TYPE_NONE (strongly *not* advised!!)
64
-
* soft == NAND_ECC_ENGINE_TYPE_SOFT
65
-
* else == NAND_ECC_ENGINE_TYPE_ON_HOST, according to ecc_bits
66
-
*
67
-
* All DaVinci-family chips support 1-bit hardware ECC.
68
-
* Newer ones also support 4-bit ECC, but are awkward
69
-
* using it with large page chips.
70
-
*/
71
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enum nand_ecc_engine_type engine_type;
72
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enum nand_ecc_placement ecc_placement;
73
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u8 ecc_bits;
74
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75
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/* e.g. NAND_BUSWIDTH_16 */
76
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unsigned options;
77
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/* e.g. NAND_BBT_USE_FLASH */
78
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unsigned bbt_options;
79
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80
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/* Main and mirror bbt descriptor overrides */
81
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struct nand_bbt_descr *bbt_td;
82
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struct nand_bbt_descr *bbt_md;
83
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84
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/* Access timings */
85
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struct davinci_aemif_timing *timing;
86
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};
87
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88
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#endif /* __ARCH_ARM_DAVINCI_NAND_H */