Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm64: dts: qcom: msm8916: specify per-sensor calibration cells
Specify pre-parsed per-sensor calibration nvmem cells in the tsens
device node rather than parsing the whole data blob in the driver.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230101194034.831222-17-dmitry.baryshkov@linaro.org
authored by
Dmitry Baryshkov
and committed by
Bjorn Andersson
24aafd04
0b3aa9aa
+79
-6
+79
-6
arch/arm64/boot/dts/qcom/msm8916.dtsi
+79
-6
arch/arm64/boot/dts/qcom/msm8916.dtsi
···
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reg = <0x0005c000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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-
tsens_caldata: caldata@d0 {
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-
reg = <0xd0 0x8>;
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+
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+
tsens_base1: base1@d0 {
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+
reg = <0xd0 0x1>;
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+
bits = <0 7>;
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};
448
-
tsens_calsel: calsel@ec {
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-
reg = <0xec 0x4>;
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+
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+
tsens_s0_p1: s0-p1@d0 {
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+
reg = <0xd0 0x2>;
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+
bits = <7 5>;
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+
};
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+
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+
tsens_s0_p2: s0-p2@d1 {
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+
reg = <0xd1 0x2>;
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+
bits = <4 5>;
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+
};
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+
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+
tsens_s1_p1: s1-p1@d2 {
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+
reg = <0xd2 0x1>;
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+
bits = <1 5>;
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+
};
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+
tsens_s1_p2: s1-p2@d2 {
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+
reg = <0xd2 0x2>;
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+
bits = <6 5>;
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+
};
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+
tsens_s2_p1: s2-p1@d3 {
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+
reg = <0xd3 0x1>;
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+
bits = <3 5>;
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+
};
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+
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+
tsens_s2_p2: s2-p2@d4 {
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+
reg = <0xd4 0x1>;
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+
bits = <0 5>;
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+
};
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+
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+
// no tsens with hw_id 3
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+
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+
tsens_s4_p1: s4-p1@d4 {
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+
reg = <0xd4 0x2>;
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+
bits = <5 5>;
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+
};
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+
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+
tsens_s4_p2: s4-p2@d5 {
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+
reg = <0xd5 0x1>;
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+
bits = <2 5>;
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+
};
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+
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+
tsens_s5_p1: s5-p1@d5 {
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+
reg = <0xd5 0x2>;
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+
bits = <7 5>;
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+
};
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+
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+
tsens_s5_p2: s5-p2@d6 {
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+
reg = <0xd6 0x2>;
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+
bits = <4 5>;
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+
};
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+
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+
tsens_base2: base2@d7 {
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+
reg = <0xd7 0x1>;
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+
bits = <1 7>;
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+
};
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+
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+
tsens_mode: mode@ec {
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+
reg = <0xef 0x1>;
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+
bits = <5 3>;
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};
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};
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511
···
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compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
533
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reg = <0x004a9000 0x1000>, /* TM */
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<0x004a8000 0x1000>; /* SROT */
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-
nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
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-
nvmem-cell-names = "calib", "calib_sel";
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+
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+
// no hw_id 3
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+
nvmem-cells = <&tsens_mode>,
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+
<&tsens_base1>, <&tsens_base2>,
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+
<&tsens_s0_p1>, <&tsens_s0_p2>,
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+
<&tsens_s1_p1>, <&tsens_s1_p2>,
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+
<&tsens_s2_p1>, <&tsens_s2_p2>,
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+
<&tsens_s4_p1>, <&tsens_s4_p2>,
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+
<&tsens_s5_p1>, <&tsens_s5_p2>;
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+
nvmem-cell-names = "mode",
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+
"base1", "base2",
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+
"s0_p1", "s0_p2",
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+
"s1_p1", "s1_p2",
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+
"s2_p1", "s2_p2",
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+
"s4_p1", "s4_p2",
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+
"s5_p1", "s5_p2";
537
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#qcom,sensors = <5>;
538
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
539
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interrupt-names = "uplow";