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Merge tag 'mfd-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones:
"New Support & Features:

- Add extensive support for the Analog Devices ADP5589 I/O expander,
including core MFD, GPIO, PWM, and a new keypad matrix input
driver. This also adds support for handling various events
including GPI, keypad, reset and unlock ev ents

- Add support for the TI TPS652G1 PMIC, a stripped-down version of
the TPS65224, including core MFD, PFSM, pinctrl, and GPIO support

- Add support for the Apple Silicon System Management Controller
(SMC), including the core MFD driver which handles the RTKit-based
protocol, a new GPIO driver for PMU GPIOs, and a new
reboot/power-off driver.

Improvements & Fixes:

- Dynamically add ADP5585 sub-devices based on device tree properties

- Move ADP5585 oscillator control from the child PWM driver to the
main MFD driver to better handle shared resources

- Add support for a hardware reset pin and VDD regulator to the
ADP5585 driver

- Update the TPS65219 MFD cell's GPIO compatible string for the
TPS65214 to reflect hardware capabilities correctly

- Separate the ChromeOS EC charge-control probing from the USB-PD
subsystem, allowing it to probe independently based on the
dedicated EC_FEATURE_CHARGER

- Fix an interrupt naming typo in the MT6370 driver

- Fix RK806 PMIC reset behavior by allowing the reset mode to be
customized via a new device tree property

- Fix AXP20X regulator cell ID conflicts for secondary PMICs on
boards without an IRQ line connected

- Fix MT6397 keypad sub-device creation to use specific names instead
of a generic one, ensuring correct driver binding

- Fix a build warning in the stm32-timers driver by adding a missing
include for export.h.

Cleanups & Refactoring:

- Refactor the ADP5585 driver to simplify how regmap defaults are
handled, making it easier to add new chip variants

- Introduce per-chip register map structures for the ADP5585/ADP5589
family to handle differences between the devices

- Convert several drivers to use dev_fwnode() instead of
of_fwnode_handle()

- Make various static structures const in the cs40l50, rohm-bd71828,
tps65219, and twl6040 drivers

- Remove redundant pm_runtime_mark_last_busy() calls from several
drivers

- Alphabetize Kconfig entries for Cirrus Logic and Maxim drivers

- Remove unused fields from the 'tps65219' struct

- Update several MFD-related headers to follow the 'Include What You
Use' (IWYU) principle.

Removals:

- Remove the old, platform-data-based adp5589-keys input driver,
which is now superseded by the new MFD-based adp5585-keys driver

- Remove the unused twl6030_mmc_card_detect() functions and
associated header declarations

- Remove the now unused pcf50633/core.h header file

- Remove the fsl,imx8qxp-csr device tree binding, which was being
used incorrectly.

Device Tree Bindings Updates:

- Add support for the Analog Devices ADP5589 I/O expander to the
adi,adp5585.yaml binding

- Add new properties to the adi,adp5585.yaml binding for input
events, including keypad pins, unlock events, and reset events

- Add a reset-gpios property to the adi,adp5585.yaml binding

- Add the TI TPS652G1 PMIC to the ti,tps6594.yaml binding

- Add new bindings for the Apple Mac System Management Controller
(SMC) and its sub-devices: apple,smc.yaml, apple,smc-gpio.yaml, and
apple,smc-reboot.yaml

- Convert the Freescale MXS LRADC binding (mxs-lradc) to YAML schema
format

- Convert and combine the NXP LPC1850 CREG, DMAMUX, and USB OTG PHY
bindings into a single YAML schema file

- Convert the TI TPS65910 binding to YAML schema format

- Add a comment to the samsung,s2mps11.yaml binding to clarify the
use of 'oneOf' for interrupt properties

- Add the rockchip,reset-mode property to the rockchip,rk806.yaml
binding to allow customization of the PMIC's reset behavior"

* tag 'mfd-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (28 commits)
mfd: dt-bindings: Convert TPS65910 to DT schema
mfd: Minor Cirrus/Maxim Kconfig order fixes
mfd: Remove redundant pm_runtime_mark_last_busy() calls
mfd: mt6397: Do not use generic name for keypad sub-devices
mfd: axp20x: Set explicit ID for regulator cell if no IRQ line is present
mfd: mt6370: Fix the interrupt naming typo
mfd: rk8xx-core: Allow to customize RK806 reset mode
dt-bindings: mfd: rk806: Allow to customize PMIC reset mode
mfd: syscon: atmel-smc: Don't use "proxy" headers
mfd: madera: Don't use "proxy" headers
mfd: wm8350-core: Don't use "proxy" headers
dt-bindings: mfd: samsung,s2mps11: Add comment about interrupts properties
mfd: davinci_voicecodec: Don't use "proxy" headers
mfd: pcf50633: Remove the header file core.h
mfd: tps65219: Remove another unused field from 'struct tps65219'
mfd: tps65219: Remove an unused field from 'struct tps65219'
mfd: tps65219: Constify struct regmap_irq_sub_irq_map and tps65219_chip_data
mfd: rohm-bd71828: Constify some structures
dt-bindings: mfd: fsl,imx8qxp-csr: Remove binding documentation
mfd: axp20x: Set explicit ID for AXP313 regulator
...

Linus Torvalds 24e5c324 cfc6d745

+779 -1024
-52
Documentation/devicetree/bindings/clock/lpc1850-creg-clk.txt
··· 1 - * NXP LPC1850 CREG clocks 2 - 3 - The NXP LPC18xx/43xx CREG (Configuration Registers) block contains 4 - control registers for two low speed clocks. One of the clocks is a 5 - 32 kHz oscillator driver with power up/down and clock gating. Next 6 - is a fixed divider that creates a 1 kHz clock from the 32 kHz osc. 7 - 8 - These clocks are used by the RTC and the Event Router peripherals. 9 - The 32 kHz can also be routed to other peripherals to enable low 10 - power modes. 11 - 12 - This binding uses the common clock binding: 13 - Documentation/devicetree/bindings/clock/clock-bindings.txt 14 - 15 - Required properties: 16 - - compatible: 17 - Should be "nxp,lpc1850-creg-clk" 18 - - #clock-cells: 19 - Shall have value <1>. 20 - - clocks: 21 - Shall contain a phandle to the fixed 32 kHz crystal. 22 - 23 - The creg-clk node must be a child of the creg syscon node. 24 - 25 - The following clocks are available from the clock node. 26 - 27 - Clock ID Name 28 - 0 1 kHz clock 29 - 1 32 kHz Oscillator 30 - 31 - Example: 32 - soc { 33 - creg: syscon@40043000 { 34 - compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; 35 - reg = <0x40043000 0x1000>; 36 - 37 - creg_clk: clock-controller { 38 - compatible = "nxp,lpc1850-creg-clk"; 39 - clocks = <&xtal32>; 40 - #clock-cells = <1>; 41 - }; 42 - 43 - ... 44 - }; 45 - 46 - rtc: rtc@40046000 { 47 - ... 48 - clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>; 49 - clock-names = "rtc", "reg"; 50 - ... 51 - }; 52 - };
-54
Documentation/devicetree/bindings/dma/lpc1850-dmamux.txt
··· 1 - NXP LPC18xx/43xx DMA MUX (DMA request router) 2 - 3 - Required properties: 4 - - compatible: "nxp,lpc1850-dmamux" 5 - - reg: Memory map for accessing module 6 - - #dma-cells: Should be set to <3>. 7 - * 1st cell contain the master dma request signal 8 - * 2nd cell contain the mux value (0-3) for the peripheral 9 - * 3rd cell contain either 1 or 2 depending on the AHB 10 - master used. 11 - - dma-requests: Number of DMA requests for the mux 12 - - dma-masters: phandle pointing to the DMA controller 13 - 14 - The DMA controller node need to have the following poroperties: 15 - - dma-requests: Number of DMA requests the controller can handle 16 - 17 - Example: 18 - 19 - dmac: dma@40002000 { 20 - compatible = "nxp,lpc1850-gpdma", "arm,pl080", "arm,primecell"; 21 - arm,primecell-periphid = <0x00041080>; 22 - reg = <0x40002000 0x1000>; 23 - interrupts = <2>; 24 - clocks = <&ccu1 CLK_CPU_DMA>; 25 - clock-names = "apb_pclk"; 26 - #dma-cells = <2>; 27 - dma-channels = <8>; 28 - dma-requests = <16>; 29 - lli-bus-interface-ahb1; 30 - lli-bus-interface-ahb2; 31 - mem-bus-interface-ahb1; 32 - mem-bus-interface-ahb2; 33 - memcpy-burst-size = <256>; 34 - memcpy-bus-width = <32>; 35 - }; 36 - 37 - dmamux: dma-mux { 38 - compatible = "nxp,lpc1850-dmamux"; 39 - #dma-cells = <3>; 40 - dma-requests = <64>; 41 - dma-masters = <&dmac>; 42 - }; 43 - 44 - uart0: serial@40081000 { 45 - compatible = "nxp,lpc1850-uart", "ns16550a"; 46 - reg = <0x40081000 0x1000>; 47 - reg-shift = <2>; 48 - interrupts = <24>; 49 - clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; 50 - clock-names = "uartclk", "reg"; 51 - dmas = <&dmamux 1 1 2 52 - &dmamux 2 1 2>; 53 - dma-names = "tx", "rx"; 54 - };
-192
Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
··· 1 - # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 - %YAML 1.2 3 - --- 4 - $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml# 5 - $schema: http://devicetree.org/meta-schemas/core.yaml# 6 - 7 - title: Freescale i.MX8qm/qxp Control and Status Registers Module 8 - 9 - maintainers: 10 - - Liu Ying <victor.liu@nxp.com> 11 - 12 - description: | 13 - As a system controller, the Freescale i.MX8qm/qxp Control and Status 14 - Registers(CSR) module represents a set of miscellaneous registers of a 15 - specific subsystem. It may provide control and/or status report interfaces 16 - to a mix of standalone hardware devices within that subsystem. One typical 17 - use-case is for some other nodes to acquire a reference to the syscon node 18 - by phandle, and the other typical use-case is that the operating system 19 - should consider all subnodes of the CSR module as separate child devices. 20 - 21 - properties: 22 - $nodename: 23 - pattern: "^syscon@[0-9a-f]+$" 24 - 25 - compatible: 26 - items: 27 - - enum: 28 - - fsl,imx8qxp-mipi-lvds-csr 29 - - fsl,imx8qm-lvds-csr 30 - - const: syscon 31 - - const: simple-mfd 32 - 33 - reg: 34 - maxItems: 1 35 - 36 - clocks: 37 - maxItems: 1 38 - 39 - clock-names: 40 - const: ipg 41 - 42 - patternProperties: 43 - "^(ldb|phy|pxl2dpi)$": 44 - type: object 45 - description: The possible child devices of the CSR module. 46 - 47 - required: 48 - - compatible 49 - - reg 50 - - clocks 51 - - clock-names 52 - 53 - allOf: 54 - - if: 55 - properties: 56 - compatible: 57 - contains: 58 - const: fsl,imx8qxp-mipi-lvds-csr 59 - then: 60 - required: 61 - - pxl2dpi 62 - - ldb 63 - 64 - - if: 65 - properties: 66 - compatible: 67 - contains: 68 - const: fsl,imx8qm-lvds-csr 69 - then: 70 - required: 71 - - phy 72 - - ldb 73 - 74 - additionalProperties: false 75 - 76 - examples: 77 - - | 78 - #include <dt-bindings/clock/imx8-lpcg.h> 79 - #include <dt-bindings/firmware/imx/rsrc.h> 80 - mipi_lvds_0_csr: syscon@56221000 { 81 - compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd"; 82 - reg = <0x56221000 0x1000>; 83 - clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>; 84 - clock-names = "ipg"; 85 - 86 - mipi_lvds_0_pxl2dpi: pxl2dpi { 87 - compatible = "fsl,imx8qxp-pxl2dpi"; 88 - fsl,sc-resource = <IMX_SC_R_MIPI_0>; 89 - power-domains = <&pd IMX_SC_R_MIPI_0>; 90 - 91 - ports { 92 - #address-cells = <1>; 93 - #size-cells = <0>; 94 - 95 - port@0 { 96 - #address-cells = <1>; 97 - #size-cells = <0>; 98 - reg = <0>; 99 - 100 - mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 { 101 - reg = <0>; 102 - remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>; 103 - }; 104 - 105 - mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 { 106 - reg = <1>; 107 - remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>; 108 - }; 109 - }; 110 - 111 - port@1 { 112 - #address-cells = <1>; 113 - #size-cells = <0>; 114 - reg = <1>; 115 - 116 - mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 { 117 - reg = <0>; 118 - remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>; 119 - }; 120 - 121 - mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 { 122 - reg = <1>; 123 - remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>; 124 - }; 125 - }; 126 - }; 127 - }; 128 - 129 - mipi_lvds_0_ldb: ldb { 130 - #address-cells = <1>; 131 - #size-cells = <0>; 132 - compatible = "fsl,imx8qxp-ldb"; 133 - clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, 134 - <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; 135 - clock-names = "pixel", "bypass"; 136 - power-domains = <&pd IMX_SC_R_LVDS_0>; 137 - 138 - channel@0 { 139 - #address-cells = <1>; 140 - #size-cells = <0>; 141 - reg = <0>; 142 - phys = <&mipi_lvds_0_phy>; 143 - phy-names = "lvds_phy"; 144 - 145 - port@0 { 146 - reg = <0>; 147 - 148 - mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint { 149 - remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>; 150 - }; 151 - }; 152 - 153 - port@1 { 154 - reg = <1>; 155 - 156 - /* ... */ 157 - }; 158 - }; 159 - 160 - channel@1 { 161 - #address-cells = <1>; 162 - #size-cells = <0>; 163 - reg = <1>; 164 - phys = <&mipi_lvds_0_phy>; 165 - phy-names = "lvds_phy"; 166 - 167 - port@0 { 168 - reg = <0>; 169 - 170 - mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint { 171 - remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>; 172 - }; 173 - }; 174 - 175 - port@1 { 176 - reg = <1>; 177 - 178 - /* ... */ 179 - }; 180 - }; 181 - }; 182 - }; 183 - 184 - mipi_lvds_0_phy: phy@56228300 { 185 - compatible = "fsl,imx8qxp-mipi-dphy"; 186 - reg = <0x56228300 0x100>; 187 - clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; 188 - clock-names = "phy_ref"; 189 - #phy-cells = <0>; 190 - fsl,syscon = <&mipi_lvds_0_csr>; 191 - power-domains = <&pd IMX_SC_R_MIPI_0>; 192 - };
-45
Documentation/devicetree/bindings/mfd/mxs-lradc.txt
··· 1 - * Freescale MXS LRADC device driver 2 - 3 - Required properties: 4 - - compatible: Should be "fsl,imx23-lradc" for i.MX23 SoC and "fsl,imx28-lradc" 5 - for i.MX28 SoC 6 - - reg: Address and length of the register set for the device 7 - - interrupts: Should contain the LRADC interrupts 8 - 9 - Optional properties: 10 - - fsl,lradc-touchscreen-wires: Number of wires used to connect the touchscreen 11 - to LRADC. Valid value is either 4 or 5. If this 12 - property is not present, then the touchscreen is 13 - disabled. 5 wires is valid for i.MX28 SoC only. 14 - - fsl,ave-ctrl: number of samples per direction to calculate an average value. 15 - Allowed value is 1 ... 32, default is 4 16 - - fsl,ave-delay: delay between consecutive samples. Allowed value is 17 - 2 ... 2048. It is used if 'fsl,ave-ctrl' > 1, counts at 18 - 2 kHz and its default is 2 (= 1 ms) 19 - - fsl,settling: delay between plate switch to next sample. Allowed value is 20 - 1 ... 2047. It counts at 2 kHz and its default is 21 - 10 (= 5 ms) 22 - 23 - Example for i.MX23 SoC: 24 - 25 - lradc@80050000 { 26 - compatible = "fsl,imx23-lradc"; 27 - reg = <0x80050000 0x2000>; 28 - interrupts = <36 37 38 39 40 41 42 43 44>; 29 - fsl,lradc-touchscreen-wires = <4>; 30 - fsl,ave-ctrl = <4>; 31 - fsl,ave-delay = <2>; 32 - fsl,settling = <10>; 33 - }; 34 - 35 - Example for i.MX28 SoC: 36 - 37 - lradc@80050000 { 38 - compatible = "fsl,imx28-lradc"; 39 - reg = <0x80050000 0x2000>; 40 - interrupts = <10 14 15 16 17 18 19 20 21 22 23 24 25>; 41 - fsl,lradc-touchscreen-wires = <5>; 42 - fsl,ave-ctrl = <4>; 43 - fsl,ave-delay = <2>; 44 - fsl,settling = <10>; 45 - };
+134
Documentation/devicetree/bindings/mfd/mxs-lradc.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mfd/mxs-lradc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale MXS Low-Resolution ADC (LRADC) 8 + 9 + maintainers: 10 + - Dario Binacchi <dario.binacchi@amarulasolutions.com> 11 + 12 + description: 13 + The LRADC provides 16 physical channels of 12-bit resolution for 14 + analog-to-digital conversion and includes an integrated 4-wire/5-wire 15 + touchscreen controller. 16 + 17 + properties: 18 + compatible: 19 + items: 20 + - enum: 21 + - fsl,imx23-lradc 22 + - fsl,imx28-lradc 23 + 24 + reg: 25 + maxItems: 1 26 + 27 + clocks: 28 + minItems: 1 29 + 30 + interrupts: 31 + minItems: 9 32 + maxItems: 13 33 + 34 + fsl,lradc-touchscreen-wires: 35 + $ref: /schemas/types.yaml#/definitions/uint32 36 + enum: [4, 5] 37 + description: > 38 + Number of wires used to connect the touchscreen to LRADC. 39 + 40 + If this property is not present, then the touchscreen is disabled. 41 + 42 + fsl,ave-ctrl: 43 + $ref: /schemas/types.yaml#/definitions/uint32 44 + minimum: 1 45 + maximum: 32 46 + default: 4 47 + description: 48 + Number of samples per direction to calculate an average value. 49 + 50 + fsl,ave-delay: 51 + $ref: /schemas/types.yaml#/definitions/uint32 52 + minimum: 2 53 + maximum: 2048 54 + default: 2 55 + description: > 56 + Delay between consecutive samples. 57 + 58 + It is used if 'fsl,ave-ctrl' > 1, counts at 2 kHz and its default value (2) 59 + is 1 ms. 60 + 61 + fsl,settling: 62 + $ref: /schemas/types.yaml#/definitions/uint32 63 + minimum: 1 64 + maximum: 2047 65 + default: 10 66 + description: > 67 + Delay between plate switch to next sample. 68 + 69 + It counts at 2 kHz and its default (10) is 5 ms. 70 + 71 + "#io-channel-cells": 72 + const: 1 73 + 74 + required: 75 + - compatible 76 + - reg 77 + - clocks 78 + - interrupts 79 + 80 + if: 81 + properties: 82 + compatible: 83 + contains: 84 + enum: 85 + - fsl,imx23-lradc 86 + then: 87 + properties: 88 + interrupts: 89 + items: 90 + - description: channel 0 91 + - description: channel 1 92 + - description: channel 2 93 + - description: channel 3 94 + - description: channel 4 95 + - description: channel 5 96 + - description: touchscreen 97 + - description: channel 6 98 + - description: channel 7 99 + fsl,lradc-touchscreen-wires: 100 + const: 4 101 + else: 102 + properties: 103 + interrupts: 104 + items: 105 + - description: threshold 0 106 + - description: threshold 1 107 + - description: channel 0 108 + - description: channel 1 109 + - description: channel 2 110 + - description: channel 3 111 + - description: channel 4 112 + - description: channel 5 113 + - description: button 0 114 + - description: button 1 115 + - description: touchscreen 116 + - description: channel 6 117 + - description: channel 7 118 + 119 + additionalProperties: false 120 + 121 + examples: 122 + - | 123 + lradc@80050000 { 124 + compatible = "fsl,imx23-lradc"; 125 + reg = <0x80050000 0x2000>; 126 + interrupts = <36>, <37>, <38>, <39>, <40>, 127 + <41>, <42>, <43>, <44>; 128 + clocks = <&clks 26>; 129 + #io-channel-cells = <1>; 130 + fsl,lradc-touchscreen-wires = <4>; 131 + fsl,ave-ctrl = <4>; 132 + fsl,ave-delay = <2>; 133 + fsl,settling = <10>; 134 + };
+148
Documentation/devicetree/bindings/mfd/nxp,lpc1850-creg.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mfd/nxp,lpc1850-creg.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: The NXP LPC18xx/43xx CREG (Configuration Registers) block 8 + 9 + maintainers: 10 + - Frank Li <Frank.Li@nxp.com> 11 + 12 + properties: 13 + compatible: 14 + items: 15 + - enum: 16 + - nxp,lpc1850-creg 17 + - const: syscon 18 + - const: simple-mfd 19 + 20 + reg: 21 + maxItems: 1 22 + 23 + clocks: 24 + maxItems: 1 25 + 26 + resets: 27 + maxItems: 1 28 + 29 + clock-controller: 30 + type: object 31 + description: 32 + The NXP LPC18xx/43xx CREG (Configuration Registers) block contains 33 + control registers for two low speed clocks. One of the clocks is a 34 + 32 kHz oscillator driver with power up/down and clock gating. Next 35 + is a fixed divider that creates a 1 kHz clock from the 32 kHz osc. 36 + 37 + These clocks are used by the RTC and the Event Router peripherals. 38 + The 32 kHz can also be routed to other peripherals to enable low 39 + power modes. 40 + 41 + properties: 42 + compatible: 43 + const: nxp,lpc1850-creg-clk 44 + 45 + clocks: 46 + maxItems: 1 47 + 48 + '#clock-cells': 49 + const: 1 50 + description: | 51 + 0 1 kHz clock 52 + 1 32 kHz Oscillator 53 + 54 + required: 55 + - compatible 56 + - clocks 57 + - '#clock-cells' 58 + 59 + additionalProperties: false 60 + 61 + phy: 62 + type: object 63 + description: the internal USB OTG PHY in NXP LPC18xx and LPC43xx SoCs 64 + properties: 65 + compatible: 66 + const: nxp,lpc1850-usb-otg-phy 67 + 68 + clocks: 69 + maxItems: 1 70 + 71 + '#phy-cells': 72 + const: 0 73 + 74 + required: 75 + - compatible 76 + - clocks 77 + - '#phy-cells' 78 + 79 + additionalProperties: false 80 + 81 + dma-mux: 82 + type: object 83 + description: NXP LPC18xx/43xx DMA MUX (DMA request router) 84 + properties: 85 + compatible: 86 + const: nxp,lpc1850-dmamux 87 + 88 + '#dma-cells': 89 + const: 3 90 + description: | 91 + Should be set to <3>. 92 + * 1st cell contain the master dma request signal 93 + * 2nd cell contain the mux value (0-3) for the peripheral 94 + * 3rd cell contain either 1 or 2 depending on the AHB master used. 95 + 96 + dma-requests: 97 + $ref: /schemas/types.yaml#/definitions/uint32 98 + maximum: 64 99 + description: Number of DMA requests the controller can handle 100 + 101 + dma-masters: 102 + $ref: /schemas/types.yaml#/definitions/phandle 103 + description: phandle pointing to the DMA controller 104 + 105 + required: 106 + - compatible 107 + - '#dma-cells' 108 + - dma-masters 109 + 110 + additionalProperties: false 111 + 112 + required: 113 + - compatible 114 + - reg 115 + - clocks 116 + - resets 117 + 118 + additionalProperties: false 119 + 120 + examples: 121 + - | 122 + #include <dt-bindings/clock/lpc18xx-ccu.h> 123 + 124 + syscon@40043000 { 125 + compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; 126 + reg = <0x40043000 0x1000>; 127 + clocks = <&ccu1 CLK_CPU_CREG>; 128 + resets = <&rgu 5>; 129 + 130 + clock-controller { 131 + compatible = "nxp,lpc1850-creg-clk"; 132 + clocks = <&xtal32>; 133 + #clock-cells = <1>; 134 + }; 135 + 136 + phy { 137 + compatible = "nxp,lpc1850-usb-otg-phy"; 138 + clocks = <&ccu1 CLK_USB0>; 139 + #phy-cells = <0>; 140 + }; 141 + 142 + dma-mux { 143 + compatible = "nxp,lpc1850-dmamux"; 144 + #dma-cells = <3>; 145 + dma-requests = <64>; 146 + dma-masters = <&dmac>; 147 + }; 148 + };
+21
Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml
··· 31 31 32 32 system-power-controller: true 33 33 34 + rockchip,reset-mode: 35 + $ref: /schemas/types.yaml#/definitions/uint32 36 + enum: [0, 1, 2] 37 + description: 38 + Mode to use when a reset of the PMIC is triggered. 39 + 40 + The reset can be triggered either programmatically, via one of 41 + the PWRCTRL pins (provided additional configuration) or 42 + asserting RESETB pin low. 43 + 44 + The following modes are supported 45 + 46 + - 0; restart PMU, 47 + - 1; reset all power off reset registers and force state to 48 + switch to ACTIVE mode, 49 + - 2; same as mode 1 and also pull RESETB pin down for 5ms, 50 + 51 + For example, some hardware may require a full restart (mode 0) 52 + in order to function properly as regulators are shortly 53 + interrupted in this mode. 54 + 34 55 vcc1-supply: 35 56 description: 36 57 The input supply for dcdc-reg1.
+3
Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml
··· 81 81 samsung,s2mps11-acokb-ground: false 82 82 samsung,s2mps11-wrstbi-ground: false 83 83 84 + # oneOf is required, because dtschema's fixups.py doesn't handle this 85 + # nesting here. Its special treatment to allow either interrupt property 86 + # when only one is specified in the binding works at the top level only. 84 87 oneOf: 85 88 - required: [interrupts] 86 89 - required: [interrupts-extended]
+318
Documentation/devicetree/bindings/mfd/ti,tps65910.yaml
··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mfd/ti,tps65910.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: TI TPS65910 Power Management Integrated Circuit 8 + 9 + maintainers: 10 + - Shree Ramamoorthy <s-ramamoorthy@ti.com> 11 + 12 + description: 13 + TPS65910 device is a Power Management IC that provides 3 step-down converters, 14 + 1 stepup converter, and 8 LDOs. The device contains an embedded power controller (EPC), 15 + 1 GPIO, and an RTC. 16 + 17 + properties: 18 + compatible: 19 + enum: 20 + - ti,tps65910 21 + - ti,tps65911 22 + 23 + reg: 24 + description: I2C slave address 25 + maxItems: 1 26 + 27 + gpio-controller: true 28 + 29 + '#gpio-cells': 30 + const: 2 31 + description: | 32 + The first cell is the GPIO number. 33 + The second cell is used to specify additional options <unused>. 34 + 35 + interrupts: 36 + maxItems: 1 37 + 38 + interrupt-controller: true 39 + 40 + '#interrupt-cells': 41 + description: Specifies the IRQ number and flags 42 + const: 2 43 + 44 + ti,vmbch-threshold: 45 + description: | 46 + (TPS65911) Main battery charged threshold comparator. 47 + See VMBCH_VSEL in TPS65910 datasheet. 48 + $ref: /schemas/types.yaml#/definitions/uint32 49 + enum: [0, 1, 2, 3] 50 + 51 + ti,vmbch2-threshold: 52 + description: | 53 + (TPS65911) Main battery discharged threshold comparator. 54 + See VMBCH_VSEL in TPS65910 datasheet. 55 + $ref: /schemas/types.yaml#/definitions/uint32 56 + enum: [0, 1, 2, 3] 57 + 58 + ti,en-ck32k-xtal: 59 + type: boolean 60 + description: Enable external 32-kHz crystal oscillator. 61 + 62 + ti,en-gpio-sleep: 63 + description: | 64 + Enable sleep control for gpios. 65 + $ref: /schemas/types.yaml#/definitions/uint32-array 66 + minItems: 9 67 + maxItems: 9 68 + items: 69 + minimum: 0 70 + maximum: 1 71 + 72 + ti,system-power-controller: 73 + type: boolean 74 + description: Identify whether or not this pmic controls the system power 75 + 76 + ti,sleep-enable: 77 + type: boolean 78 + description: Enable SLEEP state. 79 + 80 + ti,sleep-keep-therm: 81 + type: boolean 82 + description: Keep thermal monitoring on in sleep state. 83 + 84 + ti,sleep-keep-ck32k: 85 + type: boolean 86 + description: Keep the 32KHz clock output on in sleep state. 87 + 88 + ti,sleep-keep-hsclk: 89 + type: boolean 90 + description: Keep high speed internal clock on in sleep state. 91 + 92 + regulators: 93 + type: object 94 + additionalProperties: false 95 + description: List of regulators provided by this controller. 96 + 97 + patternProperties: 98 + "^(vrtc|vio|vpll|vdac|vmmc|vbb|vddctrl)$": 99 + type: object 100 + $ref: /schemas/regulator/regulator.yaml# 101 + properties: 102 + ti,regulator-ext-sleep-control: 103 + description: | 104 + Enable external sleep control through external inputs: 105 + [0 (not enabled), 1 (EN1), 2 (EN2) or 4(EN3)]. 106 + If this property is not defined, it defaults to 0 (not enabled). 107 + $ref: /schemas/types.yaml#/definitions/uint32 108 + enum: [0, 1, 2, 4, 8] 109 + unevaluatedProperties: false 110 + 111 + "^(vdd[1-3]|vaux([1-2]|33)|vdig[1-2])$": 112 + type: object 113 + $ref: /schemas/regulator/regulator.yaml# 114 + properties: 115 + ti,regulator-ext-sleep-control: 116 + description: | 117 + Enable external sleep control through external inputs: 118 + [0 (not enabled), 1 (EN1), 2 (EN2) or 4(EN3)]. 119 + If this property is not defined, it defaults to 0 (not enabled). 120 + $ref: /schemas/types.yaml#/definitions/uint32 121 + enum: [0, 1, 2, 4, 8] 122 + unevaluatedProperties: false 123 + 124 + "^ldo[1-8]$": 125 + type: object 126 + $ref: /schemas/regulator/regulator.yaml# 127 + properties: 128 + ti,regulator-ext-sleep-control: 129 + description: | 130 + Enable external sleep control through external inputs: 131 + [0 (not enabled), 1 (EN1), 2 (EN2) or 4(EN3)]. 132 + If this property is not defined, it defaults to 0 (not enabled). 133 + $ref: /schemas/types.yaml#/definitions/uint32 134 + enum: [0, 1, 2, 4, 8] 135 + unevaluatedProperties: false 136 + 137 + patternProperties: 138 + "^(vcc(io|[1-7])-supply)$": 139 + description: | 140 + Input voltage supply phandle for regulators. 141 + These entries are required if PMIC regulators are enabled, or else it 142 + can cause the regulator registration to fail. 143 + 144 + If some input supply is powered through battery or always-on supply, then 145 + it is also required to have these parameters with the proper node handle for always-on 146 + power supply. 147 + tps65910: 148 + vcc1-supply: VDD1 input. 149 + vcc2-supply: VDD2 input. 150 + vcc3-supply: VAUX33 and VMMC input. 151 + vcc4-supply: VAUX1 and VAUX2 input. 152 + vcc5-supply: VPLL and VDAC input. 153 + vcc6-supply: VDIG1 and VDIG2 input. 154 + vcc7-supply: VRTC and VBB input. 155 + vccio-supply: VIO input. 156 + tps65911: 157 + vcc1-supply: VDD1 input. 158 + vcc2-supply: VDD2 input. 159 + vcc3-supply: LDO6, LDO7 and LDO8 input. 160 + vcc4-supply: LDO5 input. 161 + vcc5-supply: LDO3 and LDO4 input. 162 + vcc6-supply: LDO1 and LDO2 input. 163 + vcc7-supply: VRTC input. 164 + vccio-supply: VIO input. 165 + 166 + required: 167 + - compatible 168 + - reg 169 + - interrupts 170 + - interrupt-controller 171 + - '#interrupt-cells' 172 + - gpio-controller 173 + - '#gpio-cells' 174 + - regulators 175 + 176 + additionalProperties: false 177 + 178 + allOf: 179 + - if: 180 + properties: 181 + compatible: 182 + contains: 183 + enum: 184 + - ti,tps65910 185 + then: 186 + properties: 187 + regulators: 188 + patternProperties: 189 + "^(ldo[1-8]|vddctrl)$": false 190 + - if: 191 + properties: 192 + compatible: 193 + contains: 194 + enum: 195 + - ti,tps65911 196 + then: 197 + properties: 198 + regulators: 199 + patternProperties: 200 + "^(vdd3|vaux([1-2]|33)|vdig[1-2])$": false 201 + "^(vpll|vdac|vmmc|vbb)$": false 202 + 203 + examples: 204 + - | 205 + #include <dt-bindings/interrupt-controller/arm-gic.h> 206 + i2c { 207 + #address-cells = <1>; 208 + #size-cells = <0>; 209 + 210 + pmic: tps65910@2d { 211 + compatible = "ti,tps65910"; 212 + reg = <0x2d>; 213 + interrupt-parent = <&intc>; 214 + interrupts = < 0 118 0x04 >; 215 + 216 + #gpio-cells = <2>; 217 + gpio-controller; 218 + 219 + #interrupt-cells = <2>; 220 + interrupt-controller; 221 + 222 + ti,system-power-controller; 223 + 224 + ti,vmbch-threshold = <0>; 225 + ti,vmbch2-threshold = <0>; 226 + ti,en-ck32k-xtal; 227 + ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; 228 + 229 + vcc1-supply = <&reg_parent>; 230 + vcc2-supply = <&some_reg>; 231 + vcc3-supply = <&vbat>; 232 + vcc4-supply = <&vbat>; 233 + vcc5-supply = <&vbat>; 234 + vcc6-supply = <&vbat>; 235 + vcc7-supply = <&vbat>; 236 + vccio-supply = <&vbat>; 237 + 238 + regulators { 239 + vio_reg: vio { 240 + regulator-name = "vio"; 241 + regulator-min-microvolt = <1500000>; 242 + regulator-max-microvolt = <3300000>; 243 + regulator-always-on; 244 + regulator-boot-on; 245 + }; 246 + vdd1_reg: vdd1 { 247 + regulator-name = "vdd1"; 248 + regulator-min-microvolt = < 600000>; 249 + regulator-max-microvolt = <1500000>; 250 + regulator-always-on; 251 + regulator-boot-on; 252 + ti,regulator-ext-sleep-control = <0>; 253 + }; 254 + vdd2_reg: vdd2 { 255 + regulator-name = "vdd2"; 256 + regulator-min-microvolt = < 600000>; 257 + regulator-max-microvolt = <1500000>; 258 + regulator-always-on; 259 + regulator-boot-on; 260 + }; 261 + vdd3_reg: vdd3 { 262 + regulator-name = "vdd3"; 263 + regulator-min-microvolt = <5000000>; 264 + regulator-max-microvolt = <5000000>; 265 + regulator-always-on; 266 + }; 267 + vdig1_reg: vdig1 { 268 + regulator-name = "vdig1"; 269 + regulator-min-microvolt = <1200000>; 270 + regulator-max-microvolt = <2700000>; 271 + regulator-always-on; 272 + }; 273 + vdig2_reg: vdig2 { 274 + regulator-name = "vdig2"; 275 + regulator-min-microvolt = <1000000>; 276 + regulator-max-microvolt = <1800000>; 277 + regulator-always-on; 278 + }; 279 + vpll_reg: vpll { 280 + regulator-name = "vpll"; 281 + regulator-min-microvolt = <1000000>; 282 + regulator-max-microvolt = <2500000>; 283 + regulator-always-on; 284 + }; 285 + vdac_reg: vdac { 286 + regulator-name = "vdac"; 287 + regulator-min-microvolt = <1800000>; 288 + regulator-max-microvolt = <2850000>; 289 + regulator-always-on; 290 + }; 291 + vaux1_reg: vaux1 { 292 + regulator-name = "vaux1"; 293 + regulator-min-microvolt = <1800000>; 294 + regulator-max-microvolt = <2850000>; 295 + regulator-always-on; 296 + }; 297 + vaux2_reg: vaux2 { 298 + regulator-name = "vaux2"; 299 + regulator-min-microvolt = <1800000>; 300 + regulator-max-microvolt = <3300000>; 301 + regulator-always-on; 302 + }; 303 + vaux33_reg: vaux33 { 304 + regulator-name = "vaux33"; 305 + regulator-min-microvolt = <1800000>; 306 + regulator-max-microvolt = <3300000>; 307 + regulator-always-on; 308 + }; 309 + vmmc_reg: vmmc { 310 + regulator-name = "vmmc"; 311 + regulator-min-microvolt = <1800000>; 312 + regulator-max-microvolt = <3300000>; 313 + regulator-always-on; 314 + regulator-boot-on; 315 + }; 316 + }; 317 + }; 318 + };
-205
Documentation/devicetree/bindings/mfd/tps65910.txt
··· 1 - TPS65910 Power Management Integrated Circuit 2 - 3 - Required properties: 4 - - compatible: "ti,tps65910" or "ti,tps65911" 5 - - reg: I2C slave address 6 - - interrupts: the interrupt outputs of the controller 7 - - #gpio-cells: number of cells to describe a GPIO, this should be 2. 8 - The first cell is the GPIO number. 9 - The second cell is used to specify additional options <unused>. 10 - - gpio-controller: mark the device as a GPIO controller 11 - - #interrupt-cells: the number of cells to describe an IRQ, this should be 2. 12 - The first cell is the IRQ number. 13 - The second cell is the flags, encoded as the trigger masks from 14 - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt 15 - - regulators: This is the list of child nodes that specify the regulator 16 - initialization data for defined regulators. Not all regulators for the given 17 - device need to be present. The definition for each of these nodes is defined 18 - using the standard binding for regulators found at 19 - Documentation/devicetree/bindings/regulator/regulator.txt. 20 - The regulator is matched with the regulator-compatible. 21 - 22 - The valid regulator-compatible values are: 23 - tps65910: vrtc, vio, vdd1, vdd2, vdd3, vdig1, vdig2, vpll, vdac, vaux1, 24 - vaux2, vaux33, vmmc, vbb 25 - tps65911: vrtc, vio, vdd1, vdd2, vddctrl, ldo1, ldo2, ldo3, ldo4, ldo5, 26 - ldo6, ldo7, ldo8 27 - 28 - - xxx-supply: Input voltage supply regulator. 29 - These entries are required if regulators are enabled for a device. Missing these 30 - properties can cause the regulator registration to fail. 31 - If some of input supply is powered through battery or always-on supply then 32 - also it is require to have these parameters with proper node handle of always 33 - on power supply. 34 - tps65910: 35 - vcc1-supply: VDD1 input. 36 - vcc2-supply: VDD2 input. 37 - vcc3-supply: VAUX33 and VMMC input. 38 - vcc4-supply: VAUX1 and VAUX2 input. 39 - vcc5-supply: VPLL and VDAC input. 40 - vcc6-supply: VDIG1 and VDIG2 input. 41 - vcc7-supply: VRTC and VBB input. 42 - vccio-supply: VIO input. 43 - tps65911: 44 - vcc1-supply: VDD1 input. 45 - vcc2-supply: VDD2 input. 46 - vcc3-supply: LDO6, LDO7 and LDO8 input. 47 - vcc4-supply: LDO5 input. 48 - vcc5-supply: LDO3 and LDO4 input. 49 - vcc6-supply: LDO1 and LDO2 input. 50 - vcc7-supply: VRTC input. 51 - vccio-supply: VIO input. 52 - 53 - Optional properties: 54 - - ti,vmbch-threshold: (tps65911) main battery charged threshold 55 - comparator. (see VMBCH_VSEL in TPS65910 datasheet) 56 - - ti,vmbch2-threshold: (tps65911) main battery discharged threshold 57 - comparator. (see VMBCH_VSEL in TPS65910 datasheet) 58 - - ti,en-ck32k-xtal: enable external 32-kHz crystal oscillator (see CK32K_CTRL 59 - in TPS6591X datasheet) 60 - - ti,en-gpio-sleep: enable sleep control for gpios 61 - There should be 9 entries here, one for each gpio. 62 - - ti,system-power-controller: Telling whether or not this pmic is controlling 63 - the system power. 64 - - ti,sleep-enable: Enable SLEEP state. 65 - - ti,sleep-keep-therm: Keep thermal monitoring on in sleep state. 66 - - ti,sleep-keep-ck32k: Keep the 32KHz clock output on in sleep state. 67 - - ti,sleep-keep-hsclk: Keep high speed internal clock on in sleep state. 68 - 69 - Regulator Optional properties: 70 - - ti,regulator-ext-sleep-control: enable external sleep 71 - control through external inputs [0 (not enabled), 1 (EN1), 2 (EN2) or 4(EN3)] 72 - If this property is not defined, it defaults to 0 (not enabled). 73 - 74 - Example: 75 - 76 - pmu: tps65910@d2 { 77 - compatible = "ti,tps65910"; 78 - reg = <0xd2>; 79 - interrupt-parent = <&intc>; 80 - interrupts = < 0 118 0x04 >; 81 - 82 - #gpio-cells = <2>; 83 - gpio-controller; 84 - 85 - #interrupt-cells = <2>; 86 - interrupt-controller; 87 - 88 - ti,system-power-controller; 89 - 90 - ti,vmbch-threshold = 0; 91 - ti,vmbch2-threshold = 0; 92 - ti,en-ck32k-xtal; 93 - ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; 94 - 95 - vcc1-supply = <&reg_parent>; 96 - vcc2-supply = <&some_reg>; 97 - vcc3-supply = <...>; 98 - vcc4-supply = <...>; 99 - vcc5-supply = <...>; 100 - vcc6-supply = <...>; 101 - vcc7-supply = <...>; 102 - vccio-supply = <...>; 103 - 104 - regulators { 105 - #address-cells = <1>; 106 - #size-cells = <0>; 107 - 108 - vdd1_reg: regulator@0 { 109 - regulator-compatible = "vdd1"; 110 - reg = <0>; 111 - regulator-min-microvolt = < 600000>; 112 - regulator-max-microvolt = <1500000>; 113 - regulator-always-on; 114 - regulator-boot-on; 115 - ti,regulator-ext-sleep-control = <0>; 116 - }; 117 - vdd2_reg: regulator@1 { 118 - regulator-compatible = "vdd2"; 119 - reg = <1>; 120 - regulator-min-microvolt = < 600000>; 121 - regulator-max-microvolt = <1500000>; 122 - regulator-always-on; 123 - regulator-boot-on; 124 - ti,regulator-ext-sleep-control = <4>; 125 - }; 126 - vddctrl_reg: regulator@2 { 127 - regulator-compatible = "vddctrl"; 128 - reg = <2>; 129 - regulator-min-microvolt = < 600000>; 130 - regulator-max-microvolt = <1400000>; 131 - regulator-always-on; 132 - regulator-boot-on; 133 - ti,regulator-ext-sleep-control = <0>; 134 - }; 135 - vio_reg: regulator@3 { 136 - regulator-compatible = "vio"; 137 - reg = <3>; 138 - regulator-min-microvolt = <1500000>; 139 - regulator-max-microvolt = <1800000>; 140 - regulator-always-on; 141 - regulator-boot-on; 142 - ti,regulator-ext-sleep-control = <1>; 143 - }; 144 - ldo1_reg: regulator@4 { 145 - regulator-compatible = "ldo1"; 146 - reg = <4>; 147 - regulator-min-microvolt = <1000000>; 148 - regulator-max-microvolt = <3300000>; 149 - ti,regulator-ext-sleep-control = <0>; 150 - }; 151 - ldo2_reg: regulator@5 { 152 - regulator-compatible = "ldo2"; 153 - reg = <5>; 154 - regulator-min-microvolt = <1050000>; 155 - regulator-max-microvolt = <1050000>; 156 - ti,regulator-ext-sleep-control = <0>; 157 - }; 158 - ldo3_reg: regulator@6 { 159 - regulator-compatible = "ldo3"; 160 - reg = <6>; 161 - regulator-min-microvolt = <1000000>; 162 - regulator-max-microvolt = <3300000>; 163 - ti,regulator-ext-sleep-control = <0>; 164 - }; 165 - ldo4_reg: regulator@7 { 166 - regulator-compatible = "ldo4"; 167 - reg = <7>; 168 - regulator-min-microvolt = <1000000>; 169 - regulator-max-microvolt = <3300000>; 170 - regulator-always-on; 171 - ti,regulator-ext-sleep-control = <0>; 172 - }; 173 - ldo5_reg: regulator@8 { 174 - regulator-compatible = "ldo5"; 175 - reg = <8>; 176 - regulator-min-microvolt = <1000000>; 177 - regulator-max-microvolt = <3300000>; 178 - ti,regulator-ext-sleep-control = <0>; 179 - }; 180 - ldo6_reg: regulator@9 { 181 - regulator-compatible = "ldo6"; 182 - reg = <9>; 183 - regulator-min-microvolt = <1200000>; 184 - regulator-max-microvolt = <1200000>; 185 - ti,regulator-ext-sleep-control = <0>; 186 - }; 187 - ldo7_reg: regulator@10 { 188 - regulator-compatible = "ldo7"; 189 - reg = <10>; 190 - regulator-min-microvolt = <1200000>; 191 - regulator-max-microvolt = <1200000>; 192 - regulator-always-on; 193 - regulator-boot-on; 194 - ti,regulator-ext-sleep-control = <1>; 195 - }; 196 - ldo8_reg: regulator@11 { 197 - regulator-compatible = "ldo8"; 198 - reg = <11>; 199 - regulator-min-microvolt = <1000000>; 200 - regulator-max-microvolt = <3300000>; 201 - regulator-always-on; 202 - ti,regulator-ext-sleep-control = <1>; 203 - }; 204 - }; 205 - };
-26
Documentation/devicetree/bindings/phy/phy-lpc18xx-usb-otg.txt
··· 1 - NXP LPC18xx/43xx internal USB OTG PHY binding 2 - --------------------------------------------- 3 - 4 - This file contains documentation for the internal USB OTG PHY found 5 - in NXP LPC18xx and LPC43xx SoCs. 6 - 7 - Required properties: 8 - - compatible : must be "nxp,lpc1850-usb-otg-phy" 9 - - clocks : must be exactly one entry 10 - See: Documentation/devicetree/bindings/clock/clock-bindings.txt 11 - - #phy-cells : must be 0 for this phy 12 - See: Documentation/devicetree/bindings/phy/phy-bindings.txt 13 - 14 - The phy node must be a child of the creg syscon node. 15 - 16 - Example: 17 - creg: syscon@40043000 { 18 - compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; 19 - reg = <0x40043000 0x1000>; 20 - 21 - usb0_otg_phy: phy { 22 - compatible = "nxp,lpc1850-usb-otg-phy"; 23 - clocks = <&ccu1 CLK_USB0>; 24 - #phy-cells = <0>; 25 - }; 26 - };
+48 -48
drivers/mfd/Kconfig
··· 261 261 To compile this driver as a module, choose M here: the module will be 262 262 called cros-ec-dev. 263 263 264 + config MFD_CS40L50_CORE 265 + tristate 266 + select MFD_CORE 267 + select FW_CS_DSP 268 + select REGMAP_IRQ 269 + 270 + config MFD_CS40L50_I2C 271 + tristate "Cirrus Logic CS40L50 (I2C)" 272 + select REGMAP_I2C 273 + select MFD_CS40L50_CORE 274 + depends on I2C 275 + help 276 + Select this to support the Cirrus Logic CS40L50 Haptic 277 + Driver over I2C. 278 + 279 + This driver can be built as a module. If built as a module it will be 280 + called "cs40l50-i2c". 281 + 282 + config MFD_CS40L50_SPI 283 + tristate "Cirrus Logic CS40L50 (SPI)" 284 + select REGMAP_SPI 285 + select MFD_CS40L50_CORE 286 + depends on SPI 287 + help 288 + Select this to support the Cirrus Logic CS40L50 Haptic 289 + Driver over SPI. 290 + 291 + This driver can be built as a module. If built as a module it will be 292 + called "cs40l50-spi". 293 + 264 294 config MFD_CS42L43 265 295 tristate 266 296 select MFD_CORE ··· 314 284 help 315 285 Select this to support the Cirrus Logic CS42L43 PC CODEC with 316 286 headphone and class D speaker drivers over SoundWire. 287 + 288 + config MFD_LOCHNAGAR 289 + bool "Cirrus Logic Lochnagar Audio Development Board" 290 + select MFD_CORE 291 + select REGMAP_I2C 292 + depends on I2C=y && OF 293 + help 294 + Support for Cirrus Logic Lochnagar audio development board. 317 295 318 296 config MFD_MACSMC 319 297 tristate "Apple Silicon System Management Controller (SMC)" ··· 369 331 help 370 332 Support for the Cirrus Logic Madera platform audio SoC 371 333 core functionality controlled via SPI. 372 - 373 - config MFD_MAX5970 374 - tristate "Maxim 5970/5978 power switch and monitor" 375 - depends on I2C && OF 376 - select MFD_SIMPLE_MFD_I2C 377 - help 378 - This driver controls a Maxim 5970/5978 switch via I2C bus. 379 - The MAX5970/5978 is a smart switch with no output regulation, but 380 - fault protection and voltage and current monitoring capabilities. 381 - Also it supports upto 4 indication leds. 382 334 383 335 config MFD_CS47L15 384 336 bool "Cirrus Logic CS47L15" ··· 875 847 This enables support for Marvell 88PM886 Power Management IC. 876 848 This includes the I2C driver and the core APIs _only_, you have to 877 849 select individual components like onkey under the corresponding menus. 850 + 851 + config MFD_MAX5970 852 + tristate "Maxim 5970/5978 power switch and monitor" 853 + depends on I2C && OF 854 + select MFD_SIMPLE_MFD_I2C 855 + help 856 + This driver controls a Maxim 5970/5978 switch via I2C bus. 857 + The MAX5970/5978 is a smart switch with no output regulation, but 858 + fault protection and voltage and current monitoring capabilities. 859 + Also it supports upto 4 indication leds. 878 860 879 861 config MFD_MAX14577 880 862 tristate "Maxim Semiconductor MAX14577/77836 MUIC + Charger Support" ··· 2008 1970 VIA VX855/VX875 south bridge. You will need to enable the vx855_spi 2009 1971 and/or vx855_gpio drivers for this to do anything useful. 2010 1972 2011 - config MFD_LOCHNAGAR 2012 - bool "Cirrus Logic Lochnagar Audio Development Board" 2013 - select MFD_CORE 2014 - select REGMAP_I2C 2015 - depends on I2C=y && OF 2016 - help 2017 - Support for Cirrus Logic Lochnagar audio development board. 2018 - 2019 1973 config MFD_ARIZONA 2020 1974 select REGMAP 2021 1975 select REGMAP_IRQ ··· 2364 2334 depends on MCP_UCB1200 && INPUT 2365 2335 2366 2336 endmenu 2367 - 2368 - config MFD_CS40L50_CORE 2369 - tristate 2370 - select MFD_CORE 2371 - select FW_CS_DSP 2372 - select REGMAP_IRQ 2373 - 2374 - config MFD_CS40L50_I2C 2375 - tristate "Cirrus Logic CS40L50 (I2C)" 2376 - select REGMAP_I2C 2377 - select MFD_CS40L50_CORE 2378 - depends on I2C 2379 - help 2380 - Select this to support the Cirrus Logic CS40L50 Haptic 2381 - Driver over I2C. 2382 - 2383 - This driver can be built as a module. If built as a module it will be 2384 - called "cs40l50-i2c". 2385 - 2386 - config MFD_CS40L50_SPI 2387 - tristate "Cirrus Logic CS40L50 (SPI)" 2388 - select REGMAP_SPI 2389 - select MFD_CS40L50_CORE 2390 - depends on SPI 2391 - help 2392 - Select this to support the Cirrus Logic CS40L50 Haptic 2393 - Driver over SPI. 2394 - 2395 - This driver can be built as a module. If built as a module it will be 2396 - called "cs40l50-spi". 2397 2337 2398 2338 config MFD_VEXPRESS_SYSREG 2399 2339 tristate "Versatile Express System Registers"
+1 -2
drivers/mfd/ab8500-core.c
··· 580 580 num_irqs = AB8500_NR_IRQS; 581 581 582 582 /* If ->irq_base is zero this will give a linear mapping */ 583 - ab8500->domain = irq_domain_create_simple(of_fwnode_handle(ab8500->dev->of_node), 584 - num_irqs, 0, 583 + ab8500->domain = irq_domain_create_simple(dev_fwnode(ab8500->dev), num_irqs, 0, 585 584 &ab8500_irq_ops, ab8500); 586 585 587 586 if (!ab8500->domain) {
-1
drivers/mfd/arizona-irq.c
··· 152 152 } 153 153 } while (poll); 154 154 155 - pm_runtime_mark_last_busy(arizona->dev); 156 155 pm_runtime_put_autosuspend(arizona->dev); 157 156 158 157 return IRQ_HANDLED;
+8 -1
drivers/mfd/atmel-smc.c
··· 8 8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com> 9 9 */ 10 10 11 - #include <linux/mfd/syscon/atmel-smc.h> 11 + #include <linux/bits.h> 12 + #include <linux/err.h> 13 + #include <linux/export.h> 14 + #include <linux/mod_devicetable.h> 15 + #include <linux/of.h> 16 + #include <linux/regmap.h> 12 17 #include <linux/string.h> 18 + 19 + #include <linux/mfd/syscon/atmel-smc.h> 13 20 14 21 /** 15 22 * atmel_smc_cs_conf_init - initialize a SMC CS conf
+4 -4
drivers/mfd/axp20x.c
··· 1053 1053 }; 1054 1054 1055 1055 static struct mfd_cell axp313a_cells[] = { 1056 - MFD_CELL_NAME("axp20x-regulator"), 1056 + /* AXP323 is sometimes paired with AXP717 as sub-PMIC */ 1057 + MFD_CELL_BASIC("axp20x-regulator", NULL, NULL, 0, 1), 1057 1058 MFD_CELL_RES("axp313a-pek", axp313a_pek_resources), 1058 1059 }; 1059 1060 ··· 1231 1230 1232 1231 /* For boards that don't have IRQ line connected to SOC. */ 1233 1232 static const struct mfd_cell axp_regulator_only_cells[] = { 1234 - { 1235 - .name = "axp20x-regulator", 1236 - }, 1233 + /* PMIC without IRQ line may be secondary PMIC */ 1234 + MFD_CELL_BASIC("axp20x-regulator", NULL, NULL, 0, 1), 1237 1235 }; 1238 1236 1239 1237 static int axp20x_power_off(struct sys_off_data *data)
+9 -1
drivers/mfd/cros_ec_dev.c
··· 87 87 }; 88 88 89 89 static const struct mfd_cell cros_usbpd_charger_cells[] = { 90 - { .name = "cros-charge-control", }, 91 90 { .name = "cros-usbpd-charger", }, 92 91 { .name = "cros-usbpd-logger", }, 93 92 }; ··· 109 110 110 111 static const struct mfd_cell cros_ec_ucsi_cells[] = { 111 112 { .name = "cros_ec_ucsi", }, 113 + }; 114 + 115 + static const struct mfd_cell cros_ec_charge_control_cells[] = { 116 + { .name = "cros-charge-control", }, 112 117 }; 113 118 114 119 static const struct cros_feature_to_cells cros_subdevices[] = { ··· 150 147 .id = EC_FEATURE_PWM_KEYB, 151 148 .mfd_cells = cros_ec_keyboard_leds_cells, 152 149 .num_cells = ARRAY_SIZE(cros_ec_keyboard_leds_cells), 150 + }, 151 + { 152 + .id = EC_FEATURE_CHARGER, 153 + .mfd_cells = cros_ec_charge_control_cells, 154 + .num_cells = ARRAY_SIZE(cros_ec_charge_control_cells), 153 155 }, 154 156 }; 155 157
+1 -2
drivers/mfd/cs40l50-core.c
··· 52 52 CS40L50_GLOBAL_ERROR_MASK), 53 53 }; 54 54 55 - static struct regmap_irq_chip cs40l50_irq_chip = { 55 + static const struct regmap_irq_chip cs40l50_irq_chip = { 56 56 .name = "cs40l50", 57 57 .status_base = CS40L50_IRQ1_INT_1, 58 58 .mask_base = CS40L50_IRQ1_MASK_1, ··· 531 531 if (ret) 532 532 return dev_err_probe(dev, ret, "Failed to request %s\n", CS40L50_FW); 533 533 534 - pm_runtime_mark_last_busy(dev); 535 534 pm_runtime_put_autosuspend(dev); 536 535 537 536 return 0;
-1
drivers/mfd/cs42l43.c
··· 962 962 goto err; 963 963 } 964 964 965 - pm_runtime_mark_last_busy(cs42l43->dev); 966 965 pm_runtime_put_autosuspend(cs42l43->dev); 967 966 968 967 return;
+2 -2
drivers/mfd/fsl-imx25-tsadc.c
··· 71 71 if (irq < 0) 72 72 return irq; 73 73 74 - tsadc->domain = irq_domain_create_simple(of_fwnode_handle(dev->of_node), 2, 0, 75 - &mx25_tsadc_domain_ops, tsadc); 74 + tsadc->domain = irq_domain_create_simple(dev_fwnode(dev), 2, 0, &mx25_tsadc_domain_ops, 75 + tsadc); 76 76 if (!tsadc->domain) { 77 77 dev_err(dev, "Failed to add irq domain\n"); 78 78 return -ENOMEM;
+1 -1
drivers/mfd/lp8788-irq.c
··· 161 161 return -ENOMEM; 162 162 163 163 irqd->lp = lp; 164 - irqd->domain = irq_domain_create_linear(of_fwnode_handle(lp->dev->of_node), LP8788_INT_MAX, 164 + irqd->domain = irq_domain_create_linear(dev_fwnode(lp->dev), LP8788_INT_MAX, 165 165 &lp8788_domain_ops, irqd); 166 166 if (!irqd->domain) { 167 167 dev_err(lp->dev, "failed to add irq domain err\n");
+1 -2
drivers/mfd/mt6358-irq.c
··· 272 272 irqd->pmic_ints[i].en_reg_shift * j, 0); 273 273 } 274 274 275 - chip->irq_domain = irq_domain_create_linear(of_fwnode_handle(chip->dev->of_node), 276 - irqd->num_pmic_irqs, 275 + chip->irq_domain = irq_domain_create_linear(dev_fwnode(chip->dev), irqd->num_pmic_irqs, 277 276 &mt6358_irq_domain_ops, chip); 278 277 if (!chip->irq_domain) { 279 278 dev_err(chip->dev, "Could not create IRQ domain\n");
+1 -1
drivers/mfd/mt6370.c
··· 95 95 REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED1_SHORT, 8), 96 96 REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED2_STRB, 8), 97 97 REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED1_STRB, 8), 98 - REGMAP_IRQ_REG_LINE(mT6370_IRQ_FLED2_STRB_TO, 8), 98 + REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED2_STRB_TO, 8), 99 99 REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED1_STRB_TO, 8), 100 100 REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED2_TOR, 8), 101 101 REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED1_TOR, 8),
+1 -1
drivers/mfd/mt6370.h
··· 69 69 #define MT6370_IRQ_FLED1_SHORT 79 70 70 #define MT6370_IRQ_FLED2_STRB 80 71 71 #define MT6370_IRQ_FLED1_STRB 81 72 - #define mT6370_IRQ_FLED2_STRB_TO 82 72 + #define MT6370_IRQ_FLED2_STRB_TO 82 73 73 #define MT6370_IRQ_FLED1_STRB_TO 83 74 74 #define MT6370_IRQ_FLED2_TOR 84 75 75 #define MT6370_IRQ_FLED1_TOR 85
+6 -6
drivers/mfd/mt6397-core.c
··· 136 136 .name = "mt6323-led", 137 137 .of_compatible = "mediatek,mt6323-led" 138 138 }, { 139 - .name = "mtk-pmic-keys", 139 + .name = "mt6323-keys", 140 140 .num_resources = ARRAY_SIZE(mt6323_keys_resources), 141 141 .resources = mt6323_keys_resources, 142 142 .of_compatible = "mediatek,mt6323-keys" ··· 153 153 .name = "mt6328-regulator", 154 154 .of_compatible = "mediatek,mt6328-regulator" 155 155 }, { 156 - .name = "mtk-pmic-keys", 156 + .name = "mt6328-keys", 157 157 .num_resources = ARRAY_SIZE(mt6328_keys_resources), 158 158 .resources = mt6328_keys_resources, 159 159 .of_compatible = "mediatek,mt6328-keys" ··· 175 175 .name = "mt6357-sound", 176 176 .of_compatible = "mediatek,mt6357-sound" 177 177 }, { 178 - .name = "mtk-pmic-keys", 178 + .name = "mt6357-keys", 179 179 .num_resources = ARRAY_SIZE(mt6357_keys_resources), 180 180 .resources = mt6357_keys_resources, 181 181 .of_compatible = "mediatek,mt6357-keys" ··· 196 196 .name = "mt6332-regulator", 197 197 .of_compatible = "mediatek,mt6332-regulator" 198 198 }, { 199 - .name = "mtk-pmic-keys", 199 + .name = "mt6331-keys", 200 200 .num_resources = ARRAY_SIZE(mt6331_keys_resources), 201 201 .resources = mt6331_keys_resources, 202 202 .of_compatible = "mediatek,mt6331-keys" ··· 240 240 }, 241 241 { .name = "mt6359-sound", }, 242 242 { 243 - .name = "mtk-pmic-keys", 243 + .name = "mt6359-keys", 244 244 .num_resources = ARRAY_SIZE(mt6359_keys_resources), 245 245 .resources = mt6359_keys_resources, 246 246 .of_compatible = "mediatek,mt6359-keys" ··· 272 272 .name = "mt6397-pinctrl", 273 273 .of_compatible = "mediatek,mt6397-pinctrl", 274 274 }, { 275 - .name = "mtk-pmic-keys", 275 + .name = "mt6397-keys", 276 276 .num_resources = ARRAY_SIZE(mt6397_keys_resources), 277 277 .resources = mt6397_keys_resources, 278 278 .of_compatible = "mediatek,mt6397-keys"
+2 -2
drivers/mfd/mt6397-irq.c
··· 216 216 regmap_write(chip->regmap, chip->int_con[2], 0x0); 217 217 218 218 chip->pm_nb.notifier_call = mt6397_irq_pm_notifier; 219 - chip->irq_domain = irq_domain_create_linear(of_fwnode_handle(chip->dev->of_node), 220 - MT6397_IRQ_NR, &mt6397_irq_domain_ops, chip); 219 + chip->irq_domain = irq_domain_create_linear(dev_fwnode(chip->dev), MT6397_IRQ_NR, 220 + &mt6397_irq_domain_ops, chip); 221 221 if (!chip->irq_domain) { 222 222 dev_err(chip->dev, "could not create irq domain\n"); 223 223 return -ENOMEM;
+2 -2
drivers/mfd/qcom-pm8xxx.c
··· 559 559 chip->pm_irq_data = data; 560 560 spin_lock_init(&chip->pm_irq_lock); 561 561 562 - chip->irqdomain = irq_domain_create_linear(of_fwnode_handle(pdev->dev.of_node), 563 - data->num_irqs, &pm8xxx_irq_domain_ops, chip); 562 + chip->irqdomain = irq_domain_create_linear(dev_fwnode(&pdev->dev), data->num_irqs, 563 + &pm8xxx_irq_domain_ops, chip); 564 564 if (!chip->irqdomain) 565 565 return -ENODEV; 566 566
+12
drivers/mfd/rk8xx-core.c
··· 10 10 * Author: Wadim Egorov <w.egorov@phytec.de> 11 11 */ 12 12 13 + #include <linux/bitfield.h> 13 14 #include <linux/interrupt.h> 14 15 #include <linux/mfd/rk808.h> 15 16 #include <linux/mfd/core.h> ··· 700 699 const struct mfd_cell *cells; 701 700 int dual_support = 0; 702 701 int nr_pre_init_regs; 702 + u32 rst_fun = 0; 703 703 int nr_cells; 704 704 int ret; 705 705 int i; ··· 728 726 cells = rk806s; 729 727 nr_cells = ARRAY_SIZE(rk806s); 730 728 dual_support = IRQF_SHARED; 729 + 730 + ret = device_property_read_u32(dev, "rockchip,reset-mode", &rst_fun); 731 + if (ret) 732 + break; 733 + 734 + ret = regmap_update_bits(rk808->regmap, RK806_SYS_CFG3, RK806_RST_FUN_MSK, 735 + FIELD_PREP(RK806_RST_FUN_MSK, rst_fun)); 736 + if (ret) 737 + return dev_err_probe(dev, ret, 738 + "Failed to configure requested restart/reset behavior\n"); 731 739 break; 732 740 case RK808_ID: 733 741 rk808->regmap_irq_chip = &rk808_irq_chip;
+6 -6
drivers/mfd/rohm-bd71828.c
··· 25 25 .type = EV_KEY, 26 26 }; 27 27 28 - static struct gpio_keys_platform_data bd71828_powerkey_data = { 28 + static const struct gpio_keys_platform_data bd71828_powerkey_data = { 29 29 .buttons = &button, 30 30 .nbuttons = 1, 31 31 .name = "bd71828-pwrkey", ··· 43 43 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd70528-rtc-alm-2"), 44 44 }; 45 45 46 - static struct resource bd71815_power_irqs[] = { 46 + static const struct resource bd71815_power_irqs[] = { 47 47 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_RMV, "bd71815-dcin-rmv"), 48 48 DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-clps-out"), 49 49 DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-clps-in"), ··· 93 93 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-bat-hi-det"), 94 94 }; 95 95 96 - static struct mfd_cell bd71815_mfd_cells[] = { 96 + static const struct mfd_cell bd71815_mfd_cells[] = { 97 97 { .name = "bd71815-pmic", }, 98 98 { .name = "bd71815-clk", }, 99 99 { .name = "bd71815-gpo", }, ··· 109 109 }, 110 110 }; 111 111 112 - static struct mfd_cell bd71828_mfd_cells[] = { 112 + static const struct mfd_cell bd71828_mfd_cells[] = { 113 113 { .name = "bd71828-pmic", }, 114 114 { .name = "bd71828-gpio", }, 115 115 { .name = "bd71828-led", .of_compatible = "rohm,bd71828-leds" }, ··· 223 223 static unsigned int bit6_offsets[] = {1, 2}; /* DCIN IRQ */ 224 224 static unsigned int bit7_offsets[] = {0}; /* BUCK IRQ */ 225 225 226 - static struct regmap_irq_sub_irq_map bd718xx_sub_irq_offsets[] = { 226 + static const struct regmap_irq_sub_irq_map bd718xx_sub_irq_offsets[] = { 227 227 REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), 228 228 REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), 229 229 REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), ··· 493 493 const struct regmap_config *regmap_config; 494 494 const struct regmap_irq_chip *irqchip; 495 495 unsigned int chip_type; 496 - struct mfd_cell *mfd; 496 + const struct mfd_cell *mfd; 497 497 int cells; 498 498 int button_irq; 499 499 int clkmode_reg;
+1
drivers/mfd/stm32-timers.c
··· 5 5 */ 6 6 7 7 #include <linux/bitfield.h> 8 + #include <linux/export.h> 8 9 #include <linux/mfd/stm32-timers.h> 9 10 #include <linux/module.h> 10 11 #include <linux/of_platform.h>
+2 -3
drivers/mfd/stmfx.c
··· 269 269 u32 irqoutpin = 0, irqtrigger; 270 270 int ret; 271 271 272 - stmfx->irq_domain = irq_domain_create_simple(of_fwnode_handle(stmfx->dev->of_node), 273 - STMFX_REG_IRQ_SRC_MAX, 0, 274 - &stmfx_irq_ops, stmfx); 272 + stmfx->irq_domain = irq_domain_create_simple(dev_fwnode(stmfx->dev), STMFX_REG_IRQ_SRC_MAX, 273 + 0, &stmfx_irq_ops, stmfx); 275 274 if (!stmfx->irq_domain) { 276 275 dev_err(stmfx->dev, "Failed to create IRQ domain\n"); 277 276 return -EINVAL;
+2 -2
drivers/mfd/tps65217.c
··· 158 158 tps65217_set_bits(tps, TPS65217_REG_INT, TPS65217_INT_MASK, 159 159 TPS65217_INT_MASK, TPS65217_PROTECT_NONE); 160 160 161 - tps->irq_domain = irq_domain_create_linear(of_fwnode_handle(tps->dev->of_node), 162 - TPS65217_NUM_IRQ, &tps65217_irq_domain_ops, tps); 161 + tps->irq_domain = irq_domain_create_linear(dev_fwnode(tps->dev), TPS65217_NUM_IRQ, 162 + &tps65217_irq_domain_ops, tps); 163 163 if (!tps->irq_domain) { 164 164 dev_err(tps->dev, "Could not create IRQ domain\n"); 165 165 return -ENOMEM;
+9 -8
drivers/mfd/tps65219.c
··· 190 190 191 191 static const struct mfd_cell tps65214_cells[] = { 192 192 MFD_CELL_RES("tps65214-regulator", tps65214_regulator_resources), 193 - MFD_CELL_NAME("tps65215-gpio"), 193 + MFD_CELL_NAME("tps65214-gpio"), 194 194 }; 195 195 196 196 static const struct mfd_cell tps65215_cells[] = { ··· 238 238 static unsigned int tps65214_bit5_offsets[] = { TPS65214_REG_INT_LDO_1_2_POS }; 239 239 static unsigned int tps65214_bit7_offsets[] = { TPS65214_REG_INT_PB_POS }; 240 240 241 - static struct regmap_irq_sub_irq_map tps65219_sub_irq_offsets[] = { 241 + static const struct regmap_irq_sub_irq_map tps65219_sub_irq_offsets[] = { 242 242 REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), 243 243 REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), 244 244 REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), ··· 249 249 REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), 250 250 }; 251 251 252 - static struct regmap_irq_sub_irq_map tps65215_sub_irq_offsets[] = { 252 + static const struct regmap_irq_sub_irq_map tps65215_sub_irq_offsets[] = { 253 253 REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), 254 254 REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), 255 255 REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), ··· 260 260 REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), 261 261 }; 262 262 263 - static struct regmap_irq_sub_irq_map tps65214_sub_irq_offsets[] = { 263 + static const struct regmap_irq_sub_irq_map tps65214_sub_irq_offsets[] = { 264 264 REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit0_offsets), 265 265 REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit1_offsets), 266 266 REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit2_offsets), ··· 455 455 int n_cells; 456 456 }; 457 457 458 - static struct tps65219_chip_data chip_info_table[] = { 458 + static const struct tps65219_chip_data chip_info_table[] = { 459 459 [TPS65214] = { 460 460 .irq_chip = &tps65214_irq_chip, 461 461 .cells = tps65214_cells, ··· 476 476 static int tps65219_probe(struct i2c_client *client) 477 477 { 478 478 struct tps65219 *tps; 479 - struct tps65219_chip_data *pmic; 479 + const struct tps65219_chip_data *pmic; 480 + unsigned int chip_id; 480 481 bool pwr_button; 481 482 int ret; 482 483 ··· 488 487 i2c_set_clientdata(client, tps); 489 488 490 489 tps->dev = &client->dev; 491 - tps->chip_id = (uintptr_t)i2c_get_match_data(client); 492 - pmic = &chip_info_table[tps->chip_id]; 490 + chip_id = (uintptr_t)i2c_get_match_data(client); 491 + pmic = &chip_info_table[chip_id]; 493 492 494 493 tps->regmap = devm_regmap_init_i2c(client, &tps65219_regmap_config); 495 494 if (IS_ERR(tps->regmap)) {
+3 -3
drivers/mfd/tps6586x.c
··· 363 363 new_irq_base = 0; 364 364 } 365 365 366 - tps6586x->irq_domain = irq_domain_create_simple(of_fwnode_handle(tps6586x->dev->of_node), 367 - irq_num, new_irq_base, &tps6586x_domain_ops, 368 - tps6586x); 366 + tps6586x->irq_domain = irq_domain_create_simple(dev_fwnode(tps6586x->dev), irq_num, 367 + new_irq_base, &tps6586x_domain_ops, 368 + tps6586x); 369 369 if (!tps6586x->irq_domain) { 370 370 dev_err(tps6586x->dev, "Failed to create IRQ domain\n"); 371 371 return -ENOMEM;
+2 -77
drivers/mfd/twl6030-irq.c
··· 256 256 } 257 257 EXPORT_SYMBOL(twl6030_interrupt_mask); 258 258 259 - int twl6030_mmc_card_detect_config(void) 260 - { 261 - int ret; 262 - u8 reg_val = 0; 263 - 264 - /* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */ 265 - twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK, 266 - REG_INT_MSK_LINE_B); 267 - twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK, 268 - REG_INT_MSK_STS_B); 269 - /* 270 - * Initially Configuring MMC_CTRL for receiving interrupts & 271 - * Card status on TWL6030 for MMC1 272 - */ 273 - ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val, TWL6030_MMCCTRL); 274 - if (ret < 0) { 275 - pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret); 276 - return ret; 277 - } 278 - reg_val &= ~VMMC_AUTO_OFF; 279 - reg_val |= SW_FC; 280 - ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL); 281 - if (ret < 0) { 282 - pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret); 283 - return ret; 284 - } 285 - 286 - /* Configuring PullUp-PullDown register */ 287 - ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val, 288 - TWL6030_CFG_INPUT_PUPD3); 289 - if (ret < 0) { 290 - pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n", 291 - ret); 292 - return ret; 293 - } 294 - reg_val &= ~(MMC_PU | MMC_PD); 295 - ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, 296 - TWL6030_CFG_INPUT_PUPD3); 297 - if (ret < 0) { 298 - pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n", 299 - ret); 300 - return ret; 301 - } 302 - 303 - return irq_find_mapping(twl6030_irq->irq_domain, 304 - MMCDETECT_INTR_OFFSET); 305 - } 306 - EXPORT_SYMBOL(twl6030_mmc_card_detect_config); 307 - 308 - int twl6030_mmc_card_detect(struct device *dev, int slot) 309 - { 310 - int ret = -EIO; 311 - u8 read_reg = 0; 312 - struct platform_device *pdev = to_platform_device(dev); 313 - 314 - if (pdev->id) { 315 - /* TWL6030 provide's Card detect support for 316 - * only MMC1 controller. 317 - */ 318 - pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__); 319 - return ret; 320 - } 321 - /* 322 - * BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1 323 - * 0 - Card not present ,1 - Card present 324 - */ 325 - ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg, 326 - TWL6030_MMCCTRL); 327 - if (ret >= 0) 328 - ret = read_reg & STS_MMC; 329 - return ret; 330 - } 331 - EXPORT_SYMBOL(twl6030_mmc_card_detect); 332 - 333 259 static int twl6030_irq_map(struct irq_domain *d, unsigned int virq, 334 260 irq_hw_number_t hwirq) 335 261 { ··· 336 410 atomic_set(&twl6030_irq->wakeirqs, 0); 337 411 twl6030_irq->irq_mapping_tbl = of_id->data; 338 412 339 - twl6030_irq->irq_domain = 340 - irq_domain_create_linear(of_fwnode_handle(dev->of_node), nr_irqs, 341 - &twl6030_irq_domain_ops, twl6030_irq); 413 + twl6030_irq->irq_domain = irq_domain_create_linear(dev_fwnode(dev), nr_irqs, 414 + &twl6030_irq_domain_ops, twl6030_irq); 342 415 if (!twl6030_irq->irq_domain) { 343 416 dev_err(dev, "Can't add irq_domain\n"); 344 417 return -ENOMEM;
+1 -1
drivers/mfd/twl6040.c
··· 69 69 { 0x2E, 0x00 }, /* REG_STATUS (ro) */ 70 70 }; 71 71 72 - static struct reg_sequence twl6040_patch[] = { 72 + static const struct reg_sequence twl6040_patch[] = { 73 73 /* 74 74 * Select I2C bus access to dual access registers 75 75 * Interrupt register is cleared on read
+4 -6
drivers/mfd/wm831x-irq.c
··· 587 587 } 588 588 589 589 if (irq_base) 590 - domain = irq_domain_create_legacy(of_fwnode_handle(wm831x->dev->of_node), 591 - ARRAY_SIZE(wm831x_irqs), irq_base, 0, 592 - &wm831x_irq_domain_ops, wm831x); 590 + domain = irq_domain_create_legacy(dev_fwnode(wm831x->dev), ARRAY_SIZE(wm831x_irqs), 591 + irq_base, 0, &wm831x_irq_domain_ops, wm831x); 593 592 else 594 - domain = irq_domain_create_linear(of_fwnode_handle(wm831x->dev->of_node), 595 - ARRAY_SIZE(wm831x_irqs), &wm831x_irq_domain_ops, 596 - wm831x); 593 + domain = irq_domain_create_linear(dev_fwnode(wm831x->dev), ARRAY_SIZE(wm831x_irqs), 594 + &wm831x_irq_domain_ops, wm831x); 597 595 598 596 if (!domain) { 599 597 dev_warn(wm831x->dev, "Failed to allocate IRQ domain\n");
+5 -3
include/linux/mfd/davinci_voicecodec.h
··· 10 10 #ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_ 11 11 #define __LINUX_MFD_DAVINCI_VOICECODEC_H_ 12 12 13 - #include <linux/kernel.h> 14 - #include <linux/platform_device.h> 13 + #include <linux/bits.h> 15 14 #include <linux/mfd/core.h> 16 - #include <linux/platform_data/edma.h> 15 + #include <linux/types.h> 17 16 17 + struct clk; 18 + struct device; 19 + struct platform_device; 18 20 struct regmap; 19 21 20 22 /*
+2 -1
include/linux/mfd/madera/pdata.h
··· 8 8 #ifndef MADERA_PDATA_H 9 9 #define MADERA_PDATA_H 10 10 11 - #include <linux/kernel.h> 12 11 #include <linux/regulator/arizona-ldo1.h> 13 12 #include <linux/regulator/arizona-micsupp.h> 14 13 #include <linux/regulator/machine.h> 14 + #include <linux/types.h> 15 + 15 16 #include <sound/madera-pdata.h> 16 17 17 18 #define MADERA_MAX_MICBIAS 4
-229
include/linux/mfd/pcf50633/core.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 - /* 3 - * core.h -- Core driver for NXP PCF50633 4 - * 5 - * (C) 2006-2008 by Openmoko, Inc. 6 - * All rights reserved. 7 - */ 8 - 9 - #ifndef __LINUX_MFD_PCF50633_CORE_H 10 - #define __LINUX_MFD_PCF50633_CORE_H 11 - 12 - #include <linux/i2c.h> 13 - #include <linux/workqueue.h> 14 - #include <linux/regulator/driver.h> 15 - #include <linux/regulator/machine.h> 16 - #include <linux/pm.h> 17 - #include <linux/power_supply.h> 18 - 19 - struct pcf50633; 20 - struct regmap; 21 - 22 - #define PCF50633_NUM_REGULATORS 11 23 - 24 - struct pcf50633_platform_data { 25 - struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS]; 26 - 27 - char **batteries; 28 - int num_batteries; 29 - 30 - /* 31 - * Should be set accordingly to the reference resistor used, see 32 - * I_{ch(ref)} charger reference current in the pcf50633 User 33 - * Manual. 34 - */ 35 - int charger_reference_current_ma; 36 - 37 - /* Callbacks */ 38 - void (*probe_done)(struct pcf50633 *); 39 - void (*mbc_event_callback)(struct pcf50633 *, int); 40 - void (*regulator_registered)(struct pcf50633 *, int); 41 - void (*force_shutdown)(struct pcf50633 *); 42 - 43 - u8 resumers[5]; 44 - }; 45 - 46 - struct pcf50633_irq { 47 - void (*handler) (int, void *); 48 - void *data; 49 - }; 50 - 51 - int pcf50633_register_irq(struct pcf50633 *pcf, int irq, 52 - void (*handler) (int, void *), void *data); 53 - int pcf50633_free_irq(struct pcf50633 *pcf, int irq); 54 - 55 - int pcf50633_irq_mask(struct pcf50633 *pcf, int irq); 56 - int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq); 57 - int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq); 58 - 59 - int pcf50633_read_block(struct pcf50633 *, u8 reg, 60 - int nr_regs, u8 *data); 61 - int pcf50633_write_block(struct pcf50633 *pcf, u8 reg, 62 - int nr_regs, u8 *data); 63 - u8 pcf50633_reg_read(struct pcf50633 *, u8 reg); 64 - int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val); 65 - 66 - int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val); 67 - int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits); 68 - 69 - /* Interrupt registers */ 70 - 71 - #define PCF50633_REG_INT1 0x02 72 - #define PCF50633_REG_INT2 0x03 73 - #define PCF50633_REG_INT3 0x04 74 - #define PCF50633_REG_INT4 0x05 75 - #define PCF50633_REG_INT5 0x06 76 - 77 - #define PCF50633_REG_INT1M 0x07 78 - #define PCF50633_REG_INT2M 0x08 79 - #define PCF50633_REG_INT3M 0x09 80 - #define PCF50633_REG_INT4M 0x0a 81 - #define PCF50633_REG_INT5M 0x0b 82 - 83 - enum { 84 - /* Chip IRQs */ 85 - PCF50633_IRQ_ADPINS, 86 - PCF50633_IRQ_ADPREM, 87 - PCF50633_IRQ_USBINS, 88 - PCF50633_IRQ_USBREM, 89 - PCF50633_IRQ_RESERVED1, 90 - PCF50633_IRQ_RESERVED2, 91 - PCF50633_IRQ_ALARM, 92 - PCF50633_IRQ_SECOND, 93 - PCF50633_IRQ_ONKEYR, 94 - PCF50633_IRQ_ONKEYF, 95 - PCF50633_IRQ_EXTON1R, 96 - PCF50633_IRQ_EXTON1F, 97 - PCF50633_IRQ_EXTON2R, 98 - PCF50633_IRQ_EXTON2F, 99 - PCF50633_IRQ_EXTON3R, 100 - PCF50633_IRQ_EXTON3F, 101 - PCF50633_IRQ_BATFULL, 102 - PCF50633_IRQ_CHGHALT, 103 - PCF50633_IRQ_THLIMON, 104 - PCF50633_IRQ_THLIMOFF, 105 - PCF50633_IRQ_USBLIMON, 106 - PCF50633_IRQ_USBLIMOFF, 107 - PCF50633_IRQ_ADCRDY, 108 - PCF50633_IRQ_ONKEY1S, 109 - PCF50633_IRQ_LOWSYS, 110 - PCF50633_IRQ_LOWBAT, 111 - PCF50633_IRQ_HIGHTMP, 112 - PCF50633_IRQ_AUTOPWRFAIL, 113 - PCF50633_IRQ_DWN1PWRFAIL, 114 - PCF50633_IRQ_DWN2PWRFAIL, 115 - PCF50633_IRQ_LEDPWRFAIL, 116 - PCF50633_IRQ_LEDOVP, 117 - PCF50633_IRQ_LDO1PWRFAIL, 118 - PCF50633_IRQ_LDO2PWRFAIL, 119 - PCF50633_IRQ_LDO3PWRFAIL, 120 - PCF50633_IRQ_LDO4PWRFAIL, 121 - PCF50633_IRQ_LDO5PWRFAIL, 122 - PCF50633_IRQ_LDO6PWRFAIL, 123 - PCF50633_IRQ_HCLDOPWRFAIL, 124 - PCF50633_IRQ_HCLDOOVL, 125 - 126 - /* Always last */ 127 - PCF50633_NUM_IRQ, 128 - }; 129 - 130 - struct pcf50633 { 131 - struct device *dev; 132 - struct regmap *regmap; 133 - 134 - struct pcf50633_platform_data *pdata; 135 - int irq; 136 - struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ]; 137 - struct work_struct irq_work; 138 - struct workqueue_struct *work_queue; 139 - struct mutex lock; 140 - 141 - u8 mask_regs[5]; 142 - 143 - u8 suspend_irq_masks[5]; 144 - u8 resume_reason[5]; 145 - int is_suspended; 146 - 147 - int onkey1s_held; 148 - 149 - struct platform_device *rtc_pdev; 150 - struct platform_device *mbc_pdev; 151 - struct platform_device *adc_pdev; 152 - struct platform_device *input_pdev; 153 - struct platform_device *bl_pdev; 154 - struct platform_device *regulator_pdev[PCF50633_NUM_REGULATORS]; 155 - }; 156 - 157 - enum pcf50633_reg_int1 { 158 - PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */ 159 - PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */ 160 - PCF50633_INT1_USBINS = 0x04, /* USB inserted */ 161 - PCF50633_INT1_USBREM = 0x08, /* USB removed */ 162 - /* reserved */ 163 - PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */ 164 - PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */ 165 - }; 166 - 167 - enum pcf50633_reg_int2 { 168 - PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */ 169 - PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */ 170 - PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */ 171 - PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */ 172 - PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */ 173 - PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */ 174 - PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */ 175 - PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */ 176 - }; 177 - 178 - enum pcf50633_reg_int3 { 179 - PCF50633_INT3_BATFULL = 0x01, /* Battery full */ 180 - PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */ 181 - PCF50633_INT3_THLIMON = 0x04, 182 - PCF50633_INT3_THLIMOFF = 0x08, 183 - PCF50633_INT3_USBLIMON = 0x10, 184 - PCF50633_INT3_USBLIMOFF = 0x20, 185 - PCF50633_INT3_ADCRDY = 0x40, /* ADC result ready */ 186 - PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */ 187 - }; 188 - 189 - enum pcf50633_reg_int4 { 190 - PCF50633_INT4_LOWSYS = 0x01, 191 - PCF50633_INT4_LOWBAT = 0x02, 192 - PCF50633_INT4_HIGHTMP = 0x04, 193 - PCF50633_INT4_AUTOPWRFAIL = 0x08, 194 - PCF50633_INT4_DWN1PWRFAIL = 0x10, 195 - PCF50633_INT4_DWN2PWRFAIL = 0x20, 196 - PCF50633_INT4_LEDPWRFAIL = 0x40, 197 - PCF50633_INT4_LEDOVP = 0x80, 198 - }; 199 - 200 - enum pcf50633_reg_int5 { 201 - PCF50633_INT5_LDO1PWRFAIL = 0x01, 202 - PCF50633_INT5_LDO2PWRFAIL = 0x02, 203 - PCF50633_INT5_LDO3PWRFAIL = 0x04, 204 - PCF50633_INT5_LDO4PWRFAIL = 0x08, 205 - PCF50633_INT5_LDO5PWRFAIL = 0x10, 206 - PCF50633_INT5_LDO6PWRFAIL = 0x20, 207 - PCF50633_INT5_HCLDOPWRFAIL = 0x40, 208 - PCF50633_INT5_HCLDOOVL = 0x80, 209 - }; 210 - 211 - /* misc. registers */ 212 - #define PCF50633_REG_OOCSHDWN 0x0c 213 - 214 - /* LED registers */ 215 - #define PCF50633_REG_LEDOUT 0x28 216 - #define PCF50633_REG_LEDENA 0x29 217 - #define PCF50633_REG_LEDCTL 0x2a 218 - #define PCF50633_REG_LEDDIM 0x2b 219 - 220 - static inline struct pcf50633 *dev_to_pcf50633(struct device *dev) 221 - { 222 - return dev_get_drvdata(dev); 223 - } 224 - 225 - int pcf50633_irq_init(struct pcf50633 *pcf, int irq); 226 - void pcf50633_irq_free(struct pcf50633 *pcf); 227 - extern const struct dev_pm_ops pcf50633_pm; 228 - 229 - #endif
+2
include/linux/mfd/rk808.h
··· 812 812 #define RK806_INT_POL_H BIT(1) 813 813 #define RK806_INT_POL_L 0 814 814 815 + /* SYS_CFG3 */ 816 + #define RK806_RST_FUN_MSK GENMASK(7, 6) 815 817 #define RK806_SLAVE_RESTART_FUN_MSK BIT(1) 816 818 #define RK806_SLAVE_RESTART_FUN_EN BIT(1) 817 819 #define RK806_SLAVE_RESTART_FUN_OFF 0
+5 -3
include/linux/mfd/syscon/atmel-smc.h
··· 11 11 #ifndef _LINUX_MFD_SYSCON_ATMEL_SMC_H_ 12 12 #define _LINUX_MFD_SYSCON_ATMEL_SMC_H_ 13 13 14 - #include <linux/kernel.h> 15 - #include <linux/of.h> 16 - #include <linux/regmap.h> 14 + #include <linux/bits.h> 15 + #include <linux/types.h> 16 + 17 + struct device_node; 18 + struct regmap; 17 19 18 20 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) 19 21 #define ATMEL_HSMC_SETUP(layout, cs) \
-5
include/linux/mfd/tps65219.h
··· 10 10 #define MFD_TPS65219_H 11 11 12 12 #include <linux/bitops.h> 13 - #include <linux/notifier.h> 14 13 #include <linux/regmap.h> 15 14 #include <linux/regulator/driver.h> 16 15 ··· 437 438 * 438 439 * @dev: MFD device 439 440 * @regmap: Regmap for accessing the device registers 440 - * @chip_id: Chip ID 441 441 * @irq_data: Regmap irq data used for the irq chip 442 - * @nb: notifier block for the restart handler 443 442 */ 444 443 struct tps65219 { 445 444 struct device *dev; 446 445 struct regmap *regmap; 447 446 448 - unsigned int chip_id; 449 447 struct regmap_irq_chip_data *irq_data; 450 - struct notifier_block nb; 451 448 }; 452 449 453 450 #endif /* MFD_TPS65219_H */
-21
include/linux/mfd/twl.h
··· 205 205 int twl6030_interrupt_unmask(u8 bit_mask, u8 offset); 206 206 int twl6030_interrupt_mask(u8 bit_mask, u8 offset); 207 207 208 - /* Card detect Configuration for MMC1 Controller on OMAP4 */ 209 - #ifdef CONFIG_TWL4030_CORE 210 - int twl6030_mmc_card_detect_config(void); 211 - #else 212 - static inline int twl6030_mmc_card_detect_config(void) 213 - { 214 - pr_debug("twl6030_mmc_card_detect_config not supported\n"); 215 - return 0; 216 - } 217 - #endif 218 - 219 - /* MMC1 Controller on OMAP4 uses Phoenix irq for Card detect */ 220 - #ifdef CONFIG_TWL4030_CORE 221 - int twl6030_mmc_card_detect(struct device *dev, int slot); 222 - #else 223 - static inline int twl6030_mmc_card_detect(struct device *dev, int slot) 224 - { 225 - pr_debug("Call back twl6030_mmc_card_detect not supported\n"); 226 - return -EIO; 227 - } 228 - #endif 229 208 /*----------------------------------------------------------------------*/ 230 209 231 210 /*
+7 -3
include/linux/mfd/wm8350/core.h
··· 8 8 #ifndef __LINUX_MFD_WM8350_CORE_H_ 9 9 #define __LINUX_MFD_WM8350_CORE_H_ 10 10 11 - #include <linux/kernel.h> 12 - #include <linux/mutex.h> 13 - #include <linux/interrupt.h> 14 11 #include <linux/completion.h> 12 + #include <linux/errno.h> 13 + #include <linux/interrupt.h> 14 + #include <linux/mutex.h> 15 15 #include <linux/regmap.h> 16 + #include <linux/types.h> 16 17 17 18 #include <linux/mfd/wm8350/audio.h> 18 19 #include <linux/mfd/wm8350/gpio.h> ··· 21 20 #include <linux/mfd/wm8350/rtc.h> 22 21 #include <linux/mfd/wm8350/supply.h> 23 22 #include <linux/mfd/wm8350/wdt.h> 23 + 24 + struct device; 25 + struct platform_device; 24 26 25 27 /* 26 28 * Register values.