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net: stmmac: mdio: clean up c22/c45 accessor split

The C45 accessors were setting the GR (register number) field twice,
once with the 16-bit register address truncated to five bits, and
then overwritten with the C45 devad. This is harmless since the field
was being cleared prior to being updated with the C45 devad, except
for the extra work.

Remove the redundant code.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/E1urGBn-00000000DCH-3swS@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Russell King (Oracle) and committed by
Jakub Kicinski 24eb86a8 5309dbc9

-4
-4
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
··· 311 311 312 312 value |= (phyaddr << priv->hw->mii.addr_shift) 313 313 & priv->hw->mii.addr_mask; 314 - value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 315 314 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 316 315 & priv->hw->mii.clk_csr_mask; 317 316 value |= MII_GMAC4_READ; 318 317 value |= MII_GMAC4_C45E; 319 - value &= ~priv->hw->mii.reg_mask; 320 318 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 321 319 322 320 data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT; ··· 407 409 408 410 value |= (phyaddr << priv->hw->mii.addr_shift) 409 411 & priv->hw->mii.addr_mask; 410 - value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 411 412 412 413 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 413 414 & priv->hw->mii.clk_csr_mask; 414 415 415 416 value |= MII_GMAC4_WRITE; 416 417 value |= MII_GMAC4_C45E; 417 - value &= ~priv->hw->mii.reg_mask; 418 418 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 419 419 420 420 data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT;