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net: dsa: vsc73xx: use defined values in phy operations

This commit changes magic numbers in phy operations.
Some shifted registers was replaced with bitfield macros.

No functional changes done.

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Pawel Dembicki and committed by
David S. Miller
2524d6c2 eb3ab13d

+33 -12
+33 -12
drivers/net/dsa/vitesse-vsc73xx-core.c
··· 21 21 #include <linux/of.h> 22 22 #include <linux/of_mdio.h> 23 23 #include <linux/bitops.h> 24 + #include <linux/bitfield.h> 24 25 #include <linux/if_bridge.h> 25 26 #include <linux/if_vlan.h> 26 27 #include <linux/etherdevice.h> ··· 42 41 #define VSC73XX_BLOCK_SYSTEM 0x7 /* Only subblock 0 */ 43 42 44 43 /* MII Block subblock */ 45 - #define VSC73XX_BLOCK_MII_INTERNAL 0x0 /* Internal MDIO subblock */ 44 + #define VSC73XX_BLOCK_MII_INTERNAL 0x0 /* Internal MDIO subblock */ 45 + #define VSC73XX_BLOCK_MII_EXTERNAL 0x1 /* External MDIO subblock */ 46 46 47 47 #define CPU_PORT 6 /* CPU port */ 48 48 ··· 226 224 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE 3 227 225 228 226 /* MII block 3 registers */ 229 - #define VSC73XX_MII_STAT 0x0 230 - #define VSC73XX_MII_CMD 0x1 231 - #define VSC73XX_MII_DATA 0x2 232 - #define VSC73XX_MII_MPRES 0x3 227 + #define VSC73XX_MII_STAT 0x0 228 + #define VSC73XX_MII_CMD 0x1 229 + #define VSC73XX_MII_DATA 0x2 230 + #define VSC73XX_MII_MPRES 0x3 231 + 232 + #define VSC73XX_MII_STAT_BUSY BIT(3) 233 + #define VSC73XX_MII_STAT_READ BIT(2) 234 + #define VSC73XX_MII_STAT_WRITE BIT(1) 235 + 236 + #define VSC73XX_MII_CMD_SCAN BIT(27) 237 + #define VSC73XX_MII_CMD_OPERATION BIT(26) 238 + #define VSC73XX_MII_CMD_PHY_ADDR GENMASK(25, 21) 239 + #define VSC73XX_MII_CMD_PHY_REG GENMASK(20, 16) 240 + #define VSC73XX_MII_CMD_WRITE_DATA GENMASK(15, 0) 241 + 242 + #define VSC73XX_MII_DATA_FAILURE BIT(16) 243 + #define VSC73XX_MII_DATA_READ_DATA GENMASK(15, 0) 233 244 234 245 #define VSC73XX_MII_MPRES_NOPREAMBLE BIT(6) 235 246 #define VSC73XX_MII_MPRES_PRESCALEVAL GENMASK(5, 0) ··· 558 543 int ret; 559 544 560 545 /* Setting bit 26 means "read" */ 561 - cmd = BIT(26) | (phy << 21) | (regnum << 16); 562 - ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); 546 + cmd = VSC73XX_MII_CMD_OPERATION | 547 + FIELD_PREP(VSC73XX_MII_CMD_PHY_ADDR, phy) | 548 + FIELD_PREP(VSC73XX_MII_CMD_PHY_REG, regnum); 549 + ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, 550 + VSC73XX_MII_CMD, cmd); 563 551 if (ret) 564 552 return ret; 565 553 msleep(2); 566 - ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, 0, 2, &val); 554 + ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, 555 + VSC73XX_MII_DATA, &val); 567 556 if (ret) 568 557 return ret; 569 - if (val & BIT(16)) { 558 + if (val & VSC73XX_MII_DATA_FAILURE) { 570 559 dev_err(vsc->dev, "reading reg %02x from phy%d failed\n", 571 560 regnum, phy); 572 561 return -EIO; 573 562 } 574 - val &= 0xFFFFU; 563 + val &= VSC73XX_MII_DATA_READ_DATA; 575 564 576 565 dev_dbg(vsc->dev, "read reg %02x from phy%d = %04x\n", 577 566 regnum, phy, val); ··· 601 582 return 0; 602 583 } 603 584 604 - cmd = (phy << 21) | (regnum << 16); 605 - ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); 585 + cmd = FIELD_PREP(VSC73XX_MII_CMD_PHY_ADDR, phy) | 586 + FIELD_PREP(VSC73XX_MII_CMD_PHY_REG, regnum); 587 + ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, 588 + VSC73XX_MII_CMD, cmd); 606 589 if (ret) 607 590 return ret; 608 591