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dt-bindings: pwm: Add bindings for OpenCores PWM Controller

Add bindings for OpenCores PWM Controller.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

authored by

William Qiu and committed by
Conor Dooley
25290858 6613476e

+55
+55
Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: OpenCores PWM controller 8 + 9 + maintainers: 10 + - William Qiu <william.qiu@starfivetech.com> 11 + 12 + description: 13 + The OpenCores PTC ip core contains a PWM controller. When operating in PWM 14 + mode, the PTC core generates binary signal with user-programmable low and 15 + high periods. All PTC counters and registers are 32-bit. 16 + 17 + allOf: 18 + - $ref: pwm.yaml# 19 + 20 + properties: 21 + compatible: 22 + items: 23 + - enum: 24 + - starfive,jh7100-pwm 25 + - starfive,jh7110-pwm 26 + - const: opencores,pwm-v1 27 + 28 + reg: 29 + maxItems: 1 30 + 31 + clocks: 32 + maxItems: 1 33 + 34 + resets: 35 + maxItems: 1 36 + 37 + "#pwm-cells": 38 + const: 3 39 + 40 + required: 41 + - compatible 42 + - reg 43 + - clocks 44 + 45 + additionalProperties: false 46 + 47 + examples: 48 + - | 49 + pwm@12490000 { 50 + compatible = "starfive,jh7110-pwm", "opencores,pwm-v1"; 51 + reg = <0x12490000 0x10000>; 52 + clocks = <&clkgen 181>; 53 + resets = <&rstgen 109>; 54 + #pwm-cells = <3>; 55 + };