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arm64: Disable GICv5 read/write/instruction traps

GICv5 trap configuration registers value is UNKNOWN at reset.

Initialize GICv5 EL2 trap configuration registers to prevent
trapping GICv5 instruction/register access upon entering the
kernel.

Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-15-12e71f1b3528@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>

authored by

Lorenzo Pieralisi and committed by
Marc Zyngier 25374470 42555929

+45
+45
arch/arm64/include/asm/el2_setup.h
··· 165 165 .Lskip_gicv3_\@: 166 166 .endm 167 167 168 + /* GICv5 system register access */ 169 + .macro __init_el2_gicv5 170 + mrs_s x0, SYS_ID_AA64PFR2_EL1 171 + ubfx x0, x0, #ID_AA64PFR2_EL1_GCIE_SHIFT, #4 172 + cbz x0, .Lskip_gicv5_\@ 173 + 174 + mov x0, #(ICH_HFGITR_EL2_GICRCDNMIA | \ 175 + ICH_HFGITR_EL2_GICRCDIA | \ 176 + ICH_HFGITR_EL2_GICCDDI | \ 177 + ICH_HFGITR_EL2_GICCDEOI | \ 178 + ICH_HFGITR_EL2_GICCDHM | \ 179 + ICH_HFGITR_EL2_GICCDRCFG | \ 180 + ICH_HFGITR_EL2_GICCDPEND | \ 181 + ICH_HFGITR_EL2_GICCDAFF | \ 182 + ICH_HFGITR_EL2_GICCDPRI | \ 183 + ICH_HFGITR_EL2_GICCDDIS | \ 184 + ICH_HFGITR_EL2_GICCDEN) 185 + msr_s SYS_ICH_HFGITR_EL2, x0 // Disable instruction traps 186 + mov_q x0, (ICH_HFGRTR_EL2_ICC_PPI_ACTIVERn_EL1 | \ 187 + ICH_HFGRTR_EL2_ICC_PPI_PRIORITYRn_EL1 | \ 188 + ICH_HFGRTR_EL2_ICC_PPI_PENDRn_EL1 | \ 189 + ICH_HFGRTR_EL2_ICC_PPI_ENABLERn_EL1 | \ 190 + ICH_HFGRTR_EL2_ICC_PPI_HMRn_EL1 | \ 191 + ICH_HFGRTR_EL2_ICC_IAFFIDR_EL1 | \ 192 + ICH_HFGRTR_EL2_ICC_ICSR_EL1 | \ 193 + ICH_HFGRTR_EL2_ICC_PCR_EL1 | \ 194 + ICH_HFGRTR_EL2_ICC_HPPIR_EL1 | \ 195 + ICH_HFGRTR_EL2_ICC_HAPR_EL1 | \ 196 + ICH_HFGRTR_EL2_ICC_CR0_EL1 | \ 197 + ICH_HFGRTR_EL2_ICC_IDRn_EL1 | \ 198 + ICH_HFGRTR_EL2_ICC_APR_EL1) 199 + msr_s SYS_ICH_HFGRTR_EL2, x0 // Disable reg read traps 200 + mov_q x0, (ICH_HFGWTR_EL2_ICC_PPI_ACTIVERn_EL1 | \ 201 + ICH_HFGWTR_EL2_ICC_PPI_PRIORITYRn_EL1 | \ 202 + ICH_HFGWTR_EL2_ICC_PPI_PENDRn_EL1 | \ 203 + ICH_HFGWTR_EL2_ICC_PPI_ENABLERn_EL1 | \ 204 + ICH_HFGWTR_EL2_ICC_ICSR_EL1 | \ 205 + ICH_HFGWTR_EL2_ICC_PCR_EL1 | \ 206 + ICH_HFGWTR_EL2_ICC_CR0_EL1 | \ 207 + ICH_HFGWTR_EL2_ICC_APR_EL1) 208 + msr_s SYS_ICH_HFGWTR_EL2, x0 // Disable reg write traps 209 + .Lskip_gicv5_\@: 210 + .endm 211 + 168 212 .macro __init_el2_hstr 169 213 msr hstr_el2, xzr // Disable CP15 traps to EL2 170 214 .endm ··· 358 314 __init_el2_lor 359 315 __init_el2_stage2 360 316 __init_el2_gicv3 317 + __init_el2_gicv5 361 318 __init_el2_hstr 362 319 __init_el2_nvhe_idregs 363 320 __init_el2_cptr