ASoC: mediatek: mt8188: revise AFE driver

+46 -20

Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml

··· 29 29 $ref: /schemas/types.yaml#/definitions/phandle 30 30 description: The phandle of the mediatek topckgen controller 31 31 32 + mediatek,infracfg: 33 + $ref: /schemas/types.yaml#/definitions/phandle 34 + description: The phandle of the mediatek infracfg controller 35 + 32 36 power-domains: 33 37 maxItems: 1 34 38 ··· 56 52 - description: mux for i2si1_mck 57 53 - description: mux for i2si2_mck 58 54 - description: audio 26m clock 55 + - description: audio pll1 divide 4 56 + - description: audio pll2 divide 4 57 + - description: clock divider for iec 58 + - description: mux for a2sys clock 59 + - description: mux for aud_iec 59 60 60 61 clock-names: 61 62 items: ··· 72 63 - const: apll12_div2 73 64 - const: apll12_div3 74 65 - const: apll12_div9 75 - - const: a1sys_hp_sel 76 - - const: aud_intbus_sel 77 - - const: audio_h_sel 78 - - const: audio_local_bus_sel 79 - - const: dptx_m_sel 80 - - const: i2so1_m_sel 81 - - const: i2so2_m_sel 82 - - const: i2si1_m_sel 83 - - const: i2si2_m_sel 66 + - const: top_a1sys_hp 67 + - const: top_aud_intbus 68 + - const: top_audio_h 69 + - const: top_audio_local_bus 70 + - const: top_dptx 71 + - const: top_i2so1 72 + - const: top_i2so2 73 + - const: top_i2si1 74 + - const: top_i2si2 84 75 - const: adsp_audio_26m 76 + - const: apll1_d4 77 + - const: apll2_d4 78 + - const: apll12_div4 79 + - const: top_a2sys 80 + - const: top_aud_iec 85 81 86 82 mediatek,etdm-in1-cowork-source: 87 83 $ref: /schemas/types.yaml#/definitions/uint32 ··· 158 144 - resets 159 145 - reset-names 160 146 - mediatek,topckgen 147 + - mediatek,infracfg 161 148 - power-domains 162 149 - clocks 163 150 - clock-names ··· 177 162 resets = <&watchdog 14>; 178 163 reset-names = "audiosys"; 179 164 mediatek,topckgen = <&topckgen>; 165 + mediatek,infracfg = <&infracfg_ao>; 180 166 power-domains = <&spm 13>; //MT8188_POWER_DOMAIN_AUDIO 181 167 mediatek,etdm-in2-cowork-source = <2>; 182 168 mediatek,etdm-out2-cowork-source = <0>; ··· 200 184 <&topckgen 78>, //CLK_TOP_I2SO2 201 185 <&topckgen 79>, //CLK_TOP_I2SI1 202 186 <&topckgen 80>, //CLK_TOP_I2SI2 203 - <&adsp_audio26m 0>; //CLK_AUDIODSP_AUDIO26M 187 + <&adsp_audio26m 0>, //CLK_AUDIODSP_AUDIO26M 188 + <&topckgen 132>, //CLK_TOP_APLL1_D4 189 + <&topckgen 133>, //CLK_TOP_APLL2_D4 190 + <&topckgen 183>, //CLK_TOP_APLL12_CK_DIV4 191 + <&topckgen 84>, //CLK_TOP_A2SYS 192 + <&topckgen 82>; //CLK_TOP_AUD_IEC>; 204 193 clock-names = "clk26m", 205 194 "apll1", 206 195 "apll2", ··· 214 193 "apll12_div2", 215 194 "apll12_div3", 216 195 "apll12_div9", 217 - "a1sys_hp_sel", 218 - "aud_intbus_sel", 219 - "audio_h_sel", 220 - "audio_local_bus_sel", 221 - "dptx_m_sel", 222 - "i2so1_m_sel", 223 - "i2so2_m_sel", 224 - "i2si1_m_sel", 225 - "i2si2_m_sel", 226 - "adsp_audio_26m"; 196 + "top_a1sys_hp", 197 + "top_aud_intbus", 198 + "top_audio_h", 199 + "top_audio_local_bus", 200 + "top_dptx", 201 + "top_i2so1", 202 + "top_i2so2", 203 + "top_i2si1", 204 + "top_i2si2", 205 + "adsp_audio_26m", 206 + "apll1_d4", 207 + "apll2_d4", 208 + "apll12_div4", 209 + "top_a2sys", 210 + "top_aud_iec"; 227 211 }; 228 212 229 213 ...

+123 -27

sound/soc/mediatek/mt8188/mt8188-afe-clk.c

··· 24 24 [MT8188_CLK_APMIXED_APLL2] = "apll2", 25 25 26 26 /* divider */ 27 + [MT8188_CLK_TOP_APLL1_D4] = "apll1_d4", 28 + [MT8188_CLK_TOP_APLL2_D4] = "apll2_d4", 27 29 [MT8188_CLK_TOP_APLL12_DIV0] = "apll12_div0", 28 30 [MT8188_CLK_TOP_APLL12_DIV1] = "apll12_div1", 29 31 [MT8188_CLK_TOP_APLL12_DIV2] = "apll12_div2", 30 32 [MT8188_CLK_TOP_APLL12_DIV3] = "apll12_div3", 33 + [MT8188_CLK_TOP_APLL12_DIV4] = "apll12_div4", 31 34 [MT8188_CLK_TOP_APLL12_DIV9] = "apll12_div9", 32 35 33 36 /* mux */ 34 37 [MT8188_CLK_TOP_A1SYS_HP_SEL] = "top_a1sys_hp", 38 + [MT8188_CLK_TOP_A2SYS_SEL] = "top_a2sys", 39 + [MT8188_CLK_TOP_AUD_IEC_SEL] = "top_aud_iec", 35 40 [MT8188_CLK_TOP_AUD_INTBUS_SEL] = "top_aud_intbus", 36 41 [MT8188_CLK_TOP_AUDIO_H_SEL] = "top_audio_h", 37 42 [MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "top_audio_local_bus", ··· 383 378 MT8188_MCK_SEL_APLL1 : MT8188_MCK_SEL_APLL2; 384 379 } 385 380 381 + int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate) 382 + { 383 + return ((rate % 8000) == 0) ? MT8188_AUD_PLL1 : MT8188_AUD_PLL2; 384 + } 385 + 386 + int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name) 387 + { 388 + if (strcmp(name, APLL1_W_NAME) == 0) 389 + return MT8188_AUD_PLL1; 390 + 391 + return MT8188_AUD_PLL2; 392 + } 393 + 386 394 int mt8188_afe_init_clock(struct mtk_base_afe *afe) 387 395 { 388 396 struct mt8188_afe_private *afe_priv = afe->platform_priv; ··· 495 477 if (clk && parent) { 496 478 ret = clk_set_parent(clk, parent); 497 479 if (ret) { 498 - dev_dbg(afe->dev, "%s(), failed to set clk parent\n", 499 - __func__); 480 + dev_dbg(afe->dev, "%s(), failed to set clk parent %d\n", 481 + __func__, ret); 500 482 return ret; 501 483 } 502 484 } ··· 623 605 return 0; 624 606 } 625 607 626 - static int mt8188_afe_enable_timing_sys(struct mtk_base_afe *afe) 608 + static int mt8188_afe_enable_a1sys(struct mtk_base_afe *afe) 609 + { 610 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 611 + int ret; 612 + 613 + ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]); 614 + if (ret) 615 + return ret; 616 + 617 + return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING); 618 + } 619 + 620 + static int mt8188_afe_disable_a1sys(struct mtk_base_afe *afe) 627 621 { 628 622 struct mt8188_afe_private *afe_priv = afe->platform_priv; 629 623 630 - mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]); 631 - mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]); 624 + mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING); 625 + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]); 626 + return 0; 627 + } 632 628 633 - mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING); 634 - mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING); 635 - mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_26M_TIMING); 629 + static int mt8188_afe_enable_a2sys(struct mtk_base_afe *afe) 630 + { 631 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 632 + int ret; 633 + 634 + ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]); 635 + if (ret) 636 + return ret; 637 + 638 + return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING); 639 + } 640 + 641 + static int mt8188_afe_disable_a2sys(struct mtk_base_afe *afe) 642 + { 643 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 644 + 645 + mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING); 646 + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]); 647 + return 0; 648 + } 649 + 650 + int mt8188_apll1_enable(struct mtk_base_afe *afe) 651 + { 652 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 653 + int ret; 654 + 655 + ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]); 656 + if (ret) 657 + return ret; 658 + 659 + ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL], 660 + afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]); 661 + if (ret) 662 + goto err_clk_parent; 663 + 664 + ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL1); 665 + if (ret) 666 + goto err_apll_tuner; 667 + 668 + ret = mt8188_afe_enable_a1sys(afe); 669 + if (ret) 670 + goto err_a1sys; 671 + 672 + return 0; 673 + 674 + err_a1sys: 675 + mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1); 676 + err_apll_tuner: 677 + mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL], 678 + afe_priv->clk[MT8188_CLK_XTAL_26M]); 679 + err_clk_parent: 680 + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]); 681 + 682 + return ret; 683 + } 684 + 685 + int mt8188_apll1_disable(struct mtk_base_afe *afe) 686 + { 687 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 688 + 689 + mt8188_afe_disable_a1sys(afe); 690 + mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1); 691 + mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL], 692 + afe_priv->clk[MT8188_CLK_XTAL_26M]); 693 + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]); 636 694 637 695 return 0; 638 696 } 639 697 640 - static int mt8188_afe_disable_timing_sys(struct mtk_base_afe *afe) 698 + int mt8188_apll2_enable(struct mtk_base_afe *afe) 641 699 { 642 - struct mt8188_afe_private *afe_priv = afe->platform_priv; 700 + int ret; 643 701 644 - mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]); 645 - mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]); 702 + ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL2); 703 + if (ret) 704 + return ret; 646 705 647 - mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_26M_TIMING); 648 - mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING); 649 - mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING); 706 + ret = mt8188_afe_enable_a2sys(afe); 707 + if (ret) 708 + goto err_a2sys; 650 709 710 + return 0; 711 + err_a2sys: 712 + mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2); 713 + 714 + return ret; 715 + } 716 + 717 + int mt8188_apll2_disable(struct mtk_base_afe *afe) 718 + { 719 + mt8188_afe_disable_a2sys(afe); 720 + mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2); 651 721 return 0; 652 722 } 653 723 654 724 int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe) 655 725 { 656 - mt8188_afe_enable_timing_sys(afe); 657 - 726 + mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_26M_TIMING); 658 727 mt8188_afe_enable_afe_on(afe); 659 - 660 - mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL1); 661 - mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL2); 662 - 663 728 return 0; 664 729 } 665 730 666 731 int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe) 667 732 { 668 - mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2); 669 - mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1); 670 - 671 733 mt8188_afe_disable_afe_on(afe); 672 - 673 - mt8188_afe_disable_timing_sys(afe); 674 - 734 + mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_26M_TIMING); 675 735 return 0; 676 736 }

+15

sound/soc/mediatek/mt8188/mt8188-afe-clk.h

··· 11 11 #ifndef _MT8188_AFE_CLK_H_ 12 12 #define _MT8188_AFE_CLK_H_ 13 13 14 + /* APLL */ 15 + #define APLL1_W_NAME "APLL1" 16 + #define APLL2_W_NAME "APLL2" 17 + 14 18 enum { 15 19 /* xtal */ 16 20 MT8188_CLK_XTAL_26M, ··· 22 18 MT8188_CLK_APMIXED_APLL1, 23 19 MT8188_CLK_APMIXED_APLL2, 24 20 /* divider */ 21 + MT8188_CLK_TOP_APLL1_D4, 22 + MT8188_CLK_TOP_APLL2_D4, 25 23 MT8188_CLK_TOP_APLL12_DIV0, 26 24 MT8188_CLK_TOP_APLL12_DIV1, 27 25 MT8188_CLK_TOP_APLL12_DIV2, 28 26 MT8188_CLK_TOP_APLL12_DIV3, 27 + MT8188_CLK_TOP_APLL12_DIV4, 29 28 MT8188_CLK_TOP_APLL12_DIV9, 30 29 /* mux */ 31 30 MT8188_CLK_TOP_A1SYS_HP_SEL, 31 + MT8188_CLK_TOP_A2SYS_SEL, 32 + MT8188_CLK_TOP_AUD_IEC_SEL, 32 33 MT8188_CLK_TOP_AUD_INTBUS_SEL, 33 34 MT8188_CLK_TOP_AUDIO_H_SEL, 34 35 MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL, ··· 108 99 int mt8188_afe_get_mclk_source_clk_id(int sel); 109 100 int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll); 110 101 int mt8188_afe_get_default_mclk_source_by_rate(int rate); 102 + int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate); 103 + int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name); 111 104 int mt8188_afe_init_clock(struct mtk_base_afe *afe); 112 105 void mt8188_afe_deinit_clock(void *priv); 113 106 int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk); ··· 118 107 unsigned int rate); 119 108 int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, 120 109 struct clk *parent); 110 + int mt8188_apll1_enable(struct mtk_base_afe *afe); 111 + int mt8188_apll1_disable(struct mtk_base_afe *afe); 112 + int mt8188_apll2_enable(struct mtk_base_afe *afe); 113 + int mt8188_apll2_disable(struct mtk_base_afe *afe); 121 114 int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe); 122 115 int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe); 123 116 int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);

+78 -35

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

··· 17 17 #include <linux/of_address.h> 18 18 #include <linux/of_platform.h> 19 19 #include <linux/pm_runtime.h> 20 + #include <linux/soc/mediatek/infracfg.h> 20 21 #include <linux/reset.h> 21 22 #include <sound/pcm_params.h> 22 23 #include "mt8188-afe-common.h" ··· 1899 1898 MT8188_AFE_MEMIF_UL10), 1900 1899 }; 1901 1900 1902 - static const struct snd_soc_component_driver mt8188_afe_pcm_dai_component = { 1903 - .name = "mt8188-afe-pcm-dai", 1904 - }; 1905 - 1906 1901 static const struct mtk_base_memif_data memif_data[MT8188_AFE_MEMIF_NUM] = { 1907 1902 [MT8188_AFE_MEMIF_DL2] = { 1908 1903 .name = "DL2", ··· 3134 3137 return 0; 3135 3138 } 3136 3139 3140 + #define MT8188_DELAY_US 10 3141 + #define MT8188_TIMEOUT_US USEC_PER_SEC 3142 + 3143 + static int bus_protect_enable(struct regmap *regmap) 3144 + { 3145 + int ret; 3146 + u32 val; 3147 + u32 mask; 3148 + 3149 + val = 0; 3150 + mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1; 3151 + regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_SET, mask); 3152 + 3153 + ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA, 3154 + val, (val & mask) == mask, 3155 + MT8188_DELAY_US, MT8188_TIMEOUT_US); 3156 + if (ret) 3157 + return ret; 3158 + 3159 + val = 0; 3160 + mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2; 3161 + regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_SET, mask); 3162 + 3163 + ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA, 3164 + val, (val & mask) == mask, 3165 + MT8188_DELAY_US, MT8188_TIMEOUT_US); 3166 + return ret; 3167 + } 3168 + 3169 + static int bus_protect_disable(struct regmap *regmap) 3170 + { 3171 + int ret; 3172 + u32 val; 3173 + u32 mask; 3174 + 3175 + val = 0; 3176 + mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2; 3177 + regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_CLR, mask); 3178 + 3179 + ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA, 3180 + val, !(val & mask), 3181 + MT8188_DELAY_US, MT8188_TIMEOUT_US); 3182 + if (ret) 3183 + return ret; 3184 + 3185 + val = 0; 3186 + mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1; 3187 + regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_CLR, mask); 3188 + 3189 + ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA, 3190 + val, !(val & mask), 3191 + MT8188_DELAY_US, MT8188_TIMEOUT_US); 3192 + return ret; 3193 + } 3194 + 3137 3195 static int mt8188_afe_pcm_dev_probe(struct platform_device *pdev) 3138 3196 { 3139 3197 struct mtk_base_afe *afe; 3140 3198 struct mt8188_afe_private *afe_priv; 3141 3199 struct device *dev; 3142 - int i, irq_id, ret; 3143 - struct snd_soc_component *component; 3144 3200 struct reset_control *rstc; 3201 + struct regmap *infra_ao; 3202 + int i, irq_id, ret; 3145 3203 3146 3204 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33)); 3147 3205 if (ret) ··· 3220 3168 return dev_err_probe(dev, PTR_ERR(afe->base_addr), 3221 3169 "AFE base_addr not found\n"); 3222 3170 3171 + infra_ao = syscon_regmap_lookup_by_phandle(dev->of_node, 3172 + "mediatek,infracfg"); 3173 + if (IS_ERR(infra_ao)) 3174 + return dev_err_probe(dev, PTR_ERR(infra_ao), 3175 + "%s() Cannot find infra_ao controller\n", 3176 + __func__); 3177 + 3223 3178 /* reset controller to reset audio regs before regmap cache */ 3224 3179 rstc = devm_reset_control_get_exclusive(dev, "audiosys"); 3225 3180 if (IS_ERR(rstc)) 3226 3181 return dev_err_probe(dev, PTR_ERR(rstc), 3227 3182 "could not get audiosys reset\n"); 3228 3183 3184 + ret = bus_protect_enable(infra_ao); 3185 + if (ret) { 3186 + dev_err(dev, "bus_protect_enable failed\n"); 3187 + return ret; 3188 + } 3189 + 3229 3190 ret = reset_control_reset(rstc); 3230 3191 if (ret) { 3231 3192 dev_err(dev, "failed to trigger audio reset:%d\n", ret); 3193 + return ret; 3194 + } 3195 + 3196 + ret = bus_protect_disable(infra_ao); 3197 + if (ret) { 3198 + dev_err(dev, "bus_protect_disable failed\n"); 3232 3199 return ret; 3233 3200 } 3234 3201 ··· 3351 3280 3352 3281 /* register component */ 3353 3282 ret = devm_snd_soc_register_component(dev, &mt8188_afe_component, 3354 - NULL, 0); 3283 + afe->dai_drivers, afe->num_dai_drivers); 3355 3284 if (ret) { 3356 3285 dev_warn(dev, "err_platform\n"); 3357 - goto err_pm_put; 3358 - } 3359 - 3360 - component = devm_kzalloc(&pdev->dev, sizeof(*component), GFP_KERNEL); 3361 - if (!component) { 3362 - ret = -ENOMEM; 3363 - goto err_pm_put; 3364 - } 3365 - 3366 - ret = snd_soc_component_initialize(component, 3367 - &mt8188_afe_pcm_dai_component, 3368 - &pdev->dev); 3369 - if (ret) 3370 - goto err_pm_put; 3371 - #ifdef CONFIG_DEBUG_FS 3372 - component->debugfs_prefix = "pcm"; 3373 - #endif 3374 - ret = snd_soc_add_component(component, 3375 - afe->dai_drivers, 3376 - afe->num_dai_drivers); 3377 - if (ret) { 3378 - dev_warn(dev, "err_add_component\n"); 3379 3286 goto err_pm_put; 3380 3287 } 3381 3288 ··· 3370 3321 pm_runtime_put_sync(dev); 3371 3322 3372 3323 return ret; 3373 - } 3374 - 3375 - static void mt8188_afe_pcm_dev_remove(struct platform_device *pdev) 3376 - { 3377 - snd_soc_unregister_component(&pdev->dev); 3378 3324 } 3379 3325 3380 3326 static const struct of_device_id mt8188_afe_pcm_dt_match[] = { ··· 3390 3346 .pm = &mt8188_afe_pm_ops, 3391 3347 }, 3392 3348 .probe = mt8188_afe_pcm_dev_probe, 3393 - .remove_new = mt8188_afe_pcm_dev_remove, 3394 3349 }; 3395 3350 3396 3351 module_platform_driver(mt8188_afe_pcm_driver);

-37

sound/soc/mediatek/mt8188/mt8188-dai-adda.c

··· 18 18 #define ADDA_HIRES_THRES 48000 19 19 20 20 enum { 21 - SUPPLY_SEQ_CLOCK_SEL, 22 21 SUPPLY_SEQ_ADDA_DL_ON, 23 22 SUPPLY_SEQ_ADDA_MTKAIF_CFG, 24 23 SUPPLY_SEQ_ADDA_UL_ON, ··· 241 242 return 0; 242 243 } 243 244 244 - static int mtk_audio_hires_event(struct snd_soc_dapm_widget *w, 245 - struct snd_kcontrol *kcontrol, 246 - int event) 247 - { 248 - struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 249 - struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 250 - struct mt8188_afe_private *afe_priv = afe->platform_priv; 251 - struct clk *clk = afe_priv->clk[MT8188_CLK_TOP_AUDIO_H_SEL]; 252 - struct clk *clk_parent; 253 - 254 - dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 255 - __func__, w->name, event); 256 - 257 - switch (event) { 258 - case SND_SOC_DAPM_PRE_PMU: 259 - clk_parent = afe_priv->clk[MT8188_CLK_APMIXED_APLL1]; 260 - break; 261 - case SND_SOC_DAPM_POST_PMD: 262 - clk_parent = afe_priv->clk[MT8188_CLK_XTAL_26M]; 263 - break; 264 - default: 265 - return 0; 266 - } 267 - mt8188_afe_set_clk_parent(afe, clk, clk_parent); 268 - 269 - return 0; 270 - } 271 - 272 245 static int mtk_afe_adc_hires_connect(struct snd_soc_dapm_widget *source, 273 246 struct snd_soc_dapm_widget *sink) 274 247 { ··· 335 364 mtk_adda_ul_event, 336 365 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 337 366 338 - SND_SOC_DAPM_SUPPLY_S("AUDIO_HIRES", SUPPLY_SEQ_CLOCK_SEL, 339 - SND_SOC_NOPM, 340 - 0, 0, 341 - mtk_audio_hires_event, 342 - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 343 - 344 367 SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG, 345 368 SND_SOC_NOPM, 346 369 0, 0, ··· 362 397 {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"}, 363 398 {"ADDA Capture", NULL, "aud_adc"}, 364 399 {"ADDA Capture", NULL, "aud_adc_hires", mtk_afe_adc_hires_connect}, 365 - {"aud_adc_hires", NULL, "AUDIO_HIRES"}, 366 400 367 401 {"I168", NULL, "ADDA Capture"}, 368 402 {"I169", NULL, "ADDA Capture"}, ··· 370 406 {"ADDA Playback", NULL, "ADDA Playback Enable"}, 371 407 {"ADDA Playback", NULL, "aud_dac"}, 372 408 {"ADDA Playback", NULL, "aud_dac_hires", mtk_afe_dac_hires_connect}, 373 - {"aud_dac_hires", NULL, "AUDIO_HIRES"}, 374 409 375 410 {"DL_GAIN", NULL, "O176"}, 376 411 {"DL_GAIN", NULL, "O177"},

+535 -387

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

··· 22 22 #define ENUM_TO_STR(x) #x 23 23 24 24 enum { 25 + SUPPLY_SEQ_APLL, 26 + SUPPLY_SEQ_ETDM_MCLK, 27 + SUPPLY_SEQ_ETDM_CG, 28 + SUPPLY_SEQ_DPTX_EN, 29 + SUPPLY_SEQ_ETDM_EN, 30 + }; 31 + 32 + enum { 25 33 MTK_DAI_ETDM_FORMAT_I2S = 0, 26 34 MTK_DAI_ETDM_FORMAT_LJ, 27 35 MTK_DAI_ETDM_FORMAT_RJ, ··· 92 84 }; 93 85 94 86 struct mtk_dai_etdm_priv { 95 - unsigned int clock_mode; 96 87 unsigned int data_mode; 97 88 bool slave_mode; 98 89 bool lrck_inv; 99 90 bool bck_inv; 91 + unsigned int rate; 100 92 unsigned int format; 101 93 unsigned int slots; 102 94 unsigned int lrck_width; ··· 108 100 unsigned int cowork_slv_count; 109 101 int cowork_slv_id[MT8188_AFE_IO_ETDM_NUM - 1]; //dai_id 110 102 bool in_disable_ch[MT8188_ETDM_MAX_CHANNELS]; 111 - unsigned int en_ref_cnt; 112 - bool is_prepared; 113 103 }; 114 104 115 105 static const struct mtk_dai_etdm_rate mt8188_etdm_rates[] = { ··· 351 345 } 352 346 } 353 347 348 + static int get_etdm_id_by_name(struct mtk_base_afe *afe, 349 + const char *name) 350 + { 351 + if (!strncmp(name, "ETDM1_IN", strlen("ETDM1_IN"))) 352 + return MT8188_AFE_IO_ETDM1_IN; 353 + else if (!strncmp(name, "ETDM2_IN", strlen("ETDM2_IN"))) 354 + return MT8188_AFE_IO_ETDM2_IN; 355 + else if (!strncmp(name, "ETDM1_OUT", strlen("ETDM1_OUT"))) 356 + return MT8188_AFE_IO_ETDM1_OUT; 357 + else if (!strncmp(name, "ETDM2_OUT", strlen("ETDM2_OUT"))) 358 + return MT8188_AFE_IO_ETDM2_OUT; 359 + else if (!strncmp(name, "ETDM3_OUT", strlen("ETDM3_OUT"))) 360 + return MT8188_AFE_IO_ETDM3_OUT; 361 + else if (!strncmp(name, "DPTX", strlen("DPTX"))) 362 + return MT8188_AFE_IO_ETDM3_OUT; 363 + else 364 + return -EINVAL; 365 + } 366 + 367 + static struct mtk_dai_etdm_priv *get_etdm_priv_by_name(struct mtk_base_afe *afe, 368 + const char *name) 369 + { 370 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 371 + int dai_id = get_etdm_id_by_name(afe, name); 372 + 373 + if (dai_id < MT8188_AFE_IO_ETDM_START || 374 + dai_id >= MT8188_AFE_IO_ETDM_END) 375 + return NULL; 376 + 377 + return afe_priv->dai_priv[dai_id]; 378 + } 379 + 354 380 static int mtk_dai_etdm_enable_mclk(struct mtk_base_afe *afe, int dai_id) 355 381 { 356 382 struct mt8188_afe_private *afe_priv = afe->platform_priv; 383 + struct mtk_dai_etdm_priv *etdm_data; 384 + struct etdm_con_reg etdm_reg; 385 + unsigned int val = 0; 386 + unsigned int mask; 387 + int clkmux_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id); 357 388 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 389 + int apll_clk_id; 390 + int apll; 391 + int ret; 358 392 359 - if (clkdiv_id < 0) 393 + if (!is_valid_etdm_dai(dai_id)) 360 394 return -EINVAL; 395 + etdm_data = afe_priv->dai_priv[dai_id]; 396 + 397 + apll = etdm_data->mclk_apll; 398 + apll_clk_id = mt8188_afe_get_mclk_source_clk_id(apll); 399 + 400 + if (clkmux_id < 0 || clkdiv_id < 0) 401 + return -EINVAL; 402 + 403 + if (apll_clk_id < 0) 404 + return apll_clk_id; 405 + 406 + ret = get_etdm_reg(dai_id, &etdm_reg); 407 + if (ret < 0) 408 + return ret; 409 + 410 + mask = ETDM_CON1_MCLK_OUTPUT; 411 + if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 412 + val = ETDM_CON1_MCLK_OUTPUT; 413 + regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 414 + 415 + /* enable parent clock before select apll*/ 416 + mt8188_afe_enable_clk(afe, afe_priv->clk[clkmux_id]); 417 + 418 + /* select apll */ 419 + ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[clkmux_id], 420 + afe_priv->clk[apll_clk_id]); 421 + if (ret) 422 + return ret; 423 + 424 + /* set rate */ 425 + ret = mt8188_afe_set_clk_rate(afe, afe_priv->clk[clkdiv_id], 426 + etdm_data->mclk_freq); 361 427 362 428 mt8188_afe_enable_clk(afe, afe_priv->clk[clkdiv_id]); 363 429 ··· 439 361 static int mtk_dai_etdm_disable_mclk(struct mtk_base_afe *afe, int dai_id) 440 362 { 441 363 struct mt8188_afe_private *afe_priv = afe->platform_priv; 364 + int clkmux_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id); 442 365 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 443 366 444 - if (clkdiv_id < 0) 367 + if (clkmux_id < 0 || clkdiv_id < 0) 445 368 return -EINVAL; 446 369 447 370 mt8188_afe_disable_clk(afe, afe_priv->clk[clkdiv_id]); 371 + mt8188_afe_disable_clk(afe, afe_priv->clk[clkmux_id]); 372 + 373 + return 0; 374 + } 375 + 376 + static int mtk_afe_etdm_apll_connect(struct snd_soc_dapm_widget *source, 377 + struct snd_soc_dapm_widget *sink) 378 + { 379 + struct snd_soc_dapm_widget *w = sink; 380 + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 381 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 382 + struct mtk_dai_etdm_priv *etdm_priv; 383 + int cur_apll; 384 + int need_apll; 385 + 386 + etdm_priv = get_etdm_priv_by_name(afe, w->name); 387 + if (!etdm_priv) { 388 + dev_dbg(afe->dev, "etdm_priv == NULL\n"); 389 + return 0; 390 + } 391 + 392 + cur_apll = mt8188_get_apll_by_name(afe, source->name); 393 + need_apll = mt8188_get_apll_by_rate(afe, etdm_priv->rate); 394 + 395 + return (need_apll == cur_apll) ? 1 : 0; 396 + } 397 + 398 + static int mtk_afe_mclk_apll_connect(struct snd_soc_dapm_widget *source, 399 + struct snd_soc_dapm_widget *sink) 400 + { 401 + struct snd_soc_dapm_widget *w = sink; 402 + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 403 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 404 + struct mtk_dai_etdm_priv *etdm_priv; 405 + int cur_apll; 406 + 407 + etdm_priv = get_etdm_priv_by_name(afe, w->name); 408 + 409 + cur_apll = mt8188_get_apll_by_name(afe, source->name); 410 + 411 + return (etdm_priv->mclk_apll == cur_apll) ? 1 : 0; 412 + } 413 + 414 + static int mtk_etdm_mclk_connect(struct snd_soc_dapm_widget *source, 415 + struct snd_soc_dapm_widget *sink) 416 + { 417 + struct snd_soc_dapm_widget *w = sink; 418 + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 419 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 420 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 421 + struct mtk_dai_etdm_priv *etdm_priv; 422 + int mclk_id; 423 + 424 + mclk_id = get_etdm_id_by_name(afe, source->name); 425 + if (mclk_id < 0) { 426 + dev_dbg(afe->dev, "mclk_id < 0\n"); 427 + return 0; 428 + } 429 + 430 + etdm_priv = get_etdm_priv_by_name(afe, w->name); 431 + if (!etdm_priv) { 432 + dev_dbg(afe->dev, "etdm_priv == NULL\n"); 433 + return 0; 434 + } 435 + 436 + if (get_etdm_id_by_name(afe, sink->name) == mclk_id) 437 + return !!(etdm_priv->mclk_freq > 0); 438 + 439 + if (etdm_priv->cowork_source_id == mclk_id) { 440 + etdm_priv = afe_priv->dai_priv[mclk_id]; 441 + return !!(etdm_priv->mclk_freq > 0); 442 + } 443 + 444 + return 0; 445 + } 446 + 447 + static int mtk_etdm_cowork_connect(struct snd_soc_dapm_widget *source, 448 + struct snd_soc_dapm_widget *sink) 449 + { 450 + struct snd_soc_dapm_widget *w = sink; 451 + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 452 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 453 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 454 + struct mtk_dai_etdm_priv *etdm_priv; 455 + int source_id; 456 + int i; 457 + 458 + source_id = get_etdm_id_by_name(afe, source->name); 459 + if (source_id < 0) { 460 + dev_dbg(afe->dev, "%s() source_id < 0\n", __func__); 461 + return 0; 462 + } 463 + 464 + etdm_priv = get_etdm_priv_by_name(afe, w->name); 465 + if (!etdm_priv) { 466 + dev_dbg(afe->dev, "%s() etdm_priv == NULL\n", __func__); 467 + return 0; 468 + } 469 + 470 + if (etdm_priv->cowork_source_id != COWORK_ETDM_NONE) { 471 + if (etdm_priv->cowork_source_id == source_id) 472 + return 1; 473 + 474 + etdm_priv = afe_priv->dai_priv[etdm_priv->cowork_source_id]; 475 + for (i = 0; i < etdm_priv->cowork_slv_count; i++) { 476 + if (etdm_priv->cowork_slv_id[i] == source_id) 477 + return 1; 478 + } 479 + } else { 480 + for (i = 0; i < etdm_priv->cowork_slv_count; i++) { 481 + if (etdm_priv->cowork_slv_id[i] == source_id) 482 + return 1; 483 + } 484 + } 485 + 486 + return 0; 487 + } 488 + 489 + static int mtk_apll_event(struct snd_soc_dapm_widget *w, 490 + struct snd_kcontrol *kcontrol, 491 + int event) 492 + { 493 + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 494 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 495 + 496 + dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 497 + __func__, w->name, event); 498 + 499 + switch (event) { 500 + case SND_SOC_DAPM_PRE_PMU: 501 + if (strcmp(w->name, APLL1_W_NAME) == 0) 502 + mt8188_apll1_enable(afe); 503 + else 504 + mt8188_apll2_enable(afe); 505 + break; 506 + case SND_SOC_DAPM_POST_PMD: 507 + if (strcmp(w->name, APLL1_W_NAME) == 0) 508 + mt8188_apll1_disable(afe); 509 + else 510 + mt8188_apll2_disable(afe); 511 + break; 512 + default: 513 + break; 514 + } 515 + 516 + return 0; 517 + } 518 + 519 + static int mtk_etdm_mclk_event(struct snd_soc_dapm_widget *w, 520 + struct snd_kcontrol *kcontrol, 521 + int event) 522 + { 523 + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 524 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 525 + int mclk_id = get_etdm_id_by_name(afe, w->name); 526 + 527 + if (mclk_id < 0) { 528 + dev_dbg(afe->dev, "%s() mclk_id < 0\n", __func__); 529 + return 0; 530 + } 531 + 532 + dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 533 + __func__, w->name, event); 534 + 535 + switch (event) { 536 + case SND_SOC_DAPM_PRE_PMU: 537 + mtk_dai_etdm_enable_mclk(afe, mclk_id); 538 + break; 539 + case SND_SOC_DAPM_POST_PMD: 540 + mtk_dai_etdm_disable_mclk(afe, mclk_id); 541 + break; 542 + default: 543 + break; 544 + } 545 + 546 + return 0; 547 + } 548 + 549 + static int mtk_dptx_mclk_event(struct snd_soc_dapm_widget *w, 550 + struct snd_kcontrol *kcontrol, 551 + int event) 552 + { 553 + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 554 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 555 + 556 + dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 557 + __func__, w->name, event); 558 + 559 + switch (event) { 560 + case SND_SOC_DAPM_PRE_PMU: 561 + mtk_dai_etdm_enable_mclk(afe, MT8188_AFE_IO_DPTX); 562 + break; 563 + case SND_SOC_DAPM_POST_PMD: 564 + mtk_dai_etdm_disable_mclk(afe, MT8188_AFE_IO_DPTX); 565 + break; 566 + default: 567 + break; 568 + } 569 + 570 + return 0; 571 + } 572 + 573 + static int mtk_etdm_cg_event(struct snd_soc_dapm_widget *w, 574 + struct snd_kcontrol *kcontrol, 575 + int event) 576 + { 577 + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 578 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 579 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 580 + int etdm_id; 581 + int cg_id; 582 + 583 + etdm_id = get_etdm_id_by_name(afe, w->name); 584 + if (etdm_id < 0) { 585 + dev_dbg(afe->dev, "%s() etdm_id < 0\n", __func__); 586 + return 0; 587 + } 588 + 589 + cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(etdm_id); 590 + if (cg_id < 0) { 591 + dev_dbg(afe->dev, "%s() cg_id < 0\n", __func__); 592 + return 0; 593 + } 594 + 595 + dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 596 + __func__, w->name, event); 597 + 598 + switch (event) { 599 + case SND_SOC_DAPM_PRE_PMU: 600 + mt8188_afe_enable_clk(afe, afe_priv->clk[cg_id]); 601 + break; 602 + case SND_SOC_DAPM_POST_PMD: 603 + mt8188_afe_disable_clk(afe, afe_priv->clk[cg_id]); 604 + break; 605 + default: 606 + break; 607 + } 608 + 609 + return 0; 610 + } 611 + 612 + static int mtk_etdm3_cg_event(struct snd_soc_dapm_widget *w, 613 + struct snd_kcontrol *kcontrol, 614 + int event) 615 + { 616 + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 617 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 618 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 619 + 620 + dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 621 + __func__, w->name, event); 622 + 623 + switch (event) { 624 + case SND_SOC_DAPM_PRE_PMU: 625 + mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_HDMI_OUT]); 626 + break; 627 + case SND_SOC_DAPM_POST_PMD: 628 + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_HDMI_OUT]); 629 + break; 630 + default: 631 + break; 632 + } 448 633 449 634 return 0; 450 635 } ··· 1247 906 SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0, 1248 907 &hdmi_ch7_mux_control), 1249 908 909 + /* mclk en */ 910 + SND_SOC_DAPM_SUPPLY_S("ETDM1_IN_MCLK", SUPPLY_SEQ_ETDM_MCLK, 911 + SND_SOC_NOPM, 0, 0, 912 + mtk_etdm_mclk_event, 913 + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 914 + SND_SOC_DAPM_SUPPLY_S("ETDM2_IN_MCLK", SUPPLY_SEQ_ETDM_MCLK, 915 + SND_SOC_NOPM, 0, 0, 916 + mtk_etdm_mclk_event, 917 + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 918 + SND_SOC_DAPM_SUPPLY_S("ETDM1_OUT_MCLK", SUPPLY_SEQ_ETDM_MCLK, 919 + SND_SOC_NOPM, 0, 0, 920 + mtk_etdm_mclk_event, 921 + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 922 + SND_SOC_DAPM_SUPPLY_S("ETDM2_OUT_MCLK", SUPPLY_SEQ_ETDM_MCLK, 923 + SND_SOC_NOPM, 0, 0, 924 + mtk_etdm_mclk_event, 925 + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 926 + SND_SOC_DAPM_SUPPLY_S("DPTX_MCLK", SUPPLY_SEQ_ETDM_MCLK, 927 + SND_SOC_NOPM, 0, 0, 928 + mtk_dptx_mclk_event, 929 + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 930 + 931 + /* cg */ 932 + SND_SOC_DAPM_SUPPLY_S("ETDM1_IN_CG", SUPPLY_SEQ_ETDM_CG, 933 + SND_SOC_NOPM, 0, 0, 934 + mtk_etdm_cg_event, 935 + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 936 + SND_SOC_DAPM_SUPPLY_S("ETDM2_IN_CG", SUPPLY_SEQ_ETDM_CG, 937 + SND_SOC_NOPM, 0, 0, 938 + mtk_etdm_cg_event, 939 + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 940 + SND_SOC_DAPM_SUPPLY_S("ETDM1_OUT_CG", SUPPLY_SEQ_ETDM_CG, 941 + SND_SOC_NOPM, 0, 0, 942 + mtk_etdm_cg_event, 943 + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 944 + SND_SOC_DAPM_SUPPLY_S("ETDM2_OUT_CG", SUPPLY_SEQ_ETDM_CG, 945 + SND_SOC_NOPM, 0, 0, 946 + mtk_etdm_cg_event, 947 + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 948 + SND_SOC_DAPM_SUPPLY_S("ETDM3_OUT_CG", SUPPLY_SEQ_ETDM_CG, 949 + SND_SOC_NOPM, 0, 0, 950 + mtk_etdm3_cg_event, 951 + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 952 + 953 + /* en */ 954 + SND_SOC_DAPM_SUPPLY_S("ETDM1_IN_EN", SUPPLY_SEQ_ETDM_EN, 955 + ETDM_IN1_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0), 956 + SND_SOC_DAPM_SUPPLY_S("ETDM2_IN_EN", SUPPLY_SEQ_ETDM_EN, 957 + ETDM_IN2_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0), 958 + SND_SOC_DAPM_SUPPLY_S("ETDM1_OUT_EN", SUPPLY_SEQ_ETDM_EN, 959 + ETDM_OUT1_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0), 960 + SND_SOC_DAPM_SUPPLY_S("ETDM2_OUT_EN", SUPPLY_SEQ_ETDM_EN, 961 + ETDM_OUT2_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0), 962 + SND_SOC_DAPM_SUPPLY_S("ETDM3_OUT_EN", SUPPLY_SEQ_ETDM_EN, 963 + ETDM_OUT3_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0), 964 + SND_SOC_DAPM_SUPPLY_S("DPTX_EN", SUPPLY_SEQ_DPTX_EN, 965 + AFE_DPTX_CON, AFE_DPTX_CON_ON_SHIFT, 0, NULL, 0), 966 + 967 + /* apll */ 968 + SND_SOC_DAPM_SUPPLY_S(APLL1_W_NAME, SUPPLY_SEQ_APLL, 969 + SND_SOC_NOPM, 0, 0, 970 + mtk_apll_event, 971 + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 972 + SND_SOC_DAPM_SUPPLY_S(APLL2_W_NAME, SUPPLY_SEQ_APLL, 973 + SND_SOC_NOPM, 0, 0, 974 + mtk_apll_event, 975 + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 976 + 1250 977 SND_SOC_DAPM_INPUT("ETDM_INPUT"), 1251 978 SND_SOC_DAPM_OUTPUT("ETDM_OUTPUT"), 1252 979 }; 1253 980 1254 981 static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = { 982 + /* mclk */ 983 + {"ETDM1_IN", NULL, "ETDM1_IN_MCLK", mtk_etdm_mclk_connect}, 984 + {"ETDM1_IN", NULL, "ETDM2_IN_MCLK", mtk_etdm_mclk_connect}, 985 + {"ETDM1_IN", NULL, "ETDM1_OUT_MCLK", mtk_etdm_mclk_connect}, 986 + {"ETDM1_IN", NULL, "ETDM2_OUT_MCLK", mtk_etdm_mclk_connect}, 987 + 988 + {"ETDM2_IN", NULL, "ETDM1_IN_MCLK", mtk_etdm_mclk_connect}, 989 + {"ETDM2_IN", NULL, "ETDM2_IN_MCLK", mtk_etdm_mclk_connect}, 990 + {"ETDM2_IN", NULL, "ETDM1_OUT_MCLK", mtk_etdm_mclk_connect}, 991 + {"ETDM2_IN", NULL, "ETDM2_OUT_MCLK", mtk_etdm_mclk_connect}, 992 + 993 + {"ETDM1_OUT", NULL, "ETDM1_IN_MCLK", mtk_etdm_mclk_connect}, 994 + {"ETDM1_OUT", NULL, "ETDM2_IN_MCLK", mtk_etdm_mclk_connect}, 995 + {"ETDM1_OUT", NULL, "ETDM1_OUT_MCLK", mtk_etdm_mclk_connect}, 996 + {"ETDM1_OUT", NULL, "ETDM2_OUT_MCLK", mtk_etdm_mclk_connect}, 997 + 998 + {"ETDM2_OUT", NULL, "ETDM1_IN_MCLK", mtk_etdm_mclk_connect}, 999 + {"ETDM2_OUT", NULL, "ETDM2_IN_MCLK", mtk_etdm_mclk_connect}, 1000 + {"ETDM2_OUT", NULL, "ETDM1_OUT_MCLK", mtk_etdm_mclk_connect}, 1001 + {"ETDM2_OUT", NULL, "ETDM2_OUT_MCLK", mtk_etdm_mclk_connect}, 1002 + 1003 + {"DPTX", NULL, "DPTX_MCLK"}, 1004 + 1005 + {"ETDM1_IN_MCLK", NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1006 + {"ETDM1_IN_MCLK", NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1007 + 1008 + {"ETDM2_IN_MCLK", NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1009 + {"ETDM2_IN_MCLK", NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1010 + 1011 + {"ETDM1_OUT_MCLK", NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1012 + {"ETDM1_OUT_MCLK", NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1013 + 1014 + {"ETDM2_OUT_MCLK", NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1015 + {"ETDM2_OUT_MCLK", NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1016 + 1017 + {"DPTX_MCLK", NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1018 + {"DPTX_MCLK", NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1019 + 1020 + /* cg */ 1021 + {"ETDM1_IN", NULL, "ETDM1_IN_CG"}, 1022 + {"ETDM1_IN", NULL, "ETDM2_IN_CG", mtk_etdm_cowork_connect}, 1023 + {"ETDM1_IN", NULL, "ETDM1_OUT_CG", mtk_etdm_cowork_connect}, 1024 + {"ETDM1_IN", NULL, "ETDM2_OUT_CG", mtk_etdm_cowork_connect}, 1025 + 1026 + {"ETDM2_IN", NULL, "ETDM1_IN_CG", mtk_etdm_cowork_connect}, 1027 + {"ETDM2_IN", NULL, "ETDM2_IN_CG"}, 1028 + {"ETDM2_IN", NULL, "ETDM1_OUT_CG", mtk_etdm_cowork_connect}, 1029 + {"ETDM2_IN", NULL, "ETDM2_OUT_CG", mtk_etdm_cowork_connect}, 1030 + 1031 + {"ETDM1_OUT", NULL, "ETDM1_IN_CG", mtk_etdm_cowork_connect}, 1032 + {"ETDM1_OUT", NULL, "ETDM2_IN_CG", mtk_etdm_cowork_connect}, 1033 + {"ETDM1_OUT", NULL, "ETDM1_OUT_CG"}, 1034 + {"ETDM1_OUT", NULL, "ETDM2_OUT_CG", mtk_etdm_cowork_connect}, 1035 + 1036 + {"ETDM2_OUT", NULL, "ETDM1_IN_CG", mtk_etdm_cowork_connect}, 1037 + {"ETDM2_OUT", NULL, "ETDM2_IN_CG", mtk_etdm_cowork_connect}, 1038 + {"ETDM2_OUT", NULL, "ETDM1_OUT_CG", mtk_etdm_cowork_connect}, 1039 + {"ETDM2_OUT", NULL, "ETDM2_OUT_CG"}, 1040 + 1041 + {"ETDM3_OUT", NULL, "ETDM3_OUT_CG"}, 1042 + {"DPTX", NULL, "ETDM3_OUT_CG"}, 1043 + 1044 + /* en */ 1045 + {"ETDM1_IN", NULL, "ETDM1_IN_EN"}, 1046 + {"ETDM1_IN", NULL, "ETDM2_IN_EN", mtk_etdm_cowork_connect}, 1047 + {"ETDM1_IN", NULL, "ETDM1_OUT_EN", mtk_etdm_cowork_connect}, 1048 + {"ETDM1_IN", NULL, "ETDM2_OUT_EN", mtk_etdm_cowork_connect}, 1049 + 1050 + {"ETDM2_IN", NULL, "ETDM1_IN_EN", mtk_etdm_cowork_connect}, 1051 + {"ETDM2_IN", NULL, "ETDM2_IN_EN"}, 1052 + {"ETDM2_IN", NULL, "ETDM1_OUT_EN", mtk_etdm_cowork_connect}, 1053 + {"ETDM2_IN", NULL, "ETDM2_OUT_EN", mtk_etdm_cowork_connect}, 1054 + 1055 + {"ETDM1_OUT", NULL, "ETDM1_IN_EN", mtk_etdm_cowork_connect}, 1056 + {"ETDM1_OUT", NULL, "ETDM2_IN_EN", mtk_etdm_cowork_connect}, 1057 + {"ETDM1_OUT", NULL, "ETDM1_OUT_EN"}, 1058 + {"ETDM1_OUT", NULL, "ETDM2_OUT_EN", mtk_etdm_cowork_connect}, 1059 + 1060 + {"ETDM2_OUT", NULL, "ETDM1_IN_EN", mtk_etdm_cowork_connect}, 1061 + {"ETDM2_OUT", NULL, "ETDM2_IN_EN", mtk_etdm_cowork_connect}, 1062 + {"ETDM2_OUT", NULL, "ETDM1_OUT_EN", mtk_etdm_cowork_connect}, 1063 + {"ETDM2_OUT", NULL, "ETDM2_OUT_EN"}, 1064 + 1065 + {"ETDM3_OUT", NULL, "ETDM3_OUT_EN"}, 1066 + {"DPTX", NULL, "ETDM3_OUT_EN"}, 1067 + {"DPTX", NULL, "DPTX_EN"}, 1068 + 1069 + {"ETDM1_IN_EN", NULL, APLL1_W_NAME, mtk_afe_etdm_apll_connect}, 1070 + {"ETDM1_IN_EN", NULL, APLL2_W_NAME, mtk_afe_etdm_apll_connect}, 1071 + 1072 + {"ETDM2_IN_EN", NULL, APLL1_W_NAME, mtk_afe_etdm_apll_connect}, 1073 + {"ETDM2_IN_EN", NULL, APLL2_W_NAME, mtk_afe_etdm_apll_connect}, 1074 + 1075 + {"ETDM1_OUT_EN", NULL, APLL1_W_NAME, mtk_afe_etdm_apll_connect}, 1076 + {"ETDM1_OUT_EN", NULL, APLL2_W_NAME, mtk_afe_etdm_apll_connect}, 1077 + 1078 + {"ETDM2_OUT_EN", NULL, APLL1_W_NAME, mtk_afe_etdm_apll_connect}, 1079 + {"ETDM2_OUT_EN", NULL, APLL2_W_NAME, mtk_afe_etdm_apll_connect}, 1080 + 1081 + {"ETDM3_OUT_EN", NULL, APLL1_W_NAME, mtk_afe_etdm_apll_connect}, 1082 + {"ETDM3_OUT_EN", NULL, APLL2_W_NAME, mtk_afe_etdm_apll_connect}, 1083 + 1255 1084 {"I012", NULL, "ETDM2_IN"}, 1256 1085 {"I013", NULL, "ETDM2_IN"}, 1257 1086 {"I014", NULL, "ETDM2_IN"}, ··· 1674 1163 {"ETDM2_IN", NULL, "ETDM_INPUT"}, 1675 1164 }; 1676 1165 1677 - static int mt8188_afe_enable_etdm(struct mtk_base_afe *afe, int dai_id) 1678 - { 1679 - struct mt8188_afe_private *afe_priv = afe->platform_priv; 1680 - struct mtk_dai_etdm_priv *etdm_data; 1681 - struct etdm_con_reg etdm_reg; 1682 - unsigned long flags; 1683 - int ret = 0; 1684 - 1685 - if (!is_valid_etdm_dai(dai_id)) 1686 - return -EINVAL; 1687 - etdm_data = afe_priv->dai_priv[dai_id]; 1688 - 1689 - dev_dbg(afe->dev, "%s [%d]%d\n", __func__, dai_id, etdm_data->en_ref_cnt); 1690 - spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags); 1691 - etdm_data->en_ref_cnt++; 1692 - if (etdm_data->en_ref_cnt == 1) { 1693 - ret = get_etdm_reg(dai_id, &etdm_reg); 1694 - if (ret < 0) 1695 - goto out; 1696 - 1697 - regmap_set_bits(afe->regmap, etdm_reg.con0, ETDM_CON0_EN); 1698 - } 1699 - 1700 - out: 1701 - spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags); 1702 - return ret; 1703 - } 1704 - 1705 - static int mt8188_afe_disable_etdm(struct mtk_base_afe *afe, int dai_id) 1706 - { 1707 - struct mt8188_afe_private *afe_priv = afe->platform_priv; 1708 - struct mtk_dai_etdm_priv *etdm_data; 1709 - struct etdm_con_reg etdm_reg; 1710 - unsigned long flags; 1711 - int ret = 0; 1712 - 1713 - if (!is_valid_etdm_dai(dai_id)) 1714 - return -EINVAL; 1715 - etdm_data = afe_priv->dai_priv[dai_id]; 1716 - 1717 - dev_dbg(afe->dev, "%s [%d]%d\n", __func__, dai_id, etdm_data->en_ref_cnt); 1718 - spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags); 1719 - if (etdm_data->en_ref_cnt > 0) { 1720 - etdm_data->en_ref_cnt--; 1721 - if (etdm_data->en_ref_cnt == 0) { 1722 - ret = get_etdm_reg(dai_id, &etdm_reg); 1723 - if (ret < 0) 1724 - goto out; 1725 - regmap_clear_bits(afe->regmap, etdm_reg.con0, 1726 - ETDM_CON0_EN); 1727 - } 1728 - } 1729 - 1730 - out: 1731 - spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags); 1732 - return ret; 1733 - } 1734 - 1735 1166 static int etdm_cowork_slv_sel(int id, int slave_mode) 1736 1167 { 1737 1168 if (slave_mode) { ··· 1861 1408 } 1862 1409 1863 1410 /* dai ops */ 1864 - static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream, 1865 - struct snd_soc_dai *dai) 1866 - { 1867 - struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1868 - struct mt8188_afe_private *afe_priv = afe->platform_priv; 1869 - struct mtk_dai_etdm_priv *mst_etdm_data; 1870 - int mst_dai_id; 1871 - int slv_dai_id; 1872 - int cg_id; 1873 - int i; 1874 - 1875 - if (is_cowork_mode(dai)) { 1876 - mst_dai_id = get_etdm_cowork_master_id(dai); 1877 - if (!is_valid_etdm_dai(mst_dai_id)) 1878 - return -EINVAL; 1879 - mtk_dai_etdm_enable_mclk(afe, mst_dai_id); 1880 - 1881 - cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id); 1882 - if (cg_id >= 0) 1883 - mt8188_afe_enable_clk(afe, afe_priv->clk[cg_id]); 1884 - 1885 - mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1886 - 1887 - for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1888 - slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1889 - cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id); 1890 - if (cg_id >= 0) 1891 - mt8188_afe_enable_clk(afe, 1892 - afe_priv->clk[cg_id]); 1893 - } 1894 - } else { 1895 - mtk_dai_etdm_enable_mclk(afe, dai->id); 1896 - 1897 - cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 1898 - if (cg_id >= 0) 1899 - mt8188_afe_enable_clk(afe, afe_priv->clk[cg_id]); 1900 - } 1901 - 1902 - return 0; 1903 - } 1904 - 1905 - static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream, 1906 - struct snd_soc_dai *dai) 1907 - { 1908 - struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1909 - struct mt8188_afe_private *afe_priv = afe->platform_priv; 1910 - struct mtk_dai_etdm_priv *mst_etdm_data; 1911 - int mst_dai_id; 1912 - int slv_dai_id; 1913 - int cg_id; 1914 - int ret; 1915 - int i; 1916 - 1917 - if (!is_valid_etdm_dai(dai->id)) 1918 - return; 1919 - mst_etdm_data = afe_priv->dai_priv[dai->id]; 1920 - 1921 - dev_dbg(afe->dev, "%s(), dai id %d, prepared %d\n", __func__, dai->id, 1922 - mst_etdm_data->is_prepared); 1923 - 1924 - if (mst_etdm_data->is_prepared) { 1925 - mst_etdm_data->is_prepared = false; 1926 - 1927 - if (is_cowork_mode(dai)) { 1928 - mst_dai_id = get_etdm_cowork_master_id(dai); 1929 - if (!is_valid_etdm_dai(mst_dai_id)) 1930 - return; 1931 - mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1932 - 1933 - ret = mt8188_afe_disable_etdm(afe, mst_dai_id); 1934 - if (ret) 1935 - dev_dbg(afe->dev, "%s disable %d failed\n", 1936 - __func__, mst_dai_id); 1937 - 1938 - for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1939 - slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1940 - ret = mt8188_afe_disable_etdm(afe, slv_dai_id); 1941 - if (ret) 1942 - dev_dbg(afe->dev, "%s disable %d failed\n", 1943 - __func__, slv_dai_id); 1944 - } 1945 - } else { 1946 - ret = mt8188_afe_disable_etdm(afe, dai->id); 1947 - if (ret) 1948 - dev_dbg(afe->dev, "%s disable %d failed\n", 1949 - __func__, dai->id); 1950 - } 1951 - } 1952 - 1953 - if (is_cowork_mode(dai)) { 1954 - mst_dai_id = get_etdm_cowork_master_id(dai); 1955 - if (!is_valid_etdm_dai(mst_dai_id)) 1956 - return; 1957 - cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id); 1958 - if (cg_id >= 0) 1959 - mt8188_afe_disable_clk(afe, afe_priv->clk[cg_id]); 1960 - 1961 - mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1962 - for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1963 - slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1964 - cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id); 1965 - if (cg_id >= 0) 1966 - mt8188_afe_disable_clk(afe, 1967 - afe_priv->clk[cg_id]); 1968 - } 1969 - mtk_dai_etdm_disable_mclk(afe, mst_dai_id); 1970 - } else { 1971 - cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 1972 - if (cg_id >= 0) 1973 - mt8188_afe_disable_clk(afe, afe_priv->clk[cg_id]); 1974 - 1975 - mtk_dai_etdm_disable_mclk(afe, dai->id); 1976 - } 1977 - } 1978 - 1979 1411 static int mtk_dai_etdm_fifo_mode(struct mtk_base_afe *afe, 1980 1412 int dai_id, unsigned int rate) 1981 1413 { ··· 2097 1759 return 0; 2098 1760 } 2099 1761 2100 - static int mtk_dai_etdm_mclk_configure(struct mtk_base_afe *afe, int dai_id) 2101 - { 2102 - struct mt8188_afe_private *afe_priv = afe->platform_priv; 2103 - struct mtk_dai_etdm_priv *etdm_data; 2104 - struct etdm_con_reg etdm_reg; 2105 - int clk_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id); 2106 - int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 2107 - int apll_clk_id; 2108 - int apll; 2109 - int ret; 2110 - 2111 - if (clk_id < 0 || clkdiv_id < 0) 2112 - return -EINVAL; 2113 - 2114 - if (!is_valid_etdm_dai(dai_id)) 2115 - return -EINVAL; 2116 - etdm_data = afe_priv->dai_priv[dai_id]; 2117 - 2118 - ret = get_etdm_reg(dai_id, &etdm_reg); 2119 - if (ret < 0) 2120 - return ret; 2121 - 2122 - if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 2123 - regmap_set_bits(afe->regmap, etdm_reg.con1, 2124 - ETDM_CON1_MCLK_OUTPUT); 2125 - else 2126 - regmap_clear_bits(afe->regmap, etdm_reg.con1, 2127 - ETDM_CON1_MCLK_OUTPUT); 2128 - 2129 - if (etdm_data->mclk_freq) { 2130 - apll = etdm_data->mclk_apll; 2131 - apll_clk_id = mt8188_afe_get_mclk_source_clk_id(apll); 2132 - if (apll_clk_id < 0) 2133 - return apll_clk_id; 2134 - 2135 - /* select apll */ 2136 - ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[clk_id], 2137 - afe_priv->clk[apll_clk_id]); 2138 - if (ret) 2139 - return ret; 2140 - 2141 - /* set rate */ 2142 - ret = mt8188_afe_set_clk_rate(afe, afe_priv->clk[clkdiv_id], 2143 - etdm_data->mclk_freq); 2144 - if (ret) 2145 - return ret; 2146 - } else { 2147 - if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 2148 - dev_dbg(afe->dev, "%s mclk freq = 0\n", __func__); 2149 - } 2150 - 2151 - return 0; 2152 - } 2153 - 2154 1762 static int mtk_dai_etdm_configure(struct mtk_base_afe *afe, 2155 1763 unsigned int rate, 2156 1764 unsigned int channels, ··· 2118 1834 return -EINVAL; 2119 1835 etdm_data = afe_priv->dai_priv[dai_id]; 2120 1836 slave_mode = etdm_data->slave_mode; 1837 + etdm_data->rate = rate; 2121 1838 2122 1839 ret = get_etdm_reg(dai_id, &etdm_reg); 2123 1840 if (ret < 0) 2124 1841 return ret; 2125 1842 2126 - dev_dbg(afe->dev, "%s fmt %u data %u lrck %d-%u bck %d, clock %u slv %u\n", 1843 + dev_dbg(afe->dev, "%s fmt %u data %u lrck %d-%u bck %d, slv %u\n", 2127 1844 __func__, etdm_data->format, etdm_data->data_mode, 2128 1845 etdm_data->lrck_inv, etdm_data->lrck_width, etdm_data->bck_inv, 2129 - etdm_data->clock_mode, etdm_data->slave_mode); 1846 + etdm_data->slave_mode); 2130 1847 dev_dbg(afe->dev, "%s rate %u channels %u bitwidth %u, id %d\n", 2131 1848 __func__, rate, channels, bit_width, dai_id); 2132 1849 ··· 2194 1909 if (!is_valid_etdm_dai(mst_dai_id)) 2195 1910 return -EINVAL; 2196 1911 2197 - ret = mtk_dai_etdm_mclk_configure(afe, mst_dai_id); 2198 - if (ret) 2199 - return ret; 1912 + mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1913 + if (mst_etdm_data->slots) 1914 + channels = mst_etdm_data->slots; 2200 1915 2201 1916 ret = mtk_dai_etdm_configure(afe, rate, channels, 2202 1917 bit_width, mst_dai_id); 2203 1918 if (ret) 2204 1919 return ret; 2205 1920 2206 - mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 2207 1921 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 2208 1922 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 2209 1923 ret = mtk_dai_etdm_configure(afe, rate, channels, ··· 2215 1931 return ret; 2216 1932 } 2217 1933 } else { 2218 - ret = mtk_dai_etdm_mclk_configure(afe, dai->id); 2219 - if (ret) 2220 - return ret; 1934 + if (!is_valid_etdm_dai(dai->id)) 1935 + return -EINVAL; 1936 + mst_etdm_data = afe_priv->dai_priv[dai->id]; 1937 + if (mst_etdm_data->slots) 1938 + channels = mst_etdm_data->slots; 2221 1939 2222 1940 ret = mtk_dai_etdm_configure(afe, rate, channels, 2223 1941 bit_width, dai->id); 2224 1942 if (ret) 2225 1943 return ret; 2226 - } 2227 - 2228 - return 0; 2229 - } 2230 - 2231 - static int mtk_dai_etdm_prepare(struct snd_pcm_substream *substream, 2232 - struct snd_soc_dai *dai) 2233 - { 2234 - struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2235 - struct mt8188_afe_private *afe_priv = afe->platform_priv; 2236 - struct mtk_dai_etdm_priv *mst_etdm_data; 2237 - int mst_dai_id; 2238 - int slv_dai_id; 2239 - int ret; 2240 - int i; 2241 - 2242 - if (!is_valid_etdm_dai(dai->id)) 2243 - return -EINVAL; 2244 - mst_etdm_data = afe_priv->dai_priv[dai->id]; 2245 - 2246 - dev_dbg(afe->dev, "%s(), dai id %d, prepared %d\n", __func__, dai->id, 2247 - mst_etdm_data->is_prepared); 2248 - 2249 - if (mst_etdm_data->is_prepared) 2250 - return 0; 2251 - 2252 - mst_etdm_data->is_prepared = true; 2253 - 2254 - if (is_cowork_mode(dai)) { 2255 - mst_dai_id = get_etdm_cowork_master_id(dai); 2256 - if (!is_valid_etdm_dai(mst_dai_id)) 2257 - return -EINVAL; 2258 - mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 2259 - 2260 - for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 2261 - slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 2262 - ret = mt8188_afe_enable_etdm(afe, slv_dai_id); 2263 - if (ret) { 2264 - dev_dbg(afe->dev, "%s enable %d failed\n", 2265 - __func__, slv_dai_id); 2266 - 2267 - return ret; 2268 - } 2269 - } 2270 - 2271 - ret = mt8188_afe_enable_etdm(afe, mst_dai_id); 2272 - if (ret) { 2273 - dev_dbg(afe->dev, "%s enable %d failed\n", 2274 - __func__, mst_dai_id); 2275 - 2276 - return ret; 2277 - } 2278 - } else { 2279 - ret = mt8188_afe_enable_etdm(afe, dai->id); 2280 - if (ret) { 2281 - dev_dbg(afe->dev, "%s enable %d failed\n", 2282 - __func__, dai->id); 2283 - 2284 - return ret; 2285 - } 2286 1944 } 2287 1945 2288 1946 return 0; ··· 2299 2073 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2300 2074 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2301 2075 struct mtk_dai_etdm_priv *etdm_data; 2076 + int dai_id; 2302 2077 2303 - if (!is_valid_etdm_dai(dai->id)) 2078 + if (is_cowork_mode(dai)) 2079 + dai_id = get_etdm_cowork_master_id(dai); 2080 + else 2081 + dai_id = dai->id; 2082 + 2083 + if (!is_valid_etdm_dai(dai_id)) 2304 2084 return -EINVAL; 2305 - etdm_data = afe_priv->dai_priv[dai->id]; 2085 + etdm_data = afe_priv->dai_priv[dai_id]; 2306 2086 2307 2087 dev_dbg(dai->dev, "%s id %d slot_width %d\n", 2308 2088 __func__, dai->id, slot_width); ··· 2383 2151 return 0; 2384 2152 } 2385 2153 2386 - static int mtk_dai_hdmitx_dptx_startup(struct snd_pcm_substream *substream, 2387 - struct snd_soc_dai *dai) 2388 - { 2389 - struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2390 - struct mt8188_afe_private *afe_priv = afe->platform_priv; 2391 - int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 2392 - 2393 - if (cg_id >= 0) 2394 - mt8188_afe_enable_clk(afe, afe_priv->clk[cg_id]); 2395 - 2396 - mtk_dai_etdm_enable_mclk(afe, dai->id); 2397 - 2398 - return 0; 2399 - } 2400 - 2401 - static void mtk_dai_hdmitx_dptx_shutdown(struct snd_pcm_substream *substream, 2402 - struct snd_soc_dai *dai) 2403 - { 2404 - struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2405 - struct mt8188_afe_private *afe_priv = afe->platform_priv; 2406 - int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 2407 - struct mtk_dai_etdm_priv *etdm_data; 2408 - int ret; 2409 - 2410 - if (!is_valid_etdm_dai(dai->id)) 2411 - return; 2412 - etdm_data = afe_priv->dai_priv[dai->id]; 2413 - 2414 - if (etdm_data->is_prepared) { 2415 - etdm_data->is_prepared = false; 2416 - /* disable etdm_out3 */ 2417 - ret = mt8188_afe_disable_etdm(afe, dai->id); 2418 - if (ret) 2419 - dev_dbg(afe->dev, "%s disable failed\n", __func__); 2420 - 2421 - /* disable dptx interface */ 2422 - if (dai->id == MT8188_AFE_IO_DPTX) 2423 - regmap_clear_bits(afe->regmap, AFE_DPTX_CON, 2424 - AFE_DPTX_CON_ON); 2425 - } 2426 - 2427 - mtk_dai_etdm_disable_mclk(afe, dai->id); 2428 - 2429 - if (cg_id >= 0) 2430 - mt8188_afe_disable_clk(afe, afe_priv->clk[cg_id]); 2431 - } 2432 - 2433 2154 static unsigned int mtk_dai_get_dptx_ch_en(unsigned int channel) 2434 2155 { 2435 2156 switch (channel) { ··· 2450 2265 etdm_data->data_mode = MTK_DAI_ETDM_DATA_MULTI_PIN; 2451 2266 } 2452 2267 2453 - ret = mtk_dai_etdm_mclk_configure(afe, dai->id); 2454 - if (ret) 2455 - return ret; 2456 - 2457 2268 ret = mtk_dai_etdm_configure(afe, rate, channels, width, dai->id); 2458 2269 2459 2270 return ret; 2460 - } 2461 - 2462 - static int mtk_dai_hdmitx_dptx_prepare(struct snd_pcm_substream *substream, 2463 - struct snd_soc_dai *dai) 2464 - { 2465 - struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2466 - struct mt8188_afe_private *afe_priv = afe->platform_priv; 2467 - struct mtk_dai_etdm_priv *etdm_data; 2468 - 2469 - if (!is_valid_etdm_dai(dai->id)) 2470 - return -EINVAL; 2471 - etdm_data = afe_priv->dai_priv[dai->id]; 2472 - 2473 - dev_dbg(afe->dev, "%s(), dai id %d, prepared %d\n", __func__, dai->id, 2474 - etdm_data->is_prepared); 2475 - 2476 - if (etdm_data->is_prepared) 2477 - return 0; 2478 - 2479 - etdm_data->is_prepared = true; 2480 - 2481 - /* enable dptx interface */ 2482 - if (dai->id == MT8188_AFE_IO_DPTX) 2483 - regmap_set_bits(afe->regmap, AFE_DPTX_CON, AFE_DPTX_CON_ON); 2484 - 2485 - /* enable etdm_out3 */ 2486 - return mt8188_afe_enable_etdm(afe, dai->id); 2487 2271 } 2488 2272 2489 2273 static int mtk_dai_hdmitx_dptx_set_sysclk(struct snd_soc_dai *dai, ··· 2476 2322 } 2477 2323 2478 2324 static const struct snd_soc_dai_ops mtk_dai_etdm_ops = { 2479 - .startup = mtk_dai_etdm_startup, 2480 - .shutdown = mtk_dai_etdm_shutdown, 2481 2325 .hw_params = mtk_dai_etdm_hw_params, 2482 - .prepare = mtk_dai_etdm_prepare, 2483 2326 .set_sysclk = mtk_dai_etdm_set_sysclk, 2484 2327 .set_fmt = mtk_dai_etdm_set_fmt, 2485 2328 .set_tdm_slot = mtk_dai_etdm_set_tdm_slot, 2486 2329 }; 2487 2330 2488 2331 static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops = { 2489 - .startup = mtk_dai_hdmitx_dptx_startup, 2490 - .shutdown = mtk_dai_hdmitx_dptx_shutdown, 2491 2332 .hw_params = mtk_dai_hdmitx_dptx_hw_params, 2492 - .prepare = mtk_dai_hdmitx_dptx_prepare, 2493 2333 .set_sysclk = mtk_dai_hdmitx_dptx_set_sysclk, 2494 2334 .set_fmt = mtk_dai_etdm_set_fmt, 2495 2335 };

+2

sound/soc/mediatek/mt8188/mt8188-reg.h

··· 3007 3007 #define ETDM_CON0_SLAVE_MODE BIT(5) 3008 3008 #define ETDM_CON0_SYNC_MODE BIT(1) 3009 3009 #define ETDM_CON0_EN BIT(0) 3010 + #define ETDM_CON0_EN_SHIFT 0 3010 3011 3011 3012 #define ETDM_OUT_CON0_RELATCH_DOMAIN_MASK GENMASK(29, 28) 3012 3013 ··· 3109 3108 #define AFE_DPTX_CON_CH_NUM_8CH (0x1 << 1) 3110 3109 #define AFE_DPTX_CON_CH_NUM_MASK BIT(1) 3111 3110 #define AFE_DPTX_CON_ON BIT(0) 3111 + #define AFE_DPTX_CON_ON_SHIFT 0 3112 3112 3113 3113 /* AFE_ADDA_DL_SRC2_CON0 */ 3114 3114 #define DL_2_INPUT_MODE_CTL_MASK GENMASK(31, 28)

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