Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
KVM: arm64: GICv2: Handle deactivation via GICV_DIR traps
Add the plumbing of GICv2 interrupt deactivation via GICV_DIR.
This requires adding a new device so that we can easily decode
the DIR address.
The deactivation itself is very similar to the GICv3 version.
Tested-by: Fuad Tabba <tabba@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Tested-by: Mark Brown <broonie@kernel.org>
Link: https://msgid.link/20251120172540.2267180-39-maz@kernel.org
Signed-off-by: Oliver Upton <oupton@kernel.org>
authored by
Marc Zyngier
and committed by
Oliver Upton
255de897
281c6c06
+112
+24
arch/arm64/kvm/vgic/vgic-mmio-v2.c
+24
arch/arm64/kvm/vgic/vgic-mmio-v2.c
···
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vgic_set_vmcr(vcpu, &vmcr);
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}
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static void vgic_mmio_write_dir(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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if (kvm_vgic_global_state.type == VGIC_V2)
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vgic_v2_deactivate(vcpu, val);
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else
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vgic_v3_deactivate(vcpu, val);
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}
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static unsigned long vgic_mmio_read_apr(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
···
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REGISTER_DESC_WITH_LENGTH(GIC_CPU_IDENT,
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vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH_UACCESS(GIC_CPU_DEACTIVATE,
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vgic_mmio_read_raz, vgic_mmio_write_dir,
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vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi,
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4, VGIC_ACCESS_32bit),
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};
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unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev)
···
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kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
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return SZ_4K;
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}
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+
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unsigned int vgic_v2_init_cpuif_iodev(struct vgic_io_device *dev)
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{
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dev->regions = vgic_v2_cpu_registers;
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dev->nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers);
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kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
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return KVM_VGIC_V2_CPU_SIZE;
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}
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int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
+1
arch/arm64/kvm/vgic/vgic-mmio.h
+1
arch/arm64/kvm/vgic/vgic-mmio.h
+85
arch/arm64/kvm/vgic/vgic-v2.c
+85
arch/arm64/kvm/vgic/vgic-v2.c
···
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#include <kvm/arm_vgic.h>
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#include <asm/kvm_mmu.h>
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#include "vgic-mmio.h"
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#include "vgic.h"
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static inline void vgic_v2_write_lr(int lr, u32 val)
···
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}
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cpuif->used_lrs = 0;
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}
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void vgic_v2_deactivate(struct kvm_vcpu *vcpu, u32 val)
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{
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struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
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struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
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struct kvm_vcpu *target_vcpu = NULL;
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bool mmio = false;
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struct vgic_irq *irq;
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unsigned long flags;
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u64 lr = 0;
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u8 cpuid;
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/* Snapshot CPUID, and remove it from the INTID */
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cpuid = FIELD_GET(GENMASK_ULL(12, 10), val);
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val &= ~GENMASK_ULL(12, 10);
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+
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/* We only deal with DIR when EOIMode==1 */
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if (!(cpuif->vgic_vmcr & GICH_VMCR_EOI_MODE_MASK))
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return;
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/* Make sure we're in the same context as LR handling */
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local_irq_save(flags);
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irq = vgic_get_vcpu_irq(vcpu, val);
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if (WARN_ON_ONCE(!irq))
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goto out;
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/* See the corresponding v3 code for the rationale */
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scoped_guard(raw_spinlock, &irq->irq_lock) {
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target_vcpu = irq->vcpu;
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/* Not on any ap_list? */
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if (!target_vcpu)
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goto put;
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+
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/*
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* Urgh. We're deactivating something that we cannot
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* observe yet... Big hammer time.
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*/
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if (irq->on_lr) {
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mmio = true;
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goto put;
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}
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/* SGI: check that the cpuid matches */
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if (val < VGIC_NR_SGIS && irq->active_source != cpuid) {
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target_vcpu = NULL;
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goto put;
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}
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/* (with a Dalek voice) DEACTIVATE!!!! */
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lr = vgic_v2_compute_lr(vcpu, irq) & ~GICH_LR_ACTIVE_BIT;
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}
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if (lr & GICH_LR_HW)
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writel_relaxed(FIELD_GET(GICH_LR_PHYSID_CPUID, lr),
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kvm_vgic_global_state.gicc_base + GIC_CPU_DEACTIVATE);
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vgic_v2_fold_lr(vcpu, lr);
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put:
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vgic_put_irq(vcpu->kvm, irq);
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out:
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local_irq_restore(flags);
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if (mmio)
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vgic_mmio_write_cactive(vcpu, (val / 32) * 4, 4, BIT(val % 32));
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/* Force the ap_list to be pruned */
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if (target_vcpu)
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kvm_make_request(KVM_REQ_VGIC_PROCESS_UPDATE, target_vcpu);
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}
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static u32 vgic_v2_compute_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq)
···
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int vgic_v2_map_resources(struct kvm *kvm)
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{
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struct vgic_dist *dist = &kvm->arch.vgic;
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unsigned int len;
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int ret = 0;
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if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
···
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kvm_err("Unable to initialize VGIC dynamic data structures\n");
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return ret;
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}
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+
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len = vgic_v2_init_cpuif_iodev(&dist->cpuif_iodev);
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dist->cpuif_iodev.base_addr = dist->vgic_cpu_base;
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dist->cpuif_iodev.iodev_type = IODEV_CPUIF;
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dist->cpuif_iodev.redist_vcpu = NULL;
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ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist->vgic_cpu_base,
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len, &dist->cpuif_iodev.dev);
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if (ret)
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return ret;
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if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
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ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
+1
arch/arm64/kvm/vgic/vgic.h
+1
arch/arm64/kvm/vgic/vgic.h
···
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void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
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void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
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void vgic_v2_deactivate(struct kvm_vcpu *vcpu, u32 val);
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void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
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void vgic_v2_configure_hcr(struct kvm_vcpu *vcpu, struct ap_list_summary *als);
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int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);