Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull radeon and minor nouveau fixes from Dave Airlie:
"Just a radeon pull from Alex, fixes a few regressions since 3.7 and
reworks some of the reset handling, and two minor nouveau fixes I
found on the list, Ben will be back next week to take care of the
couple of larger nouveau patches that I see outstanding."
* 'drm-next' of git://people.freedesktop.org/~airlied/linux:
drm/nouveau: fix init with agpgart-uninorth
drm: nouveau: Fix build warning seen if HWMON is undefined
drm/radeon: switch to a finer grained reset for SI (v2)
drm/radeon: switch to a finer grained reset for cayman/TN
drm/radeon: switch to a finer grained reset for evergreen
drm/radeon: switch to a finer grained reset for r6xx/7xx
drm/radeon: add GPU reset flags
drm/radeon: fix typo in evergreen dma fence
drm/radeon: Properly handle DDC probe for DP bridges
drm/radeon: reset dma engine on gpu reset (v2)
drm/radeon: print dma status reg on lockup (v2)
drm/radeon: improve ring debugfs printing
drm/radeon: add debugfs file for dma rings
drm/radeon/r6xx: fix DMA engine for ttm bo transfers
drm/radeon: add connector table for Mac G4 Silver
+416
-102
+1
-1
drivers/gpu/drm/nouveau/nouveau_bo.c
+1
-1
drivers/gpu/drm/nouveau/nouveau_bo.c
+2
-2
drivers/gpu/drm/nouveau/nouveau_pm.c
+2
-2
drivers/gpu/drm/nouveau/nouveau_pm.c
···
698
698
nouveau_hwmon_init(struct drm_device *dev)
699
699
{
700
700
struct nouveau_pm *pm = nouveau_pm(dev);
701
-
struct nouveau_drm *drm = nouveau_drm(dev);
702
-
struct nouveau_therm *therm = nouveau_therm(drm->device);
703
701
704
702
#if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE))
703
+
struct nouveau_drm *drm = nouveau_drm(dev);
704
+
struct nouveau_therm *therm = nouveau_therm(drm->device);
705
705
struct device *hwmon_dev;
706
706
int ret = 0;
707
707
+66
-20
drivers/gpu/drm/radeon/evergreen.c
+66
-20
drivers/gpu/drm/radeon/evergreen.c
···
2306
2306
return radeon_ring_test_lockup(rdev, ring);
2307
2307
}
2308
2308
2309
-
static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2309
+
static void evergreen_gpu_soft_reset_gfx(struct radeon_device *rdev)
2310
2310
{
2311
-
struct evergreen_mc_save save;
2312
2311
u32 grbm_reset = 0;
2313
2312
2314
2313
if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2315
-
return 0;
2314
+
return;
2316
2315
2317
-
dev_info(rdev->dev, "GPU softreset \n");
2318
-
dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2316
+
dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
2319
2317
RREG32(GRBM_STATUS));
2320
-
dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2318
+
dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
2321
2319
RREG32(GRBM_STATUS_SE0));
2322
-
dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2320
+
dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
2323
2321
RREG32(GRBM_STATUS_SE1));
2324
-
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2322
+
dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
2325
2323
RREG32(SRBM_STATUS));
2326
2324
dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2327
2325
RREG32(CP_STALLED_STAT1));
···
2329
2331
RREG32(CP_BUSY_STAT));
2330
2332
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
2331
2333
RREG32(CP_STAT));
2332
-
evergreen_mc_stop(rdev, &save);
2333
-
if (evergreen_mc_wait_for_idle(rdev)) {
2334
-
dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2335
-
}
2334
+
2336
2335
/* Disable CP parsing/prefetching */
2337
2336
WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2338
2337
···
2353
2358
udelay(50);
2354
2359
WREG32(GRBM_SOFT_RESET, 0);
2355
2360
(void)RREG32(GRBM_SOFT_RESET);
2356
-
/* Wait a little for things to settle down */
2357
-
udelay(50);
2358
-
dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2361
+
2362
+
dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
2359
2363
RREG32(GRBM_STATUS));
2360
-
dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2364
+
dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
2361
2365
RREG32(GRBM_STATUS_SE0));
2362
-
dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2366
+
dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
2363
2367
RREG32(GRBM_STATUS_SE1));
2364
-
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2368
+
dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
2365
2369
RREG32(SRBM_STATUS));
2366
2370
dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2367
2371
RREG32(CP_STALLED_STAT1));
···
2370
2376
RREG32(CP_BUSY_STAT));
2371
2377
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
2372
2378
RREG32(CP_STAT));
2379
+
}
2380
+
2381
+
static void evergreen_gpu_soft_reset_dma(struct radeon_device *rdev)
2382
+
{
2383
+
u32 tmp;
2384
+
2385
+
if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
2386
+
return;
2387
+
2388
+
dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
2389
+
RREG32(DMA_STATUS_REG));
2390
+
2391
+
/* Disable DMA */
2392
+
tmp = RREG32(DMA_RB_CNTL);
2393
+
tmp &= ~DMA_RB_ENABLE;
2394
+
WREG32(DMA_RB_CNTL, tmp);
2395
+
2396
+
/* Reset dma */
2397
+
WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2398
+
RREG32(SRBM_SOFT_RESET);
2399
+
udelay(50);
2400
+
WREG32(SRBM_SOFT_RESET, 0);
2401
+
2402
+
dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
2403
+
RREG32(DMA_STATUS_REG));
2404
+
}
2405
+
2406
+
static int evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2407
+
{
2408
+
struct evergreen_mc_save save;
2409
+
2410
+
if (reset_mask == 0)
2411
+
return 0;
2412
+
2413
+
dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2414
+
2415
+
evergreen_mc_stop(rdev, &save);
2416
+
if (evergreen_mc_wait_for_idle(rdev)) {
2417
+
dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2418
+
}
2419
+
2420
+
if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
2421
+
evergreen_gpu_soft_reset_gfx(rdev);
2422
+
2423
+
if (reset_mask & RADEON_RESET_DMA)
2424
+
evergreen_gpu_soft_reset_dma(rdev);
2425
+
2426
+
/* Wait a little for things to settle down */
2427
+
udelay(50);
2428
+
2373
2429
evergreen_mc_resume(rdev, &save);
2374
2430
return 0;
2375
2431
}
2376
2432
2377
2433
int evergreen_asic_reset(struct radeon_device *rdev)
2378
2434
{
2379
-
return evergreen_gpu_soft_reset(rdev);
2435
+
return evergreen_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
2436
+
RADEON_RESET_COMPUTE |
2437
+
RADEON_RESET_DMA));
2380
2438
}
2381
2439
2382
2440
/* Interrupts */
···
3261
3215
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
3262
3216
/* flush HDP */
3263
3217
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
3264
-
radeon_ring_write(ring, (0xf << 16) | HDP_MEM_COHERENCY_FLUSH_CNTL);
3218
+
radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
3265
3219
radeon_ring_write(ring, 1);
3266
3220
}
3267
3221
+13
-1
drivers/gpu/drm/radeon/evergreend.h
+13
-1
drivers/gpu/drm/radeon/evergreend.h
···
742
742
#define SOFT_RESET_ROM (1 << 14)
743
743
#define SOFT_RESET_SEM (1 << 15)
744
744
#define SOFT_RESET_VMC (1 << 17)
745
+
#define SOFT_RESET_DMA (1 << 20)
745
746
#define SOFT_RESET_TST (1 << 21)
746
-
#define SOFT_RESET_REGBB (1 << 22)
747
+
#define SOFT_RESET_REGBB (1 << 22)
747
748
#define SOFT_RESET_ORB (1 << 23)
748
749
749
750
/* display watermarks */
···
2027
2026
#define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358
2028
2027
/* cayman packet3 addition */
2029
2028
#define CAYMAN_PACKET3_DEALLOC_STATE 0x14
2029
+
2030
+
/* DMA regs common on r6xx/r7xx/evergreen/ni */
2031
+
#define DMA_RB_CNTL 0xd000
2032
+
# define DMA_RB_ENABLE (1 << 0)
2033
+
# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
2034
+
# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
2035
+
# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
2036
+
# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
2037
+
# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
2038
+
#define DMA_STATUS_REG 0xd034
2039
+
# define DMA_IDLE (1 << 0)
2030
2040
2031
2041
#endif
+79
-27
drivers/gpu/drm/radeon/ni.c
+79
-27
drivers/gpu/drm/radeon/ni.c
···
1306
1306
radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
1307
1307
}
1308
1308
1309
-
static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1309
+
static void cayman_gpu_soft_reset_gfx(struct radeon_device *rdev)
1310
1310
{
1311
-
struct evergreen_mc_save save;
1312
1311
u32 grbm_reset = 0;
1313
1312
1314
1313
if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1315
-
return 0;
1314
+
return;
1316
1315
1317
-
dev_info(rdev->dev, "GPU softreset \n");
1318
-
dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1316
+
dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
1319
1317
RREG32(GRBM_STATUS));
1320
-
dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1318
+
dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
1321
1319
RREG32(GRBM_STATUS_SE0));
1322
-
dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1320
+
dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
1323
1321
RREG32(GRBM_STATUS_SE1));
1324
-
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1322
+
dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
1325
1323
RREG32(SRBM_STATUS));
1326
1324
dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1327
1325
RREG32(CP_STALLED_STAT1));
···
1329
1331
RREG32(CP_BUSY_STAT));
1330
1332
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1331
1333
RREG32(CP_STAT));
1332
-
dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1333
-
RREG32(0x14F8));
1334
-
dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1335
-
RREG32(0x14D8));
1336
-
dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1337
-
RREG32(0x14FC));
1338
-
dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1339
-
RREG32(0x14DC));
1340
1334
1341
-
evergreen_mc_stop(rdev, &save);
1342
-
if (evergreen_mc_wait_for_idle(rdev)) {
1343
-
dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1344
-
}
1345
1335
/* Disable CP parsing/prefetching */
1346
1336
WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1347
1337
···
1354
1368
udelay(50);
1355
1369
WREG32(GRBM_SOFT_RESET, 0);
1356
1370
(void)RREG32(GRBM_SOFT_RESET);
1357
-
/* Wait a little for things to settle down */
1358
-
udelay(50);
1359
1371
1360
-
dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1372
+
dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
1361
1373
RREG32(GRBM_STATUS));
1362
-
dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1374
+
dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
1363
1375
RREG32(GRBM_STATUS_SE0));
1364
-
dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1376
+
dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
1365
1377
RREG32(GRBM_STATUS_SE1));
1366
-
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1378
+
dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
1367
1379
RREG32(SRBM_STATUS));
1368
1380
dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1369
1381
RREG32(CP_STALLED_STAT1));
···
1371
1387
RREG32(CP_BUSY_STAT));
1372
1388
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1373
1389
RREG32(CP_STAT));
1390
+
1391
+
}
1392
+
1393
+
static void cayman_gpu_soft_reset_dma(struct radeon_device *rdev)
1394
+
{
1395
+
u32 tmp;
1396
+
1397
+
if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
1398
+
return;
1399
+
1400
+
dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1401
+
RREG32(DMA_STATUS_REG));
1402
+
1403
+
/* dma0 */
1404
+
tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1405
+
tmp &= ~DMA_RB_ENABLE;
1406
+
WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1407
+
1408
+
/* dma1 */
1409
+
tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1410
+
tmp &= ~DMA_RB_ENABLE;
1411
+
WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1412
+
1413
+
/* Reset dma */
1414
+
WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
1415
+
RREG32(SRBM_SOFT_RESET);
1416
+
udelay(50);
1417
+
WREG32(SRBM_SOFT_RESET, 0);
1418
+
1419
+
dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1420
+
RREG32(DMA_STATUS_REG));
1421
+
1422
+
}
1423
+
1424
+
static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1425
+
{
1426
+
struct evergreen_mc_save save;
1427
+
1428
+
if (reset_mask == 0)
1429
+
return 0;
1430
+
1431
+
dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1432
+
1433
+
dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1434
+
RREG32(0x14F8));
1435
+
dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1436
+
RREG32(0x14D8));
1437
+
dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1438
+
RREG32(0x14FC));
1439
+
dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1440
+
RREG32(0x14DC));
1441
+
1442
+
evergreen_mc_stop(rdev, &save);
1443
+
if (evergreen_mc_wait_for_idle(rdev)) {
1444
+
dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1445
+
}
1446
+
1447
+
if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
1448
+
cayman_gpu_soft_reset_gfx(rdev);
1449
+
1450
+
if (reset_mask & RADEON_RESET_DMA)
1451
+
cayman_gpu_soft_reset_dma(rdev);
1452
+
1453
+
/* Wait a little for things to settle down */
1454
+
udelay(50);
1455
+
1374
1456
evergreen_mc_resume(rdev, &save);
1375
1457
return 0;
1376
1458
}
1377
1459
1378
1460
int cayman_asic_reset(struct radeon_device *rdev)
1379
1461
{
1380
-
return cayman_gpu_soft_reset(rdev);
1462
+
return cayman_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
1463
+
RADEON_RESET_COMPUTE |
1464
+
RADEON_RESET_DMA));
1381
1465
}
1382
1466
1383
1467
/**
+1
-2
drivers/gpu/drm/radeon/nid.h
+1
-2
drivers/gpu/drm/radeon/nid.h
···
65
65
#define SOFT_RESET_VMC (1 << 17)
66
66
#define SOFT_RESET_DMA (1 << 20)
67
67
#define SOFT_RESET_TST (1 << 21)
68
-
#define SOFT_RESET_REGBB (1 << 22)
68
+
#define SOFT_RESET_REGBB (1 << 22)
69
69
#define SOFT_RESET_ORB (1 << 23)
70
70
71
71
#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
···
675
675
#define DMA_PACKET_NOP 0xf
676
676
677
677
#endif
678
-
+70
-19
drivers/gpu/drm/radeon/r600.c
+70
-19
drivers/gpu/drm/radeon/r600.c
···
1258
1258
* reset, it's up to the caller to determine if the GPU needs one. We
1259
1259
* might add an helper function to check that.
1260
1260
*/
1261
-
static int r600_gpu_soft_reset(struct radeon_device *rdev)
1261
+
static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev)
1262
1262
{
1263
-
struct rv515_mc_save save;
1264
1263
u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1265
1264
S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1266
1265
S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
···
1279
1280
u32 tmp;
1280
1281
1281
1282
if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1282
-
return 0;
1283
+
return;
1283
1284
1284
-
dev_info(rdev->dev, "GPU softreset \n");
1285
-
dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1285
+
dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
1286
1286
RREG32(R_008010_GRBM_STATUS));
1287
-
dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1287
+
dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
1288
1288
RREG32(R_008014_GRBM_STATUS2));
1289
-
dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1289
+
dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
1290
1290
RREG32(R_000E50_SRBM_STATUS));
1291
1291
dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1292
1292
RREG32(CP_STALLED_STAT1));
···
1295
1297
RREG32(CP_BUSY_STAT));
1296
1298
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1297
1299
RREG32(CP_STAT));
1298
-
rv515_mc_stop(rdev, &save);
1299
-
if (r600_mc_wait_for_idle(rdev)) {
1300
-
dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1301
-
}
1300
+
1302
1301
/* Disable CP parsing/prefetching */
1303
1302
WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1303
+
1304
1304
/* Check if any of the rendering block is busy and reset it */
1305
1305
if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1306
1306
(RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
···
1328
1332
RREG32(R_008020_GRBM_SOFT_RESET);
1329
1333
mdelay(15);
1330
1334
WREG32(R_008020_GRBM_SOFT_RESET, 0);
1331
-
/* Wait a little for things to settle down */
1332
-
mdelay(1);
1333
-
dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1335
+
1336
+
dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
1334
1337
RREG32(R_008010_GRBM_STATUS));
1335
-
dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1338
+
dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
1336
1339
RREG32(R_008014_GRBM_STATUS2));
1337
-
dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1340
+
dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
1338
1341
RREG32(R_000E50_SRBM_STATUS));
1339
1342
dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1340
1343
RREG32(CP_STALLED_STAT1));
···
1343
1348
RREG32(CP_BUSY_STAT));
1344
1349
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1345
1350
RREG32(CP_STAT));
1351
+
1352
+
}
1353
+
1354
+
static void r600_gpu_soft_reset_dma(struct radeon_device *rdev)
1355
+
{
1356
+
u32 tmp;
1357
+
1358
+
if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
1359
+
return;
1360
+
1361
+
dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1362
+
RREG32(DMA_STATUS_REG));
1363
+
1364
+
/* Disable DMA */
1365
+
tmp = RREG32(DMA_RB_CNTL);
1366
+
tmp &= ~DMA_RB_ENABLE;
1367
+
WREG32(DMA_RB_CNTL, tmp);
1368
+
1369
+
/* Reset dma */
1370
+
if (rdev->family >= CHIP_RV770)
1371
+
WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
1372
+
else
1373
+
WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
1374
+
RREG32(SRBM_SOFT_RESET);
1375
+
udelay(50);
1376
+
WREG32(SRBM_SOFT_RESET, 0);
1377
+
1378
+
dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1379
+
RREG32(DMA_STATUS_REG));
1380
+
}
1381
+
1382
+
static int r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1383
+
{
1384
+
struct rv515_mc_save save;
1385
+
1386
+
if (reset_mask == 0)
1387
+
return 0;
1388
+
1389
+
dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1390
+
1391
+
rv515_mc_stop(rdev, &save);
1392
+
if (r600_mc_wait_for_idle(rdev)) {
1393
+
dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1394
+
}
1395
+
1396
+
if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
1397
+
r600_gpu_soft_reset_gfx(rdev);
1398
+
1399
+
if (reset_mask & RADEON_RESET_DMA)
1400
+
r600_gpu_soft_reset_dma(rdev);
1401
+
1402
+
/* Wait a little for things to settle down */
1403
+
mdelay(1);
1404
+
1346
1405
rv515_mc_resume(rdev, &save);
1347
1406
return 0;
1348
1407
}
···
1444
1395
1445
1396
int r600_asic_reset(struct radeon_device *rdev)
1446
1397
{
1447
-
return r600_gpu_soft_reset(rdev);
1398
+
return r600_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
1399
+
RADEON_RESET_COMPUTE |
1400
+
RADEON_RESET_DMA));
1448
1401
}
1449
1402
1450
1403
u32 r6xx_remap_render_backend(struct radeon_device *rdev,
···
2687
2636
2688
2637
for (i = 0; i < num_loops; i++) {
2689
2638
cur_size_in_dw = size_in_dw;
2690
-
if (cur_size_in_dw > 0xFFFF)
2691
-
cur_size_in_dw = 0xFFFF;
2639
+
if (cur_size_in_dw > 0xFFFE)
2640
+
cur_size_in_dw = 0xFFFE;
2692
2641
size_in_dw -= cur_size_in_dw;
2693
2642
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
2694
2643
radeon_ring_write(ring, dst_offset & 0xfffffffc);
+5
drivers/gpu/drm/radeon/radeon.h
+5
drivers/gpu/drm/radeon/radeon.h
···
132
132
#define RADEON_VA_RESERVED_SIZE (8 << 20)
133
133
#define RADEON_IB_VM_MAX_SIZE (64 << 10)
134
134
135
+
/* reset flags */
136
+
#define RADEON_RESET_GFX (1 << 0)
137
+
#define RADEON_RESET_COMPUTE (1 << 1)
138
+
#define RADEON_RESET_DMA (1 << 2)
139
+
135
140
/*
136
141
* Errata workarounds.
137
142
*/
+51
drivers/gpu/drm/radeon/radeon_combios.c
+51
drivers/gpu/drm/radeon/radeon_combios.c
···
1548
1548
of_machine_is_compatible("PowerBook6,7")) {
1549
1549
/* ibook */
1550
1550
rdev->mode_info.connector_table = CT_IBOOK;
1551
+
} else if (of_machine_is_compatible("PowerMac3,5")) {
1552
+
/* PowerMac G4 Silver radeon 7500 */
1553
+
rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1551
1554
} else if (of_machine_is_compatible("PowerMac4,4")) {
1552
1555
/* emac */
1553
1556
rdev->mode_info.connector_table = CT_EMAC;
···
2210
2207
2),
2211
2208
ATOM_DEVICE_TV1_SUPPORT);
2212
2209
radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2210
+
DRM_MODE_CONNECTOR_SVIDEO,
2211
+
&ddc_i2c,
2212
+
CONNECTOR_OBJECT_ID_SVIDEO,
2213
+
&hpd);
2214
+
break;
2215
+
case CT_MAC_G4_SILVER:
2216
+
DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2217
+
rdev->mode_info.connector_table);
2218
+
/* DVI-I - tv dac, int tmds */
2219
+
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2220
+
hpd.hpd = RADEON_HPD_1; /* ??? */
2221
+
radeon_add_legacy_encoder(dev,
2222
+
radeon_get_encoder_enum(dev,
2223
+
ATOM_DEVICE_DFP1_SUPPORT,
2224
+
0),
2225
+
ATOM_DEVICE_DFP1_SUPPORT);
2226
+
radeon_add_legacy_encoder(dev,
2227
+
radeon_get_encoder_enum(dev,
2228
+
ATOM_DEVICE_CRT2_SUPPORT,
2229
+
2),
2230
+
ATOM_DEVICE_CRT2_SUPPORT);
2231
+
radeon_add_legacy_connector(dev, 0,
2232
+
ATOM_DEVICE_DFP1_SUPPORT |
2233
+
ATOM_DEVICE_CRT2_SUPPORT,
2234
+
DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2235
+
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2236
+
&hpd);
2237
+
/* VGA - primary dac */
2238
+
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2239
+
hpd.hpd = RADEON_HPD_NONE;
2240
+
radeon_add_legacy_encoder(dev,
2241
+
radeon_get_encoder_enum(dev,
2242
+
ATOM_DEVICE_CRT1_SUPPORT,
2243
+
1),
2244
+
ATOM_DEVICE_CRT1_SUPPORT);
2245
+
radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2246
+
DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2247
+
CONNECTOR_OBJECT_ID_VGA,
2248
+
&hpd);
2249
+
/* TV - TV DAC */
2250
+
ddc_i2c.valid = false;
2251
+
hpd.hpd = RADEON_HPD_NONE;
2252
+
radeon_add_legacy_encoder(dev,
2253
+
radeon_get_encoder_enum(dev,
2254
+
ATOM_DEVICE_TV1_SUPPORT,
2255
+
2),
2256
+
ATOM_DEVICE_TV1_SUPPORT);
2257
+
radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2213
2258
DRM_MODE_CONNECTOR_SVIDEO,
2214
2259
&ddc_i2c,
2215
2260
CONNECTOR_OBJECT_ID_SVIDEO,
+6
-4
drivers/gpu/drm/radeon/radeon_connectors.c
+6
-4
drivers/gpu/drm/radeon/radeon_connectors.c
···
741
741
ret = connector_status_disconnected;
742
742
743
743
if (radeon_connector->ddc_bus)
744
-
dret = radeon_ddc_probe(radeon_connector);
744
+
dret = radeon_ddc_probe(radeon_connector, false);
745
745
if (dret) {
746
746
radeon_connector->detected_by_load = false;
747
747
if (radeon_connector->edid) {
···
947
947
return connector->status;
948
948
949
949
if (radeon_connector->ddc_bus)
950
-
dret = radeon_ddc_probe(radeon_connector);
950
+
dret = radeon_ddc_probe(radeon_connector, false);
951
951
if (dret) {
952
952
radeon_connector->detected_by_load = false;
953
953
if (radeon_connector->edid) {
···
1401
1401
if (encoder) {
1402
1402
/* setup ddc on the bridge */
1403
1403
radeon_atom_ext_encoder_setup_ddc(encoder);
1404
-
if (radeon_ddc_probe(radeon_connector)) /* try DDC */
1404
+
/* bridge chips are always aux */
1405
+
if (radeon_ddc_probe(radeon_connector, true)) /* try DDC */
1405
1406
ret = connector_status_connected;
1406
1407
else if (radeon_connector->dac_load_detect) { /* try load detection */
1407
1408
struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
···
1420
1419
if (radeon_dp_getdpcd(radeon_connector))
1421
1420
ret = connector_status_connected;
1422
1421
} else {
1423
-
if (radeon_ddc_probe(radeon_connector))
1422
+
/* try non-aux ddc (DP to DVI/HMDI/etc. adapter) */
1423
+
if (radeon_ddc_probe(radeon_connector, false))
1424
1424
ret = connector_status_connected;
1425
1425
}
1426
1426
}
+9
-4
drivers/gpu/drm/radeon/radeon_display.c
+9
-4
drivers/gpu/drm/radeon/radeon_display.c
···
699
699
if (radeon_connector->router.ddc_valid)
700
700
radeon_router_select_ddc_port(radeon_connector);
701
701
702
-
if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
703
-
(radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) ||
704
-
(radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
705
-
ENCODER_OBJECT_ID_NONE)) {
702
+
if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
703
+
ENCODER_OBJECT_ID_NONE) {
704
+
struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
705
+
706
+
if (dig->dp_i2c_bus)
707
+
radeon_connector->edid = drm_get_edid(&radeon_connector->base,
708
+
&dig->dp_i2c_bus->adapter);
709
+
} else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
710
+
(radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
706
711
struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
707
712
708
713
if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
+8
-2
drivers/gpu/drm/radeon/radeon_i2c.c
+8
-2
drivers/gpu/drm/radeon/radeon_i2c.c
···
39
39
* radeon_ddc_probe
40
40
*
41
41
*/
42
-
bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
42
+
bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux)
43
43
{
44
44
u8 out = 0x0;
45
45
u8 buf[8];
···
63
63
if (radeon_connector->router.ddc_valid)
64
64
radeon_router_select_ddc_port(radeon_connector);
65
65
66
-
ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
66
+
if (use_aux) {
67
+
struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
68
+
ret = i2c_transfer(&dig->dp_i2c_bus->adapter, msgs, 2);
69
+
} else {
70
+
ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
71
+
}
72
+
67
73
if (ret != 2)
68
74
/* Couldn't find an accessible DDC on this connector */
69
75
return false;
+3
-2
drivers/gpu/drm/radeon/radeon_mode.h
+3
-2
drivers/gpu/drm/radeon/radeon_mode.h
···
209
209
CT_RN50_POWER,
210
210
CT_MAC_X800,
211
211
CT_MAC_G5_9600,
212
-
CT_SAM440EP
212
+
CT_SAM440EP,
213
+
CT_MAC_G4_SILVER
213
214
};
214
215
215
216
enum radeon_dvo_chip {
···
559
558
u8 val);
560
559
extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
561
560
extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
562
-
extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
561
+
extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
563
562
extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
564
563
565
564
extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
+17
-7
drivers/gpu/drm/radeon/radeon_ring.c
+17
-7
drivers/gpu/drm/radeon/radeon_ring.c
···
770
770
int ridx = *(int*)node->info_ent->data;
771
771
struct radeon_ring *ring = &rdev->ring[ridx];
772
772
unsigned count, i, j;
773
+
u32 tmp;
773
774
774
775
radeon_ring_free_size(rdev, ring);
775
776
count = (ring->ring_size / 4) - ring->ring_free_dw;
776
-
seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg));
777
-
seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg));
777
+
tmp = RREG32(ring->wptr_reg) >> ring->ptr_reg_shift;
778
+
seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp);
779
+
tmp = RREG32(ring->rptr_reg) >> ring->ptr_reg_shift;
780
+
seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp);
778
781
if (ring->rptr_save_reg) {
779
782
seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg,
780
783
RREG32(ring->rptr_save_reg));
781
784
}
782
-
seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr);
783
-
seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr);
785
+
seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", ring->wptr, ring->wptr);
786
+
seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n", ring->rptr, ring->rptr);
784
787
seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
785
788
seq_printf(m, "%u dwords in ring\n", count);
786
-
i = ring->rptr;
787
-
for (j = 0; j <= count; j++) {
788
-
seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
789
+
/* print 8 dw before current rptr as often it's the last executed
790
+
* packet that is the root issue
791
+
*/
792
+
i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
793
+
for (j = 0; j <= (count + 32); j++) {
794
+
seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]);
789
795
i = (i + 1) & ring->ptr_mask;
790
796
}
791
797
return 0;
···
800
794
static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
801
795
static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
802
796
static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
797
+
static int radeon_ring_type_dma1_index = R600_RING_TYPE_DMA_INDEX;
798
+
static int radeon_ring_type_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
803
799
804
800
static struct drm_info_list radeon_debugfs_ring_info_list[] = {
805
801
{"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index},
806
802
{"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index},
807
803
{"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index},
804
+
{"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma1_index},
805
+
{"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma2_index},
808
806
};
809
807
810
808
static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
+67
-11
drivers/gpu/drm/radeon/si.c
+67
-11
drivers/gpu/drm/radeon/si.c
···
2126
2126
return radeon_ring_test_lockup(rdev, ring);
2127
2127
}
2128
2128
2129
-
static int si_gpu_soft_reset(struct radeon_device *rdev)
2129
+
static void si_gpu_soft_reset_gfx(struct radeon_device *rdev)
2130
2130
{
2131
-
struct evergreen_mc_save save;
2132
2131
u32 grbm_reset = 0;
2133
2132
2134
2133
if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2135
-
return 0;
2134
+
return;
2136
2135
2137
-
dev_info(rdev->dev, "GPU softreset \n");
2138
2136
dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2139
2137
RREG32(GRBM_STATUS));
2140
2138
dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
···
2143
2145
RREG32(GRBM_STATUS_SE1));
2144
2146
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2145
2147
RREG32(SRBM_STATUS));
2146
-
evergreen_mc_stop(rdev, &save);
2147
-
if (radeon_mc_wait_for_idle(rdev)) {
2148
-
dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2149
-
}
2148
+
2150
2149
/* Disable CP parsing/prefetching */
2151
2150
WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
2152
2151
···
2168
2173
udelay(50);
2169
2174
WREG32(GRBM_SOFT_RESET, 0);
2170
2175
(void)RREG32(GRBM_SOFT_RESET);
2171
-
/* Wait a little for things to settle down */
2172
-
udelay(50);
2176
+
2173
2177
dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2174
2178
RREG32(GRBM_STATUS));
2175
2179
dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
···
2179
2185
RREG32(GRBM_STATUS_SE1));
2180
2186
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2181
2187
RREG32(SRBM_STATUS));
2188
+
}
2189
+
2190
+
static void si_gpu_soft_reset_dma(struct radeon_device *rdev)
2191
+
{
2192
+
u32 tmp;
2193
+
2194
+
if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
2195
+
return;
2196
+
2197
+
dev_info(rdev->dev, " DMA_STATUS_REG = 0x%08X\n",
2198
+
RREG32(DMA_STATUS_REG));
2199
+
2200
+
/* dma0 */
2201
+
tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
2202
+
tmp &= ~DMA_RB_ENABLE;
2203
+
WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
2204
+
2205
+
/* dma1 */
2206
+
tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
2207
+
tmp &= ~DMA_RB_ENABLE;
2208
+
WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
2209
+
2210
+
/* Reset dma */
2211
+
WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
2212
+
RREG32(SRBM_SOFT_RESET);
2213
+
udelay(50);
2214
+
WREG32(SRBM_SOFT_RESET, 0);
2215
+
2216
+
dev_info(rdev->dev, " DMA_STATUS_REG = 0x%08X\n",
2217
+
RREG32(DMA_STATUS_REG));
2218
+
}
2219
+
2220
+
static int si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2221
+
{
2222
+
struct evergreen_mc_save save;
2223
+
2224
+
if (reset_mask == 0)
2225
+
return 0;
2226
+
2227
+
dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2228
+
2229
+
dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
2230
+
RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
2231
+
dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
2232
+
RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
2233
+
2234
+
evergreen_mc_stop(rdev, &save);
2235
+
if (radeon_mc_wait_for_idle(rdev)) {
2236
+
dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2237
+
}
2238
+
2239
+
if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
2240
+
si_gpu_soft_reset_gfx(rdev);
2241
+
2242
+
if (reset_mask & RADEON_RESET_DMA)
2243
+
si_gpu_soft_reset_dma(rdev);
2244
+
2245
+
/* Wait a little for things to settle down */
2246
+
udelay(50);
2247
+
2182
2248
evergreen_mc_resume(rdev, &save);
2183
2249
return 0;
2184
2250
}
2185
2251
2186
2252
int si_asic_reset(struct radeon_device *rdev)
2187
2253
{
2188
-
return si_gpu_soft_reset(rdev);
2254
+
return si_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
2255
+
RADEON_RESET_COMPUTE |
2256
+
RADEON_RESET_DMA));
2189
2257
}
2190
2258
2191
2259
/* MC */
+18
drivers/gpu/drm/radeon/sid.h
+18
drivers/gpu/drm/radeon/sid.h
···
62
62
63
63
#define SRBM_STATUS 0xE50
64
64
65
+
#define SRBM_SOFT_RESET 0x0E60
66
+
#define SOFT_RESET_BIF (1 << 1)
67
+
#define SOFT_RESET_DC (1 << 5)
68
+
#define SOFT_RESET_DMA1 (1 << 6)
69
+
#define SOFT_RESET_GRBM (1 << 8)
70
+
#define SOFT_RESET_HDP (1 << 9)
71
+
#define SOFT_RESET_IH (1 << 10)
72
+
#define SOFT_RESET_MC (1 << 11)
73
+
#define SOFT_RESET_ROM (1 << 14)
74
+
#define SOFT_RESET_SEM (1 << 15)
75
+
#define SOFT_RESET_VMC (1 << 17)
76
+
#define SOFT_RESET_DMA (1 << 20)
77
+
#define SOFT_RESET_TST (1 << 21)
78
+
#define SOFT_RESET_REGBB (1 << 22)
79
+
#define SOFT_RESET_ORB (1 << 23)
80
+
65
81
#define CC_SYS_RB_BACKEND_DISABLE 0xe80
66
82
#define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
67
83
···
1029
1013
# define DATA_SWAP_ENABLE (1 << 3)
1030
1014
# define FENCE_SWAP_ENABLE (1 << 4)
1031
1015
# define CTXEMPTY_INT_ENABLE (1 << 28)
1016
+
#define DMA_STATUS_REG 0xd034
1017
+
# define DMA_IDLE (1 << 0)
1032
1018
#define DMA_TILING_CONFIG 0xd0b8
1033
1019
1034
1020
#define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \