tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support

The CMN PLL in IPQ5018 SoC supplies fixed clocks to XO, sleep, and the
ethernet block.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-3-389a6b30e504@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

George Moussalem and committed by
Bjorn Andersson 25d12630 693a7232

+23 -14
+23 -14
drivers/clk/qcom/ipq-cmn-pll.c
··· 50 50 #include <linux/regmap.h> 51 51 52 52 #include <dt-bindings/clock/qcom,ipq-cmn-pll.h> 53 + #include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h> 53 54 #include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h> 54 55 55 56 #define CMN_PLL_REFCLK_SRC_SELECTION 0x28 ··· 111 110 .fast_io = true, 112 111 }; 113 112 114 - static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { 115 - CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 116 - CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 117 - CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), 118 - CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), 119 - CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), 120 - CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), 121 - CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), 122 - CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), 123 - CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), 113 + static const struct cmn_pll_fixed_output_clk ipq5018_output_clks[] = { 114 + CLK_PLL_OUTPUT(IPQ5018_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 115 + CLK_PLL_OUTPUT(IPQ5018_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 116 + CLK_PLL_OUTPUT(IPQ5018_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL), 124 117 { /* Sentinel */ } 125 118 }; 126 119 ··· 128 133 CLK_PLL_OUTPUT(IPQ5424_ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), 129 134 CLK_PLL_OUTPUT(IPQ5424_ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), 130 135 CLK_PLL_OUTPUT(IPQ5424_ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), 136 + { /* Sentinel */ } 137 + }; 138 + 139 + static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { 140 + CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 141 + CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 142 + CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), 143 + CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), 144 + CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), 145 + CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), 146 + CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), 147 + CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), 148 + CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), 131 149 { /* Sentinel */ } 132 150 }; 133 151 ··· 407 399 */ 408 400 ret = pm_clk_add(dev, "ahb"); 409 401 if (ret) 410 - return dev_err_probe(dev, ret, "Fail to add AHB clock\n"); 402 + return dev_err_probe(dev, ret, "Failed to add AHB clock\n"); 411 403 412 404 ret = pm_clk_add(dev, "sys"); 413 405 if (ret) 414 - return dev_err_probe(dev, ret, "Fail to add SYS clock\n"); 406 + return dev_err_probe(dev, ret, "Failed to add SYS clock\n"); 415 407 416 408 ret = pm_runtime_resume_and_get(dev); 417 409 if (ret) ··· 422 414 pm_runtime_put(dev); 423 415 if (ret) 424 416 return dev_err_probe(dev, ret, 425 - "Fail to register CMN PLL clocks\n"); 417 + "Failed to register CMN PLL clocks\n"); 426 418 427 419 return 0; 428 420 } ··· 447 439 }; 448 440 449 441 static const struct of_device_id ipq_cmn_pll_clk_ids[] = { 450 - { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks }, 442 + { .compatible = "qcom,ipq5018-cmn-pll", .data = &ipq5018_output_clks }, 451 443 { .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks }, 444 + { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks }, 452 445 { } 453 446 }; 454 447 MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids);