drm/msm/dpu: Defer SSPP allocation until CRTC check

+80 -81

2 changed files

expand all

drivers

gpu

drm

msm

disp

dpu1

dpu_crtc.c

dpu_plane.c

+19 -6

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

··· 1321 1321 return false; 1322 1322 } 1323 1323 1324 - static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) 1324 + static int dpu_crtc_assign_planes(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) 1325 1325 { 1326 1326 int total_planes = crtc->dev->mode_config.num_total_plane; 1327 1327 struct drm_atomic_state *state = crtc_state->state; ··· 1333 1333 global_state = dpu_kms_get_global_state(crtc_state->state); 1334 1334 if (IS_ERR(global_state)) 1335 1335 return PTR_ERR(global_state); 1336 - 1337 - dpu_rm_release_all_sspp(global_state, crtc); 1338 1336 1339 1337 if (!crtc_state->enable) 1340 1338 return 0; ··· 1358 1360 done: 1359 1361 kfree(states); 1360 1362 return ret; 1363 + } 1364 + 1365 + static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) 1366 + { 1367 + struct dpu_global_state *global_state; 1368 + 1369 + global_state = dpu_kms_get_global_state(crtc_state->state); 1370 + if (IS_ERR(global_state)) 1371 + return PTR_ERR(global_state); 1372 + 1373 + dpu_rm_release_all_sspp(global_state, crtc); 1374 + 1375 + return dpu_crtc_assign_planes(crtc, crtc_state); 1361 1376 } 1362 1377 1363 1378 #define MAX_CHANNELS_PER_CRTC PIPES_PER_PLANE ··· 1542 1531 return rc; 1543 1532 } 1544 1533 1545 - if (dpu_use_virtual_planes && 1546 - (crtc_state->planes_changed || crtc_state->zpos_changed)) { 1547 - rc = dpu_crtc_reassign_planes(crtc, crtc_state); 1534 + if (crtc_state->planes_changed || crtc_state->zpos_changed) { 1535 + if (dpu_use_virtual_planes) 1536 + rc = dpu_crtc_reassign_planes(crtc, crtc_state); 1537 + else 1538 + rc = dpu_crtc_assign_planes(crtc, crtc_state); 1548 1539 if (rc < 0) 1549 1540 return rc; 1550 1541 }

+61 -75

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

··· 1110 1110 static int dpu_plane_atomic_check(struct drm_plane *plane, 1111 1111 struct drm_atomic_state *state) 1112 1112 { 1113 - struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1114 - plane); 1115 - int ret = 0; 1116 - struct dpu_plane *pdpu = to_dpu_plane(plane); 1117 - struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 1118 - struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1119 - struct dpu_sw_pipe *pipe = &pstate->pipe[0]; 1120 - struct dpu_sw_pipe *r_pipe = &pstate->pipe[1]; 1121 - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0]; 1122 - struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1]; 1123 - const struct drm_crtc_state *crtc_state = NULL; 1124 - uint32_t max_linewidth = dpu_kms->catalog->caps->max_linewidth; 1125 - 1126 - if (new_plane_state->crtc) 1127 - crtc_state = drm_atomic_get_new_crtc_state(state, 1128 - new_plane_state->crtc); 1129 - 1130 - pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); 1131 - 1132 - if (!pipe->sspp) 1133 - return -EINVAL; 1134 - 1135 - ret = dpu_plane_atomic_check_nosspp(plane, new_plane_state, crtc_state); 1136 - if (ret) 1137 - return ret; 1138 - 1139 - if (!new_plane_state->visible) 1140 - return 0; 1141 - 1142 - ret = dpu_plane_split(plane, new_plane_state, crtc_state); 1143 - if (ret) 1144 - return ret; 1145 - 1146 - if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, 1147 - pipe->sspp, 1148 - msm_framebuffer_format(new_plane_state->fb), 1149 - max_linewidth)) { 1150 - DPU_DEBUG_PLANE(pdpu, "invalid " DRM_RECT_FMT " /" DRM_RECT_FMT 1151 - " max_line:%u, can't use split source\n", 1152 - DRM_RECT_ARG(&pipe_cfg->src_rect), 1153 - DRM_RECT_ARG(&r_pipe_cfg->src_rect), 1154 - max_linewidth); 1155 - return -E2BIG; 1156 - } 1157 - 1158 - return dpu_plane_atomic_check_sspp(plane, state, crtc_state); 1159 - } 1160 - 1161 - static int dpu_plane_virtual_atomic_check(struct drm_plane *plane, 1162 - struct drm_atomic_state *state) 1163 - { 1164 1113 struct drm_plane_state *plane_state = 1165 1114 drm_atomic_get_plane_state(state, plane); 1166 1115 struct drm_plane_state *old_plane_state = 1167 1116 drm_atomic_get_old_plane_state(state, plane); 1168 - struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state); 1117 + int ret = 0; 1169 1118 struct drm_crtc_state *crtc_state = NULL; 1170 - int ret, i; 1171 1119 1172 1120 if (IS_ERR(plane_state)) 1173 1121 return PTR_ERR(plane_state); ··· 1128 1180 if (ret) 1129 1181 return ret; 1130 1182 1131 - if (!plane_state->visible) { 1132 - /* 1133 - * resources are freed by dpu_crtc_assign_plane_resources(), 1134 - * but clean them here. 1135 - */ 1136 - for (i = 0; i < PIPES_PER_PLANE; i++) 1137 - pstate->pipe[i].sspp = NULL; 1138 - 1183 + if (!plane_state->visible) 1139 1184 return 0; 1140 - } 1141 - 1142 - ret = dpu_plane_split(plane, plane_state, crtc_state); 1143 - if (ret) 1144 - return ret; 1145 1185 1146 1186 /* 1147 1187 * Force resource reallocation if the format of FB or src/dst have ··· 1144 1208 msm_framebuffer_format(old_plane_state->fb) != 1145 1209 msm_framebuffer_format(plane_state->fb)) 1146 1210 crtc_state->planes_changed = true; 1147 - 1148 1211 return 0; 1149 1212 } 1150 1213 ··· 1190 1255 struct dpu_global_state *global_state, 1191 1256 struct drm_atomic_state *state, 1192 1257 struct drm_plane_state *plane_state, 1258 + const struct drm_crtc_state *crtc_state, 1193 1259 struct drm_plane_state **prev_adjacent_plane_state) 1194 1260 { 1195 - const struct drm_crtc_state *crtc_state = NULL; 1196 1261 struct drm_plane *plane = plane_state->plane; 1197 1262 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1198 1263 struct dpu_rm_sspp_requirements reqs; ··· 1201 1266 struct dpu_sw_pipe_cfg *pipe_cfg; 1202 1267 const struct msm_format *fmt; 1203 1268 int i, ret; 1204 - 1205 - if (plane_state->crtc) 1206 - crtc_state = drm_atomic_get_new_crtc_state(state, 1207 - plane_state->crtc); 1208 1269 1209 1270 pstate = to_dpu_plane_state(plane_state); 1210 1271 for (i = 0; i < STAGES_PER_PLANE; i++) ··· 1212 1281 1213 1282 if (!plane_state->fb) 1214 1283 return -EINVAL; 1284 + 1285 + ret = dpu_plane_split(plane, plane_state, crtc_state); 1286 + if (ret) 1287 + return ret; 1215 1288 1216 1289 fmt = msm_framebuffer_format(plane_state->fb); 1217 1290 reqs.yuv = MSM_FORMAT_IS_YUV(fmt); ··· 1247 1312 return dpu_plane_atomic_check_sspp(plane, state, crtc_state); 1248 1313 } 1249 1314 1315 + static int dpu_plane_assign_resources(struct drm_crtc *crtc, 1316 + struct dpu_global_state *global_state, 1317 + struct drm_atomic_state *state, 1318 + struct drm_plane_state *plane_state, 1319 + const struct drm_crtc_state *crtc_state) 1320 + { 1321 + struct drm_plane *plane = plane_state->plane; 1322 + struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1323 + struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state); 1324 + struct dpu_sw_pipe *pipe = &pstate->pipe[0]; 1325 + struct dpu_sw_pipe *r_pipe = &pstate->pipe[1]; 1326 + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0]; 1327 + struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1]; 1328 + struct dpu_plane *pdpu = to_dpu_plane(plane); 1329 + int ret; 1330 + 1331 + pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); 1332 + if (!pipe->sspp) 1333 + return -EINVAL; 1334 + 1335 + ret = dpu_plane_split(plane, plane_state, crtc_state); 1336 + if (ret) 1337 + return ret; 1338 + 1339 + if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, 1340 + pipe->sspp, 1341 + msm_framebuffer_format(plane_state->fb), 1342 + dpu_kms->catalog->caps->max_linewidth)) { 1343 + DPU_DEBUG_PLANE(pdpu, "invalid " DRM_RECT_FMT " /" DRM_RECT_FMT 1344 + " max_line:%u, can't use split source\n", 1345 + DRM_RECT_ARG(&pipe_cfg->src_rect), 1346 + DRM_RECT_ARG(&r_pipe_cfg->src_rect), 1347 + dpu_kms->catalog->caps->max_linewidth); 1348 + return -E2BIG; 1349 + } 1350 + 1351 + return dpu_plane_atomic_check_sspp(plane, state, crtc_state); 1352 + } 1353 + 1250 1354 int dpu_assign_plane_resources(struct dpu_global_state *global_state, 1251 1355 struct drm_atomic_state *state, 1252 1356 struct drm_crtc *crtc, 1253 1357 struct drm_plane_state **states, 1254 1358 unsigned int num_planes) 1255 1359 { 1256 - unsigned int i; 1257 1360 struct drm_plane_state *prev_adjacent_plane_state[STAGES_PER_PLANE] = { NULL }; 1361 + const struct drm_crtc_state *crtc_state = NULL; 1362 + unsigned int i; 1363 + int ret; 1258 1364 1259 1365 for (i = 0; i < num_planes; i++) { 1260 1366 struct drm_plane_state *plane_state = states[i]; ··· 1304 1328 !plane_state->visible) 1305 1329 continue; 1306 1330 1307 - int ret = dpu_plane_virtual_assign_resources(crtc, global_state, 1331 + if (plane_state->crtc) 1332 + crtc_state = drm_atomic_get_new_crtc_state(state, 1333 + plane_state->crtc); 1334 + 1335 + if (!dpu_use_virtual_planes) 1336 + ret = dpu_plane_assign_resources(crtc, global_state, 1337 + state, plane_state, 1338 + crtc_state); 1339 + else 1340 + ret = dpu_plane_virtual_assign_resources(crtc, global_state, 1308 1341 state, plane_state, 1342 + crtc_state, 1309 1343 prev_adjacent_plane_state); 1310 1344 if (ret) 1311 1345 return ret; ··· 1752 1766 static const struct drm_plane_helper_funcs dpu_plane_virtual_helper_funcs = { 1753 1767 .prepare_fb = dpu_plane_prepare_fb, 1754 1768 .cleanup_fb = dpu_plane_cleanup_fb, 1755 - .atomic_check = dpu_plane_virtual_atomic_check, 1769 + .atomic_check = dpu_plane_atomic_check, 1756 1770 .atomic_update = dpu_plane_atomic_update, 1757 1771 }; 1758 1772

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