Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'x86-irq-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 irq updates from Thomas Gleixner:
"Trivial cleanups for the posted MSI interrupt handling"
* tag 'x86-irq-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/irq_remapping: Sanitize posted_msi_supported()
x86/irq: Cleanup posted MSI code
+18
-22
+3
-2
arch/x86/include/asm/irq_remapping.h
+3
-2
arch/x86/include/asm/irq_remapping.h
···
67
67
68
68
extern bool enable_posted_msi;
69
69
70
-
static inline bool posted_msi_supported(void)
70
+
static inline bool posted_msi_enabled(void)
71
71
{
72
-
return enable_posted_msi && irq_remapping_cap(IRQ_POSTING_CAP);
72
+
return IS_ENABLED(CONFIG_X86_POSTED_MSI) &&
73
+
enable_posted_msi && irq_remapping_cap(IRQ_POSTING_CAP);
73
74
}
74
75
75
76
#else /* CONFIG_IRQ_REMAP */
+13
-18
arch/x86/kernel/irq.c
+13
-18
arch/x86/kernel/irq.c
···
420
420
421
421
void intel_posted_msi_init(void)
422
422
{
423
-
u32 destination;
424
-
u32 apic_id;
423
+
u32 destination, apic_id;
425
424
426
425
this_cpu_write(posted_msi_pi_desc.nv, POSTED_MSI_NOTIFICATION_VECTOR);
427
-
428
426
/*
429
427
* APIC destination ID is stored in bit 8:15 while in XAPIC mode.
430
428
* VT-d spec. CH 9.11
···
466
468
}
467
469
468
470
/*
469
-
* Performance data shows that 3 is good enough to harvest 90+% of the benefit
470
-
* on high IRQ rate workload.
471
+
* Performance data shows that 3 is good enough to harvest 90+% of the
472
+
* benefit on high interrupt rate workloads.
471
473
*/
472
474
#define MAX_POSTED_MSI_COALESCING_LOOP 3
473
475
···
477
479
*/
478
480
DEFINE_IDTENTRY_SYSVEC(sysvec_posted_msi_notification)
479
481
{
482
+
struct pi_desc *pid = this_cpu_ptr(&posted_msi_pi_desc);
480
483
struct pt_regs *old_regs = set_irq_regs(regs);
481
-
struct pi_desc *pid;
482
-
int i = 0;
483
-
484
-
pid = this_cpu_ptr(&posted_msi_pi_desc);
485
484
486
485
/* Mark the handler active for intel_ack_posted_msi_irq() */
487
486
__this_cpu_write(posted_msi_handler_active, true);
···
486
491
irq_enter();
487
492
488
493
/*
489
-
* Max coalescing count includes the extra round of handle_pending_pir
490
-
* after clearing the outstanding notification bit. Hence, at most
491
-
* MAX_POSTED_MSI_COALESCING_LOOP - 1 loops are executed here.
494
+
* Loop only MAX_POSTED_MSI_COALESCING_LOOP - 1 times here to take
495
+
* the final handle_pending_pir() invocation after clearing the
496
+
* outstanding notification bit into account.
492
497
*/
493
-
while (++i < MAX_POSTED_MSI_COALESCING_LOOP) {
498
+
for (int i = 1; i < MAX_POSTED_MSI_COALESCING_LOOP; i++) {
494
499
if (!handle_pending_pir(pid->pir, regs))
495
500
break;
496
501
}
497
502
498
503
/*
499
-
* Clear outstanding notification bit to allow new IRQ notifications,
500
-
* do this last to maximize the window of interrupt coalescing.
504
+
* Clear the outstanding notification bit to rearm the notification
505
+
* mechanism.
501
506
*/
502
507
pi_clear_on(pid);
503
508
504
509
/*
505
-
* There could be a race of PI notification and the clearing of ON bit,
506
-
* process PIR bits one last time such that handling the new interrupts
507
-
* are not delayed until the next IRQ.
510
+
* Clearing the ON bit can race with a notification. Process the
511
+
* PIR bits one last time so that handling the new interrupts is
512
+
* not delayed until the next notification happens.
508
513
*/
509
514
handle_pending_pir(pid->pir, regs);
510
515
+2
-2
drivers/iommu/intel/irq_remapping.c
+2
-2
drivers/iommu/intel/irq_remapping.c
···
1368
1368
break;
1369
1369
case X86_IRQ_ALLOC_TYPE_PCI_MSI:
1370
1370
case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
1371
-
if (posted_msi_supported()) {
1371
+
if (posted_msi_enabled()) {
1372
1372
prepare_irte_posted(irte);
1373
1373
data->irq_2_iommu.posted_msi = 1;
1374
1374
}
···
1460
1460
1461
1461
irq_data->hwirq = (index << 16) + i;
1462
1462
irq_data->chip_data = ird;
1463
-
if (posted_msi_supported() &&
1463
+
if (posted_msi_enabled() &&
1464
1464
((info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI) ||
1465
1465
(info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX)))
1466
1466
irq_data->chip = &intel_ir_chip_post_msi;