Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm

+11 -1

arch/arm/Kconfig

··· 1189 1189 is not correctly implemented in PL310 as clean lines are not 1190 1190 invalidated as a result of these operations. 1191 1191 1192 + config ARM_ERRATA_643719 1193 + bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1194 + depends on CPU_V7 && SMP 1195 + help 1196 + This option enables the workaround for the 643719 Cortex-A9 (prior to 1197 + r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1198 + register returns zero when it should return one. The workaround 1199 + corrects this value, ensuring cache maintenance operations which use 1200 + it behave as intended and avoiding data corruption. 1201 + 1192 1202 config ARM_ERRATA_720789 1193 1203 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1194 1204 depends on CPU_V7 ··· 2016 2006 2017 2007 config KEXEC 2018 2008 bool "Kexec system call (EXPERIMENTAL)" 2019 - depends on (!SMP || HOTPLUG_CPU) 2009 + depends on (!SMP || PM_SLEEP_SMP) 2020 2010 help 2021 2011 kexec is a system call that implements the ability to shutdown your 2022 2012 current kernel, and to start another kernel. It is like a reboot

+2 -1

arch/arm/boot/compressed/Makefile

··· 116 116 117 117 # Make sure files are removed during clean 118 118 extra-y += piggy.gzip piggy.lzo piggy.lzma piggy.xzkern \ 119 - lib1funcs.S ashldi3.S $(libfdt) $(libfdt_hdrs) 119 + lib1funcs.S ashldi3.S $(libfdt) $(libfdt_hdrs) \ 120 + hyp-stub.S 120 121 121 122 ifeq ($(CONFIG_FUNCTION_TRACER),y) 122 123 ORIG_CFLAGS := $(KBUILD_CFLAGS)

+1 -3

arch/arm/include/asm/cacheflush.h

··· 320 320 } 321 321 322 322 #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE 323 - static inline void flush_kernel_dcache_page(struct page *page) 324 - { 325 - } 323 + extern void flush_kernel_dcache_page(struct page *); 326 324 327 325 #define flush_dcache_mmap_lock(mapping) \ 328 326 spin_lock_irq(&(mapping)->tree_lock)

+4

arch/arm/kernel/machine_kexec.c

··· 134 134 unsigned long reboot_code_buffer_phys; 135 135 void *reboot_code_buffer; 136 136 137 + if (num_online_cpus() > 1) { 138 + pr_err("kexec: error: multiple CPUs still online\n"); 139 + return; 140 + } 137 141 138 142 page_list = image->head & PAGE_MASK; 139 143

+37 -6

arch/arm/kernel/process.c

··· 184 184 185 185 __setup("reboot=", reboot_setup); 186 186 187 + /* 188 + * Called by kexec, immediately prior to machine_kexec(). 189 + * 190 + * This must completely disable all secondary CPUs; simply causing those CPUs 191 + * to execute e.g. a RAM-based pin loop is not sufficient. This allows the 192 + * kexec'd kernel to use any and all RAM as it sees fit, without having to 193 + * avoid any code or data used by any SW CPU pin loop. The CPU hotplug 194 + * functionality embodied in disable_nonboot_cpus() to achieve this. 195 + */ 187 196 void machine_shutdown(void) 188 197 { 189 - #ifdef CONFIG_SMP 190 - smp_send_stop(); 191 - #endif 198 + disable_nonboot_cpus(); 192 199 } 193 200 201 + /* 202 + * Halting simply requires that the secondary CPUs stop performing any 203 + * activity (executing tasks, handling interrupts). smp_send_stop() 204 + * achieves this. 205 + */ 194 206 void machine_halt(void) 195 207 { 196 - machine_shutdown(); 208 + smp_send_stop(); 209 + 197 210 local_irq_disable(); 198 211 while (1); 199 212 } 200 213 214 + /* 215 + * Power-off simply requires that the secondary CPUs stop performing any 216 + * activity (executing tasks, handling interrupts). smp_send_stop() 217 + * achieves this. When the system power is turned off, it will take all CPUs 218 + * with it. 219 + */ 201 220 void machine_power_off(void) 202 221 { 203 - machine_shutdown(); 222 + smp_send_stop(); 223 + 204 224 if (pm_power_off) 205 225 pm_power_off(); 206 226 } 207 227 228 + /* 229 + * Restart requires that the secondary CPUs stop performing any activity 230 + * while the primary CPU resets the system. Systems with a single CPU can 231 + * use soft_restart() as their machine descriptor's .restart hook, since that 232 + * will cause the only available CPU to reset. Systems with multiple CPUs must 233 + * provide a HW restart implementation, to ensure that all CPUs reset at once. 234 + * This is required so that any code running after reset on the primary CPU 235 + * doesn't have to co-ordinate with other CPUs to ensure they aren't still 236 + * executing pre-reset code, and using RAM that the primary CPU's code wishes 237 + * to use. Implementing such co-ordination would be essentially impossible. 238 + */ 208 239 void machine_restart(char *cmd) 209 240 { 210 - machine_shutdown(); 241 + smp_send_stop(); 211 242 212 243 arm_pm_restart(reboot_mode, cmd); 213 244

-13

arch/arm/kernel/smp.c

··· 651 651 smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); 652 652 } 653 653 654 - #ifdef CONFIG_HOTPLUG_CPU 655 - static void smp_kill_cpus(cpumask_t *mask) 656 - { 657 - unsigned int cpu; 658 - for_each_cpu(cpu, mask) 659 - platform_cpu_kill(cpu); 660 - } 661 - #else 662 - static void smp_kill_cpus(cpumask_t *mask) { } 663 - #endif 664 - 665 654 void smp_send_stop(void) 666 655 { 667 656 unsigned long timeout; ··· 668 679 669 680 if (num_online_cpus() > 1) 670 681 pr_warning("SMP: failed to stop secondary CPUs\n"); 671 - 672 - smp_kill_cpus(&mask); 673 682 } 674 683 675 684 /*

+8

arch/arm/mm/cache-v7.S

··· 92 92 mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr 93 93 ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr 94 94 ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr 95 + #ifdef CONFIG_ARM_ERRATA_643719 96 + ALT_SMP(mrceq p15, 0, r2, c0, c0, 0) @ read main ID register 97 + ALT_UP(moveq pc, lr) @ LoUU is zero, so nothing to do 98 + ldreq r1, =0x410fc090 @ ID of ARM Cortex A9 r0p? 99 + biceq r2, r2, #0x0000000f @ clear minor revision number 100 + teqeq r2, r1 @ test for errata affected core and if so... 101 + orreqs r3, #(1 << 21) @ fix LoUIS value (and set flags state to 'ne') 102 + #endif 95 103 ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2 96 104 ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2 97 105 moveq pc, lr @ return if level == 0

+33

arch/arm/mm/flush.c

··· 301 301 EXPORT_SYMBOL(flush_dcache_page); 302 302 303 303 /* 304 + * Ensure cache coherency for the kernel mapping of this page. We can 305 + * assume that the page is pinned via kmap. 306 + * 307 + * If the page only exists in the page cache and there are no user 308 + * space mappings, this is a no-op since the page was already marked 309 + * dirty at creation. Otherwise, we need to flush the dirty kernel 310 + * cache lines directly. 311 + */ 312 + void flush_kernel_dcache_page(struct page *page) 313 + { 314 + if (cache_is_vivt() || cache_is_vipt_aliasing()) { 315 + struct address_space *mapping; 316 + 317 + mapping = page_mapping(page); 318 + 319 + if (!mapping || mapping_mapped(mapping)) { 320 + void *addr; 321 + 322 + addr = page_address(page); 323 + /* 324 + * kmap_atomic() doesn't set the page virtual 325 + * address for highmem pages, and 326 + * kunmap_atomic() takes care of cache 327 + * flushing already. 328 + */ 329 + if (!IS_ENABLED(CONFIG_HIGHMEM) || addr) 330 + __cpuc_flush_dcache_area(addr, PAGE_SIZE); 331 + } 332 + } 333 + } 334 + EXPORT_SYMBOL(flush_kernel_dcache_page); 335 + 336 + /* 304 337 * Flush an anonymous page so that users of get_user_pages() 305 338 * can safely access the data. The expected sequence is: 306 339 *

+5 -3

arch/arm/mm/mmu.c

··· 616 616 } while (pte++, addr += PAGE_SIZE, addr != end); 617 617 } 618 618 619 - static void __init map_init_section(pmd_t *pmd, unsigned long addr, 619 + static void __init __map_init_section(pmd_t *pmd, unsigned long addr, 620 620 unsigned long end, phys_addr_t phys, 621 621 const struct mem_type *type) 622 622 { 623 + pmd_t *p = pmd; 624 + 623 625 #ifndef CONFIG_ARM_LPAE 624 626 /* 625 627 * In classic MMU format, puds and pmds are folded in to ··· 640 638 phys += SECTION_SIZE; 641 639 } while (pmd++, addr += SECTION_SIZE, addr != end); 642 640 643 - flush_pmd_entry(pmd); 641 + flush_pmd_entry(p); 644 642 } 645 643 646 644 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, ··· 663 661 */ 664 662 if (type->prot_sect && 665 663 ((addr | next | phys) & ~SECTION_MASK) == 0) { 666 - map_init_section(pmd, addr, next, phys, type); 664 + __map_init_section(pmd, addr, next, phys, type); 667 665 } else { 668 666 alloc_init_pte(pmd, addr, next, 669 667 __phys_to_pfn(phys), type);

+2 -2

arch/arm/mm/proc-v7.S

··· 409 409 */ 410 410 .type __v7_pj4b_proc_info, #object 411 411 __v7_pj4b_proc_info: 412 - .long 0x562f5840 413 - .long 0xfffffff0 412 + .long 0x560f5800 413 + .long 0xff0fff00 414 414 __v7_proc __v7_pj4b_setup 415 415 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info 416 416

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