Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch '20230909123431.1725728-1-quic_ajipan@quicinc.com' into clk-for-6.7
Merge the SM4450 RPMHCC and GCC through a topic branch, to allow reuse
of the defines from the DeviceTree binding in the DeviceTree source.
+3181
+1
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
+1
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
+55
Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml
+55
Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,sm4450-gcc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Global Clock & Reset Controller on SM4450
8
+
9
+
maintainers:
10
+
- Ajit Pandey <quic_ajipan@quicinc.com>
11
+
- Taniya Das <quic_tdas@quicinc.com>
12
+
13
+
description: |
14
+
Qualcomm global clock control module provides the clocks, resets and power
15
+
domains on SM4450
16
+
17
+
See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h
18
+
19
+
properties:
20
+
compatible:
21
+
const: qcom,sm4450-gcc
22
+
23
+
clocks:
24
+
items:
25
+
- description: Board XO source
26
+
- description: Sleep clock source
27
+
- description: UFS Phy Rx symbol 0 clock source
28
+
- description: UFS Phy Rx symbol 1 clock source
29
+
- description: UFS Phy Tx symbol 0 clock source
30
+
- description: USB3 Phy wrapper pipe clock source
31
+
32
+
required:
33
+
- compatible
34
+
- clocks
35
+
36
+
allOf:
37
+
- $ref: qcom,gcc.yaml#
38
+
39
+
unevaluatedProperties: false
40
+
41
+
examples:
42
+
- |
43
+
#include <dt-bindings/clock/qcom,rpmh.h>
44
+
clock-controller@100000 {
45
+
compatible = "qcom,sm4450-gcc";
46
+
reg = <0x00100000 0x001f4200>;
47
+
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
48
+
<&ufs_mem_phy 0>, <&ufs_mem_phy 1>,
49
+
<&ufs_mem_phy 2>, <&usb_1_qmpphy>;
50
+
#clock-cells = <1>;
51
+
#reset-cells = <1>;
52
+
#power-domain-cells = <1>;
53
+
};
54
+
55
+
...
+9
drivers/clk/qcom/Kconfig
+9
drivers/clk/qcom/Kconfig
···
841
841
Say Y if you want to support display devices and functionality such as
842
842
splash screen.
843
843
844
+
config SM_GCC_4450
845
+
tristate "SM4450 Global Clock Controller"
846
+
depends on ARM64 || COMPILE_TEST
847
+
select QCOM_GDSC
848
+
help
849
+
Support for the global clock controller on SM4450 devices.
850
+
Say Y if you want to use peripheral devices such as UART, SPI,
851
+
I2C, USB, SD/UFS, PCIe, etc.
852
+
844
853
config SM_GCC_6115
845
854
tristate "SM6115 and SM4250 Global Clock Controller"
846
855
depends on ARM64 || COMPILE_TEST
+1
drivers/clk/qcom/Makefile
+1
drivers/clk/qcom/Makefile
···
110
110
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
111
111
obj-$(CONFIG_SM_DISPCC_8450) += dispcc-sm8450.o
112
112
obj-$(CONFIG_SM_DISPCC_8550) += dispcc-sm8550.o
113
+
obj-$(CONFIG_SM_GCC_4450) += gcc-sm4450.o
113
114
obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o
114
115
obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o
115
116
obj-$(CONFIG_SM_GCC_6350) += gcc-sm6350.o
+21
drivers/clk/qcom/clk-rpmh.c
+21
drivers/clk/qcom/clk-rpmh.c
···
350
350
351
351
DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a4, "lnbclka1", 4);
352
352
DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a4, "lnbclka2", 4);
353
+
DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a4, "lnbclka3", 4);
353
354
354
355
DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _g4, "lnbclkg2", 4);
355
356
DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _g4, "lnbclkg3", 4);
···
718
717
.num_clks = ARRAY_SIZE(sdx75_rpmh_clocks),
719
718
};
720
719
720
+
static struct clk_hw *sm4450_rpmh_clocks[] = {
721
+
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
722
+
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
723
+
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a4.hw,
724
+
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw,
725
+
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a4.hw,
726
+
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a4_ao.hw,
727
+
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
728
+
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
729
+
[RPMH_RF_CLK5] = &clk_rpmh_rf_clk5_a.hw,
730
+
[RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a_ao.hw,
731
+
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
732
+
};
733
+
734
+
static const struct clk_rpmh_desc clk_rpmh_sm4450 = {
735
+
.clks = sm4450_rpmh_clocks,
736
+
.num_clks = ARRAY_SIZE(sm4450_rpmh_clocks),
737
+
};
738
+
721
739
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
722
740
void *data)
723
741
{
···
830
810
{ .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55},
831
811
{ .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65},
832
812
{ .compatible = "qcom,sdx75-rpmh-clk", .data = &clk_rpmh_sdx75},
813
+
{ .compatible = "qcom,sm4450-rpmh-clk", .data = &clk_rpmh_sm4450},
833
814
{ .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350},
834
815
{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
835
816
{ .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
+2897
drivers/clk/qcom/gcc-sm4450.c
+2897
drivers/clk/qcom/gcc-sm4450.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/module.h>
8
+
#include <linux/of_device.h>
9
+
#include <linux/regmap.h>
10
+
11
+
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
12
+
13
+
#include "clk-alpha-pll.h"
14
+
#include "clk-branch.h"
15
+
#include "clk-rcg.h"
16
+
#include "clk-regmap.h"
17
+
#include "clk-regmap-divider.h"
18
+
#include "clk-regmap-mux.h"
19
+
#include "clk-regmap-phy-mux.h"
20
+
#include "gdsc.h"
21
+
#include "reset.h"
22
+
23
+
enum {
24
+
DT_BI_TCXO,
25
+
DT_SLEEP_CLK,
26
+
DT_PCIE_0_PIPE_CLK,
27
+
DT_UFS_PHY_RX_SYMBOL_0_CLK,
28
+
DT_UFS_PHY_RX_SYMBOL_1_CLK,
29
+
DT_UFS_PHY_TX_SYMBOL_0_CLK,
30
+
DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
31
+
};
32
+
33
+
enum {
34
+
P_BI_TCXO,
35
+
P_GCC_GPLL0_OUT_EVEN,
36
+
P_GCC_GPLL0_OUT_MAIN,
37
+
P_GCC_GPLL0_OUT_ODD,
38
+
P_GCC_GPLL1_OUT_MAIN,
39
+
P_GCC_GPLL3_OUT_MAIN,
40
+
P_GCC_GPLL4_OUT_MAIN,
41
+
P_GCC_GPLL9_OUT_MAIN,
42
+
P_GCC_GPLL10_OUT_MAIN,
43
+
P_SLEEP_CLK,
44
+
P_UFS_PHY_RX_SYMBOL_0_CLK,
45
+
P_UFS_PHY_RX_SYMBOL_1_CLK,
46
+
P_UFS_PHY_TX_SYMBOL_0_CLK,
47
+
P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
48
+
};
49
+
50
+
static const struct pll_vco lucid_evo_vco[] = {
51
+
{ 249600000, 2020000000, 0 },
52
+
};
53
+
54
+
static struct clk_alpha_pll gcc_gpll0 = {
55
+
.offset = 0x0,
56
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
57
+
.clkr = {
58
+
.enable_reg = 0x62018,
59
+
.enable_mask = BIT(0),
60
+
.hw.init = &(const struct clk_init_data) {
61
+
.name = "gcc_gpll0",
62
+
.parent_data = &(const struct clk_parent_data) {
63
+
.index = DT_BI_TCXO,
64
+
},
65
+
.num_parents = 1,
66
+
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
67
+
},
68
+
},
69
+
};
70
+
71
+
static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
72
+
{ 0x1, 2 },
73
+
{ }
74
+
};
75
+
76
+
static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
77
+
.offset = 0x0,
78
+
.post_div_shift = 10,
79
+
.post_div_table = post_div_table_gcc_gpll0_out_even,
80
+
.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
81
+
.width = 4,
82
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
83
+
.clkr.hw.init = &(const struct clk_init_data) {
84
+
.name = "gcc_gpll0_out_even",
85
+
.parent_hws = (const struct clk_hw*[]) {
86
+
&gcc_gpll0.clkr.hw,
87
+
},
88
+
.num_parents = 1,
89
+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
90
+
},
91
+
};
92
+
93
+
static const struct clk_div_table post_div_table_gcc_gpll0_out_odd[] = {
94
+
{ 0x2, 3 },
95
+
{ }
96
+
};
97
+
98
+
static struct clk_alpha_pll_postdiv gcc_gpll0_out_odd = {
99
+
.offset = 0x0,
100
+
.post_div_shift = 14,
101
+
.post_div_table = post_div_table_gcc_gpll0_out_odd,
102
+
.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_odd),
103
+
.width = 4,
104
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
105
+
.clkr.hw.init = &(const struct clk_init_data) {
106
+
.name = "gcc_gpll0_out_odd",
107
+
.parent_hws = (const struct clk_hw*[]) {
108
+
&gcc_gpll0.clkr.hw,
109
+
},
110
+
.num_parents = 1,
111
+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
112
+
},
113
+
};
114
+
115
+
static struct clk_alpha_pll gcc_gpll1 = {
116
+
.offset = 0x1000,
117
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
118
+
.clkr = {
119
+
.enable_reg = 0x62018,
120
+
.enable_mask = BIT(1),
121
+
.hw.init = &(const struct clk_init_data) {
122
+
.name = "gcc_gpll1",
123
+
.parent_data = &(const struct clk_parent_data) {
124
+
.index = DT_BI_TCXO,
125
+
},
126
+
.num_parents = 1,
127
+
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
128
+
},
129
+
},
130
+
};
131
+
132
+
static const struct alpha_pll_config gcc_gpll3_config = {
133
+
.l = 0x14,
134
+
.alpha = 0xd555,
135
+
.config_ctl_val = 0x20485699,
136
+
.config_ctl_hi_val = 0x00182261,
137
+
.config_ctl_hi1_val = 0x32aa299c,
138
+
.user_ctl_val = 0x00000000,
139
+
.user_ctl_hi_val = 0x00000805,
140
+
};
141
+
142
+
static struct clk_alpha_pll gcc_gpll3 = {
143
+
.offset = 0x3000,
144
+
.vco_table = lucid_evo_vco,
145
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
146
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
147
+
.clkr = {
148
+
.enable_reg = 0x62018,
149
+
.enable_mask = BIT(3),
150
+
.hw.init = &(const struct clk_init_data) {
151
+
.name = "gcc_gpll3",
152
+
.parent_data = &(const struct clk_parent_data) {
153
+
.index = DT_BI_TCXO,
154
+
},
155
+
.num_parents = 1,
156
+
.ops = &clk_alpha_pll_lucid_evo_ops,
157
+
},
158
+
},
159
+
};
160
+
161
+
static struct clk_alpha_pll gcc_gpll4 = {
162
+
.offset = 0x4000,
163
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
164
+
.clkr = {
165
+
.enable_reg = 0x62018,
166
+
.enable_mask = BIT(4),
167
+
.hw.init = &(const struct clk_init_data) {
168
+
.name = "gcc_gpll4",
169
+
.parent_data = &(const struct clk_parent_data) {
170
+
.index = DT_BI_TCXO,
171
+
},
172
+
.num_parents = 1,
173
+
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
174
+
},
175
+
},
176
+
};
177
+
178
+
static struct clk_alpha_pll gcc_gpll9 = {
179
+
.offset = 0x9000,
180
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
181
+
.clkr = {
182
+
.enable_reg = 0x62018,
183
+
.enable_mask = BIT(9),
184
+
.hw.init = &(const struct clk_init_data) {
185
+
.name = "gcc_gpll9",
186
+
.parent_data = &(const struct clk_parent_data) {
187
+
.index = DT_BI_TCXO,
188
+
},
189
+
.num_parents = 1,
190
+
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
191
+
},
192
+
},
193
+
};
194
+
195
+
static struct clk_alpha_pll gcc_gpll10 = {
196
+
.offset = 0xa000,
197
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
198
+
.clkr = {
199
+
.enable_reg = 0x62018,
200
+
.enable_mask = BIT(10),
201
+
.hw.init = &(const struct clk_init_data) {
202
+
.name = "gcc_gpll10",
203
+
.parent_data = &(const struct clk_parent_data) {
204
+
.index = DT_BI_TCXO,
205
+
},
206
+
.num_parents = 1,
207
+
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
208
+
},
209
+
},
210
+
};
211
+
212
+
static const struct parent_map gcc_parent_map_0[] = {
213
+
{ P_BI_TCXO, 0 },
214
+
{ P_GCC_GPLL0_OUT_MAIN, 1 },
215
+
{ P_GCC_GPLL0_OUT_EVEN, 6 },
216
+
};
217
+
218
+
static const struct clk_parent_data gcc_parent_data_0[] = {
219
+
{ .index = DT_BI_TCXO },
220
+
{ .hw = &gcc_gpll0.clkr.hw },
221
+
{ .hw = &gcc_gpll0_out_even.clkr.hw },
222
+
};
223
+
224
+
static const struct parent_map gcc_parent_map_1[] = {
225
+
{ P_BI_TCXO, 0 },
226
+
{ P_GCC_GPLL0_OUT_MAIN, 1 },
227
+
{ P_SLEEP_CLK, 5 },
228
+
{ P_GCC_GPLL0_OUT_EVEN, 6 },
229
+
};
230
+
231
+
static const struct clk_parent_data gcc_parent_data_1[] = {
232
+
{ .index = DT_BI_TCXO },
233
+
{ .hw = &gcc_gpll0.clkr.hw },
234
+
{ .index = DT_SLEEP_CLK },
235
+
{ .hw = &gcc_gpll0_out_even.clkr.hw },
236
+
};
237
+
238
+
static const struct parent_map gcc_parent_map_2[] = {
239
+
{ P_BI_TCXO, 0 },
240
+
{ P_GCC_GPLL0_OUT_MAIN, 1 },
241
+
{ P_GCC_GPLL1_OUT_MAIN, 4 },
242
+
{ P_GCC_GPLL4_OUT_MAIN, 5 },
243
+
{ P_GCC_GPLL0_OUT_EVEN, 6 },
244
+
};
245
+
246
+
static const struct clk_parent_data gcc_parent_data_2[] = {
247
+
{ .index = DT_BI_TCXO },
248
+
{ .hw = &gcc_gpll0.clkr.hw },
249
+
{ .hw = &gcc_gpll1.clkr.hw },
250
+
{ .hw = &gcc_gpll4.clkr.hw },
251
+
{ .hw = &gcc_gpll0_out_even.clkr.hw },
252
+
};
253
+
254
+
static const struct parent_map gcc_parent_map_3[] = {
255
+
{ P_BI_TCXO, 0 },
256
+
{ P_SLEEP_CLK, 5 },
257
+
};
258
+
259
+
static const struct clk_parent_data gcc_parent_data_3[] = {
260
+
{ .index = DT_BI_TCXO },
261
+
{ .index = DT_SLEEP_CLK },
262
+
};
263
+
264
+
static const struct parent_map gcc_parent_map_4[] = {
265
+
{ P_BI_TCXO, 0 },
266
+
{ P_GCC_GPLL0_OUT_MAIN, 1 },
267
+
{ P_GCC_GPLL0_OUT_ODD, 2 },
268
+
{ P_GCC_GPLL10_OUT_MAIN, 3 },
269
+
{ P_GCC_GPLL0_OUT_EVEN, 6 },
270
+
};
271
+
272
+
static const struct clk_parent_data gcc_parent_data_4[] = {
273
+
{ .index = DT_BI_TCXO },
274
+
{ .hw = &gcc_gpll0.clkr.hw },
275
+
{ .hw = &gcc_gpll0_out_odd.clkr.hw },
276
+
{ .hw = &gcc_gpll10.clkr.hw },
277
+
{ .hw = &gcc_gpll0_out_even.clkr.hw },
278
+
};
279
+
280
+
static const struct parent_map gcc_parent_map_5[] = {
281
+
{ P_BI_TCXO, 0 },
282
+
};
283
+
284
+
static const struct clk_parent_data gcc_parent_data_5[] = {
285
+
{ .index = DT_BI_TCXO },
286
+
};
287
+
288
+
static const struct parent_map gcc_parent_map_6[] = {
289
+
{ P_BI_TCXO, 0 },
290
+
{ P_GCC_GPLL0_OUT_MAIN, 1 },
291
+
{ P_GCC_GPLL9_OUT_MAIN, 2 },
292
+
{ P_GCC_GPLL4_OUT_MAIN, 5 },
293
+
{ P_GCC_GPLL0_OUT_EVEN, 6 },
294
+
};
295
+
296
+
static const struct clk_parent_data gcc_parent_data_6[] = {
297
+
{ .index = DT_BI_TCXO },
298
+
{ .hw = &gcc_gpll0.clkr.hw },
299
+
{ .hw = &gcc_gpll9.clkr.hw },
300
+
{ .hw = &gcc_gpll4.clkr.hw },
301
+
{ .hw = &gcc_gpll0_out_even.clkr.hw },
302
+
};
303
+
304
+
static const struct parent_map gcc_parent_map_7[] = {
305
+
{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
306
+
{ P_BI_TCXO, 2 },
307
+
};
308
+
309
+
static const struct clk_parent_data gcc_parent_data_7[] = {
310
+
{ .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },
311
+
{ .index = DT_BI_TCXO },
312
+
};
313
+
314
+
static const struct parent_map gcc_parent_map_8[] = {
315
+
{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
316
+
{ P_BI_TCXO, 2 },
317
+
};
318
+
319
+
static const struct clk_parent_data gcc_parent_data_8[] = {
320
+
{ .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },
321
+
{ .index = DT_BI_TCXO },
322
+
};
323
+
324
+
static const struct parent_map gcc_parent_map_9[] = {
325
+
{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
326
+
{ P_BI_TCXO, 2 },
327
+
};
328
+
329
+
static const struct clk_parent_data gcc_parent_data_9[] = {
330
+
{ .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },
331
+
{ .index = DT_BI_TCXO },
332
+
};
333
+
334
+
static const struct parent_map gcc_parent_map_10[] = {
335
+
{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
336
+
{ P_BI_TCXO, 2 },
337
+
};
338
+
339
+
static const struct clk_parent_data gcc_parent_data_10[] = {
340
+
{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK },
341
+
{ .index = DT_BI_TCXO },
342
+
};
343
+
344
+
static const struct parent_map gcc_parent_map_11[] = {
345
+
{ P_BI_TCXO, 0 },
346
+
{ P_GCC_GPLL0_OUT_MAIN, 1 },
347
+
{ P_GCC_GPLL3_OUT_MAIN, 5 },
348
+
};
349
+
350
+
static const struct clk_parent_data gcc_parent_data_11[] = {
351
+
{ .index = DT_BI_TCXO },
352
+
{ .hw = &gcc_gpll0.clkr.hw },
353
+
{ .hw = &gcc_gpll3.clkr.hw },
354
+
};
355
+
356
+
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
357
+
.reg = 0x7b060,
358
+
.clkr = {
359
+
.hw.init = &(const struct clk_init_data) {
360
+
.name = "gcc_pcie_0_pipe_clk_src",
361
+
.parent_data = &(const struct clk_parent_data) {
362
+
.index = DT_PCIE_0_PIPE_CLK,
363
+
},
364
+
.num_parents = 1,
365
+
.ops = &clk_regmap_phy_mux_ops,
366
+
},
367
+
},
368
+
};
369
+
370
+
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
371
+
.reg = 0x87060,
372
+
.shift = 0,
373
+
.width = 2,
374
+
.parent_map = gcc_parent_map_7,
375
+
.clkr = {
376
+
.hw.init = &(const struct clk_init_data) {
377
+
.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
378
+
.parent_data = gcc_parent_data_7,
379
+
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
380
+
.ops = &clk_regmap_mux_closest_ops,
381
+
},
382
+
},
383
+
};
384
+
385
+
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
386
+
.reg = 0x870d0,
387
+
.shift = 0,
388
+
.width = 2,
389
+
.parent_map = gcc_parent_map_8,
390
+
.clkr = {
391
+
.hw.init = &(const struct clk_init_data) {
392
+
.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
393
+
.parent_data = gcc_parent_data_8,
394
+
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
395
+
.ops = &clk_regmap_mux_closest_ops,
396
+
},
397
+
},
398
+
};
399
+
400
+
static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
401
+
.reg = 0x87050,
402
+
.shift = 0,
403
+
.width = 2,
404
+
.parent_map = gcc_parent_map_9,
405
+
.clkr = {
406
+
.hw.init = &(const struct clk_init_data) {
407
+
.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
408
+
.parent_data = gcc_parent_data_9,
409
+
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
410
+
.ops = &clk_regmap_mux_closest_ops,
411
+
},
412
+
},
413
+
};
414
+
415
+
static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
416
+
.reg = 0x49068,
417
+
.shift = 0,
418
+
.width = 2,
419
+
.parent_map = gcc_parent_map_10,
420
+
.clkr = {
421
+
.hw.init = &(const struct clk_init_data) {
422
+
.name = "gcc_usb3_prim_phy_pipe_clk_src",
423
+
.parent_data = gcc_parent_data_10,
424
+
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
425
+
.ops = &clk_regmap_mux_closest_ops,
426
+
},
427
+
},
428
+
};
429
+
430
+
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
431
+
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
432
+
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
433
+
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
434
+
{ }
435
+
};
436
+
437
+
static struct clk_rcg2 gcc_gp1_clk_src = {
438
+
.cmd_rcgr = 0x74004,
439
+
.mnd_width = 16,
440
+
.hid_width = 5,
441
+
.parent_map = gcc_parent_map_1,
442
+
.freq_tbl = ftbl_gcc_gp1_clk_src,
443
+
.clkr.hw.init = &(const struct clk_init_data) {
444
+
.name = "gcc_gp1_clk_src",
445
+
.parent_data = gcc_parent_data_1,
446
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
447
+
.flags = CLK_SET_RATE_PARENT,
448
+
.ops = &clk_rcg2_shared_ops,
449
+
},
450
+
};
451
+
452
+
static struct clk_rcg2 gcc_gp2_clk_src = {
453
+
.cmd_rcgr = 0x75004,
454
+
.mnd_width = 16,
455
+
.hid_width = 5,
456
+
.parent_map = gcc_parent_map_1,
457
+
.freq_tbl = ftbl_gcc_gp1_clk_src,
458
+
.clkr.hw.init = &(const struct clk_init_data) {
459
+
.name = "gcc_gp2_clk_src",
460
+
.parent_data = gcc_parent_data_1,
461
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
462
+
.flags = CLK_SET_RATE_PARENT,
463
+
.ops = &clk_rcg2_shared_ops,
464
+
},
465
+
};
466
+
467
+
static struct clk_rcg2 gcc_gp3_clk_src = {
468
+
.cmd_rcgr = 0x76004,
469
+
.mnd_width = 16,
470
+
.hid_width = 5,
471
+
.parent_map = gcc_parent_map_1,
472
+
.freq_tbl = ftbl_gcc_gp1_clk_src,
473
+
.clkr.hw.init = &(const struct clk_init_data) {
474
+
.name = "gcc_gp3_clk_src",
475
+
.parent_data = gcc_parent_data_1,
476
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
477
+
.flags = CLK_SET_RATE_PARENT,
478
+
.ops = &clk_rcg2_shared_ops,
479
+
},
480
+
};
481
+
482
+
static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
483
+
F(9600000, P_BI_TCXO, 2, 0, 0),
484
+
F(19200000, P_BI_TCXO, 1, 0, 0),
485
+
{ }
486
+
};
487
+
488
+
static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
489
+
.cmd_rcgr = 0x7b064,
490
+
.mnd_width = 16,
491
+
.hid_width = 5,
492
+
.parent_map = gcc_parent_map_3,
493
+
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
494
+
.clkr.hw.init = &(const struct clk_init_data) {
495
+
.name = "gcc_pcie_0_aux_clk_src",
496
+
.parent_data = gcc_parent_data_3,
497
+
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
498
+
.flags = CLK_SET_RATE_PARENT,
499
+
.ops = &clk_rcg2_shared_ops,
500
+
},
501
+
};
502
+
503
+
static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
504
+
F(19200000, P_BI_TCXO, 1, 0, 0),
505
+
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
506
+
{ }
507
+
};
508
+
509
+
static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
510
+
.cmd_rcgr = 0x7b048,
511
+
.mnd_width = 0,
512
+
.hid_width = 5,
513
+
.parent_map = gcc_parent_map_0,
514
+
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
515
+
.clkr.hw.init = &(const struct clk_init_data) {
516
+
.name = "gcc_pcie_0_phy_rchng_clk_src",
517
+
.parent_data = gcc_parent_data_0,
518
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
519
+
.flags = CLK_SET_RATE_PARENT,
520
+
.ops = &clk_rcg2_shared_ops,
521
+
},
522
+
};
523
+
524
+
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
525
+
F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
526
+
{ }
527
+
};
528
+
529
+
static struct clk_rcg2 gcc_pdm2_clk_src = {
530
+
.cmd_rcgr = 0x43010,
531
+
.mnd_width = 0,
532
+
.hid_width = 5,
533
+
.parent_map = gcc_parent_map_0,
534
+
.freq_tbl = ftbl_gcc_pdm2_clk_src,
535
+
.clkr.hw.init = &(const struct clk_init_data) {
536
+
.name = "gcc_pdm2_clk_src",
537
+
.parent_data = gcc_parent_data_0,
538
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
539
+
.flags = CLK_SET_RATE_PARENT,
540
+
.ops = &clk_rcg2_shared_ops,
541
+
},
542
+
};
543
+
544
+
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
545
+
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
546
+
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
547
+
F(19200000, P_BI_TCXO, 1, 0, 0),
548
+
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
549
+
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
550
+
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
551
+
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
552
+
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
553
+
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
554
+
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
555
+
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
556
+
F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
557
+
F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
558
+
F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
559
+
F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
560
+
{ }
561
+
};
562
+
563
+
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
564
+
.name = "gcc_qupv3_wrap0_s0_clk_src",
565
+
.parent_data = gcc_parent_data_0,
566
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
567
+
.flags = CLK_SET_RATE_PARENT,
568
+
.ops = &clk_rcg2_shared_ops,
569
+
};
570
+
571
+
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
572
+
.cmd_rcgr = 0x27014,
573
+
.mnd_width = 16,
574
+
.hid_width = 5,
575
+
.parent_map = gcc_parent_map_0,
576
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
577
+
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
578
+
};
579
+
580
+
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s1_clk_src[] = {
581
+
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
582
+
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
583
+
F(19200000, P_BI_TCXO, 1, 0, 0),
584
+
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
585
+
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
586
+
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
587
+
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
588
+
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
589
+
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
590
+
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
591
+
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
592
+
{ }
593
+
};
594
+
595
+
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
596
+
.name = "gcc_qupv3_wrap0_s1_clk_src",
597
+
.parent_data = gcc_parent_data_0,
598
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
599
+
.flags = CLK_SET_RATE_PARENT,
600
+
.ops = &clk_rcg2_shared_ops,
601
+
};
602
+
603
+
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
604
+
.cmd_rcgr = 0x27148,
605
+
.mnd_width = 16,
606
+
.hid_width = 5,
607
+
.parent_map = gcc_parent_map_0,
608
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
609
+
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
610
+
};
611
+
612
+
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
613
+
.name = "gcc_qupv3_wrap0_s2_clk_src",
614
+
.parent_data = gcc_parent_data_0,
615
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
616
+
.flags = CLK_SET_RATE_PARENT,
617
+
.ops = &clk_rcg2_shared_ops,
618
+
};
619
+
620
+
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
621
+
.cmd_rcgr = 0x2727c,
622
+
.mnd_width = 16,
623
+
.hid_width = 5,
624
+
.parent_map = gcc_parent_map_0,
625
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
626
+
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
627
+
};
628
+
629
+
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
630
+
.name = "gcc_qupv3_wrap0_s3_clk_src",
631
+
.parent_data = gcc_parent_data_0,
632
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
633
+
.flags = CLK_SET_RATE_PARENT,
634
+
.ops = &clk_rcg2_shared_ops,
635
+
};
636
+
637
+
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
638
+
.cmd_rcgr = 0x273b0,
639
+
.mnd_width = 16,
640
+
.hid_width = 5,
641
+
.parent_map = gcc_parent_map_0,
642
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
643
+
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
644
+
};
645
+
646
+
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
647
+
.name = "gcc_qupv3_wrap0_s4_clk_src",
648
+
.parent_data = gcc_parent_data_0,
649
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
650
+
.flags = CLK_SET_RATE_PARENT,
651
+
.ops = &clk_rcg2_shared_ops,
652
+
};
653
+
654
+
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
655
+
.cmd_rcgr = 0x274e4,
656
+
.mnd_width = 16,
657
+
.hid_width = 5,
658
+
.parent_map = gcc_parent_map_0,
659
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
660
+
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
661
+
};
662
+
663
+
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
664
+
.name = "gcc_qupv3_wrap1_s0_clk_src",
665
+
.parent_data = gcc_parent_data_0,
666
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
667
+
.flags = CLK_SET_RATE_PARENT,
668
+
.ops = &clk_rcg2_shared_ops,
669
+
};
670
+
671
+
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
672
+
.cmd_rcgr = 0x28014,
673
+
.mnd_width = 16,
674
+
.hid_width = 5,
675
+
.parent_map = gcc_parent_map_0,
676
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
677
+
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
678
+
};
679
+
680
+
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
681
+
.name = "gcc_qupv3_wrap1_s1_clk_src",
682
+
.parent_data = gcc_parent_data_0,
683
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
684
+
.flags = CLK_SET_RATE_PARENT,
685
+
.ops = &clk_rcg2_shared_ops,
686
+
};
687
+
688
+
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
689
+
.cmd_rcgr = 0x28148,
690
+
.mnd_width = 16,
691
+
.hid_width = 5,
692
+
.parent_map = gcc_parent_map_0,
693
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
694
+
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
695
+
};
696
+
697
+
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
698
+
.name = "gcc_qupv3_wrap1_s2_clk_src",
699
+
.parent_data = gcc_parent_data_0,
700
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
701
+
.flags = CLK_SET_RATE_PARENT,
702
+
.ops = &clk_rcg2_shared_ops,
703
+
};
704
+
705
+
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
706
+
.cmd_rcgr = 0x2827c,
707
+
.mnd_width = 16,
708
+
.hid_width = 5,
709
+
.parent_map = gcc_parent_map_0,
710
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
711
+
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
712
+
};
713
+
714
+
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
715
+
.name = "gcc_qupv3_wrap1_s3_clk_src",
716
+
.parent_data = gcc_parent_data_0,
717
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
718
+
.flags = CLK_SET_RATE_PARENT,
719
+
.ops = &clk_rcg2_shared_ops,
720
+
};
721
+
722
+
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
723
+
.cmd_rcgr = 0x283b0,
724
+
.mnd_width = 16,
725
+
.hid_width = 5,
726
+
.parent_map = gcc_parent_map_0,
727
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
728
+
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
729
+
};
730
+
731
+
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
732
+
.name = "gcc_qupv3_wrap1_s4_clk_src",
733
+
.parent_data = gcc_parent_data_0,
734
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
735
+
.flags = CLK_SET_RATE_PARENT,
736
+
.ops = &clk_rcg2_shared_ops,
737
+
};
738
+
739
+
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
740
+
.cmd_rcgr = 0x284e4,
741
+
.mnd_width = 16,
742
+
.hid_width = 5,
743
+
.parent_map = gcc_parent_map_0,
744
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
745
+
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
746
+
};
747
+
748
+
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
749
+
F(144000, P_BI_TCXO, 16, 3, 25),
750
+
F(400000, P_BI_TCXO, 12, 1, 4),
751
+
F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3),
752
+
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
753
+
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
754
+
F(100000000, P_GCC_GPLL0_OUT_ODD, 2, 0, 0),
755
+
F(192000000, P_GCC_GPLL10_OUT_MAIN, 2, 0, 0),
756
+
F(384000000, P_GCC_GPLL10_OUT_MAIN, 1, 0, 0),
757
+
{ }
758
+
};
759
+
760
+
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
761
+
.cmd_rcgr = 0xb3010,
762
+
.mnd_width = 8,
763
+
.hid_width = 5,
764
+
.parent_map = gcc_parent_map_4,
765
+
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
766
+
.clkr.hw.init = &(const struct clk_init_data) {
767
+
.name = "gcc_sdcc1_apps_clk_src",
768
+
.parent_data = gcc_parent_data_4,
769
+
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
770
+
.flags = CLK_SET_RATE_PARENT,
771
+
.ops = &clk_rcg2_floor_ops,
772
+
},
773
+
};
774
+
775
+
static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
776
+
F(100000000, P_GCC_GPLL0_OUT_ODD, 2, 0, 0),
777
+
F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
778
+
F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
779
+
{ }
780
+
};
781
+
782
+
static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
783
+
.cmd_rcgr = 0xb3030,
784
+
.mnd_width = 0,
785
+
.hid_width = 5,
786
+
.parent_map = gcc_parent_map_4,
787
+
.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
788
+
.clkr.hw.init = &(const struct clk_init_data) {
789
+
.name = "gcc_sdcc1_ice_core_clk_src",
790
+
.parent_data = gcc_parent_data_4,
791
+
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
792
+
.flags = CLK_SET_RATE_PARENT,
793
+
.ops = &clk_rcg2_floor_ops,
794
+
},
795
+
};
796
+
797
+
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
798
+
F(400000, P_BI_TCXO, 12, 1, 4),
799
+
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
800
+
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
801
+
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
802
+
F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
803
+
{ }
804
+
};
805
+
806
+
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
807
+
.cmd_rcgr = 0x24014,
808
+
.mnd_width = 8,
809
+
.hid_width = 5,
810
+
.parent_map = gcc_parent_map_6,
811
+
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
812
+
.clkr.hw.init = &(const struct clk_init_data) {
813
+
.name = "gcc_sdcc2_apps_clk_src",
814
+
.parent_data = gcc_parent_data_6,
815
+
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
816
+
.flags = CLK_SET_RATE_PARENT,
817
+
.ops = &clk_rcg2_floor_ops,
818
+
},
819
+
};
820
+
821
+
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
822
+
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
823
+
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
824
+
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
825
+
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
826
+
{ }
827
+
};
828
+
829
+
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
830
+
.cmd_rcgr = 0x8702c,
831
+
.mnd_width = 8,
832
+
.hid_width = 5,
833
+
.parent_map = gcc_parent_map_0,
834
+
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
835
+
.clkr.hw.init = &(const struct clk_init_data) {
836
+
.name = "gcc_ufs_phy_axi_clk_src",
837
+
.parent_data = gcc_parent_data_0,
838
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
839
+
.flags = CLK_SET_RATE_PARENT,
840
+
.ops = &clk_rcg2_shared_ops,
841
+
},
842
+
};
843
+
844
+
static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
845
+
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
846
+
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
847
+
F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
848
+
{ }
849
+
};
850
+
851
+
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
852
+
.cmd_rcgr = 0x87074,
853
+
.mnd_width = 0,
854
+
.hid_width = 5,
855
+
.parent_map = gcc_parent_map_2,
856
+
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
857
+
.clkr.hw.init = &(const struct clk_init_data) {
858
+
.name = "gcc_ufs_phy_ice_core_clk_src",
859
+
.parent_data = gcc_parent_data_2,
860
+
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
861
+
.flags = CLK_SET_RATE_PARENT,
862
+
.ops = &clk_rcg2_shared_ops,
863
+
},
864
+
};
865
+
866
+
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
867
+
.cmd_rcgr = 0x870a8,
868
+
.mnd_width = 0,
869
+
.hid_width = 5,
870
+
.parent_map = gcc_parent_map_5,
871
+
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
872
+
.clkr.hw.init = &(const struct clk_init_data) {
873
+
.name = "gcc_ufs_phy_phy_aux_clk_src",
874
+
.parent_data = gcc_parent_data_5,
875
+
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
876
+
.flags = CLK_SET_RATE_PARENT,
877
+
.ops = &clk_rcg2_shared_ops,
878
+
},
879
+
};
880
+
881
+
static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
882
+
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
883
+
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
884
+
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
885
+
{ }
886
+
};
887
+
888
+
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
889
+
.cmd_rcgr = 0x8708c,
890
+
.mnd_width = 0,
891
+
.hid_width = 5,
892
+
.parent_map = gcc_parent_map_0,
893
+
.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
894
+
.clkr.hw.init = &(const struct clk_init_data) {
895
+
.name = "gcc_ufs_phy_unipro_core_clk_src",
896
+
.parent_data = gcc_parent_data_0,
897
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
898
+
.flags = CLK_SET_RATE_PARENT,
899
+
.ops = &clk_rcg2_shared_ops,
900
+
},
901
+
};
902
+
903
+
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
904
+
F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
905
+
F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
906
+
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
907
+
F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
908
+
{ }
909
+
};
910
+
911
+
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
912
+
.cmd_rcgr = 0x49028,
913
+
.mnd_width = 8,
914
+
.hid_width = 5,
915
+
.parent_map = gcc_parent_map_0,
916
+
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
917
+
.clkr.hw.init = &(const struct clk_init_data) {
918
+
.name = "gcc_usb30_prim_master_clk_src",
919
+
.parent_data = gcc_parent_data_0,
920
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
921
+
.flags = CLK_SET_RATE_PARENT,
922
+
.ops = &clk_rcg2_shared_ops,
923
+
},
924
+
};
925
+
926
+
static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
927
+
F(19200000, P_BI_TCXO, 1, 0, 0),
928
+
{ }
929
+
};
930
+
931
+
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
932
+
.cmd_rcgr = 0x49040,
933
+
.mnd_width = 0,
934
+
.hid_width = 5,
935
+
.parent_map = gcc_parent_map_0,
936
+
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
937
+
.clkr.hw.init = &(const struct clk_init_data) {
938
+
.name = "gcc_usb30_prim_mock_utmi_clk_src",
939
+
.parent_data = gcc_parent_data_0,
940
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
941
+
.flags = CLK_SET_RATE_PARENT,
942
+
.ops = &clk_rcg2_shared_ops,
943
+
},
944
+
};
945
+
946
+
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
947
+
.cmd_rcgr = 0x4906c,
948
+
.mnd_width = 0,
949
+
.hid_width = 5,
950
+
.parent_map = gcc_parent_map_3,
951
+
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
952
+
.clkr.hw.init = &(const struct clk_init_data) {
953
+
.name = "gcc_usb3_prim_phy_aux_clk_src",
954
+
.parent_data = gcc_parent_data_3,
955
+
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
956
+
.flags = CLK_SET_RATE_PARENT,
957
+
.ops = &clk_rcg2_shared_ops,
958
+
},
959
+
};
960
+
961
+
static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = {
962
+
F(133333333, P_GCC_GPLL3_OUT_MAIN, 3, 0, 0),
963
+
F(240000000, P_GCC_GPLL3_OUT_MAIN, 2, 0, 0),
964
+
F(365000000, P_GCC_GPLL3_OUT_MAIN, 2, 0, 0),
965
+
F(384000000, P_GCC_GPLL3_OUT_MAIN, 2, 0, 0),
966
+
{ }
967
+
};
968
+
969
+
static struct clk_rcg2 gcc_video_venus_clk_src = {
970
+
.cmd_rcgr = 0xb6004,
971
+
.mnd_width = 0,
972
+
.hid_width = 5,
973
+
.parent_map = gcc_parent_map_11,
974
+
.freq_tbl = ftbl_gcc_video_venus_clk_src,
975
+
.clkr.hw.init = &(const struct clk_init_data) {
976
+
.name = "gcc_video_venus_clk_src",
977
+
.parent_data = gcc_parent_data_11,
978
+
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
979
+
.flags = CLK_SET_RATE_PARENT,
980
+
.ops = &clk_rcg2_shared_ops,
981
+
},
982
+
};
983
+
984
+
static struct clk_regmap_div gcc_pcie_0_pipe_div2_clk_src = {
985
+
.reg = 0x7b084,
986
+
.shift = 0,
987
+
.width = 4,
988
+
.clkr.hw.init = &(const struct clk_init_data) {
989
+
.name = "gcc_pcie_0_pipe_div2_clk_src",
990
+
.parent_hws = (const struct clk_hw*[]) {
991
+
&gcc_pcie_0_pipe_clk_src.clkr.hw,
992
+
},
993
+
.num_parents = 1,
994
+
.flags = CLK_SET_RATE_PARENT,
995
+
.ops = &clk_regmap_div_ro_ops,
996
+
},
997
+
};
998
+
999
+
static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1000
+
.reg = 0x49058,
1001
+
.shift = 0,
1002
+
.width = 4,
1003
+
.clkr.hw.init = &(const struct clk_init_data) {
1004
+
.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1005
+
.parent_hws = (const struct clk_hw*[]) {
1006
+
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1007
+
},
1008
+
.num_parents = 1,
1009
+
.flags = CLK_SET_RATE_PARENT,
1010
+
.ops = &clk_regmap_div_ro_ops,
1011
+
},
1012
+
};
1013
+
1014
+
static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
1015
+
.halt_reg = 0x7b08c,
1016
+
.halt_check = BRANCH_HALT_SKIP,
1017
+
.hwcg_reg = 0x7b08c,
1018
+
.hwcg_bit = 1,
1019
+
.clkr = {
1020
+
.enable_reg = 0x62000,
1021
+
.enable_mask = BIT(12),
1022
+
.hw.init = &(const struct clk_init_data) {
1023
+
.name = "gcc_aggre_noc_pcie_0_axi_clk",
1024
+
.ops = &clk_branch2_ops,
1025
+
},
1026
+
},
1027
+
};
1028
+
1029
+
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1030
+
.halt_reg = 0x870d4,
1031
+
.halt_check = BRANCH_HALT_VOTED,
1032
+
.hwcg_reg = 0x870d4,
1033
+
.hwcg_bit = 1,
1034
+
.clkr = {
1035
+
.enable_reg = 0x870d4,
1036
+
.enable_mask = BIT(0),
1037
+
.hw.init = &(const struct clk_init_data) {
1038
+
.name = "gcc_aggre_ufs_phy_axi_clk",
1039
+
.parent_hws = (const struct clk_hw*[]) {
1040
+
&gcc_ufs_phy_axi_clk_src.clkr.hw,
1041
+
},
1042
+
.num_parents = 1,
1043
+
.flags = CLK_SET_RATE_PARENT,
1044
+
.ops = &clk_branch2_ops,
1045
+
},
1046
+
},
1047
+
};
1048
+
1049
+
static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1050
+
.halt_reg = 0x870d4,
1051
+
.halt_check = BRANCH_HALT_VOTED,
1052
+
.hwcg_reg = 0x870d4,
1053
+
.hwcg_bit = 1,
1054
+
.clkr = {
1055
+
.enable_reg = 0x870d4,
1056
+
.enable_mask = BIT(1),
1057
+
.hw.init = &(const struct clk_init_data) {
1058
+
.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1059
+
.parent_hws = (const struct clk_hw*[]) {
1060
+
&gcc_ufs_phy_axi_clk_src.clkr.hw,
1061
+
},
1062
+
.num_parents = 1,
1063
+
.flags = CLK_SET_RATE_PARENT,
1064
+
.ops = &clk_branch2_ops,
1065
+
},
1066
+
},
1067
+
};
1068
+
1069
+
static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1070
+
.halt_reg = 0x49088,
1071
+
.halt_check = BRANCH_HALT_VOTED,
1072
+
.hwcg_reg = 0x49088,
1073
+
.hwcg_bit = 1,
1074
+
.clkr = {
1075
+
.enable_reg = 0x49088,
1076
+
.enable_mask = BIT(0),
1077
+
.hw.init = &(const struct clk_init_data) {
1078
+
.name = "gcc_aggre_usb3_prim_axi_clk",
1079
+
.parent_hws = (const struct clk_hw*[]) {
1080
+
&gcc_usb30_prim_master_clk_src.clkr.hw,
1081
+
},
1082
+
.num_parents = 1,
1083
+
.flags = CLK_SET_RATE_PARENT,
1084
+
.ops = &clk_branch2_ops,
1085
+
},
1086
+
},
1087
+
};
1088
+
1089
+
static struct clk_branch gcc_boot_rom_ahb_clk = {
1090
+
.halt_reg = 0x48004,
1091
+
.halt_check = BRANCH_HALT_VOTED,
1092
+
.hwcg_reg = 0x48004,
1093
+
.hwcg_bit = 1,
1094
+
.clkr = {
1095
+
.enable_reg = 0x62000,
1096
+
.enable_mask = BIT(10),
1097
+
.hw.init = &(const struct clk_init_data) {
1098
+
.name = "gcc_boot_rom_ahb_clk",
1099
+
.ops = &clk_branch2_ops,
1100
+
},
1101
+
},
1102
+
};
1103
+
1104
+
static struct clk_branch gcc_camera_hf_axi_clk = {
1105
+
.halt_reg = 0x36010,
1106
+
.halt_check = BRANCH_HALT_SKIP,
1107
+
.hwcg_reg = 0x36010,
1108
+
.hwcg_bit = 1,
1109
+
.clkr = {
1110
+
.enable_reg = 0x36010,
1111
+
.enable_mask = BIT(0),
1112
+
.hw.init = &(const struct clk_init_data) {
1113
+
.name = "gcc_camera_hf_axi_clk",
1114
+
.ops = &clk_branch2_ops,
1115
+
},
1116
+
},
1117
+
};
1118
+
1119
+
static struct clk_branch gcc_camera_sf_axi_clk = {
1120
+
.halt_reg = 0x36014,
1121
+
.halt_check = BRANCH_HALT_SKIP,
1122
+
.hwcg_reg = 0x36014,
1123
+
.hwcg_bit = 1,
1124
+
.clkr = {
1125
+
.enable_reg = 0x36014,
1126
+
.enable_mask = BIT(0),
1127
+
.hw.init = &(const struct clk_init_data) {
1128
+
.name = "gcc_camera_sf_axi_clk",
1129
+
.ops = &clk_branch2_ops,
1130
+
},
1131
+
},
1132
+
};
1133
+
1134
+
static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
1135
+
.halt_reg = 0x20030,
1136
+
.halt_check = BRANCH_HALT_VOTED,
1137
+
.hwcg_reg = 0x20030,
1138
+
.hwcg_bit = 1,
1139
+
.clkr = {
1140
+
.enable_reg = 0x62000,
1141
+
.enable_mask = BIT(20),
1142
+
.hw.init = &(const struct clk_init_data) {
1143
+
.name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
1144
+
.ops = &clk_branch2_ops,
1145
+
},
1146
+
},
1147
+
};
1148
+
1149
+
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1150
+
.halt_reg = 0x49084,
1151
+
.halt_check = BRANCH_HALT_VOTED,
1152
+
.hwcg_reg = 0x49084,
1153
+
.hwcg_bit = 1,
1154
+
.clkr = {
1155
+
.enable_reg = 0x49084,
1156
+
.enable_mask = BIT(0),
1157
+
.hw.init = &(const struct clk_init_data) {
1158
+
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1159
+
.parent_hws = (const struct clk_hw*[]) {
1160
+
&gcc_usb30_prim_master_clk_src.clkr.hw,
1161
+
},
1162
+
.num_parents = 1,
1163
+
.flags = CLK_SET_RATE_PARENT,
1164
+
.ops = &clk_branch2_ops,
1165
+
},
1166
+
},
1167
+
};
1168
+
1169
+
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1170
+
.halt_reg = 0x81154,
1171
+
.halt_check = BRANCH_HALT_SKIP,
1172
+
.hwcg_reg = 0x81154,
1173
+
.hwcg_bit = 1,
1174
+
.clkr = {
1175
+
.enable_reg = 0x81154,
1176
+
.enable_mask = BIT(0),
1177
+
.hw.init = &(const struct clk_init_data) {
1178
+
.name = "gcc_ddrss_gpu_axi_clk",
1179
+
.ops = &clk_branch2_aon_ops,
1180
+
},
1181
+
},
1182
+
};
1183
+
1184
+
static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
1185
+
.halt_reg = 0x7b090,
1186
+
.halt_check = BRANCH_HALT_SKIP,
1187
+
.hwcg_reg = 0x7b090,
1188
+
.hwcg_bit = 1,
1189
+
.clkr = {
1190
+
.enable_reg = 0x62000,
1191
+
.enable_mask = BIT(19),
1192
+
.hw.init = &(const struct clk_init_data) {
1193
+
.name = "gcc_ddrss_pcie_sf_tbu_clk",
1194
+
.ops = &clk_branch2_ops,
1195
+
},
1196
+
},
1197
+
};
1198
+
1199
+
static struct clk_branch gcc_disp_hf_axi_clk = {
1200
+
.halt_reg = 0x3700c,
1201
+
.halt_check = BRANCH_HALT_SKIP,
1202
+
.hwcg_reg = 0x3700c,
1203
+
.hwcg_bit = 1,
1204
+
.clkr = {
1205
+
.enable_reg = 0x3700c,
1206
+
.enable_mask = BIT(0),
1207
+
.hw.init = &(const struct clk_init_data) {
1208
+
.name = "gcc_disp_hf_axi_clk",
1209
+
.ops = &clk_branch2_ops,
1210
+
},
1211
+
},
1212
+
};
1213
+
1214
+
static struct clk_branch gcc_eusb3_0_clkref_en = {
1215
+
.halt_reg = 0x9c00c,
1216
+
.halt_check = BRANCH_HALT_DELAY,
1217
+
.clkr = {
1218
+
.enable_reg = 0x9c00c,
1219
+
.enable_mask = BIT(0),
1220
+
.hw.init = &(const struct clk_init_data) {
1221
+
.name = "gcc_eusb3_0_clkref_en",
1222
+
.ops = &clk_branch2_ops,
1223
+
},
1224
+
},
1225
+
};
1226
+
1227
+
static struct clk_branch gcc_gp1_clk = {
1228
+
.halt_reg = 0x74000,
1229
+
.halt_check = BRANCH_HALT,
1230
+
.clkr = {
1231
+
.enable_reg = 0x74000,
1232
+
.enable_mask = BIT(0),
1233
+
.hw.init = &(const struct clk_init_data) {
1234
+
.name = "gcc_gp1_clk",
1235
+
.parent_hws = (const struct clk_hw*[]) {
1236
+
&gcc_gp1_clk_src.clkr.hw,
1237
+
},
1238
+
.num_parents = 1,
1239
+
.flags = CLK_SET_RATE_PARENT,
1240
+
.ops = &clk_branch2_ops,
1241
+
},
1242
+
},
1243
+
};
1244
+
1245
+
static struct clk_branch gcc_gp2_clk = {
1246
+
.halt_reg = 0x75000,
1247
+
.halt_check = BRANCH_HALT,
1248
+
.clkr = {
1249
+
.enable_reg = 0x75000,
1250
+
.enable_mask = BIT(0),
1251
+
.hw.init = &(const struct clk_init_data) {
1252
+
.name = "gcc_gp2_clk",
1253
+
.parent_hws = (const struct clk_hw*[]) {
1254
+
&gcc_gp2_clk_src.clkr.hw,
1255
+
},
1256
+
.num_parents = 1,
1257
+
.flags = CLK_SET_RATE_PARENT,
1258
+
.ops = &clk_branch2_ops,
1259
+
},
1260
+
},
1261
+
};
1262
+
1263
+
static struct clk_branch gcc_gp3_clk = {
1264
+
.halt_reg = 0x76000,
1265
+
.halt_check = BRANCH_HALT,
1266
+
.clkr = {
1267
+
.enable_reg = 0x76000,
1268
+
.enable_mask = BIT(0),
1269
+
.hw.init = &(const struct clk_init_data) {
1270
+
.name = "gcc_gp3_clk",
1271
+
.parent_hws = (const struct clk_hw*[]) {
1272
+
&gcc_gp3_clk_src.clkr.hw,
1273
+
},
1274
+
.num_parents = 1,
1275
+
.flags = CLK_SET_RATE_PARENT,
1276
+
.ops = &clk_branch2_ops,
1277
+
},
1278
+
},
1279
+
};
1280
+
1281
+
static struct clk_branch gcc_gpu_gpll0_clk_src = {
1282
+
.halt_check = BRANCH_HALT_DELAY,
1283
+
.clkr = {
1284
+
.enable_reg = 0x62000,
1285
+
.enable_mask = BIT(15),
1286
+
.hw.init = &(const struct clk_init_data) {
1287
+
.name = "gcc_gpu_gpll0_clk_src",
1288
+
.parent_hws = (const struct clk_hw*[]) {
1289
+
&gcc_gpll0.clkr.hw,
1290
+
},
1291
+
.num_parents = 1,
1292
+
.flags = CLK_SET_RATE_PARENT,
1293
+
.ops = &clk_branch2_ops,
1294
+
},
1295
+
},
1296
+
};
1297
+
1298
+
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1299
+
.halt_check = BRANCH_HALT_DELAY,
1300
+
.clkr = {
1301
+
.enable_reg = 0x62000,
1302
+
.enable_mask = BIT(16),
1303
+
.hw.init = &(const struct clk_init_data) {
1304
+
.name = "gcc_gpu_gpll0_div_clk_src",
1305
+
.parent_hws = (const struct clk_hw*[]) {
1306
+
&gcc_gpll0_out_even.clkr.hw,
1307
+
},
1308
+
.num_parents = 1,
1309
+
.flags = CLK_SET_RATE_PARENT,
1310
+
.ops = &clk_branch2_ops,
1311
+
},
1312
+
},
1313
+
};
1314
+
1315
+
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1316
+
.halt_reg = 0x81010,
1317
+
.halt_check = BRANCH_HALT_VOTED,
1318
+
.hwcg_reg = 0x81010,
1319
+
.hwcg_bit = 1,
1320
+
.clkr = {
1321
+
.enable_reg = 0x81010,
1322
+
.enable_mask = BIT(0),
1323
+
.hw.init = &(const struct clk_init_data) {
1324
+
.name = "gcc_gpu_memnoc_gfx_clk",
1325
+
.ops = &clk_branch2_ops,
1326
+
},
1327
+
},
1328
+
};
1329
+
1330
+
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1331
+
.halt_reg = 0x81018,
1332
+
.halt_check = BRANCH_HALT_DELAY,
1333
+
.clkr = {
1334
+
.enable_reg = 0x81018,
1335
+
.enable_mask = BIT(0),
1336
+
.hw.init = &(const struct clk_init_data) {
1337
+
.name = "gcc_gpu_snoc_dvm_gfx_clk",
1338
+
.ops = &clk_branch2_ops,
1339
+
},
1340
+
},
1341
+
};
1342
+
1343
+
static struct clk_branch gcc_hlos1_vote_aggre_noc_mmu_audio_tbu_clk = {
1344
+
.halt_reg = 0x8d004,
1345
+
.halt_check = BRANCH_HALT_VOTED,
1346
+
.clkr = {
1347
+
.enable_reg = 0x8d004,
1348
+
.enable_mask = BIT(0),
1349
+
.hw.init = &(const struct clk_init_data){
1350
+
.name = "gcc_hlos1_vote_aggre_noc_mmu_audio_tbu_clk",
1351
+
.ops = &clk_branch2_ops,
1352
+
},
1353
+
},
1354
+
};
1355
+
1356
+
static struct clk_branch gcc_hlos1_vote_aggre_noc_mmu_pcie_tbu_clk = {
1357
+
.halt_reg = 0x8d010,
1358
+
.halt_check = BRANCH_HALT_VOTED,
1359
+
.clkr = {
1360
+
.enable_reg = 0x8d010,
1361
+
.enable_mask = BIT(0),
1362
+
.hw.init = &(const struct clk_init_data){
1363
+
.name = "gcc_hlos1_vote_aggre_noc_mmu_pcie_tbu_clk",
1364
+
.ops = &clk_branch2_ops,
1365
+
},
1366
+
},
1367
+
};
1368
+
1369
+
static struct clk_branch gcc_hlos1_vote_aggre_noc_mmu_tbu1_clk = {
1370
+
.halt_reg = 0x8d008,
1371
+
.halt_check = BRANCH_HALT_VOTED,
1372
+
.clkr = {
1373
+
.enable_reg = 0x8d008,
1374
+
.enable_mask = BIT(0),
1375
+
.hw.init = &(const struct clk_init_data){
1376
+
.name = "gcc_hlos1_vote_aggre_noc_mmu_tbu1_clk",
1377
+
.ops = &clk_branch2_ops,
1378
+
},
1379
+
},
1380
+
};
1381
+
1382
+
static struct clk_branch gcc_hlos1_vote_aggre_noc_mmu_tbu2_clk = {
1383
+
.halt_reg = 0x8d00c,
1384
+
.halt_check = BRANCH_HALT_VOTED,
1385
+
.clkr = {
1386
+
.enable_reg = 0x8d00c,
1387
+
.enable_mask = BIT(0),
1388
+
.hw.init = &(const struct clk_init_data){
1389
+
.name = "gcc_hlos1_vote_aggre_noc_mmu_tbu2_clk",
1390
+
.ops = &clk_branch2_ops,
1391
+
},
1392
+
},
1393
+
};
1394
+
1395
+
static struct clk_branch gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_clk = {
1396
+
.halt_reg = 0x8d018,
1397
+
.halt_check = BRANCH_HALT_VOTED,
1398
+
.clkr = {
1399
+
.enable_reg = 0x8d018,
1400
+
.enable_mask = BIT(0),
1401
+
.hw.init = &(const struct clk_init_data){
1402
+
.name = "gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_clk",
1403
+
.ops = &clk_branch2_ops,
1404
+
},
1405
+
},
1406
+
};
1407
+
1408
+
static struct clk_branch gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_clk = {
1409
+
.halt_reg = 0x8d01c,
1410
+
.halt_check = BRANCH_HALT_VOTED,
1411
+
.clkr = {
1412
+
.enable_reg = 0x8d01c,
1413
+
.enable_mask = BIT(0),
1414
+
.hw.init = &(const struct clk_init_data){
1415
+
.name = "gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_clk",
1416
+
.ops = &clk_branch2_ops,
1417
+
},
1418
+
},
1419
+
};
1420
+
1421
+
static struct clk_branch gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_clk = {
1422
+
.halt_reg = 0x8d014,
1423
+
.halt_check = BRANCH_HALT_VOTED,
1424
+
.clkr = {
1425
+
.enable_reg = 0x8d014,
1426
+
.enable_mask = BIT(0),
1427
+
.hw.init = &(const struct clk_init_data){
1428
+
.name = "gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_clk",
1429
+
.ops = &clk_branch2_ops,
1430
+
},
1431
+
},
1432
+
};
1433
+
1434
+
static struct clk_branch gcc_hlos1_vote_mmu_tcu_clk = {
1435
+
.halt_reg = 0x8d02c,
1436
+
.halt_check = BRANCH_HALT_VOTED,
1437
+
.clkr = {
1438
+
.enable_reg = 0x8d02c,
1439
+
.enable_mask = BIT(0),
1440
+
.hw.init = &(const struct clk_init_data){
1441
+
.name = "gcc_hlos1_vote_mmu_tcu_clk",
1442
+
.ops = &clk_branch2_ops,
1443
+
},
1444
+
},
1445
+
};
1446
+
1447
+
static struct clk_branch gcc_pcie_0_aux_clk = {
1448
+
.halt_reg = 0x7b034,
1449
+
.halt_check = BRANCH_HALT_VOTED,
1450
+
.clkr = {
1451
+
.enable_reg = 0x62008,
1452
+
.enable_mask = BIT(3),
1453
+
.hw.init = &(const struct clk_init_data) {
1454
+
.name = "gcc_pcie_0_aux_clk",
1455
+
.parent_hws = (const struct clk_hw*[]) {
1456
+
&gcc_pcie_0_aux_clk_src.clkr.hw,
1457
+
},
1458
+
.num_parents = 1,
1459
+
.flags = CLK_SET_RATE_PARENT,
1460
+
.ops = &clk_branch2_ops,
1461
+
},
1462
+
},
1463
+
};
1464
+
1465
+
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1466
+
.halt_reg = 0x7b030,
1467
+
.halt_check = BRANCH_HALT_VOTED,
1468
+
.hwcg_reg = 0x7b030,
1469
+
.hwcg_bit = 1,
1470
+
.clkr = {
1471
+
.enable_reg = 0x62008,
1472
+
.enable_mask = BIT(2),
1473
+
.hw.init = &(const struct clk_init_data) {
1474
+
.name = "gcc_pcie_0_cfg_ahb_clk",
1475
+
.ops = &clk_branch2_ops,
1476
+
},
1477
+
},
1478
+
};
1479
+
1480
+
static struct clk_branch gcc_pcie_0_clkref_en = {
1481
+
.halt_reg = 0x9c004,
1482
+
.halt_check = BRANCH_HALT_DELAY,
1483
+
.clkr = {
1484
+
.enable_reg = 0x9c004,
1485
+
.enable_mask = BIT(0),
1486
+
.hw.init = &(const struct clk_init_data) {
1487
+
.name = "gcc_pcie_0_clkref_en",
1488
+
.ops = &clk_branch2_ops,
1489
+
},
1490
+
},
1491
+
};
1492
+
1493
+
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1494
+
.halt_reg = 0x7b028,
1495
+
.halt_check = BRANCH_HALT_SKIP,
1496
+
.clkr = {
1497
+
.enable_reg = 0x62008,
1498
+
.enable_mask = BIT(1),
1499
+
.hw.init = &(const struct clk_init_data) {
1500
+
.name = "gcc_pcie_0_mstr_axi_clk",
1501
+
.ops = &clk_branch2_ops,
1502
+
},
1503
+
},
1504
+
};
1505
+
1506
+
static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
1507
+
.halt_reg = 0x7b044,
1508
+
.halt_check = BRANCH_HALT_VOTED,
1509
+
.clkr = {
1510
+
.enable_reg = 0x62000,
1511
+
.enable_mask = BIT(22),
1512
+
.hw.init = &(const struct clk_init_data) {
1513
+
.name = "gcc_pcie_0_phy_rchng_clk",
1514
+
.parent_hws = (const struct clk_hw*[]) {
1515
+
&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1516
+
},
1517
+
.num_parents = 1,
1518
+
.flags = CLK_SET_RATE_PARENT,
1519
+
.ops = &clk_branch2_ops,
1520
+
},
1521
+
},
1522
+
};
1523
+
1524
+
static struct clk_branch gcc_pcie_0_pipe_clk = {
1525
+
.halt_reg = 0x7b03c,
1526
+
.halt_check = BRANCH_HALT_SKIP,
1527
+
.clkr = {
1528
+
.enable_reg = 0x62008,
1529
+
.enable_mask = BIT(4),
1530
+
.hw.init = &(const struct clk_init_data) {
1531
+
.name = "gcc_pcie_0_pipe_clk",
1532
+
.parent_hws = (const struct clk_hw*[]) {
1533
+
&gcc_pcie_0_pipe_clk_src.clkr.hw,
1534
+
},
1535
+
.num_parents = 1,
1536
+
.flags = CLK_SET_RATE_PARENT,
1537
+
.ops = &clk_branch2_ops,
1538
+
},
1539
+
},
1540
+
};
1541
+
1542
+
static struct clk_branch gcc_pcie_0_pipe_div2_clk = {
1543
+
.halt_reg = 0x7b094,
1544
+
.halt_check = BRANCH_HALT_SKIP,
1545
+
.clkr = {
1546
+
.enable_reg = 0x62010,
1547
+
.enable_mask = BIT(26),
1548
+
.hw.init = &(const struct clk_init_data) {
1549
+
.name = "gcc_pcie_0_pipe_div2_clk",
1550
+
.parent_hws = (const struct clk_hw*[]) {
1551
+
&gcc_pcie_0_pipe_div2_clk_src.clkr.hw,
1552
+
},
1553
+
.num_parents = 1,
1554
+
.flags = CLK_SET_RATE_PARENT,
1555
+
.ops = &clk_branch2_ops,
1556
+
},
1557
+
},
1558
+
};
1559
+
1560
+
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1561
+
.halt_reg = 0x7b020,
1562
+
.halt_check = BRANCH_HALT_VOTED,
1563
+
.hwcg_reg = 0x7b020,
1564
+
.hwcg_bit = 1,
1565
+
.clkr = {
1566
+
.enable_reg = 0x62008,
1567
+
.enable_mask = BIT(0),
1568
+
.hw.init = &(const struct clk_init_data) {
1569
+
.name = "gcc_pcie_0_slv_axi_clk",
1570
+
.ops = &clk_branch2_ops,
1571
+
},
1572
+
},
1573
+
};
1574
+
1575
+
static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1576
+
.halt_reg = 0x7b01c,
1577
+
.halt_check = BRANCH_HALT_VOTED,
1578
+
.clkr = {
1579
+
.enable_reg = 0x62008,
1580
+
.enable_mask = BIT(5),
1581
+
.hw.init = &(const struct clk_init_data) {
1582
+
.name = "gcc_pcie_0_slv_q2a_axi_clk",
1583
+
.ops = &clk_branch2_ops,
1584
+
},
1585
+
},
1586
+
};
1587
+
1588
+
static struct clk_branch gcc_pdm2_clk = {
1589
+
.halt_reg = 0x4300c,
1590
+
.halt_check = BRANCH_HALT,
1591
+
.clkr = {
1592
+
.enable_reg = 0x4300c,
1593
+
.enable_mask = BIT(0),
1594
+
.hw.init = &(const struct clk_init_data) {
1595
+
.name = "gcc_pdm2_clk",
1596
+
.parent_hws = (const struct clk_hw*[]) {
1597
+
&gcc_pdm2_clk_src.clkr.hw,
1598
+
},
1599
+
.num_parents = 1,
1600
+
.flags = CLK_SET_RATE_PARENT,
1601
+
.ops = &clk_branch2_ops,
1602
+
},
1603
+
},
1604
+
};
1605
+
1606
+
static struct clk_branch gcc_pdm_ahb_clk = {
1607
+
.halt_reg = 0x43004,
1608
+
.halt_check = BRANCH_HALT_VOTED,
1609
+
.hwcg_reg = 0x43004,
1610
+
.hwcg_bit = 1,
1611
+
.clkr = {
1612
+
.enable_reg = 0x43004,
1613
+
.enable_mask = BIT(0),
1614
+
.hw.init = &(const struct clk_init_data) {
1615
+
.name = "gcc_pdm_ahb_clk",
1616
+
.ops = &clk_branch2_ops,
1617
+
},
1618
+
},
1619
+
};
1620
+
1621
+
static struct clk_branch gcc_pdm_xo4_clk = {
1622
+
.halt_reg = 0x43008,
1623
+
.halt_check = BRANCH_HALT,
1624
+
.clkr = {
1625
+
.enable_reg = 0x43008,
1626
+
.enable_mask = BIT(0),
1627
+
.hw.init = &(const struct clk_init_data) {
1628
+
.name = "gcc_pdm_xo4_clk",
1629
+
.ops = &clk_branch2_ops,
1630
+
},
1631
+
},
1632
+
};
1633
+
1634
+
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
1635
+
.halt_reg = 0x36008,
1636
+
.halt_check = BRANCH_HALT_VOTED,
1637
+
.hwcg_reg = 0x36008,
1638
+
.hwcg_bit = 1,
1639
+
.clkr = {
1640
+
.enable_reg = 0x36008,
1641
+
.enable_mask = BIT(0),
1642
+
.hw.init = &(const struct clk_init_data) {
1643
+
.name = "gcc_qmip_camera_nrt_ahb_clk",
1644
+
.ops = &clk_branch2_ops,
1645
+
},
1646
+
},
1647
+
};
1648
+
1649
+
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
1650
+
.halt_reg = 0x3600c,
1651
+
.halt_check = BRANCH_HALT_VOTED,
1652
+
.hwcg_reg = 0x3600c,
1653
+
.hwcg_bit = 1,
1654
+
.clkr = {
1655
+
.enable_reg = 0x3600c,
1656
+
.enable_mask = BIT(0),
1657
+
.hw.init = &(const struct clk_init_data) {
1658
+
.name = "gcc_qmip_camera_rt_ahb_clk",
1659
+
.ops = &clk_branch2_ops,
1660
+
},
1661
+
},
1662
+
};
1663
+
1664
+
static struct clk_branch gcc_qmip_disp_ahb_clk = {
1665
+
.halt_reg = 0x37008,
1666
+
.halt_check = BRANCH_HALT_VOTED,
1667
+
.hwcg_reg = 0x37008,
1668
+
.hwcg_bit = 1,
1669
+
.clkr = {
1670
+
.enable_reg = 0x37008,
1671
+
.enable_mask = BIT(0),
1672
+
.hw.init = &(const struct clk_init_data) {
1673
+
.name = "gcc_qmip_disp_ahb_clk",
1674
+
.ops = &clk_branch2_ops,
1675
+
},
1676
+
},
1677
+
};
1678
+
1679
+
static struct clk_branch gcc_qmip_gpu_ahb_clk = {
1680
+
.halt_reg = 0x81008,
1681
+
.halt_check = BRANCH_HALT_VOTED,
1682
+
.hwcg_reg = 0x81008,
1683
+
.hwcg_bit = 1,
1684
+
.clkr = {
1685
+
.enable_reg = 0x81008,
1686
+
.enable_mask = BIT(0),
1687
+
.hw.init = &(const struct clk_init_data) {
1688
+
.name = "gcc_qmip_gpu_ahb_clk",
1689
+
.ops = &clk_branch2_ops,
1690
+
},
1691
+
},
1692
+
};
1693
+
1694
+
static struct clk_branch gcc_qmip_pcie_ahb_clk = {
1695
+
.halt_reg = 0x7b018,
1696
+
.halt_check = BRANCH_HALT_VOTED,
1697
+
.hwcg_reg = 0x7b018,
1698
+
.hwcg_bit = 1,
1699
+
.clkr = {
1700
+
.enable_reg = 0x7b018,
1701
+
.enable_mask = BIT(0),
1702
+
.hw.init = &(const struct clk_init_data) {
1703
+
.name = "gcc_qmip_pcie_ahb_clk",
1704
+
.ops = &clk_branch2_ops,
1705
+
},
1706
+
},
1707
+
};
1708
+
1709
+
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
1710
+
.halt_reg = 0x42008,
1711
+
.halt_check = BRANCH_HALT_VOTED,
1712
+
.hwcg_reg = 0x42008,
1713
+
.hwcg_bit = 1,
1714
+
.clkr = {
1715
+
.enable_reg = 0x42008,
1716
+
.enable_mask = BIT(0),
1717
+
.hw.init = &(const struct clk_init_data) {
1718
+
.name = "gcc_qmip_video_vcodec_ahb_clk",
1719
+
.ops = &clk_branch2_ops,
1720
+
},
1721
+
},
1722
+
};
1723
+
1724
+
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1725
+
.halt_reg = 0x3300c,
1726
+
.halt_check = BRANCH_HALT_VOTED,
1727
+
.clkr = {
1728
+
.enable_reg = 0x62008,
1729
+
.enable_mask = BIT(9),
1730
+
.hw.init = &(const struct clk_init_data) {
1731
+
.name = "gcc_qupv3_wrap0_core_2x_clk",
1732
+
.ops = &clk_branch2_ops,
1733
+
},
1734
+
},
1735
+
};
1736
+
1737
+
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1738
+
.halt_reg = 0x33000,
1739
+
.halt_check = BRANCH_HALT_VOTED,
1740
+
.clkr = {
1741
+
.enable_reg = 0x62008,
1742
+
.enable_mask = BIT(8),
1743
+
.hw.init = &(const struct clk_init_data) {
1744
+
.name = "gcc_qupv3_wrap0_core_clk",
1745
+
.ops = &clk_branch2_ops,
1746
+
},
1747
+
},
1748
+
};
1749
+
1750
+
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1751
+
.halt_reg = 0x2700c,
1752
+
.halt_check = BRANCH_HALT_VOTED,
1753
+
.clkr = {
1754
+
.enable_reg = 0x62008,
1755
+
.enable_mask = BIT(10),
1756
+
.hw.init = &(const struct clk_init_data) {
1757
+
.name = "gcc_qupv3_wrap0_s0_clk",
1758
+
.parent_hws = (const struct clk_hw*[]) {
1759
+
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1760
+
},
1761
+
.num_parents = 1,
1762
+
.flags = CLK_SET_RATE_PARENT,
1763
+
.ops = &clk_branch2_ops,
1764
+
},
1765
+
},
1766
+
};
1767
+
1768
+
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1769
+
.halt_reg = 0x27140,
1770
+
.halt_check = BRANCH_HALT_VOTED,
1771
+
.clkr = {
1772
+
.enable_reg = 0x62008,
1773
+
.enable_mask = BIT(11),
1774
+
.hw.init = &(const struct clk_init_data) {
1775
+
.name = "gcc_qupv3_wrap0_s1_clk",
1776
+
.parent_hws = (const struct clk_hw*[]) {
1777
+
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1778
+
},
1779
+
.num_parents = 1,
1780
+
.flags = CLK_SET_RATE_PARENT,
1781
+
.ops = &clk_branch2_ops,
1782
+
},
1783
+
},
1784
+
};
1785
+
1786
+
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1787
+
.halt_reg = 0x27274,
1788
+
.halt_check = BRANCH_HALT_VOTED,
1789
+
.clkr = {
1790
+
.enable_reg = 0x62008,
1791
+
.enable_mask = BIT(12),
1792
+
.hw.init = &(const struct clk_init_data) {
1793
+
.name = "gcc_qupv3_wrap0_s2_clk",
1794
+
.parent_hws = (const struct clk_hw*[]) {
1795
+
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1796
+
},
1797
+
.num_parents = 1,
1798
+
.flags = CLK_SET_RATE_PARENT,
1799
+
.ops = &clk_branch2_ops,
1800
+
},
1801
+
},
1802
+
};
1803
+
1804
+
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1805
+
.halt_reg = 0x273a8,
1806
+
.halt_check = BRANCH_HALT_VOTED,
1807
+
.clkr = {
1808
+
.enable_reg = 0x62008,
1809
+
.enable_mask = BIT(13),
1810
+
.hw.init = &(const struct clk_init_data) {
1811
+
.name = "gcc_qupv3_wrap0_s3_clk",
1812
+
.parent_hws = (const struct clk_hw*[]) {
1813
+
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1814
+
},
1815
+
.num_parents = 1,
1816
+
.flags = CLK_SET_RATE_PARENT,
1817
+
.ops = &clk_branch2_ops,
1818
+
},
1819
+
},
1820
+
};
1821
+
1822
+
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
1823
+
.halt_reg = 0x274dc,
1824
+
.halt_check = BRANCH_HALT_VOTED,
1825
+
.clkr = {
1826
+
.enable_reg = 0x62008,
1827
+
.enable_mask = BIT(14),
1828
+
.hw.init = &(const struct clk_init_data) {
1829
+
.name = "gcc_qupv3_wrap0_s4_clk",
1830
+
.parent_hws = (const struct clk_hw*[]) {
1831
+
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
1832
+
},
1833
+
.num_parents = 1,
1834
+
.flags = CLK_SET_RATE_PARENT,
1835
+
.ops = &clk_branch2_ops,
1836
+
},
1837
+
},
1838
+
};
1839
+
1840
+
static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
1841
+
.halt_reg = 0x3314c,
1842
+
.halt_check = BRANCH_HALT_VOTED,
1843
+
.clkr = {
1844
+
.enable_reg = 0x62008,
1845
+
.enable_mask = BIT(18),
1846
+
.hw.init = &(const struct clk_init_data) {
1847
+
.name = "gcc_qupv3_wrap1_core_2x_clk",
1848
+
.ops = &clk_branch2_ops,
1849
+
},
1850
+
},
1851
+
};
1852
+
1853
+
static struct clk_branch gcc_qupv3_wrap1_core_clk = {
1854
+
.halt_reg = 0x33140,
1855
+
.halt_check = BRANCH_HALT_VOTED,
1856
+
.clkr = {
1857
+
.enable_reg = 0x62008,
1858
+
.enable_mask = BIT(19),
1859
+
.hw.init = &(const struct clk_init_data) {
1860
+
.name = "gcc_qupv3_wrap1_core_clk",
1861
+
.ops = &clk_branch2_ops,
1862
+
},
1863
+
},
1864
+
};
1865
+
1866
+
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
1867
+
.halt_reg = 0x2800c,
1868
+
.halt_check = BRANCH_HALT_VOTED,
1869
+
.clkr = {
1870
+
.enable_reg = 0x62008,
1871
+
.enable_mask = BIT(22),
1872
+
.hw.init = &(const struct clk_init_data) {
1873
+
.name = "gcc_qupv3_wrap1_s0_clk",
1874
+
.parent_hws = (const struct clk_hw*[]) {
1875
+
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
1876
+
},
1877
+
.num_parents = 1,
1878
+
.flags = CLK_SET_RATE_PARENT,
1879
+
.ops = &clk_branch2_ops,
1880
+
},
1881
+
},
1882
+
};
1883
+
1884
+
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
1885
+
.halt_reg = 0x28140,
1886
+
.halt_check = BRANCH_HALT_VOTED,
1887
+
.clkr = {
1888
+
.enable_reg = 0x62008,
1889
+
.enable_mask = BIT(23),
1890
+
.hw.init = &(const struct clk_init_data) {
1891
+
.name = "gcc_qupv3_wrap1_s1_clk",
1892
+
.parent_hws = (const struct clk_hw*[]) {
1893
+
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
1894
+
},
1895
+
.num_parents = 1,
1896
+
.flags = CLK_SET_RATE_PARENT,
1897
+
.ops = &clk_branch2_ops,
1898
+
},
1899
+
},
1900
+
};
1901
+
1902
+
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
1903
+
.halt_reg = 0x28274,
1904
+
.halt_check = BRANCH_HALT_VOTED,
1905
+
.clkr = {
1906
+
.enable_reg = 0x62008,
1907
+
.enable_mask = BIT(24),
1908
+
.hw.init = &(const struct clk_init_data) {
1909
+
.name = "gcc_qupv3_wrap1_s2_clk",
1910
+
.parent_hws = (const struct clk_hw*[]) {
1911
+
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
1912
+
},
1913
+
.num_parents = 1,
1914
+
.flags = CLK_SET_RATE_PARENT,
1915
+
.ops = &clk_branch2_ops,
1916
+
},
1917
+
},
1918
+
};
1919
+
1920
+
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
1921
+
.halt_reg = 0x283a8,
1922
+
.halt_check = BRANCH_HALT_VOTED,
1923
+
.clkr = {
1924
+
.enable_reg = 0x62008,
1925
+
.enable_mask = BIT(25),
1926
+
.hw.init = &(const struct clk_init_data) {
1927
+
.name = "gcc_qupv3_wrap1_s3_clk",
1928
+
.parent_hws = (const struct clk_hw*[]) {
1929
+
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
1930
+
},
1931
+
.num_parents = 1,
1932
+
.flags = CLK_SET_RATE_PARENT,
1933
+
.ops = &clk_branch2_ops,
1934
+
},
1935
+
},
1936
+
};
1937
+
1938
+
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
1939
+
.halt_reg = 0x284dc,
1940
+
.halt_check = BRANCH_HALT_VOTED,
1941
+
.clkr = {
1942
+
.enable_reg = 0x62008,
1943
+
.enable_mask = BIT(26),
1944
+
.hw.init = &(const struct clk_init_data) {
1945
+
.name = "gcc_qupv3_wrap1_s4_clk",
1946
+
.parent_hws = (const struct clk_hw*[]) {
1947
+
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
1948
+
},
1949
+
.num_parents = 1,
1950
+
.flags = CLK_SET_RATE_PARENT,
1951
+
.ops = &clk_branch2_ops,
1952
+
},
1953
+
},
1954
+
};
1955
+
1956
+
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
1957
+
.halt_reg = 0x27004,
1958
+
.halt_check = BRANCH_HALT_VOTED,
1959
+
.hwcg_reg = 0x27004,
1960
+
.hwcg_bit = 1,
1961
+
.clkr = {
1962
+
.enable_reg = 0x62008,
1963
+
.enable_mask = BIT(6),
1964
+
.hw.init = &(const struct clk_init_data) {
1965
+
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
1966
+
.ops = &clk_branch2_ops,
1967
+
},
1968
+
},
1969
+
};
1970
+
1971
+
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
1972
+
.halt_reg = 0x27008,
1973
+
.halt_check = BRANCH_HALT_VOTED,
1974
+
.hwcg_reg = 0x27008,
1975
+
.hwcg_bit = 1,
1976
+
.clkr = {
1977
+
.enable_reg = 0x62008,
1978
+
.enable_mask = BIT(7),
1979
+
.hw.init = &(const struct clk_init_data) {
1980
+
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
1981
+
.ops = &clk_branch2_ops,
1982
+
},
1983
+
},
1984
+
};
1985
+
1986
+
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
1987
+
.halt_reg = 0x28004,
1988
+
.halt_check = BRANCH_HALT_VOTED,
1989
+
.hwcg_reg = 0x28004,
1990
+
.hwcg_bit = 1,
1991
+
.clkr = {
1992
+
.enable_reg = 0x62008,
1993
+
.enable_mask = BIT(20),
1994
+
.hw.init = &(const struct clk_init_data) {
1995
+
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
1996
+
.ops = &clk_branch2_ops,
1997
+
},
1998
+
},
1999
+
};
2000
+
2001
+
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2002
+
.halt_reg = 0x28008,
2003
+
.halt_check = BRANCH_HALT_VOTED,
2004
+
.hwcg_reg = 0x28008,
2005
+
.hwcg_bit = 1,
2006
+
.clkr = {
2007
+
.enable_reg = 0x62008,
2008
+
.enable_mask = BIT(21),
2009
+
.hw.init = &(const struct clk_init_data) {
2010
+
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
2011
+
.ops = &clk_branch2_ops,
2012
+
},
2013
+
},
2014
+
};
2015
+
2016
+
static struct clk_branch gcc_sdcc1_ahb_clk = {
2017
+
.halt_reg = 0xb3004,
2018
+
.halt_check = BRANCH_HALT,
2019
+
.clkr = {
2020
+
.enable_reg = 0xb3004,
2021
+
.enable_mask = BIT(0),
2022
+
.hw.init = &(const struct clk_init_data) {
2023
+
.name = "gcc_sdcc1_ahb_clk",
2024
+
.ops = &clk_branch2_ops,
2025
+
},
2026
+
},
2027
+
};
2028
+
2029
+
static struct clk_branch gcc_sdcc1_apps_clk = {
2030
+
.halt_reg = 0xb3008,
2031
+
.halt_check = BRANCH_HALT,
2032
+
.clkr = {
2033
+
.enable_reg = 0xb3008,
2034
+
.enable_mask = BIT(0),
2035
+
.hw.init = &(const struct clk_init_data) {
2036
+
.name = "gcc_sdcc1_apps_clk",
2037
+
.parent_hws = (const struct clk_hw*[]) {
2038
+
&gcc_sdcc1_apps_clk_src.clkr.hw,
2039
+
},
2040
+
.num_parents = 1,
2041
+
.flags = CLK_SET_RATE_PARENT,
2042
+
.ops = &clk_branch2_ops,
2043
+
},
2044
+
},
2045
+
};
2046
+
2047
+
static struct clk_branch gcc_sdcc1_ice_core_clk = {
2048
+
.halt_reg = 0xb3028,
2049
+
.halt_check = BRANCH_HALT_VOTED,
2050
+
.hwcg_reg = 0xb3028,
2051
+
.hwcg_bit = 1,
2052
+
.clkr = {
2053
+
.enable_reg = 0xb3028,
2054
+
.enable_mask = BIT(0),
2055
+
.hw.init = &(const struct clk_init_data) {
2056
+
.name = "gcc_sdcc1_ice_core_clk",
2057
+
.parent_hws = (const struct clk_hw*[]) {
2058
+
&gcc_sdcc1_ice_core_clk_src.clkr.hw,
2059
+
},
2060
+
.num_parents = 1,
2061
+
.flags = CLK_SET_RATE_PARENT,
2062
+
.ops = &clk_branch2_ops,
2063
+
},
2064
+
},
2065
+
};
2066
+
2067
+
static struct clk_branch gcc_sdcc2_ahb_clk = {
2068
+
.halt_reg = 0x2400c,
2069
+
.halt_check = BRANCH_HALT,
2070
+
.clkr = {
2071
+
.enable_reg = 0x2400c,
2072
+
.enable_mask = BIT(0),
2073
+
.hw.init = &(const struct clk_init_data) {
2074
+
.name = "gcc_sdcc2_ahb_clk",
2075
+
.ops = &clk_branch2_ops,
2076
+
},
2077
+
},
2078
+
};
2079
+
2080
+
static struct clk_branch gcc_sdcc2_apps_clk = {
2081
+
.halt_reg = 0x24004,
2082
+
.halt_check = BRANCH_HALT,
2083
+
.clkr = {
2084
+
.enable_reg = 0x24004,
2085
+
.enable_mask = BIT(0),
2086
+
.hw.init = &(const struct clk_init_data) {
2087
+
.name = "gcc_sdcc2_apps_clk",
2088
+
.parent_hws = (const struct clk_hw*[]) {
2089
+
&gcc_sdcc2_apps_clk_src.clkr.hw,
2090
+
},
2091
+
.num_parents = 1,
2092
+
.flags = CLK_SET_RATE_PARENT,
2093
+
.ops = &clk_branch2_ops,
2094
+
},
2095
+
},
2096
+
};
2097
+
2098
+
static struct clk_branch gcc_ufs_0_clkref_en = {
2099
+
.halt_reg = 0x9c000,
2100
+
.halt_check = BRANCH_HALT_DELAY,
2101
+
.clkr = {
2102
+
.enable_reg = 0x9c000,
2103
+
.enable_mask = BIT(0),
2104
+
.hw.init = &(const struct clk_init_data) {
2105
+
.name = "gcc_ufs_0_clkref_en",
2106
+
.ops = &clk_branch2_ops,
2107
+
},
2108
+
},
2109
+
};
2110
+
2111
+
static struct clk_branch gcc_ufs_pad_clkref_en = {
2112
+
.halt_reg = 0x9c024,
2113
+
.halt_check = BRANCH_HALT_DELAY,
2114
+
.clkr = {
2115
+
.enable_reg = 0x9c024,
2116
+
.enable_mask = BIT(0),
2117
+
.hw.init = &(const struct clk_init_data) {
2118
+
.name = "gcc_ufs_pad_clkref_en",
2119
+
.ops = &clk_branch2_ops,
2120
+
},
2121
+
},
2122
+
};
2123
+
2124
+
static struct clk_branch gcc_ufs_phy_ahb_clk = {
2125
+
.halt_reg = 0x87020,
2126
+
.halt_check = BRANCH_HALT_VOTED,
2127
+
.hwcg_reg = 0x87020,
2128
+
.hwcg_bit = 1,
2129
+
.clkr = {
2130
+
.enable_reg = 0x87020,
2131
+
.enable_mask = BIT(0),
2132
+
.hw.init = &(const struct clk_init_data) {
2133
+
.name = "gcc_ufs_phy_ahb_clk",
2134
+
.ops = &clk_branch2_ops,
2135
+
},
2136
+
},
2137
+
};
2138
+
2139
+
static struct clk_branch gcc_ufs_phy_axi_clk = {
2140
+
.halt_reg = 0x87018,
2141
+
.halt_check = BRANCH_HALT_VOTED,
2142
+
.hwcg_reg = 0x87018,
2143
+
.hwcg_bit = 1,
2144
+
.clkr = {
2145
+
.enable_reg = 0x87018,
2146
+
.enable_mask = BIT(0),
2147
+
.hw.init = &(const struct clk_init_data) {
2148
+
.name = "gcc_ufs_phy_axi_clk",
2149
+
.parent_hws = (const struct clk_hw*[]) {
2150
+
&gcc_ufs_phy_axi_clk_src.clkr.hw,
2151
+
},
2152
+
.num_parents = 1,
2153
+
.flags = CLK_SET_RATE_PARENT,
2154
+
.ops = &clk_branch2_ops,
2155
+
},
2156
+
},
2157
+
};
2158
+
2159
+
static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2160
+
.halt_reg = 0x87018,
2161
+
.halt_check = BRANCH_HALT_VOTED,
2162
+
.hwcg_reg = 0x87018,
2163
+
.hwcg_bit = 1,
2164
+
.clkr = {
2165
+
.enable_reg = 0x87018,
2166
+
.enable_mask = BIT(1),
2167
+
.hw.init = &(const struct clk_init_data) {
2168
+
.name = "gcc_ufs_phy_axi_hw_ctl_clk",
2169
+
.parent_hws = (const struct clk_hw*[]) {
2170
+
&gcc_ufs_phy_axi_clk_src.clkr.hw,
2171
+
},
2172
+
.num_parents = 1,
2173
+
.flags = CLK_SET_RATE_PARENT,
2174
+
.ops = &clk_branch2_ops,
2175
+
},
2176
+
},
2177
+
};
2178
+
2179
+
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2180
+
.halt_reg = 0x8706c,
2181
+
.halt_check = BRANCH_HALT_VOTED,
2182
+
.hwcg_reg = 0x8706c,
2183
+
.hwcg_bit = 1,
2184
+
.clkr = {
2185
+
.enable_reg = 0x8706c,
2186
+
.enable_mask = BIT(0),
2187
+
.hw.init = &(const struct clk_init_data) {
2188
+
.name = "gcc_ufs_phy_ice_core_clk",
2189
+
.parent_hws = (const struct clk_hw*[]) {
2190
+
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2191
+
},
2192
+
.num_parents = 1,
2193
+
.flags = CLK_SET_RATE_PARENT,
2194
+
.ops = &clk_branch2_ops,
2195
+
},
2196
+
},
2197
+
};
2198
+
2199
+
static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
2200
+
.halt_reg = 0x8706c,
2201
+
.halt_check = BRANCH_HALT_VOTED,
2202
+
.hwcg_reg = 0x8706c,
2203
+
.hwcg_bit = 1,
2204
+
.clkr = {
2205
+
.enable_reg = 0x8706c,
2206
+
.enable_mask = BIT(1),
2207
+
.hw.init = &(const struct clk_init_data) {
2208
+
.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
2209
+
.parent_hws = (const struct clk_hw*[]) {
2210
+
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2211
+
},
2212
+
.num_parents = 1,
2213
+
.flags = CLK_SET_RATE_PARENT,
2214
+
.ops = &clk_branch2_ops,
2215
+
},
2216
+
},
2217
+
};
2218
+
2219
+
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2220
+
.halt_reg = 0x870a4,
2221
+
.halt_check = BRANCH_HALT_VOTED,
2222
+
.hwcg_reg = 0x870a4,
2223
+
.hwcg_bit = 1,
2224
+
.clkr = {
2225
+
.enable_reg = 0x870a4,
2226
+
.enable_mask = BIT(0),
2227
+
.hw.init = &(const struct clk_init_data) {
2228
+
.name = "gcc_ufs_phy_phy_aux_clk",
2229
+
.parent_hws = (const struct clk_hw*[]) {
2230
+
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2231
+
},
2232
+
.num_parents = 1,
2233
+
.flags = CLK_SET_RATE_PARENT,
2234
+
.ops = &clk_branch2_ops,
2235
+
},
2236
+
},
2237
+
};
2238
+
2239
+
static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
2240
+
.halt_reg = 0x870a4,
2241
+
.halt_check = BRANCH_HALT_VOTED,
2242
+
.hwcg_reg = 0x870a4,
2243
+
.hwcg_bit = 1,
2244
+
.clkr = {
2245
+
.enable_reg = 0x870a4,
2246
+
.enable_mask = BIT(1),
2247
+
.hw.init = &(const struct clk_init_data) {
2248
+
.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
2249
+
.parent_hws = (const struct clk_hw*[]) {
2250
+
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2251
+
},
2252
+
.num_parents = 1,
2253
+
.flags = CLK_SET_RATE_PARENT,
2254
+
.ops = &clk_branch2_ops,
2255
+
},
2256
+
},
2257
+
};
2258
+
2259
+
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2260
+
.halt_reg = 0x87028,
2261
+
.halt_check = BRANCH_HALT_DELAY,
2262
+
.clkr = {
2263
+
.enable_reg = 0x87028,
2264
+
.enable_mask = BIT(0),
2265
+
.hw.init = &(const struct clk_init_data) {
2266
+
.name = "gcc_ufs_phy_rx_symbol_0_clk",
2267
+
.parent_hws = (const struct clk_hw*[]) {
2268
+
&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
2269
+
},
2270
+
.num_parents = 1,
2271
+
.flags = CLK_SET_RATE_PARENT,
2272
+
.ops = &clk_branch2_ops,
2273
+
},
2274
+
},
2275
+
};
2276
+
2277
+
static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2278
+
.halt_reg = 0x870c0,
2279
+
.halt_check = BRANCH_HALT_DELAY,
2280
+
.clkr = {
2281
+
.enable_reg = 0x870c0,
2282
+
.enable_mask = BIT(0),
2283
+
.hw.init = &(const struct clk_init_data) {
2284
+
.name = "gcc_ufs_phy_rx_symbol_1_clk",
2285
+
.parent_hws = (const struct clk_hw*[]) {
2286
+
&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
2287
+
},
2288
+
.num_parents = 1,
2289
+
.flags = CLK_SET_RATE_PARENT,
2290
+
.ops = &clk_branch2_ops,
2291
+
},
2292
+
},
2293
+
};
2294
+
2295
+
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2296
+
.halt_reg = 0x87024,
2297
+
.halt_check = BRANCH_HALT_DELAY,
2298
+
.clkr = {
2299
+
.enable_reg = 0x87024,
2300
+
.enable_mask = BIT(0),
2301
+
.hw.init = &(const struct clk_init_data) {
2302
+
.name = "gcc_ufs_phy_tx_symbol_0_clk",
2303
+
.parent_hws = (const struct clk_hw*[]) {
2304
+
&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
2305
+
},
2306
+
.num_parents = 1,
2307
+
.flags = CLK_SET_RATE_PARENT,
2308
+
.ops = &clk_branch2_ops,
2309
+
},
2310
+
},
2311
+
};
2312
+
2313
+
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2314
+
.halt_reg = 0x87064,
2315
+
.halt_check = BRANCH_HALT_VOTED,
2316
+
.hwcg_reg = 0x87064,
2317
+
.hwcg_bit = 1,
2318
+
.clkr = {
2319
+
.enable_reg = 0x87064,
2320
+
.enable_mask = BIT(0),
2321
+
.hw.init = &(const struct clk_init_data) {
2322
+
.name = "gcc_ufs_phy_unipro_core_clk",
2323
+
.parent_hws = (const struct clk_hw*[]) {
2324
+
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2325
+
},
2326
+
.num_parents = 1,
2327
+
.flags = CLK_SET_RATE_PARENT,
2328
+
.ops = &clk_branch2_ops,
2329
+
},
2330
+
},
2331
+
};
2332
+
2333
+
static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
2334
+
.halt_reg = 0x87064,
2335
+
.halt_check = BRANCH_HALT_VOTED,
2336
+
.hwcg_reg = 0x87064,
2337
+
.hwcg_bit = 1,
2338
+
.clkr = {
2339
+
.enable_reg = 0x87064,
2340
+
.enable_mask = BIT(1),
2341
+
.hw.init = &(const struct clk_init_data) {
2342
+
.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
2343
+
.parent_hws = (const struct clk_hw*[]) {
2344
+
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2345
+
},
2346
+
.num_parents = 1,
2347
+
.flags = CLK_SET_RATE_PARENT,
2348
+
.ops = &clk_branch2_ops,
2349
+
},
2350
+
},
2351
+
};
2352
+
2353
+
static struct clk_branch gcc_usb30_prim_master_clk = {
2354
+
.halt_reg = 0x49018,
2355
+
.halt_check = BRANCH_HALT,
2356
+
.clkr = {
2357
+
.enable_reg = 0x49018,
2358
+
.enable_mask = BIT(0),
2359
+
.hw.init = &(const struct clk_init_data) {
2360
+
.name = "gcc_usb30_prim_master_clk",
2361
+
.parent_hws = (const struct clk_hw*[]) {
2362
+
&gcc_usb30_prim_master_clk_src.clkr.hw,
2363
+
},
2364
+
.num_parents = 1,
2365
+
.flags = CLK_SET_RATE_PARENT,
2366
+
.ops = &clk_branch2_ops,
2367
+
},
2368
+
},
2369
+
};
2370
+
2371
+
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2372
+
.halt_reg = 0x49024,
2373
+
.halt_check = BRANCH_HALT,
2374
+
.clkr = {
2375
+
.enable_reg = 0x49024,
2376
+
.enable_mask = BIT(0),
2377
+
.hw.init = &(const struct clk_init_data) {
2378
+
.name = "gcc_usb30_prim_mock_utmi_clk",
2379
+
.parent_hws = (const struct clk_hw*[]) {
2380
+
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
2381
+
},
2382
+
.num_parents = 1,
2383
+
.flags = CLK_SET_RATE_PARENT,
2384
+
.ops = &clk_branch2_ops,
2385
+
},
2386
+
},
2387
+
};
2388
+
2389
+
static struct clk_branch gcc_usb30_prim_sleep_clk = {
2390
+
.halt_reg = 0x49020,
2391
+
.halt_check = BRANCH_HALT,
2392
+
.clkr = {
2393
+
.enable_reg = 0x49020,
2394
+
.enable_mask = BIT(0),
2395
+
.hw.init = &(const struct clk_init_data) {
2396
+
.name = "gcc_usb30_prim_sleep_clk",
2397
+
.ops = &clk_branch2_ops,
2398
+
},
2399
+
},
2400
+
};
2401
+
2402
+
static struct clk_branch gcc_usb3_0_clkref_en = {
2403
+
.halt_reg = 0x9c010,
2404
+
.halt_check = BRANCH_HALT_DELAY,
2405
+
.clkr = {
2406
+
.enable_reg = 0x9c010,
2407
+
.enable_mask = BIT(0),
2408
+
.hw.init = &(const struct clk_init_data) {
2409
+
.name = "gcc_usb3_0_clkref_en",
2410
+
.ops = &clk_branch2_ops,
2411
+
},
2412
+
},
2413
+
};
2414
+
2415
+
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2416
+
.halt_reg = 0x4905c,
2417
+
.halt_check = BRANCH_HALT,
2418
+
.clkr = {
2419
+
.enable_reg = 0x4905c,
2420
+
.enable_mask = BIT(0),
2421
+
.hw.init = &(const struct clk_init_data) {
2422
+
.name = "gcc_usb3_prim_phy_aux_clk",
2423
+
.parent_hws = (const struct clk_hw*[]) {
2424
+
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2425
+
},
2426
+
.num_parents = 1,
2427
+
.flags = CLK_SET_RATE_PARENT,
2428
+
.ops = &clk_branch2_ops,
2429
+
},
2430
+
},
2431
+
};
2432
+
2433
+
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2434
+
.halt_reg = 0x49060,
2435
+
.halt_check = BRANCH_HALT,
2436
+
.clkr = {
2437
+
.enable_reg = 0x49060,
2438
+
.enable_mask = BIT(0),
2439
+
.hw.init = &(const struct clk_init_data) {
2440
+
.name = "gcc_usb3_prim_phy_com_aux_clk",
2441
+
.parent_hws = (const struct clk_hw*[]) {
2442
+
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2443
+
},
2444
+
.num_parents = 1,
2445
+
.flags = CLK_SET_RATE_PARENT,
2446
+
.ops = &clk_branch2_ops,
2447
+
},
2448
+
},
2449
+
};
2450
+
2451
+
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2452
+
.halt_reg = 0x49064,
2453
+
.halt_check = BRANCH_HALT_DELAY,
2454
+
.hwcg_reg = 0x49064,
2455
+
.hwcg_bit = 1,
2456
+
.clkr = {
2457
+
.enable_reg = 0x49064,
2458
+
.enable_mask = BIT(0),
2459
+
.hw.init = &(const struct clk_init_data) {
2460
+
.name = "gcc_usb3_prim_phy_pipe_clk",
2461
+
.parent_hws = (const struct clk_hw*[]) {
2462
+
&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
2463
+
},
2464
+
.num_parents = 1,
2465
+
.flags = CLK_SET_RATE_PARENT,
2466
+
.ops = &clk_branch2_ops,
2467
+
},
2468
+
},
2469
+
};
2470
+
2471
+
static struct clk_branch gcc_vcodec0_axi_clk = {
2472
+
.halt_reg = 0x42020,
2473
+
.halt_check = BRANCH_HALT_SKIP,
2474
+
.hwcg_reg = 0x42020,
2475
+
.hwcg_bit = 1,
2476
+
.clkr = {
2477
+
.enable_reg = 0x42020,
2478
+
.enable_mask = BIT(0),
2479
+
.hw.init = &(const struct clk_init_data) {
2480
+
.name = "gcc_vcodec0_axi_clk",
2481
+
.ops = &clk_branch2_ops,
2482
+
},
2483
+
},
2484
+
};
2485
+
2486
+
static struct clk_branch gcc_venus_ctl_axi_clk = {
2487
+
.halt_reg = 0x4201c,
2488
+
.halt_check = BRANCH_HALT_SKIP,
2489
+
.clkr = {
2490
+
.enable_reg = 0x4201c,
2491
+
.enable_mask = BIT(0),
2492
+
.hw.init = &(const struct clk_init_data) {
2493
+
.name = "gcc_venus_ctl_axi_clk",
2494
+
.ops = &clk_branch2_ops,
2495
+
},
2496
+
},
2497
+
};
2498
+
2499
+
static struct clk_branch gcc_video_throttle_core_clk = {
2500
+
.halt_reg = 0x42014,
2501
+
.halt_check = BRANCH_HALT_SKIP,
2502
+
.hwcg_reg = 0x42014,
2503
+
.hwcg_bit = 1,
2504
+
.clkr = {
2505
+
.enable_reg = 0x42014,
2506
+
.enable_mask = BIT(0),
2507
+
.hw.init = &(const struct clk_init_data) {
2508
+
.name = "gcc_video_throttle_core_clk",
2509
+
.ops = &clk_branch2_ops,
2510
+
},
2511
+
},
2512
+
};
2513
+
2514
+
static struct clk_branch gcc_video_vcodec0_sys_clk = {
2515
+
.halt_reg = 0xb6058,
2516
+
.halt_check = BRANCH_HALT_VOTED,
2517
+
.hwcg_reg = 0xb6058,
2518
+
.hwcg_bit = 1,
2519
+
.clkr = {
2520
+
.enable_reg = 0xb6058,
2521
+
.enable_mask = BIT(0),
2522
+
.hw.init = &(const struct clk_init_data) {
2523
+
.name = "gcc_video_vcodec0_sys_clk",
2524
+
.parent_hws = (const struct clk_hw*[]) {
2525
+
&gcc_video_venus_clk_src.clkr.hw,
2526
+
},
2527
+
.num_parents = 1,
2528
+
.flags = CLK_SET_RATE_PARENT,
2529
+
.ops = &clk_branch2_ops,
2530
+
},
2531
+
},
2532
+
};
2533
+
2534
+
static struct clk_branch gcc_video_venus_ctl_clk = {
2535
+
.halt_reg = 0xb6038,
2536
+
.halt_check = BRANCH_HALT,
2537
+
.clkr = {
2538
+
.enable_reg = 0xb6038,
2539
+
.enable_mask = BIT(0),
2540
+
.hw.init = &(const struct clk_init_data) {
2541
+
.name = "gcc_video_venus_ctl_clk",
2542
+
.parent_hws = (const struct clk_hw*[]) {
2543
+
&gcc_video_venus_clk_src.clkr.hw,
2544
+
},
2545
+
.num_parents = 1,
2546
+
.flags = CLK_SET_RATE_PARENT,
2547
+
.ops = &clk_branch2_ops,
2548
+
},
2549
+
},
2550
+
};
2551
+
2552
+
static struct gdsc gcc_pcie_0_gdsc = {
2553
+
.gdscr = 0x7b004,
2554
+
.en_rest_wait_val = 0x2,
2555
+
.en_few_wait_val = 0x2,
2556
+
.clk_dis_wait_val = 0xf,
2557
+
.pd = {
2558
+
.name = "gcc_pcie_0_gdsc",
2559
+
},
2560
+
.pwrsts = PWRSTS_OFF_ON,
2561
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
2562
+
};
2563
+
2564
+
static struct gdsc gcc_ufs_phy_gdsc = {
2565
+
.gdscr = 0x87004,
2566
+
.en_rest_wait_val = 0x2,
2567
+
.en_few_wait_val = 0x2,
2568
+
.clk_dis_wait_val = 0xf,
2569
+
.pd = {
2570
+
.name = "gcc_ufs_phy_gdsc",
2571
+
},
2572
+
.pwrsts = PWRSTS_OFF_ON,
2573
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
2574
+
};
2575
+
2576
+
static struct gdsc gcc_usb30_prim_gdsc = {
2577
+
.gdscr = 0x49004,
2578
+
.en_rest_wait_val = 0x2,
2579
+
.en_few_wait_val = 0x2,
2580
+
.clk_dis_wait_val = 0xf,
2581
+
.pd = {
2582
+
.name = "gcc_usb30_prim_gdsc",
2583
+
},
2584
+
.pwrsts = PWRSTS_OFF_ON,
2585
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
2586
+
};
2587
+
2588
+
static struct gdsc gcc_vcodec0_gdsc = {
2589
+
.gdscr = 0xb6044,
2590
+
.en_rest_wait_val = 0x2,
2591
+
.en_few_wait_val = 0x2,
2592
+
.clk_dis_wait_val = 0xf,
2593
+
.pd = {
2594
+
.name = "gcc_vcodec0_gdsc",
2595
+
},
2596
+
.pwrsts = PWRSTS_OFF_ON,
2597
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
2598
+
};
2599
+
2600
+
static struct gdsc gcc_venus_gdsc = {
2601
+
.gdscr = 0xb6020,
2602
+
.en_rest_wait_val = 0x2,
2603
+
.en_few_wait_val = 0x2,
2604
+
.clk_dis_wait_val = 0xf,
2605
+
.pd = {
2606
+
.name = "gcc_venus_gdsc",
2607
+
},
2608
+
.pwrsts = PWRSTS_OFF_ON,
2609
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
2610
+
};
2611
+
2612
+
static struct clk_regmap *gcc_sm4450_clocks[] = {
2613
+
[GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
2614
+
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
2615
+
[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
2616
+
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2617
+
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2618
+
[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
2619
+
[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
2620
+
[GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
2621
+
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2622
+
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2623
+
[GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
2624
+
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
2625
+
[GCC_EUSB3_0_CLKREF_EN] = &gcc_eusb3_0_clkref_en.clkr,
2626
+
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2627
+
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2628
+
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2629
+
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2630
+
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2631
+
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2632
+
[GCC_GPLL0] = &gcc_gpll0.clkr,
2633
+
[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
2634
+
[GCC_GPLL0_OUT_ODD] = &gcc_gpll0_out_odd.clkr,
2635
+
[GCC_GPLL1] = &gcc_gpll1.clkr,
2636
+
[GCC_GPLL3] = &gcc_gpll3.clkr,
2637
+
[GCC_GPLL4] = &gcc_gpll4.clkr,
2638
+
[GCC_GPLL9] = &gcc_gpll9.clkr,
2639
+
[GCC_GPLL10] = &gcc_gpll10.clkr,
2640
+
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
2641
+
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
2642
+
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
2643
+
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2644
+
[GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK] =
2645
+
&gcc_hlos1_vote_aggre_noc_mmu_audio_tbu_clk.clkr,
2646
+
[GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK] =
2647
+
&gcc_hlos1_vote_aggre_noc_mmu_pcie_tbu_clk.clkr,
2648
+
[GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK] = &gcc_hlos1_vote_aggre_noc_mmu_tbu1_clk.clkr,
2649
+
[GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK] = &gcc_hlos1_vote_aggre_noc_mmu_tbu2_clk.clkr,
2650
+
[GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK] = &gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_clk.clkr,
2651
+
[GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK] = &gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_clk.clkr,
2652
+
[GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK] = &gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_clk.clkr,
2653
+
[GCC_HLOS1_VOTE_MMU_TCU_CLK] = &gcc_hlos1_vote_mmu_tcu_clk.clkr,
2654
+
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2655
+
[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
2656
+
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2657
+
[GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
2658
+
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2659
+
[GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
2660
+
[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
2661
+
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2662
+
[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
2663
+
[GCC_PCIE_0_PIPE_DIV2_CLK] = &gcc_pcie_0_pipe_div2_clk.clkr,
2664
+
[GCC_PCIE_0_PIPE_DIV2_CLK_SRC] = &gcc_pcie_0_pipe_div2_clk_src.clkr,
2665
+
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2666
+
[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
2667
+
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2668
+
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2669
+
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2670
+
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2671
+
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
2672
+
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
2673
+
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
2674
+
[GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
2675
+
[GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
2676
+
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
2677
+
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2678
+
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2679
+
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2680
+
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2681
+
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2682
+
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2683
+
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2684
+
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2685
+
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2686
+
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2687
+
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2688
+
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2689
+
[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
2690
+
[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
2691
+
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
2692
+
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
2693
+
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
2694
+
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
2695
+
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
2696
+
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
2697
+
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
2698
+
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
2699
+
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
2700
+
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
2701
+
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2702
+
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2703
+
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
2704
+
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
2705
+
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2706
+
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2707
+
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2708
+
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2709
+
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2710
+
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2711
+
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2712
+
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
2713
+
[GCC_UFS_0_CLKREF_EN] = &gcc_ufs_0_clkref_en.clkr,
2714
+
[GCC_UFS_PAD_CLKREF_EN] = &gcc_ufs_pad_clkref_en.clkr,
2715
+
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
2716
+
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
2717
+
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
2718
+
[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
2719
+
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
2720
+
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
2721
+
[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
2722
+
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
2723
+
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
2724
+
[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
2725
+
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
2726
+
[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
2727
+
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
2728
+
[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
2729
+
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
2730
+
[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
2731
+
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
2732
+
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
2733
+
[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
2734
+
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
2735
+
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
2736
+
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
2737
+
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
2738
+
[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
2739
+
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
2740
+
[GCC_USB3_0_CLKREF_EN] = &gcc_usb3_0_clkref_en.clkr,
2741
+
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
2742
+
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
2743
+
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
2744
+
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
2745
+
[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
2746
+
[GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr,
2747
+
[GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr,
2748
+
[GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr,
2749
+
[GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr,
2750
+
[GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr,
2751
+
[GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr,
2752
+
};
2753
+
2754
+
static struct gdsc *gcc_sm4450_gdscs[] = {
2755
+
[GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc,
2756
+
[GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
2757
+
[GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
2758
+
[GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc,
2759
+
[GCC_VENUS_GDSC] = &gcc_venus_gdsc,
2760
+
};
2761
+
2762
+
static const struct qcom_reset_map gcc_sm4450_resets[] = {
2763
+
[GCC_CAMERA_BCR] = { 0x36000 },
2764
+
[GCC_DISPLAY_BCR] = { 0x37000 },
2765
+
[GCC_GPU_BCR] = { 0x81000 },
2766
+
[GCC_PCIE_0_BCR] = { 0x7b000 },
2767
+
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x7c014 },
2768
+
[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x7c020 },
2769
+
[GCC_PCIE_0_PHY_BCR] = { 0x7c01c },
2770
+
[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x7c028 },
2771
+
[GCC_PCIE_PHY_BCR] = { 0x7f000 },
2772
+
[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
2773
+
[GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
2774
+
[GCC_PDM_BCR] = { 0x43000 },
2775
+
[GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 },
2776
+
[GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 },
2777
+
[GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 },
2778
+
[GCC_QUSB2PHY_SEC_BCR] = { 0x22004 },
2779
+
[GCC_SDCC1_BCR] = { 0xb3000 },
2780
+
[GCC_SDCC2_BCR] = { 0x24000 },
2781
+
[GCC_UFS_PHY_BCR] = { 0x87000 },
2782
+
[GCC_USB30_PRIM_BCR] = { 0x49000 },
2783
+
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 },
2784
+
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 },
2785
+
[GCC_USB3_PHY_PRIM_BCR] = { 0x60000 },
2786
+
[GCC_USB3_PHY_SEC_BCR] = { 0x6000c },
2787
+
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
2788
+
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
2789
+
[GCC_VCODEC0_BCR] = { 0xb6040 },
2790
+
[GCC_VENUS_BCR] = { 0xb601c },
2791
+
[GCC_VIDEO_BCR] = { 0x42000 },
2792
+
[GCC_VIDEO_VENUS_BCR] = { 0xb6000 },
2793
+
[GCC_VENUS_CTL_AXI_CLK_ARES] = { 0x4201c, 2 },
2794
+
[GCC_VIDEO_VENUS_CTL_CLK_ARES] = { 0xb6038, 2 },
2795
+
};
2796
+
2797
+
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
2798
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2799
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2800
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2801
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2802
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2803
+
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
2804
+
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
2805
+
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
2806
+
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
2807
+
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
2808
+
};
2809
+
2810
+
static const struct regmap_config gcc_sm4450_regmap_config = {
2811
+
.reg_bits = 32,
2812
+
.reg_stride = 4,
2813
+
.val_bits = 32,
2814
+
.max_register = 0x1f41f0,
2815
+
.fast_io = true,
2816
+
};
2817
+
2818
+
static const struct qcom_cc_desc gcc_sm4450_desc = {
2819
+
.config = &gcc_sm4450_regmap_config,
2820
+
.clks = gcc_sm4450_clocks,
2821
+
.num_clks = ARRAY_SIZE(gcc_sm4450_clocks),
2822
+
.resets = gcc_sm4450_resets,
2823
+
.num_resets = ARRAY_SIZE(gcc_sm4450_resets),
2824
+
.gdscs = gcc_sm4450_gdscs,
2825
+
.num_gdscs = ARRAY_SIZE(gcc_sm4450_gdscs),
2826
+
};
2827
+
2828
+
static const struct of_device_id gcc_sm4450_match_table[] = {
2829
+
{ .compatible = "qcom,sm4450-gcc" },
2830
+
{ }
2831
+
};
2832
+
MODULE_DEVICE_TABLE(of, gcc_sm4450_match_table);
2833
+
2834
+
static int gcc_sm4450_probe(struct platform_device *pdev)
2835
+
{
2836
+
struct regmap *regmap;
2837
+
int ret;
2838
+
2839
+
regmap = qcom_cc_map(pdev, &gcc_sm4450_desc);
2840
+
if (IS_ERR(regmap))
2841
+
return PTR_ERR(regmap);
2842
+
2843
+
clk_lucid_evo_pll_configure(&gcc_gpll3, regmap, &gcc_gpll3_config);
2844
+
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
2845
+
ARRAY_SIZE(gcc_dfs_clocks));
2846
+
if (ret)
2847
+
return ret;
2848
+
2849
+
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
2850
+
2851
+
/*
2852
+
* Keep clocks always enabled:
2853
+
* gcc_camera_ahb_clk
2854
+
* gcc_camera_sleep_clk
2855
+
* gcc_camera_xo_clk
2856
+
* gcc_disp_ahb_clk
2857
+
* gcc_disp_xo_clk
2858
+
* gcc_gpu_cfg_ahb_clk
2859
+
* gcc_video_ahb_clk
2860
+
* gcc_video_xo_clk
2861
+
*/
2862
+
regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0));
2863
+
regmap_update_bits(regmap, 0x36018, BIT(0), BIT(0));
2864
+
regmap_update_bits(regmap, 0x3601c, BIT(0), BIT(0));
2865
+
regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0));
2866
+
regmap_update_bits(regmap, 0x37014, BIT(0), BIT(0));
2867
+
regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0));
2868
+
regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0));
2869
+
regmap_update_bits(regmap, 0x42018, BIT(0), BIT(0));
2870
+
2871
+
regmap_update_bits(regmap, 0x4201c, BIT(21), BIT(21));
2872
+
2873
+
return qcom_cc_really_probe(pdev, &gcc_sm4450_desc, regmap);
2874
+
}
2875
+
2876
+
static struct platform_driver gcc_sm4450_driver = {
2877
+
.probe = gcc_sm4450_probe,
2878
+
.driver = {
2879
+
.name = "gcc-sm4450",
2880
+
.of_match_table = gcc_sm4450_match_table,
2881
+
},
2882
+
};
2883
+
2884
+
static int __init gcc_sm4450_init(void)
2885
+
{
2886
+
return platform_driver_register(&gcc_sm4450_driver);
2887
+
}
2888
+
subsys_initcall(gcc_sm4450_init);
2889
+
2890
+
static void __exit gcc_sm4450_exit(void)
2891
+
{
2892
+
platform_driver_unregister(&gcc_sm4450_driver);
2893
+
}
2894
+
module_exit(gcc_sm4450_exit);
2895
+
2896
+
MODULE_DESCRIPTION("QTI GCC SM4450 Driver");
2897
+
MODULE_LICENSE("GPL");
+197
include/dt-bindings/clock/qcom,sm4450-gcc.h
+197
include/dt-bindings/clock/qcom,sm4450-gcc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM4450_H
7
+
#define _DT_BINDINGS_CLK_QCOM_GCC_SM4450_H
8
+
9
+
/* GCC clocks */
10
+
#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 0
11
+
#define GCC_AGGRE_UFS_PHY_AXI_CLK 1
12
+
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2
13
+
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
14
+
#define GCC_BOOT_ROM_AHB_CLK 4
15
+
#define GCC_CAMERA_AHB_CLK 5
16
+
#define GCC_CAMERA_HF_AXI_CLK 6
17
+
#define GCC_CAMERA_SF_AXI_CLK 7
18
+
#define GCC_CAMERA_SLEEP_CLK 8
19
+
#define GCC_CAMERA_XO_CLK 9
20
+
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 10
21
+
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 11
22
+
#define GCC_DDRSS_GPU_AXI_CLK 12
23
+
#define GCC_DDRSS_PCIE_SF_TBU_CLK 13
24
+
#define GCC_DISP_AHB_CLK 14
25
+
#define GCC_DISP_HF_AXI_CLK 15
26
+
#define GCC_DISP_XO_CLK 16
27
+
#define GCC_EUSB3_0_CLKREF_EN 17
28
+
#define GCC_GP1_CLK 18
29
+
#define GCC_GP1_CLK_SRC 19
30
+
#define GCC_GP2_CLK 20
31
+
#define GCC_GP2_CLK_SRC 21
32
+
#define GCC_GP3_CLK 22
33
+
#define GCC_GP3_CLK_SRC 23
34
+
#define GCC_GPLL0 24
35
+
#define GCC_GPLL0_OUT_EVEN 25
36
+
#define GCC_GPLL0_OUT_ODD 26
37
+
#define GCC_GPLL1 27
38
+
#define GCC_GPLL3 28
39
+
#define GCC_GPLL4 29
40
+
#define GCC_GPLL9 30
41
+
#define GCC_GPLL10 31
42
+
#define GCC_GPU_CFG_AHB_CLK 32
43
+
#define GCC_GPU_GPLL0_CLK_SRC 33
44
+
#define GCC_GPU_GPLL0_DIV_CLK_SRC 34
45
+
#define GCC_GPU_MEMNOC_GFX_CLK 35
46
+
#define GCC_GPU_SNOC_DVM_GFX_CLK 36
47
+
#define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK 37
48
+
#define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK 38
49
+
#define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK 39
50
+
#define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK 40
51
+
#define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK 41
52
+
#define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK 42
53
+
#define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK 43
54
+
#define GCC_HLOS1_VOTE_MMU_TCU_CLK 44
55
+
#define GCC_PCIE_0_AUX_CLK 45
56
+
#define GCC_PCIE_0_AUX_CLK_SRC 46
57
+
#define GCC_PCIE_0_CFG_AHB_CLK 47
58
+
#define GCC_PCIE_0_CLKREF_EN 48
59
+
#define GCC_PCIE_0_MSTR_AXI_CLK 49
60
+
#define GCC_PCIE_0_PHY_RCHNG_CLK 50
61
+
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 51
62
+
#define GCC_PCIE_0_PIPE_CLK 52
63
+
#define GCC_PCIE_0_PIPE_CLK_SRC 53
64
+
#define GCC_PCIE_0_PIPE_DIV2_CLK 54
65
+
#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC 55
66
+
#define GCC_PCIE_0_SLV_AXI_CLK 56
67
+
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57
68
+
#define GCC_PDM2_CLK 58
69
+
#define GCC_PDM2_CLK_SRC 59
70
+
#define GCC_PDM_AHB_CLK 60
71
+
#define GCC_PDM_XO4_CLK 61
72
+
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 62
73
+
#define GCC_QMIP_CAMERA_RT_AHB_CLK 63
74
+
#define GCC_QMIP_DISP_AHB_CLK 64
75
+
#define GCC_QMIP_GPU_AHB_CLK 65
76
+
#define GCC_QMIP_PCIE_AHB_CLK 66
77
+
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 67
78
+
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 68
79
+
#define GCC_QUPV3_WRAP0_CORE_CLK 69
80
+
#define GCC_QUPV3_WRAP0_S0_CLK 70
81
+
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 71
82
+
#define GCC_QUPV3_WRAP0_S1_CLK 72
83
+
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 73
84
+
#define GCC_QUPV3_WRAP0_S2_CLK 74
85
+
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 75
86
+
#define GCC_QUPV3_WRAP0_S3_CLK 76
87
+
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 77
88
+
#define GCC_QUPV3_WRAP0_S4_CLK 78
89
+
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 79
90
+
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 80
91
+
#define GCC_QUPV3_WRAP1_CORE_CLK 81
92
+
#define GCC_QUPV3_WRAP1_S0_CLK 82
93
+
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 83
94
+
#define GCC_QUPV3_WRAP1_S1_CLK 84
95
+
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 85
96
+
#define GCC_QUPV3_WRAP1_S2_CLK 86
97
+
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 87
98
+
#define GCC_QUPV3_WRAP1_S3_CLK 88
99
+
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 89
100
+
#define GCC_QUPV3_WRAP1_S4_CLK 90
101
+
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 91
102
+
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 92
103
+
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 93
104
+
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 94
105
+
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 95
106
+
#define GCC_SDCC1_AHB_CLK 96
107
+
#define GCC_SDCC1_APPS_CLK 97
108
+
#define GCC_SDCC1_APPS_CLK_SRC 98
109
+
#define GCC_SDCC1_ICE_CORE_CLK 99
110
+
#define GCC_SDCC1_ICE_CORE_CLK_SRC 100
111
+
#define GCC_SDCC2_AHB_CLK 101
112
+
#define GCC_SDCC2_APPS_CLK 102
113
+
#define GCC_SDCC2_APPS_CLK_SRC 103
114
+
#define GCC_UFS_0_CLKREF_EN 104
115
+
#define GCC_UFS_PAD_CLKREF_EN 105
116
+
#define GCC_UFS_PHY_AHB_CLK 106
117
+
#define GCC_UFS_PHY_AXI_CLK 107
118
+
#define GCC_UFS_PHY_AXI_CLK_SRC 108
119
+
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 109
120
+
#define GCC_UFS_PHY_ICE_CORE_CLK 110
121
+
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 111
122
+
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 112
123
+
#define GCC_UFS_PHY_PHY_AUX_CLK 113
124
+
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 114
125
+
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 115
126
+
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 116
127
+
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 117
128
+
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 118
129
+
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 119
130
+
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 120
131
+
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 121
132
+
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 122
133
+
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 123
134
+
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 124
135
+
#define GCC_USB30_PRIM_MASTER_CLK 125
136
+
#define GCC_USB30_PRIM_MASTER_CLK_SRC 126
137
+
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 127
138
+
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 128
139
+
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 129
140
+
#define GCC_USB30_PRIM_SLEEP_CLK 130
141
+
#define GCC_USB3_0_CLKREF_EN 131
142
+
#define GCC_USB3_PRIM_PHY_AUX_CLK 132
143
+
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 133
144
+
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 134
145
+
#define GCC_USB3_PRIM_PHY_PIPE_CLK 135
146
+
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 136
147
+
#define GCC_VCODEC0_AXI_CLK 137
148
+
#define GCC_VENUS_CTL_AXI_CLK 138
149
+
#define GCC_VIDEO_AHB_CLK 139
150
+
#define GCC_VIDEO_THROTTLE_CORE_CLK 140
151
+
#define GCC_VIDEO_VCODEC0_SYS_CLK 141
152
+
#define GCC_VIDEO_VENUS_CLK_SRC 142
153
+
#define GCC_VIDEO_VENUS_CTL_CLK 143
154
+
#define GCC_VIDEO_XO_CLK 144
155
+
156
+
/* GCC power domains */
157
+
#define GCC_PCIE_0_GDSC 0
158
+
#define GCC_UFS_PHY_GDSC 1
159
+
#define GCC_USB30_PRIM_GDSC 2
160
+
#define GCC_VCODEC0_GDSC 3
161
+
#define GCC_VENUS_GDSC 4
162
+
163
+
/* GCC resets */
164
+
#define GCC_CAMERA_BCR 0
165
+
#define GCC_DISPLAY_BCR 1
166
+
#define GCC_GPU_BCR 2
167
+
#define GCC_PCIE_0_BCR 3
168
+
#define GCC_PCIE_0_LINK_DOWN_BCR 4
169
+
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
170
+
#define GCC_PCIE_0_PHY_BCR 6
171
+
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
172
+
#define GCC_PCIE_PHY_BCR 8
173
+
#define GCC_PCIE_PHY_CFG_AHB_BCR 9
174
+
#define GCC_PCIE_PHY_COM_BCR 10
175
+
#define GCC_PDM_BCR 11
176
+
#define GCC_QUPV3_WRAPPER_0_BCR 12
177
+
#define GCC_QUPV3_WRAPPER_1_BCR 13
178
+
#define GCC_QUSB2PHY_PRIM_BCR 14
179
+
#define GCC_QUSB2PHY_SEC_BCR 15
180
+
#define GCC_SDCC1_BCR 16
181
+
#define GCC_SDCC2_BCR 17
182
+
#define GCC_UFS_PHY_BCR 18
183
+
#define GCC_USB30_PRIM_BCR 19
184
+
#define GCC_USB3_DP_PHY_PRIM_BCR 20
185
+
#define GCC_USB3_DP_PHY_SEC_BCR 21
186
+
#define GCC_USB3_PHY_PRIM_BCR 22
187
+
#define GCC_USB3_PHY_SEC_BCR 23
188
+
#define GCC_USB3PHY_PHY_PRIM_BCR 24
189
+
#define GCC_USB3PHY_PHY_SEC_BCR 25
190
+
#define GCC_VCODEC0_BCR 26
191
+
#define GCC_VENUS_BCR 27
192
+
#define GCC_VIDEO_BCR 28
193
+
#define GCC_VIDEO_VENUS_BCR 29
194
+
#define GCC_VENUS_CTL_AXI_CLK_ARES 30
195
+
#define GCC_VIDEO_VENUS_CTL_CLK_ARES 31
196
+
197
+
#endif