tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 arch fixes from Peter Anvin:
"Here is a collection of fixes for 3.7-rc7. This is a superset of
tglx' earlier pull request."

* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86-64: Fix ordering of CFI directives and recent ASM_CLAC additions
x86, microcode, AMD: Add support for family 16h processors
x86-32: Export kernel_stack_pointer() for modules
x86-32: Fix invalid stack address while in softirq
x86, efi: Fix processor-specific memcpy() build error
x86: remove dummy long from EFI stub
x86, mm: Correct vmflag test for checking VM_HUGETLB
x86, amd: Disable way access filter on Piledriver CPUs
x86/mce: Do not change worker's running cpu in cmci_rediscover().
x86/ce4100: Fix PCI configuration register access for devices without interrupts
x86/ce4100: Fix reboot by forcing the reboot method to be KBD
x86/ce4100: Fix pm_poweroff
MAINTAINERS: Update email address for Robert Richter
x86, microcode_amd: Change email addresses, MAINTAINERS entry
MAINTAINERS: Change Boris' email address
EDAC: Change Boris' email address
x86, AMD: Change Boris' email address

Linus Torvalds 2654ad44 35f95d22

+132 -50
+7 -7
MAINTAINERS
··· 534 534 F: include/linux/amd-iommu.h 535 535 536 536 AMD MICROCODE UPDATE SUPPORT 537 - M: Andreas Herrmann <andreas.herrmann3@amd.com> 537 + M: Andreas Herrmann <herrmann.der.user@googlemail.com> 538 538 L: amd64-microcode@amd64.org 539 - S: Supported 539 + S: Maintained 540 540 F: arch/x86/kernel/microcode_amd.c 541 541 542 542 AMS (Apple Motion Sensor) DRIVER ··· 2716 2716 2717 2717 EDAC-AMD64 2718 2718 M: Doug Thompson <dougthompson@xmission.com> 2719 - M: Borislav Petkov <borislav.petkov@amd.com> 2719 + M: Borislav Petkov <bp@alien8.de> 2720 2720 L: linux-edac@vger.kernel.org 2721 2721 W: bluesmoke.sourceforge.net 2722 - S: Supported 2722 + S: Maintained 2723 2723 F: drivers/edac/amd64_edac* 2724 2724 2725 2725 EDAC-E752X ··· 3761 3761 F: drivers/platform/x86/ideapad-laptop.c 3762 3762 3763 3763 IDE/ATAPI DRIVERS 3764 - M: Borislav Petkov <petkovbb@gmail.com> 3764 + M: Borislav Petkov <bp@alien8.de> 3765 3765 L: linux-ide@vger.kernel.org 3766 3766 S: Maintained 3767 3767 F: Documentation/cdrom/ide-cd ··· 5421 5421 F: sound/drivers/opl4/ 5422 5422 5423 5423 OPROFILE 5424 - M: Robert Richter <robert.richter@amd.com> 5424 + M: Robert Richter <rric@kernel.org> 5425 5425 L: oprofile-list@lists.sf.net 5426 5426 S: Maintained 5427 5427 F: arch/*/include/asm/oprofile*.h ··· 8206 8206 8207 8207 X86 MCE INFRASTRUCTURE 8208 8208 M: Tony Luck <tony.luck@intel.com> 8209 - M: Borislav Petkov <bp@amd64.org> 8209 + M: Borislav Petkov <bp@alien8.de> 8210 8210 L: linux-edac@vger.kernel.org 8211 8211 S: Maintained 8212 8212 F: arch/x86/kernel/cpu/mcheck/*
+2
arch/x86/boot/compressed/eboot.c
··· 12 12 #include <asm/setup.h> 13 13 #include <asm/desc.h> 14 14 15 + #undef memcpy /* Use memcpy from misc.c */ 16 + 15 17 #include "eboot.h" 16 18 17 19 static efi_system_table_t *sys_table;
-3
arch/x86/boot/header.S
··· 476 476 setup_corrupt: 477 477 .byte 7 478 478 .string "No setup signature found...\n" 479 - 480 - .data 481 - dummy: .long 0
+4 -11
arch/x86/include/asm/ptrace.h
··· 205 205 } 206 206 #endif 207 207 208 - /* 209 - * X86_32 CPUs don't save ss and esp if the CPU is already in kernel mode 210 - * when it traps. The previous stack will be directly underneath the saved 211 - * registers, and 'sp/ss' won't even have been saved. Thus the '&regs->sp'. 212 - * 213 - * This is valid only for kernel mode traps. 214 - */ 208 + #ifdef CONFIG_X86_32 209 + extern unsigned long kernel_stack_pointer(struct pt_regs *regs); 210 + #else 215 211 static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) 216 212 { 217 - #ifdef CONFIG_X86_32 218 - return (unsigned long)(&regs->sp); 219 - #else 220 213 return regs->sp; 221 - #endif 222 214 } 215 + #endif 223 216 224 217 #define GET_IP(regs) ((regs)->ip) 225 218 #define GET_FP(regs) ((regs)->bp)
+14
arch/x86/kernel/cpu/amd.c
··· 631 631 } 632 632 } 633 633 634 + /* 635 + * The way access filter has a performance penalty on some workloads. 636 + * Disable it on the affected CPUs. 637 + */ 638 + if ((c->x86 == 0x15) && 639 + (c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 640 + u64 val; 641 + 642 + if (!rdmsrl_safe(0xc0011021, &val) && !(val & 0x1E)) { 643 + val |= 0x1E; 644 + wrmsrl_safe(0xc0011021, val); 645 + } 646 + } 647 + 634 648 cpu_detect_cache_sizes(c); 635 649 636 650 /* Multi core CPU? */
+1 -1
arch/x86/kernel/cpu/mcheck/mce_amd.c
··· 6 6 * 7 7 * Written by Jacob Shin - AMD, Inc. 8 8 * 9 - * Support: borislav.petkov@amd.com 9 + * Maintained by: Borislav Petkov <bp@alien8.de> 10 10 * 11 11 * April 2006 12 12 * - added support for AMD Family 0x10 processors
+19 -14
arch/x86/kernel/cpu/mcheck/mce_intel.c
··· 285 285 raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); 286 286 } 287 287 288 + static long cmci_rediscover_work_func(void *arg) 289 + { 290 + int banks; 291 + 292 + /* Recheck banks in case CPUs don't all have the same */ 293 + if (cmci_supported(&banks)) 294 + cmci_discover(banks); 295 + 296 + return 0; 297 + } 298 + 288 299 /* 289 300 * After a CPU went down cycle through all the others and rediscover 290 301 * Must run in process context. 291 302 */ 292 303 void cmci_rediscover(int dying) 293 304 { 294 - int banks; 295 - int cpu; 296 - cpumask_var_t old; 305 + int cpu, banks; 297 306 298 307 if (!cmci_supported(&banks)) 299 308 return; 300 - if (!alloc_cpumask_var(&old, GFP_KERNEL)) 301 - return; 302 - cpumask_copy(old, &current->cpus_allowed); 303 309 304 310 for_each_online_cpu(cpu) { 305 311 if (cpu == dying) 306 312 continue; 307 - if (set_cpus_allowed_ptr(current, cpumask_of(cpu))) 308 - continue; 309 - /* Recheck banks in case CPUs don't all have the same */ 310 - if (cmci_supported(&banks)) 311 - cmci_discover(banks); 312 - } 313 313 314 - set_cpus_allowed_ptr(current, old); 315 - free_cpumask_var(old); 314 + if (cpu == smp_processor_id()) { 315 + cmci_rediscover_work_func(NULL); 316 + continue; 317 + } 318 + 319 + work_on_cpu(cpu, cmci_rediscover_work_func, NULL); 320 + } 316 321 } 317 322 318 323 /*
+7 -7
arch/x86/kernel/entry_64.S
··· 995 995 */ 996 996 .p2align CONFIG_X86_L1_CACHE_SHIFT 997 997 common_interrupt: 998 - ASM_CLAC 999 998 XCPT_FRAME 999 + ASM_CLAC 1000 1000 addq $-0x80,(%rsp) /* Adjust vector to [-256,-1] range */ 1001 1001 interrupt do_IRQ 1002 1002 /* 0(%rsp): old_rsp-ARGOFFSET */ ··· 1135 1135 */ 1136 1136 .macro apicinterrupt num sym do_sym 1137 1137 ENTRY(\sym) 1138 - ASM_CLAC 1139 1138 INTR_FRAME 1139 + ASM_CLAC 1140 1140 pushq_cfi $~(\num) 1141 1141 .Lcommon_\sym: 1142 1142 interrupt \do_sym ··· 1190 1190 */ 1191 1191 .macro zeroentry sym do_sym 1192 1192 ENTRY(\sym) 1193 - ASM_CLAC 1194 1193 INTR_FRAME 1194 + ASM_CLAC 1195 1195 PARAVIRT_ADJUST_EXCEPTION_FRAME 1196 1196 pushq_cfi $-1 /* ORIG_RAX: no syscall to restart */ 1197 1197 subq $ORIG_RAX-R15, %rsp ··· 1208 1208 1209 1209 .macro paranoidzeroentry sym do_sym 1210 1210 ENTRY(\sym) 1211 - ASM_CLAC 1212 1211 INTR_FRAME 1212 + ASM_CLAC 1213 1213 PARAVIRT_ADJUST_EXCEPTION_FRAME 1214 1214 pushq_cfi $-1 /* ORIG_RAX: no syscall to restart */ 1215 1215 subq $ORIG_RAX-R15, %rsp ··· 1227 1227 #define INIT_TSS_IST(x) PER_CPU_VAR(init_tss) + (TSS_ist + ((x) - 1) * 8) 1228 1228 .macro paranoidzeroentry_ist sym do_sym ist 1229 1229 ENTRY(\sym) 1230 - ASM_CLAC 1231 1230 INTR_FRAME 1231 + ASM_CLAC 1232 1232 PARAVIRT_ADJUST_EXCEPTION_FRAME 1233 1233 pushq_cfi $-1 /* ORIG_RAX: no syscall to restart */ 1234 1234 subq $ORIG_RAX-R15, %rsp ··· 1247 1247 1248 1248 .macro errorentry sym do_sym 1249 1249 ENTRY(\sym) 1250 - ASM_CLAC 1251 1250 XCPT_FRAME 1251 + ASM_CLAC 1252 1252 PARAVIRT_ADJUST_EXCEPTION_FRAME 1253 1253 subq $ORIG_RAX-R15, %rsp 1254 1254 CFI_ADJUST_CFA_OFFSET ORIG_RAX-R15 ··· 1266 1266 /* error code is on the stack already */ 1267 1267 .macro paranoiderrorentry sym do_sym 1268 1268 ENTRY(\sym) 1269 - ASM_CLAC 1270 1269 XCPT_FRAME 1270 + ASM_CLAC 1271 1271 PARAVIRT_ADJUST_EXCEPTION_FRAME 1272 1272 subq $ORIG_RAX-R15, %rsp 1273 1273 CFI_ADJUST_CFA_OFFSET ORIG_RAX-R15
+6 -2
arch/x86/kernel/microcode_amd.c
··· 8 8 * Tigran Aivazian <tigran@aivazian.fsnet.co.uk> 9 9 * 10 10 * Maintainers: 11 - * Andreas Herrmann <andreas.herrmann3@amd.com> 12 - * Borislav Petkov <borislav.petkov@amd.com> 11 + * Andreas Herrmann <herrmann.der.user@googlemail.com> 12 + * Borislav Petkov <bp@alien8.de> 13 13 * 14 14 * This driver allows to upgrade microcode on F10h AMD 15 15 * CPUs and later. ··· 190 190 #define F1XH_MPB_MAX_SIZE 2048 191 191 #define F14H_MPB_MAX_SIZE 1824 192 192 #define F15H_MPB_MAX_SIZE 4096 193 + #define F16H_MPB_MAX_SIZE 3458 193 194 194 195 switch (c->x86) { 195 196 case 0x14: ··· 198 197 break; 199 198 case 0x15: 200 199 max_size = F15H_MPB_MAX_SIZE; 200 + break; 201 + case 0x16: 202 + max_size = F16H_MPB_MAX_SIZE; 201 203 break; 202 204 default: 203 205 max_size = F1XH_MPB_MAX_SIZE;
+30
arch/x86/kernel/ptrace.c
··· 22 22 #include <linux/perf_event.h> 23 23 #include <linux/hw_breakpoint.h> 24 24 #include <linux/rcupdate.h> 25 + #include <linux/module.h> 25 26 26 27 #include <asm/uaccess.h> 27 28 #include <asm/pgtable.h> ··· 166 165 #ifdef CONFIG_X86_32 167 166 168 167 #define FLAG_MASK FLAG_MASK_32 168 + 169 + /* 170 + * X86_32 CPUs don't save ss and esp if the CPU is already in kernel mode 171 + * when it traps. The previous stack will be directly underneath the saved 172 + * registers, and 'sp/ss' won't even have been saved. Thus the '&regs->sp'. 173 + * 174 + * Now, if the stack is empty, '&regs->sp' is out of range. In this 175 + * case we try to take the previous stack. To always return a non-null 176 + * stack pointer we fall back to regs as stack if no previous stack 177 + * exists. 178 + * 179 + * This is valid only for kernel mode traps. 180 + */ 181 + unsigned long kernel_stack_pointer(struct pt_regs *regs) 182 + { 183 + unsigned long context = (unsigned long)regs & ~(THREAD_SIZE - 1); 184 + unsigned long sp = (unsigned long)&regs->sp; 185 + struct thread_info *tinfo; 186 + 187 + if (context == (sp & ~(THREAD_SIZE - 1))) 188 + return sp; 189 + 190 + tinfo = (struct thread_info *)context; 191 + if (tinfo->previous_esp) 192 + return tinfo->previous_esp; 193 + 194 + return (unsigned long)regs; 195 + } 196 + EXPORT_SYMBOL_GPL(kernel_stack_pointer); 169 197 170 198 static unsigned long *pt_regs_access(struct pt_regs *regs, unsigned long regno) 171 199 {
+1 -1
arch/x86/mm/tlb.c
··· 197 197 } 198 198 199 199 if (end == TLB_FLUSH_ALL || tlb_flushall_shift == -1 200 - || vmflag == VM_HUGETLB) { 200 + || vmflag & VM_HUGETLB) { 201 201 local_flush_tlb(); 202 202 goto flush_all; 203 203 }
+13
arch/x86/pci/ce4100.c
··· 115 115 reg_read(reg, value); 116 116 } 117 117 118 + static void reg_noirq_read(struct sim_dev_reg *reg, u32 *value) 119 + { 120 + unsigned long flags; 121 + 122 + raw_spin_lock_irqsave(&pci_config_lock, flags); 123 + /* force interrupt pin value to 0 */ 124 + *value = reg->sim_reg.value & 0xfff00ff; 125 + raw_spin_unlock_irqrestore(&pci_config_lock, flags); 126 + } 127 + 118 128 static struct sim_dev_reg bus1_fixups[] = { 119 129 DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write) 120 130 DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write) ··· 154 144 DEFINE_REG(11, 5, 0x10, (64*KB), reg_init, reg_read, reg_write) 155 145 DEFINE_REG(11, 6, 0x10, (256), reg_init, reg_read, reg_write) 156 146 DEFINE_REG(11, 7, 0x10, (64*KB), reg_init, reg_read, reg_write) 147 + DEFINE_REG(11, 7, 0x3c, 256, reg_init, reg_noirq_read, reg_write) 157 148 DEFINE_REG(12, 0, 0x10, (128*KB), reg_init, reg_read, reg_write) 158 149 DEFINE_REG(12, 0, 0x14, (256), reg_init, reg_read, reg_write) 159 150 DEFINE_REG(12, 1, 0x10, (1024), reg_init, reg_read, reg_write) ··· 172 161 DEFINE_REG(16, 0, 0x10, (64*KB), reg_init, reg_read, reg_write) 173 162 DEFINE_REG(16, 0, 0x14, (64*MB), reg_init, reg_read, reg_write) 174 163 DEFINE_REG(16, 0, 0x18, (64*MB), reg_init, reg_read, reg_write) 164 + DEFINE_REG(16, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write) 175 165 DEFINE_REG(17, 0, 0x10, (128*KB), reg_init, reg_read, reg_write) 176 166 DEFINE_REG(18, 0, 0x10, (1*KB), reg_init, reg_read, reg_write) 167 + DEFINE_REG(18, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write) 177 168 }; 178 169 179 170 static void __init init_sim_regs(void)
+24
arch/x86/platform/ce4100/ce4100.c
··· 21 21 #include <asm/i8259.h> 22 22 #include <asm/io.h> 23 23 #include <asm/io_apic.h> 24 + #include <asm/emergency-restart.h> 24 25 25 26 static int ce4100_i8042_detect(void) 26 27 { 27 28 return 0; 29 + } 30 + 31 + /* 32 + * The CE4100 platform has an internal 8051 Microcontroller which is 33 + * responsible for signaling to the external Power Management Unit the 34 + * intention to reset, reboot or power off the system. This 8051 device has 35 + * its command register mapped at I/O port 0xcf9 and the value 0x4 is used 36 + * to power off the system. 37 + */ 38 + static void ce4100_power_off(void) 39 + { 40 + outb(0x4, 0xcf9); 28 41 } 29 42 30 43 #ifdef CONFIG_SERIAL_8250 ··· 152 139 x86_init.mpparse.find_smp_config = x86_init_noop; 153 140 x86_init.pci.init = ce4100_pci_init; 154 141 142 + /* 143 + * By default, the reboot method is ACPI which is supported by the 144 + * CE4100 bootloader CEFDK using FADT.ResetReg Address and ResetValue 145 + * the bootloader will however issue a system power off instead of 146 + * reboot. By using BOOT_KBD we ensure proper system reboot as 147 + * expected. 148 + */ 149 + reboot_type = BOOT_KBD; 150 + 155 151 #ifdef CONFIG_X86_IO_APIC 156 152 x86_init.pci.init_irq = sdv_pci_init; 157 153 x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc_nocheck; 158 154 #endif 155 + 156 + pm_power_off = ce4100_power_off; 159 157 }
+1 -1
drivers/edac/amd64_edac.h
··· 33 33 * detection. The mods to Rev F required more family 34 34 * information detection. 35 35 * 36 - * Changes/Fixes by Borislav Petkov <borislav.petkov@amd.com>: 36 + * Changes/Fixes by Borislav Petkov <bp@alien8.de>: 37 37 * - misc fixes and code cleanups 38 38 * 39 39 * This module is based on the following documents
+1 -1
drivers/edac/edac_stub.c
··· 5 5 * 6 6 * 2007 (c) MontaVista Software, Inc. 7 7 * 2010 (c) Advanced Micro Devices Inc. 8 - * Borislav Petkov <borislav.petkov@amd.com> 8 + * Borislav Petkov <bp@alien8.de> 9 9 * 10 10 * This file is licensed under the terms of the GNU General Public 11 11 * License version 2. This program is licensed "as is" without any
+2 -2
drivers/edac/mce_amd_inj.c
··· 6 6 * This file may be distributed under the terms of the GNU General Public 7 7 * License version 2. 8 8 * 9 - * Copyright (c) 2010: Borislav Petkov <borislav.petkov@amd.com> 9 + * Copyright (c) 2010: Borislav Petkov <bp@alien8.de> 10 10 * Advanced Micro Devices Inc. 11 11 */ 12 12 ··· 168 168 module_exit(edac_exit_mce_inject); 169 169 170 170 MODULE_LICENSE("GPL"); 171 - MODULE_AUTHOR("Borislav Petkov <borislav.petkov@amd.com>"); 171 + MODULE_AUTHOR("Borislav Petkov <bp@alien8.de>"); 172 172 MODULE_AUTHOR("AMD Inc."); 173 173 MODULE_DESCRIPTION("MCE injection facility for testing MCE decoding");