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phy: qcom-qmp-ufs: Switch to devm_clk_bulk_get_all() API

Device drivers should just rely on the clocks provided by the devicetree
and enable/disable them based on the requirement. There is no need to
validate the clocks provided by devicetree in the driver. That's the job
of DT schema.

So let's switch to devm_clk_bulk_get_all() API that just gets the clocks
provided by devicetree and remove hardcoded clocks info.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-2-58a49d2f4605@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Manivannan Sadhasivam and committed by
Vinod Koul 2668cae8 b0bcec86

+7 -56
+7 -56
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
··· 923 923 /* Additional sequence for different HS Gears */ 924 924 const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY]; 925 925 926 - /* clock ids to be requested */ 927 - const char * const *clk_list; 928 - int num_clks; 929 926 /* regulators to be requested */ 930 927 const char * const *vreg_list; 931 928 int num_vregs; ··· 948 951 void __iomem *rx2; 949 952 950 953 struct clk_bulk_data *clks; 954 + int num_clks; 951 955 struct regulator_bulk_data *vregs; 952 956 struct reset_control *ufs_reset; 953 957 ··· 980 982 /* ensure that above write is through */ 981 983 readl(base + offset); 982 984 } 983 - 984 - /* list of clocks required by phy */ 985 - static const char * const msm8996_ufs_phy_clk_l[] = { 986 - "ref", 987 - }; 988 - 989 - /* the primary usb3 phy on sm8250 doesn't have a ref clock */ 990 - static const char * const sm8450_ufs_phy_clk_l[] = { 991 - "qref", "ref", "ref_aux", 992 - }; 993 - 994 - static const char * const sdm845_ufs_phy_clk_l[] = { 995 - "ref", "ref_aux", 996 - }; 997 985 998 986 /* list of regulators */ 999 987 static const char * const qmp_phy_vreg_l[] = { ··· 1019 1035 .rx_num = ARRAY_SIZE(msm8996_ufsphy_rx), 1020 1036 }, 1021 1037 1022 - .clk_list = msm8996_ufs_phy_clk_l, 1023 - .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), 1024 - 1025 1038 .vreg_list = qmp_phy_vreg_l, 1026 1039 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1027 1040 ··· 1056 1075 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1057 1076 .max_gear = UFS_HS_G4, 1058 1077 }, 1059 - .clk_list = sm8450_ufs_phy_clk_l, 1060 - .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), 1061 1078 .vreg_list = qmp_phy_vreg_l, 1062 1079 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1063 1080 .regs = ufsphy_v5_regs_layout, ··· 1090 1111 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), 1091 1112 .max_gear = UFS_HS_G4, 1092 1113 }, 1093 - .clk_list = sm8450_ufs_phy_clk_l, 1094 - .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), 1095 1114 .vreg_list = qmp_phy_vreg_l, 1096 1115 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1097 1116 .regs = ufsphy_v4_regs_layout, ··· 1124 1147 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1125 1148 .max_gear = UFS_HS_G4, 1126 1149 }, 1127 - .clk_list = sdm845_ufs_phy_clk_l, 1128 - .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 1129 1150 .vreg_list = qmp_phy_vreg_l, 1130 1151 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1131 1152 .regs = ufsphy_v5_regs_layout, ··· 1149 1174 .serdes = sdm845_ufsphy_hs_b_serdes, 1150 1175 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), 1151 1176 }, 1152 - .clk_list = sdm845_ufs_phy_clk_l, 1153 - .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 1154 1177 .vreg_list = qmp_phy_vreg_l, 1155 1178 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1156 1179 .regs = ufsphy_v3_regs_layout, ··· 1176 1203 .serdes = sm6115_ufsphy_hs_b_serdes, 1177 1204 .serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes), 1178 1205 }, 1179 - .clk_list = sdm845_ufs_phy_clk_l, 1180 - .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 1181 1206 .vreg_list = qmp_phy_vreg_l, 1182 1207 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1183 1208 .regs = ufsphy_v2_regs_layout, ··· 1203 1232 .serdes = sdm845_ufsphy_hs_b_serdes, 1204 1233 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), 1205 1234 }, 1206 - .clk_list = sdm845_ufs_phy_clk_l, 1207 - .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 1208 1235 .vreg_list = qmp_phy_vreg_l, 1209 1236 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1210 1237 .regs = ufsphy_v3_regs_layout, ··· 1239 1270 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), 1240 1271 .max_gear = UFS_HS_G4, 1241 1272 }, 1242 - .clk_list = sdm845_ufs_phy_clk_l, 1243 - .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 1244 1273 .vreg_list = qmp_phy_vreg_l, 1245 1274 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1246 1275 .regs = ufsphy_v4_regs_layout, ··· 1273 1306 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), 1274 1307 .max_gear = UFS_HS_G4, 1275 1308 }, 1276 - .clk_list = sdm845_ufs_phy_clk_l, 1277 - .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 1278 1309 .vreg_list = qmp_phy_vreg_l, 1279 1310 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1280 1311 .regs = ufsphy_v4_regs_layout, ··· 1307 1342 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1308 1343 .max_gear = UFS_HS_G4, 1309 1344 }, 1310 - .clk_list = sdm845_ufs_phy_clk_l, 1311 - .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 1312 1345 .vreg_list = qmp_phy_vreg_l, 1313 1346 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1314 1347 .regs = ufsphy_v5_regs_layout, ··· 1341 1378 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1342 1379 .max_gear = UFS_HS_G4, 1343 1380 }, 1344 - .clk_list = sm8450_ufs_phy_clk_l, 1345 - .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), 1346 1381 .vreg_list = qmp_phy_vreg_l, 1347 1382 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1348 1383 .regs = ufsphy_v5_regs_layout, ··· 1386 1425 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs), 1387 1426 .max_gear = UFS_HS_G5, 1388 1427 }, 1389 - .clk_list = sdm845_ufs_phy_clk_l, 1390 - .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 1391 1428 .vreg_list = qmp_phy_vreg_l, 1392 1429 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1393 1430 .regs = ufsphy_v6_regs_layout, ··· 1407 1448 .pcs = sm8650_ufsphy_pcs, 1408 1449 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_pcs), 1409 1450 }, 1410 - .clk_list = sdm845_ufs_phy_clk_l, 1411 - .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 1412 1451 .vreg_list = qmp_phy_vreg_l, 1413 1452 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1414 1453 .regs = ufsphy_v6_regs_layout, ··· 1498 1541 return ret; 1499 1542 } 1500 1543 1501 - ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1544 + ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 1502 1545 if (ret) 1503 1546 goto err_disable_regulators; 1504 1547 ··· 1518 1561 1519 1562 reset_control_assert(qmp->ufs_reset); 1520 1563 1521 - clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1564 + clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 1522 1565 1523 1566 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1524 1567 ··· 1694 1737 1695 1738 static int qmp_ufs_clk_init(struct qmp_ufs *qmp) 1696 1739 { 1697 - const struct qmp_phy_cfg *cfg = qmp->cfg; 1698 1740 struct device *dev = qmp->dev; 1699 - int num = cfg->num_clks; 1700 - int i; 1701 1741 1702 - qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 1703 - if (!qmp->clks) 1704 - return -ENOMEM; 1742 + qmp->num_clks = devm_clk_bulk_get_all(dev, &qmp->clks); 1743 + if (qmp->num_clks < 0) 1744 + return qmp->num_clks; 1705 1745 1706 - for (i = 0; i < num; i++) 1707 - qmp->clks[i].id = cfg->clk_list[i]; 1708 - 1709 - return devm_clk_bulk_get(dev, num, qmp->clks); 1746 + return 0; 1710 1747 } 1711 1748 1712 1749 static void qmp_ufs_clk_release_provider(void *res)