Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk
In preparation for support for additional platforms, convert the phy
register access clock to using the clk_bulk interfaces.
Newer SoCs like Google Tensor gs101 require additional clocks for
access to additional (different) register areas (PHY, PMA, PCS), and
converting to clk_bulk simplifies addition of those extra clocks.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Link: https://lore.kernel.org/r/20240617-usb-phy-gs101-v3-4-b66de9ae7424@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
André Draszik
and committed by
Vinod Koul
26ba3261
54290bd9
+39
-15
+39
-15
drivers/phy/samsung/phy-exynos5-usbdrd.c
+39
-15
drivers/phy/samsung/phy-exynos5-usbdrd.c
···
185
185
struct exynos5_usbdrd_phy_drvdata {
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const struct exynos5_usbdrd_phy_config *phy_cfg;
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const struct phy_ops *phy_ops;
188
+
const char * const *clk_names;
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+
int n_clks;
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const char * const *core_clk_names;
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int n_core_clks;
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u32 pmu_offset_usbdrd0_phy;
···
198
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* struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
199
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* @dev: pointer to device instance of this platform device
200
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* @reg_phy: usb phy controller register memory base
201
-
* @clk: phy clock for register access
199
+
* @clks: clocks for register access
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* @core_clks: core clocks for phy (ref, pipe3, utmi+, ITP, etc. as required)
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* @drv_data: pointer to SoC level driver data structure
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* @phys: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
···
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struct exynos5_usbdrd_phy {
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struct device *dev;
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void __iomem *reg_phy;
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-
struct clk *clk;
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+
struct clk_bulk_data *clks;
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struct clk_bulk_data *core_clks;
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const struct exynos5_usbdrd_phy_drvdata *drv_data;
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struct phy_usb_instance {
···
404
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struct phy_usb_instance *inst = phy_get_drvdata(phy);
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struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
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404
407
-
ret = clk_prepare_enable(phy_drd->clk);
405
+
ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
408
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if (ret)
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return ret;
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···
454
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reg &= ~PHYCLKRST_PORTRESET;
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writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
456
454
457
-
clk_disable_unprepare(phy_drd->clk);
455
+
clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
458
456
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457
return 0;
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}
···
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struct phy_usb_instance *inst = phy_get_drvdata(phy);
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struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
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-
ret = clk_prepare_enable(phy_drd->clk);
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+
ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
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if (ret)
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return ret;
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···
488
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PHYTEST_POWERDOWN_HSP;
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writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
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-
clk_disable_unprepare(phy_drd->clk);
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+
clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
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return 0;
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}
···
813
811
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
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int ret;
815
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-
ret = clk_prepare_enable(phy_drd->clk);
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+
ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
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815
if (ret)
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return ret;
819
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820
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/* UTMI or PIPE3 specific init */
821
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inst->phy_cfg->phy_init(phy_drd);
822
820
823
-
clk_disable_unprepare(phy_drd->clk);
821
+
clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
824
822
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return 0;
826
824
}
···
833
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u32 reg;
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int ret;
835
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836
-
ret = clk_prepare_enable(phy_drd->clk);
834
+
ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
837
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if (ret)
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return ret;
839
837
···
856
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reg &= ~CLKRST_LINK_SW_RST;
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writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
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-
clk_disable_unprepare(phy_drd->clk);
857
+
clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
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return 0;
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}
···
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struct clk *ref_clk;
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unsigned long ref_rate;
877
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878
-
phy_drd->clk = devm_clk_get(phy_drd->dev, "phy");
879
-
if (IS_ERR(phy_drd->clk)) {
880
-
dev_err(phy_drd->dev, "Failed to get phy clock\n");
881
-
return PTR_ERR(phy_drd->clk);
882
-
}
876
+
phy_drd->clks = devm_kcalloc(phy_drd->dev, phy_drd->drv_data->n_clks,
877
+
sizeof(*phy_drd->clks), GFP_KERNEL);
878
+
if (!phy_drd->clks)
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+
return -ENOMEM;
880
+
881
+
for (int i = 0; i < phy_drd->drv_data->n_clks; ++i)
882
+
phy_drd->clks[i].id = phy_drd->drv_data->clk_names[i];
883
+
884
+
ret = devm_clk_bulk_get(phy_drd->dev, phy_drd->drv_data->n_clks,
885
+
phy_drd->clks);
886
+
if (ret)
887
+
return dev_err_probe(phy_drd->dev, ret,
888
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"failed to get phy clock(s)\n");
883
889
884
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phy_drd->core_clks = devm_kcalloc(phy_drd->dev,
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phy_drd->drv_data->n_core_clks,
···
949
939
},
950
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};
951
941
942
+
static const char * const exynos5_clk_names[] = {
943
+
"phy",
944
+
};
945
+
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946
static const char * const exynos5_core_clk_names[] = {
953
947
"ref",
954
948
};
···
966
952
.phy_ops = &exynos5_usbdrd_phy_ops,
967
953
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
968
954
.pmu_offset_usbdrd1_phy = EXYNOS5420_USBDRD1_PHY_CONTROL,
955
+
.clk_names = exynos5_clk_names,
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+
.n_clks = ARRAY_SIZE(exynos5_clk_names),
969
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.core_clk_names = exynos5_core_clk_names,
970
958
.n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
971
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};
···
976
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.phy_cfg = phy_cfg_exynos5,
977
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.phy_ops = &exynos5_usbdrd_phy_ops,
978
962
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
963
+
.clk_names = exynos5_clk_names,
964
+
.n_clks = ARRAY_SIZE(exynos5_clk_names),
979
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.core_clk_names = exynos5_core_clk_names,
980
966
.n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
981
967
};
···
987
969
.phy_ops = &exynos5_usbdrd_phy_ops,
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.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
989
971
.pmu_offset_usbdrd1_phy = EXYNOS5433_USBHOST30_PHY_CONTROL,
972
+
.clk_names = exynos5_clk_names,
973
+
.n_clks = ARRAY_SIZE(exynos5_clk_names),
990
974
.core_clk_names = exynos5433_core_clk_names,
991
975
.n_core_clks = ARRAY_SIZE(exynos5433_core_clk_names),
992
976
};
···
997
977
.phy_cfg = phy_cfg_exynos5,
998
978
.phy_ops = &exynos5_usbdrd_phy_ops,
999
979
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
980
+
.clk_names = exynos5_clk_names,
981
+
.n_clks = ARRAY_SIZE(exynos5_clk_names),
1000
982
.core_clk_names = exynos5433_core_clk_names,
1001
983
.n_core_clks = ARRAY_SIZE(exynos5433_core_clk_names),
1002
984
};
···
1007
985
.phy_cfg = phy_cfg_exynos850,
1008
986
.phy_ops = &exynos850_usbdrd_phy_ops,
1009
987
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
988
+
.clk_names = exynos5_clk_names,
989
+
.n_clks = ARRAY_SIZE(exynos5_clk_names),
1010
990
.core_clk_names = exynos5_core_clk_names,
1011
991
.n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
1012
992
};