tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2026-03-28-1' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
"Weekly fixes, still a bit busy, but the usual suspects amdgpu and
i915/xe have a bunch of small fixes, and otherwise it's just a few
minor driver fixes.

loognsoon:
- update MAINTAINERS

shmem:
- fault handler fix

syncobj:
- fix GFP flags

amdgpu:
- DSC fix
- Module parameter parsing fix
- PASID reuse fix
- drm_edid leak fix
- SMU 13.x fixes
- SMU 14.x fix
- Fence fix in amdgpu_amdkfd_submit_ib()
- LVDS fixes
- GPU page fault fix for non-4K pages

amdkfd:
- Ordering fix in kfd_ioctl_create_process()

i915/display:
- DP tunnel error handling fix
- Spurious GMBUS timeout fix
- Unlink NV12 planes earlier
- Order OP vs. timeout correctly in __wait_for()

xe:
- Fix UAF in SRIOV migration restore
- Updates to HW W/a
- VMBind remap fix

ivpu:
- poweroff fix

mediatek:
- fix register ordering"

* tag 'drm-fixes-2026-03-28-1' of https://gitlab.freedesktop.org/drm/kernel: (25 commits)
MAINTAINERS: Update GPU driver maintainer information
drm/xe: always keep track of remap prev/next
drm/syncobj: Fix xa_alloc allocation flags
drm/amd/display: Fix DCE LVDS handling
drm/amdgpu: Handle GPU page faults correctly on non-4K page systems
drm/amd/pm: disable OD_FAN_CURVE if temp or pwm range invalid for smu v14
drm/amdkfd: Fix NULL pointer check order in kfd_ioctl_create_process
drm/amd/display: check if ext_caps is valid in BL setup
drm/amdgpu: Fix fence put before wait in amdgpu_amdkfd_submit_ib
drm/xe: Implement recent spec updates to Wa_16025250150
accel/ivpu: Add disable clock relinquish workaround for NVL-A0
drm/i915/dp_tunnel: Fix error handling when clearing stream BW in atomic state
drm/amd/pm: disable OD_FAN_CURVE if temp or pwm range invalid for smu v13
drm/amd/pm: Return -EOPNOTSUPP for unsupported OD_MCLK on smu_v13_0_6
drm/amd/pm: Skip redundant UCLK restore in smu_v13_0_6
drm/amd/display: Fix drm_edid leak in amdgpu_dm
drm/amdgpu: prevent immediate PASID reuse case
drm/amdgpu: fix strsep() corrupting lockup_timeout on multi-GPU (v3)
drm/amd/display: Do not skip unrelated mode changes in DSC validation
drm/xe/pf: Fix use-after-free in migration restore
...

Linus Torvalds 26df51ad 335c9017

+312 -116
+7 -1
MAINTAINERS
··· 8628 8628 F: include/uapi/drm/lima_drm.h 8629 8629 8630 8630 DRM DRIVERS FOR LOONGSON 8631 + M: Jianmin Lv <lvjianmin@loongson.cn> 8632 + M: Qianhai Wu <wuqianhai@loongson.cn> 8633 + R: Huacai Chen <chenhuacai@kernel.org> 8634 + R: Mingcong Bai <jeffbai@aosc.io> 8635 + R: Xi Ruoyao <xry111@xry111.site> 8636 + R: Icenowy Zheng <zhengxingda@iscas.ac.cn> 8631 8637 L: dri-devel@lists.freedesktop.org 8632 - S: Orphan 8638 + S: Maintained 8633 8639 T: git https://gitlab.freedesktop.org/drm/misc/kernel.git 8634 8640 F: drivers/gpu/drm/loongson/ 8635 8641
+1
drivers/accel/ivpu/ivpu_drv.h
··· 35 35 #define IVPU_HW_IP_60XX 60 36 36 37 37 #define IVPU_HW_IP_REV_LNL_B0 4 38 + #define IVPU_HW_IP_REV_NVL_A0 0 38 39 39 40 #define IVPU_HW_BTRS_MTL 1 40 41 #define IVPU_HW_BTRS_LNL 2
+4 -2
drivers/accel/ivpu/ivpu_hw.c
··· 70 70 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) 71 71 vdev->wa.interrupt_clear_with_0 = ivpu_hw_btrs_irqs_clear_with_0_mtl(vdev); 72 72 73 - if (ivpu_device_id(vdev) == PCI_DEVICE_ID_LNL && 74 - ivpu_revision(vdev) < IVPU_HW_IP_REV_LNL_B0) 73 + if ((ivpu_device_id(vdev) == PCI_DEVICE_ID_LNL && 74 + ivpu_revision(vdev) < IVPU_HW_IP_REV_LNL_B0) || 75 + (ivpu_device_id(vdev) == PCI_DEVICE_ID_NVL && 76 + ivpu_revision(vdev) == IVPU_HW_IP_REV_NVL_A0)) 75 77 vdev->wa.disable_clock_relinquish = true; 76 78 77 79 if (ivpu_test_mode & IVPU_TEST_MODE_CLK_RELINQ_ENABLE)
+2 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
··· 692 692 goto err_ib_sched; 693 693 } 694 694 695 - /* Drop the initial kref_init count (see drm_sched_main as example) */ 696 - dma_fence_put(f); 697 695 ret = dma_fence_wait(f, false); 696 + /* Drop the returned fence reference after the wait completes */ 697 + dma_fence_put(f); 698 698 699 699 err_ib_sched: 700 700 amdgpu_job_free(job);
+11 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 4207 4207 4208 4208 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) 4209 4209 { 4210 - char *input = amdgpu_lockup_timeout; 4210 + char buf[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 4211 + char *input = buf; 4211 4212 char *timeout_setting = NULL; 4212 4213 int index = 0; 4213 4214 long timeout; ··· 4218 4217 adev->gfx_timeout = adev->compute_timeout = adev->sdma_timeout = 4219 4218 adev->video_timeout = msecs_to_jiffies(2000); 4220 4219 4221 - if (!strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) 4220 + if (!strnlen(amdgpu_lockup_timeout, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) 4222 4221 return 0; 4222 + 4223 + /* 4224 + * strsep() destructively modifies its input by replacing delimiters 4225 + * with '\0'. Use a stack copy so the global module parameter buffer 4226 + * remains intact for multi-GPU systems where this function is called 4227 + * once per device. 4228 + */ 4229 + strscpy(buf, amdgpu_lockup_timeout, sizeof(buf)); 4223 4230 4224 4231 while ((timeout_setting = strsep(&input, ",")) && 4225 4232 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
+32 -13
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
··· 35 35 * PASIDs are global address space identifiers that can be shared 36 36 * between the GPU, an IOMMU and the driver. VMs on different devices 37 37 * may use the same PASID if they share the same address 38 - * space. Therefore PASIDs are allocated using a global IDA. VMs are 39 - * looked up from the PASID per amdgpu_device. 38 + * space. Therefore PASIDs are allocated using IDR cyclic allocator 39 + * (similar to kernel PID allocation) which naturally delays reuse. 40 + * VMs are looked up from the PASID per amdgpu_device. 40 41 */ 41 - static DEFINE_IDA(amdgpu_pasid_ida); 42 + 43 + static DEFINE_IDR(amdgpu_pasid_idr); 44 + static DEFINE_SPINLOCK(amdgpu_pasid_idr_lock); 42 45 43 46 /* Helper to free pasid from a fence callback */ 44 47 struct amdgpu_pasid_cb { ··· 53 50 * amdgpu_pasid_alloc - Allocate a PASID 54 51 * @bits: Maximum width of the PASID in bits, must be at least 1 55 52 * 56 - * Allocates a PASID of the given width while keeping smaller PASIDs 57 - * available if possible. 53 + * Uses kernel's IDR cyclic allocator (same as PID allocation). 54 + * Allocates sequentially with automatic wrap-around. 58 55 * 59 56 * Returns a positive integer on success. Returns %-EINVAL if bits==0. 60 57 * Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on ··· 62 59 */ 63 60 int amdgpu_pasid_alloc(unsigned int bits) 64 61 { 65 - int pasid = -EINVAL; 62 + int pasid; 66 63 67 - for (bits = min(bits, 31U); bits > 0; bits--) { 68 - pasid = ida_alloc_range(&amdgpu_pasid_ida, 1U << (bits - 1), 69 - (1U << bits) - 1, GFP_KERNEL); 70 - if (pasid != -ENOSPC) 71 - break; 72 - } 64 + if (bits == 0) 65 + return -EINVAL; 66 + 67 + spin_lock(&amdgpu_pasid_idr_lock); 68 + pasid = idr_alloc_cyclic(&amdgpu_pasid_idr, NULL, 1, 69 + 1U << bits, GFP_KERNEL); 70 + spin_unlock(&amdgpu_pasid_idr_lock); 73 71 74 72 if (pasid >= 0) 75 73 trace_amdgpu_pasid_allocated(pasid); ··· 85 81 void amdgpu_pasid_free(u32 pasid) 86 82 { 87 83 trace_amdgpu_pasid_freed(pasid); 88 - ida_free(&amdgpu_pasid_ida, pasid); 84 + 85 + spin_lock(&amdgpu_pasid_idr_lock); 86 + idr_remove(&amdgpu_pasid_idr, pasid); 87 + spin_unlock(&amdgpu_pasid_idr_lock); 89 88 } 90 89 91 90 static void amdgpu_pasid_free_cb(struct dma_fence *fence, ··· 622 615 dma_fence_put(id->pasid_mapping); 623 616 } 624 617 } 618 + } 619 + 620 + /** 621 + * amdgpu_pasid_mgr_cleanup - cleanup PASID manager 622 + * 623 + * Cleanup the IDR allocator. 624 + */ 625 + void amdgpu_pasid_mgr_cleanup(void) 626 + { 627 + spin_lock(&amdgpu_pasid_idr_lock); 628 + idr_destroy(&amdgpu_pasid_idr); 629 + spin_unlock(&amdgpu_pasid_idr_lock); 625 630 }
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
··· 74 74 void amdgpu_pasid_free(u32 pasid); 75 75 void amdgpu_pasid_free_delayed(struct dma_resv *resv, 76 76 u32 pasid); 77 + void amdgpu_pasid_mgr_cleanup(void); 77 78 78 79 bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev, 79 80 struct amdgpu_vmid *id);
+4 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
··· 2898 2898 xa_destroy(&adev->vm_manager.pasids); 2899 2899 2900 2900 amdgpu_vmid_mgr_fini(adev); 2901 + amdgpu_pasid_mgr_cleanup(); 2901 2902 } 2902 2903 2903 2904 /** ··· 2974 2973 if (!root) 2975 2974 return false; 2976 2975 2977 - addr /= AMDGPU_GPU_PAGE_SIZE; 2978 - 2979 2976 if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid, 2980 - node_id, addr, ts, write_fault)) { 2977 + node_id, addr >> PAGE_SHIFT, ts, write_fault)) { 2981 2978 amdgpu_bo_unref(&root); 2982 2979 return true; 2983 2980 } 2981 + 2982 + addr /= AMDGPU_GPU_PAGE_SIZE; 2984 2983 2985 2984 r = amdgpu_bo_reserve(root, true); 2986 2985 if (r)
+3 -3
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
··· 3170 3170 struct kfd_process *process; 3171 3171 int ret; 3172 3172 3173 - /* Each FD owns only one kfd_process */ 3174 - if (p->context_id != KFD_CONTEXT_ID_PRIMARY) 3173 + if (!filep->private_data || !p) 3175 3174 return -EINVAL; 3176 3175 3177 - if (!filep->private_data || !p) 3176 + /* Each FD owns only one kfd_process */ 3177 + if (p->context_id != KFD_CONTEXT_ID_PRIMARY) 3178 3178 return -EINVAL; 3179 3179 3180 3180 mutex_lock(&kfd_processes_mutex);
+8 -2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 3909 3909 3910 3910 aconnector->dc_sink = sink; 3911 3911 dc_sink_retain(aconnector->dc_sink); 3912 + drm_edid_free(aconnector->drm_edid); 3913 + aconnector->drm_edid = NULL; 3912 3914 if (sink->dc_edid.length == 0) { 3913 - aconnector->drm_edid = NULL; 3914 3915 hdmi_cec_unset_edid(aconnector); 3915 3916 if (aconnector->dc_link->aux_mode) { 3916 3917 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); ··· 5423 5422 caps = &dm->backlight_caps[aconnector->bl_idx]; 5424 5423 5425 5424 /* Only offer ABM property when non-OLED and user didn't turn off by module parameter */ 5426 - if (!caps->ext_caps->bits.oled && amdgpu_dm_abm_level < 0) 5425 + if (caps->ext_caps && !caps->ext_caps->bits.oled && amdgpu_dm_abm_level < 0) 5427 5426 drm_object_attach_property(&aconnector->base.base, 5428 5427 dm->adev->mode_info.abm_level_property, 5429 5428 ABM_SYSFS_CONTROL); ··· 12524 12523 } 12525 12524 12526 12525 if (dc_resource_is_dsc_encoding_supported(dc)) { 12526 + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 12527 + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 12528 + dm_new_crtc_state->mode_changed_independent_from_dsc = new_crtc_state->mode_changed; 12529 + } 12530 + 12527 12531 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 12528 12532 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 12529 12533 ret = add_affected_mst_dsc_crtcs(state, crtc);
+1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
··· 984 984 985 985 bool freesync_vrr_info_changed; 986 986 987 + bool mode_changed_independent_from_dsc; 987 988 bool dsc_force_changed; 988 989 bool vrr_supported; 989 990 struct mod_freesync_config freesync_config;
+3 -1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
··· 1744 1744 int ind = find_crtc_index_in_state_by_stream(state, stream); 1745 1745 1746 1746 if (ind >= 0) { 1747 + struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(state->crtcs[ind].new_state); 1748 + 1747 1749 DRM_INFO_ONCE("%s:%d MST_DSC no mode changed for stream 0x%p\n", 1748 1750 __func__, __LINE__, stream); 1749 - state->crtcs[ind].new_state->mode_changed = 0; 1751 + dm_new_crtc_state->base.mode_changed = dm_new_crtc_state->mode_changed_independent_from_dsc; 1750 1752 } 1751 1753 } 1752 1754 }
+2 -4
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
··· 650 650 return &enc110->base; 651 651 } 652 652 653 - if (enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 654 - return NULL; 655 - 656 653 link_regs_id = 657 654 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 658 655 ··· 658 661 &link_enc_feature, 659 662 &link_enc_regs[link_regs_id], 660 663 &link_enc_aux_regs[enc_init_data->channel - 1], 661 - &link_enc_hpd_regs[enc_init_data->hpd_source]); 664 + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? 665 + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); 662 666 return &enc110->base; 663 667 } 664 668
+3 -2
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
··· 671 671 kzalloc_obj(struct dce110_link_encoder); 672 672 int link_regs_id; 673 673 674 - if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 674 + if (!enc110) 675 675 return NULL; 676 676 677 677 link_regs_id = ··· 682 682 &link_enc_feature, 683 683 &link_enc_regs[link_regs_id], 684 684 &link_enc_aux_regs[enc_init_data->channel - 1], 685 - &link_enc_hpd_regs[enc_init_data->hpd_source]); 685 + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? 686 + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); 686 687 return &enc110->base; 687 688 } 688 689
+3 -2
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
··· 632 632 kzalloc_obj(struct dce110_link_encoder); 633 633 int link_regs_id; 634 634 635 - if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 635 + if (!enc110) 636 636 return NULL; 637 637 638 638 link_regs_id = ··· 643 643 &link_enc_feature, 644 644 &link_enc_regs[link_regs_id], 645 645 &link_enc_aux_regs[enc_init_data->channel - 1], 646 - &link_enc_hpd_regs[enc_init_data->hpd_source]); 646 + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? 647 + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); 647 648 return &enc110->base; 648 649 } 649 650
+3 -2
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
··· 716 716 kzalloc_obj(struct dce110_link_encoder); 717 717 int link_regs_id; 718 718 719 - if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 719 + if (!enc110) 720 720 return NULL; 721 721 722 722 link_regs_id = ··· 727 727 &link_enc_feature, 728 728 &link_enc_regs[link_regs_id], 729 729 &link_enc_aux_regs[enc_init_data->channel - 1], 730 - &link_enc_hpd_regs[enc_init_data->hpd_source]); 730 + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? 731 + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); 731 732 732 733 return &enc110->base; 733 734 }
+6 -8
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
··· 746 746 return &enc110->base; 747 747 } 748 748 749 - if (enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 750 - return NULL; 751 - 752 749 link_regs_id = 753 750 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 754 751 755 752 dce60_link_encoder_construct(enc110, 756 - enc_init_data, 757 - &link_enc_feature, 758 - &link_enc_regs[link_regs_id], 759 - &link_enc_aux_regs[enc_init_data->channel - 1], 760 - &link_enc_hpd_regs[enc_init_data->hpd_source]); 753 + enc_init_data, 754 + &link_enc_feature, 755 + &link_enc_regs[link_regs_id], 756 + &link_enc_aux_regs[enc_init_data->channel - 1], 757 + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? 758 + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); 761 759 return &enc110->base; 762 760 } 763 761
+2 -4
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
··· 752 752 return &enc110->base; 753 753 } 754 754 755 - if (enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 756 - return NULL; 757 - 758 755 link_regs_id = 759 756 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 760 757 ··· 760 763 &link_enc_feature, 761 764 &link_enc_regs[link_regs_id], 762 765 &link_enc_aux_regs[enc_init_data->channel - 1], 763 - &link_enc_hpd_regs[enc_init_data->hpd_source]); 766 + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? 767 + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); 764 768 return &enc110->base; 765 769 } 766 770
+32 -1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
··· 59 59 60 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 61 62 + static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu, 63 + int od_feature_bit, 64 + int32_t *min, int32_t *max); 65 + 62 66 static const struct smu_feature_bits smu_v13_0_0_dpm_features = { 63 67 .bits = { 64 68 SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), ··· 1047 1043 PPTable_t *pptable = smu->smu_table.driver_pptable; 1048 1044 const OverDriveLimits_t * const overdrive_upperlimits = 1049 1045 &pptable->SkuTable.OverDriveLimitsBasicMax; 1046 + int32_t min_value, max_value; 1047 + bool feature_enabled; 1050 1048 1051 - return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit); 1049 + switch (od_feature_bit) { 1050 + case PP_OD_FEATURE_FAN_CURVE_BIT: 1051 + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); 1052 + if (feature_enabled) { 1053 + smu_v13_0_0_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_TEMP, 1054 + &min_value, &max_value); 1055 + if (!min_value && !max_value) { 1056 + feature_enabled = false; 1057 + goto out; 1058 + } 1059 + 1060 + smu_v13_0_0_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_PWM, 1061 + &min_value, &max_value); 1062 + if (!min_value && !max_value) { 1063 + feature_enabled = false; 1064 + goto out; 1065 + } 1066 + } 1067 + break; 1068 + default: 1069 + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); 1070 + break; 1071 + } 1072 + 1073 + out: 1074 + return feature_enabled; 1052 1075 } 1053 1076 1054 1077 static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu,
+12 -9
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
··· 1391 1391 break; 1392 1392 case SMU_OD_MCLK: 1393 1393 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SET_UCLK_MAX))) 1394 - return 0; 1394 + return -EOPNOTSUPP; 1395 1395 1396 1396 size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK"); 1397 1397 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", ··· 2122 2122 { 2123 2123 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 2124 2124 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 2125 + struct smu_dpm_table *uclk_table = &dpm_context->dpm_tables.uclk_table; 2125 2126 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 2126 2127 uint32_t min_clk; 2127 2128 uint32_t max_clk; ··· 2222 2221 if (ret) 2223 2222 return ret; 2224 2223 2225 - min_clk = SMU_DPM_TABLE_MIN( 2226 - &dpm_context->dpm_tables.uclk_table); 2227 - max_clk = SMU_DPM_TABLE_MAX( 2228 - &dpm_context->dpm_tables.uclk_table); 2229 - ret = smu_v13_0_6_set_soft_freq_limited_range( 2230 - smu, SMU_UCLK, min_clk, max_clk, false); 2231 - if (ret) 2232 - return ret; 2224 + if (SMU_DPM_TABLE_MAX(uclk_table) != 2225 + pstate_table->uclk_pstate.curr.max) { 2226 + min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.uclk_table); 2227 + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.uclk_table); 2228 + ret = smu_v13_0_6_set_soft_freq_limited_range(smu, 2229 + SMU_UCLK, min_clk, 2230 + max_clk, false); 2231 + if (ret) 2232 + return ret; 2233 + } 2233 2234 smu_v13_0_reset_custom_level(smu); 2234 2235 } 2235 2236 break;
+32 -1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
··· 59 59 60 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 61 62 + static void smu_v13_0_7_get_od_setting_limits(struct smu_context *smu, 63 + int od_feature_bit, 64 + int32_t *min, int32_t *max); 65 + 62 66 static const struct smu_feature_bits smu_v13_0_7_dpm_features = { 63 67 .bits = { 64 68 SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), ··· 1057 1053 PPTable_t *pptable = smu->smu_table.driver_pptable; 1058 1054 const OverDriveLimits_t * const overdrive_upperlimits = 1059 1055 &pptable->SkuTable.OverDriveLimitsBasicMax; 1056 + int32_t min_value, max_value; 1057 + bool feature_enabled; 1060 1058 1061 - return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit); 1059 + switch (od_feature_bit) { 1060 + case PP_OD_FEATURE_FAN_CURVE_BIT: 1061 + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); 1062 + if (feature_enabled) { 1063 + smu_v13_0_7_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_TEMP, 1064 + &min_value, &max_value); 1065 + if (!min_value && !max_value) { 1066 + feature_enabled = false; 1067 + goto out; 1068 + } 1069 + 1070 + smu_v13_0_7_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_PWM, 1071 + &min_value, &max_value); 1072 + if (!min_value && !max_value) { 1073 + feature_enabled = false; 1074 + goto out; 1075 + } 1076 + } 1077 + break; 1078 + default: 1079 + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); 1080 + break; 1081 + } 1082 + 1083 + out: 1084 + return feature_enabled; 1062 1085 } 1063 1086 1064 1087 static void smu_v13_0_7_get_od_setting_limits(struct smu_context *smu,
+32 -1
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
··· 56 56 57 57 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 58 58 59 + static void smu_v14_0_2_get_od_setting_limits(struct smu_context *smu, 60 + int od_feature_bit, 61 + int32_t *min, int32_t *max); 62 + 59 63 static const struct smu_feature_bits smu_v14_0_2_dpm_features = { 60 64 .bits = { SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), 61 65 SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), ··· 926 922 PPTable_t *pptable = smu->smu_table.driver_pptable; 927 923 const OverDriveLimits_t * const overdrive_upperlimits = 928 924 &pptable->SkuTable.OverDriveLimitsBasicMax; 925 + int32_t min_value, max_value; 926 + bool feature_enabled; 929 927 930 - return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit); 928 + switch (od_feature_bit) { 929 + case PP_OD_FEATURE_FAN_CURVE_BIT: 930 + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); 931 + if (feature_enabled) { 932 + smu_v14_0_2_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_TEMP, 933 + &min_value, &max_value); 934 + if (!min_value && !max_value) { 935 + feature_enabled = false; 936 + goto out; 937 + } 938 + 939 + smu_v14_0_2_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_PWM, 940 + &min_value, &max_value); 941 + if (!min_value && !max_value) { 942 + feature_enabled = false; 943 + goto out; 944 + } 945 + } 946 + break; 947 + default: 948 + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); 949 + break; 950 + } 951 + 952 + out: 953 + return feature_enabled; 931 954 } 932 955 933 956 static void smu_v14_0_2_get_od_setting_limits(struct smu_context *smu,
+27 -21
drivers/gpu/drm/drm_gem_shmem_helper.c
··· 550 550 } 551 551 EXPORT_SYMBOL_GPL(drm_gem_shmem_dumb_create); 552 552 553 - static bool drm_gem_shmem_try_map_pmd(struct vm_fault *vmf, unsigned long addr, 554 - struct page *page) 553 + static vm_fault_t try_insert_pfn(struct vm_fault *vmf, unsigned int order, 554 + unsigned long pfn) 555 555 { 556 + if (!order) { 557 + return vmf_insert_pfn(vmf->vma, vmf->address, pfn); 556 558 #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP 557 - unsigned long pfn = page_to_pfn(page); 558 - unsigned long paddr = pfn << PAGE_SHIFT; 559 - bool aligned = (addr & ~PMD_MASK) == (paddr & ~PMD_MASK); 559 + } else if (order == PMD_ORDER) { 560 + unsigned long paddr = pfn << PAGE_SHIFT; 561 + bool aligned = (vmf->address & ~PMD_MASK) == (paddr & ~PMD_MASK); 560 562 561 - if (aligned && 562 - pmd_none(*vmf->pmd) && 563 - folio_test_pmd_mappable(page_folio(page))) { 564 - pfn &= PMD_MASK >> PAGE_SHIFT; 565 - if (vmf_insert_pfn_pmd(vmf, pfn, false) == VM_FAULT_NOPAGE) 566 - return true; 567 - } 563 + if (aligned && 564 + folio_test_pmd_mappable(page_folio(pfn_to_page(pfn)))) { 565 + pfn &= PMD_MASK >> PAGE_SHIFT; 566 + return vmf_insert_pfn_pmd(vmf, pfn, false); 567 + } 568 568 #endif 569 - 570 - return false; 569 + } 570 + return VM_FAULT_FALLBACK; 571 571 } 572 572 573 - static vm_fault_t drm_gem_shmem_fault(struct vm_fault *vmf) 573 + static vm_fault_t drm_gem_shmem_any_fault(struct vm_fault *vmf, unsigned int order) 574 574 { 575 575 struct vm_area_struct *vma = vmf->vma; 576 576 struct drm_gem_object *obj = vma->vm_private_data; ··· 580 580 struct page **pages = shmem->pages; 581 581 pgoff_t page_offset; 582 582 unsigned long pfn; 583 + 584 + if (order && order != PMD_ORDER) 585 + return VM_FAULT_FALLBACK; 583 586 584 587 /* Offset to faulty address in the VMA. */ 585 588 page_offset = vmf->pgoff - vma->vm_pgoff; ··· 596 593 goto out; 597 594 } 598 595 599 - if (drm_gem_shmem_try_map_pmd(vmf, vmf->address, pages[page_offset])) { 600 - ret = VM_FAULT_NOPAGE; 601 - goto out; 602 - } 603 - 604 596 pfn = page_to_pfn(pages[page_offset]); 605 - ret = vmf_insert_pfn(vma, vmf->address, pfn); 597 + ret = try_insert_pfn(vmf, order, pfn); 606 598 607 599 out: 608 600 dma_resv_unlock(shmem->base.resv); 609 601 610 602 return ret; 603 + } 604 + 605 + static vm_fault_t drm_gem_shmem_fault(struct vm_fault *vmf) 606 + { 607 + return drm_gem_shmem_any_fault(vmf, 0); 611 608 } 612 609 613 610 static void drm_gem_shmem_vm_open(struct vm_area_struct *vma) ··· 646 643 647 644 const struct vm_operations_struct drm_gem_shmem_vm_ops = { 648 645 .fault = drm_gem_shmem_fault, 646 + #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP 647 + .huge_fault = drm_gem_shmem_any_fault, 648 + #endif 649 649 .open = drm_gem_shmem_vm_open, 650 650 .close = drm_gem_shmem_vm_close, 651 651 };
+2 -2
drivers/gpu/drm/drm_syncobj.c
··· 602 602 drm_syncobj_get(syncobj); 603 603 604 604 ret = xa_alloc(&file_private->syncobj_xa, handle, syncobj, xa_limit_32b, 605 - GFP_NOWAIT); 605 + GFP_KERNEL); 606 606 if (ret) 607 607 drm_syncobj_put(syncobj); 608 608 ··· 716 716 drm_syncobj_get(syncobj); 717 717 718 718 ret = xa_alloc(&file_private->syncobj_xa, handle, syncobj, xa_limit_32b, 719 - GFP_NOWAIT); 719 + GFP_KERNEL); 720 720 if (ret) 721 721 drm_syncobj_put(syncobj); 722 722
+7 -1
drivers/gpu/drm/i915/display/intel_display.c
··· 4602 4602 struct intel_crtc_state *crtc_state = 4603 4603 intel_atomic_get_new_crtc_state(state, crtc); 4604 4604 struct intel_crtc_state *saved_state; 4605 + int err; 4605 4606 4606 4607 saved_state = intel_crtc_state_alloc(crtc); 4607 4608 if (!saved_state) ··· 4611 4610 /* free the old crtc_state->hw members */ 4612 4611 intel_crtc_free_hw_state(crtc_state); 4613 4612 4614 - intel_dp_tunnel_atomic_clear_stream_bw(state, crtc_state); 4613 + err = intel_dp_tunnel_atomic_clear_stream_bw(state, crtc_state); 4614 + if (err) { 4615 + kfree(saved_state); 4616 + 4617 + return err; 4618 + } 4615 4619 4616 4620 /* FIXME: before the switch to atomic started, a new pipe_config was 4617 4621 * kzalloc'd. Code that depends on any field being zero should be
+14 -6
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
··· 621 621 * 622 622 * Clear any DP tunnel stream BW requirement set by 623 623 * intel_dp_tunnel_atomic_compute_stream_bw(). 624 + * 625 + * Returns 0 in case of success, a negative error code otherwise. 624 626 */ 625 - void intel_dp_tunnel_atomic_clear_stream_bw(struct intel_atomic_state *state, 626 - struct intel_crtc_state *crtc_state) 627 + int intel_dp_tunnel_atomic_clear_stream_bw(struct intel_atomic_state *state, 628 + struct intel_crtc_state *crtc_state) 627 629 { 628 630 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 631 + int err; 629 632 630 633 if (!crtc_state->dp_tunnel_ref.tunnel) 631 - return; 634 + return 0; 632 635 633 - drm_dp_tunnel_atomic_set_stream_bw(&state->base, 634 - crtc_state->dp_tunnel_ref.tunnel, 635 - crtc->pipe, 0); 636 + err = drm_dp_tunnel_atomic_set_stream_bw(&state->base, 637 + crtc_state->dp_tunnel_ref.tunnel, 638 + crtc->pipe, 0); 639 + if (err) 640 + return err; 641 + 636 642 drm_dp_tunnel_ref_put(&crtc_state->dp_tunnel_ref); 643 + 644 + return 0; 637 645 } 638 646 639 647 /**
+7 -4
drivers/gpu/drm/i915/display/intel_dp_tunnel.h
··· 40 40 struct intel_dp *intel_dp, 41 41 const struct intel_connector *connector, 42 42 struct intel_crtc_state *crtc_state); 43 - void intel_dp_tunnel_atomic_clear_stream_bw(struct intel_atomic_state *state, 44 - struct intel_crtc_state *crtc_state); 43 + int intel_dp_tunnel_atomic_clear_stream_bw(struct intel_atomic_state *state, 44 + struct intel_crtc_state *crtc_state); 45 45 46 46 int intel_dp_tunnel_atomic_add_state_for_crtc(struct intel_atomic_state *state, 47 47 struct intel_crtc *crtc); ··· 88 88 return 0; 89 89 } 90 90 91 - static inline void 91 + static inline int 92 92 intel_dp_tunnel_atomic_clear_stream_bw(struct intel_atomic_state *state, 93 - struct intel_crtc_state *crtc_state) {} 93 + struct intel_crtc_state *crtc_state) 94 + { 95 + return 0; 96 + } 94 97 95 98 static inline int 96 99 intel_dp_tunnel_atomic_add_state_for_crtc(struct intel_atomic_state *state,
+3 -1
drivers/gpu/drm/i915/display/intel_gmbus.c
··· 496 496 497 497 val = intel_de_read_fw(display, GMBUS3(display)); 498 498 do { 499 - if (extra_byte_added && len == 1) 499 + if (extra_byte_added && len == 1) { 500 + len--; 500 501 break; 502 + } 501 503 502 504 *buf++ = val & 0xff; 503 505 val >>= 8;
+9 -2
drivers/gpu/drm/i915/display/intel_plane.c
··· 436 436 drm_framebuffer_get(plane_state->hw.fb); 437 437 } 438 438 439 + static void unlink_nv12_plane(struct intel_crtc_state *crtc_state, 440 + struct intel_plane_state *plane_state); 441 + 439 442 void intel_plane_set_invisible(struct intel_crtc_state *crtc_state, 440 443 struct intel_plane_state *plane_state) 441 444 { 442 445 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 446 + 447 + unlink_nv12_plane(crtc_state, plane_state); 443 448 444 449 crtc_state->active_planes &= ~BIT(plane->id); 445 450 crtc_state->scaled_planes &= ~BIT(plane->id); ··· 1518 1513 struct intel_display *display = to_intel_display(plane_state); 1519 1514 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1520 1515 1516 + if (!plane_state->planar_linked_plane) 1517 + return; 1518 + 1521 1519 plane_state->planar_linked_plane = NULL; 1522 1520 1523 1521 if (!plane_state->is_y_plane) ··· 1558 1550 if (plane->pipe != crtc->pipe) 1559 1551 continue; 1560 1552 1561 - if (plane_state->planar_linked_plane) 1562 - unlink_nv12_plane(crtc_state, plane_state); 1553 + unlink_nv12_plane(crtc_state, plane_state); 1563 1554 } 1564 1555 1565 1556 if (!crtc_state->nv12_planes)
+1 -1
drivers/gpu/drm/i915/i915_wait_util.h
··· 25 25 might_sleep(); \ 26 26 for (;;) { \ 27 27 const bool expired__ = ktime_after(ktime_get_raw(), end__); \ 28 - OP; \ 29 28 /* Guarantee COND check prior to timeout */ \ 30 29 barrier(); \ 30 + OP; \ 31 31 if (COND) { \ 32 32 ret__ = 0; \ 33 33 break; \
+5 -4
drivers/gpu/drm/mediatek/mtk_dsi.c
··· 1236 1236 1237 1237 dsi->host.ops = &mtk_dsi_ops; 1238 1238 dsi->host.dev = dev; 1239 + 1240 + init_waitqueue_head(&dsi->irq_wait_queue); 1241 + 1242 + platform_set_drvdata(pdev, dsi); 1243 + 1239 1244 ret = mipi_dsi_host_register(&dsi->host); 1240 1245 if (ret < 0) 1241 1246 return dev_err_probe(dev, ret, "Failed to register DSI host\n"); ··· 1251 1246 mipi_dsi_host_unregister(&dsi->host); 1252 1247 return dev_err_probe(&pdev->dev, ret, "Failed to request DSI irq\n"); 1253 1248 } 1254 - 1255 - init_waitqueue_head(&dsi->irq_wait_queue); 1256 - 1257 - platform_set_drvdata(pdev, dsi); 1258 1249 1259 1250 dsi->bridge.of_node = dev->of_node; 1260 1251 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
+1
drivers/gpu/drm/xe/regs/xe_gt_regs.h
··· 553 553 #define ENABLE_SMP_LD_RENDER_SURFACE_CONTROL REG_BIT(44 - 32) 554 554 #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32) 555 555 #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32) 556 + #define L3_128B_256B_WRT_DIS REG_BIT(40 - 32) 556 557 #define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32) 557 558 #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32) 558 559
+6 -6
drivers/gpu/drm/xe/xe_pt.c
··· 1442 1442 err = vma_check_userptr(vm, op->map.vma, pt_update); 1443 1443 break; 1444 1444 case DRM_GPUVA_OP_REMAP: 1445 - if (op->remap.prev) 1445 + if (op->remap.prev && !op->remap.skip_prev) 1446 1446 err = vma_check_userptr(vm, op->remap.prev, pt_update); 1447 - if (!err && op->remap.next) 1447 + if (!err && op->remap.next && !op->remap.skip_next) 1448 1448 err = vma_check_userptr(vm, op->remap.next, pt_update); 1449 1449 break; 1450 1450 case DRM_GPUVA_OP_UNMAP: ··· 2198 2198 2199 2199 err = unbind_op_prepare(tile, pt_update_ops, old); 2200 2200 2201 - if (!err && op->remap.prev) { 2201 + if (!err && op->remap.prev && !op->remap.skip_prev) { 2202 2202 err = bind_op_prepare(vm, tile, pt_update_ops, 2203 2203 op->remap.prev, false); 2204 2204 pt_update_ops->wait_vm_bookkeep = true; 2205 2205 } 2206 - if (!err && op->remap.next) { 2206 + if (!err && op->remap.next && !op->remap.skip_next) { 2207 2207 err = bind_op_prepare(vm, tile, pt_update_ops, 2208 2208 op->remap.next, false); 2209 2209 pt_update_ops->wait_vm_bookkeep = true; ··· 2428 2428 2429 2429 unbind_op_commit(vm, tile, pt_update_ops, old, fence, fence2); 2430 2430 2431 - if (op->remap.prev) 2431 + if (op->remap.prev && !op->remap.skip_prev) 2432 2432 bind_op_commit(vm, tile, pt_update_ops, op->remap.prev, 2433 2433 fence, fence2, false); 2434 - if (op->remap.next) 2434 + if (op->remap.next && !op->remap.skip_next) 2435 2435 bind_op_commit(vm, tile, pt_update_ops, op->remap.next, 2436 2436 fence, fence2, false); 2437 2437 break;
+2
drivers/gpu/drm/xe/xe_sriov_packet.c
··· 341 341 ret = xe_sriov_pf_migration_restore_produce(xe, vfid, *data); 342 342 if (ret) { 343 343 xe_sriov_packet_free(*data); 344 + *data = NULL; 345 + 344 346 return ret; 345 347 } 346 348
+18 -4
drivers/gpu/drm/xe/xe_vm.c
··· 2554 2554 if (!err && op->remap.skip_prev) { 2555 2555 op->remap.prev->tile_present = 2556 2556 tile_present; 2557 - op->remap.prev = NULL; 2558 2557 } 2559 2558 } 2560 2559 if (op->remap.next) { ··· 2563 2564 if (!err && op->remap.skip_next) { 2564 2565 op->remap.next->tile_present = 2565 2566 tile_present; 2566 - op->remap.next = NULL; 2567 2567 } 2568 2568 } 2569 2569 2570 - /* Adjust for partial unbind after removing VMA from VM */ 2570 + /* 2571 + * Adjust for partial unbind after removing VMA from VM. In case 2572 + * of unwind we might need to undo this later. 2573 + */ 2571 2574 if (!err) { 2572 2575 op->base.remap.unmap->va->va.addr = op->remap.start; 2573 2576 op->base.remap.unmap->va->va.range = op->remap.range; ··· 2688 2687 2689 2688 op->remap.start = xe_vma_start(old); 2690 2689 op->remap.range = xe_vma_size(old); 2690 + op->remap.old_start = op->remap.start; 2691 + op->remap.old_range = op->remap.range; 2691 2692 2692 2693 flags |= op->base.remap.unmap->va->flags & XE_VMA_CREATE_MASK; 2693 2694 if (op->base.remap.prev) { ··· 2838 2835 xe_svm_notifier_lock(vm); 2839 2836 vma->gpuva.flags &= ~XE_VMA_DESTROYED; 2840 2837 xe_svm_notifier_unlock(vm); 2841 - if (post_commit) 2838 + if (post_commit) { 2839 + /* 2840 + * Restore the old va range, in case of the 2841 + * prev/next skip optimisation. Otherwise what 2842 + * we re-insert here could be smaller than the 2843 + * original range. 2844 + */ 2845 + op->base.remap.unmap->va->va.addr = 2846 + op->remap.old_start; 2847 + op->base.remap.unmap->va->va.range = 2848 + op->remap.old_range; 2842 2849 xe_vm_insert_vma(vm, vma); 2850 + } 2843 2851 } 2844 2852 break; 2845 2853 }
+4
drivers/gpu/drm/xe/xe_vm_types.h
··· 373 373 u64 start; 374 374 /** @range: range of the VMA unmap */ 375 375 u64 range; 376 + /** @old_start: Original start of the VMA we unmap */ 377 + u64 old_start; 378 + /** @old_range: Original range of the VMA we unmap */ 379 + u64 old_range; 376 380 /** @skip_prev: skip prev rebind */ 377 381 bool skip_prev; 378 382 /** @skip_next: skip next rebind */
+2 -1
drivers/gpu/drm/xe/xe_wa.c
··· 247 247 LSN_DIM_Z_WGT_MASK, 248 248 LSN_LNI_WGT(1) | LSN_LNE_WGT(1) | 249 249 LSN_DIM_X_WGT(1) | LSN_DIM_Y_WGT(1) | 250 - LSN_DIM_Z_WGT(1))) 250 + LSN_DIM_Z_WGT(1)), 251 + SET(LSC_CHICKEN_BIT_0_UDW, L3_128B_256B_WRT_DIS)) 251 252 }, 252 253 253 254 /* Xe2_HPM */