Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch kvm-arm64/fwb-for-all into kvmarm-master/next
* kvm-arm64/fwb-for-all:
: .
: Allow pKVM's host stage-2 mappings to use the Force Write Back version
: of the memory attributes by using the "pass-through' encoding.
:
: This avoids having two separate encodings for S2 on a given platform.
: .
KVM: arm64: Simplify PAGE_S2_MEMATTR
KVM: arm64: Kill KVM_PGTABLE_S2_NOFWB
KVM: arm64: Switch pKVM host S2 over to KVM_PGTABLE_S2_AS_S1
KVM: arm64: Add KVM_PGTABLE_S2_AS_S1 flag
arm64: Add MT_S2{,_FWB}_AS_S1 encodings
Signed-off-by: Marc Zyngier <maz@kernel.org>
+30
-22
+3
-4
arch/arm64/include/asm/kvm_pgtable.h
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-4
arch/arm64/include/asm/kvm_pgtable.h
···
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/**
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* enum kvm_pgtable_stage2_flags - Stage-2 page-table flags.
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-
* @KVM_PGTABLE_S2_NOFWB: Don't enforce Normal-WB even if the CPUs have
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-
* ARM64_HAS_STAGE2_FWB.
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* @KVM_PGTABLE_S2_IDMAP: Only use identity mappings.
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* @KVM_PGTABLE_S2_AS_S1: Final memory attributes are that of Stage-1.
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*/
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enum kvm_pgtable_stage2_flags {
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-
KVM_PGTABLE_S2_NOFWB = BIT(0),
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-
KVM_PGTABLE_S2_IDMAP = BIT(1),
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KVM_PGTABLE_S2_IDMAP = BIT(0),
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KVM_PGTABLE_S2_AS_S1 = BIT(1),
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};
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/**
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-3
arch/arm64/include/asm/memory.h
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arch/arm64/include/asm/memory.h
···
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#define MT_DEVICE_nGnRE 4
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/*
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-
* Memory types for Stage-2 translation
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* Memory types for Stage-2 translation when HCR_EL2.FWB=0. See R_HMNDG,
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* R_TNHFM, R_GQFSF and I_MCQKW for the details on how these attributes get
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* combined with Stage-1.
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*/
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#define MT_S2_NORMAL 0xf
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#define MT_S2_NORMAL_NC 0x5
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#define MT_S2_DEVICE_nGnRE 0x1
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#define MT_S2_AS_S1 MT_S2_NORMAL
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/*
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* Memory types for Stage-2 translation when ID_AA64MMFR2_EL1.FWB is 0001
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* Stage-2 enforces Normal-WB and Device-nGnRE
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* Memory types for Stage-2 translation when HCR_EL2.FWB=1. Stage-2 enforces
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* Normal-WB and Device-nGnRE, unless we actively say that S1 wins. See
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* R_VRJSW and R_RHWZM for details.
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*/
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#define MT_S2_FWB_NORMAL 6
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#define MT_S2_FWB_NORMAL_NC 5
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#define MT_S2_FWB_DEVICE_nGnRE 1
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#define MT_S2_FWB_AS_S1 7
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#ifdef CONFIG_ARM64_4K_PAGES
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#define IOREMAP_MAX_ORDER (PUD_SHIFT)
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arch/arm64/include/asm/pgtable-prot.h
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arch/arm64/include/asm/pgtable-prot.h
···
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#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC)
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#define PAGE_KERNEL_EXEC_CONT __pgprot(_PAGE_KERNEL_EXEC_CONT)
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-
#define PAGE_S2_MEMATTR(attr, has_fwb) \
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#define PAGE_S2_MEMATTR(attr) \
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({ \
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u64 __val; \
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-
if (has_fwb) \
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if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) \
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__val = PTE_S2_MEMATTR(MT_S2_FWB_ ## attr); \
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else \
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__val = PTE_S2_MEMATTR(MT_S2_ ## attr); \
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-1
arch/arm64/kvm/hyp/nvhe/mem_protect.c
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arch/arm64/kvm/hyp/nvhe/mem_protect.c
···
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#include <nvhe/mem_protect.h>
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#include <nvhe/mm.h>
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#define KVM_HOST_S2_FLAGS (KVM_PGTABLE_S2_NOFWB | KVM_PGTABLE_S2_IDMAP)
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#define KVM_HOST_S2_FLAGS (KVM_PGTABLE_S2_AS_S1 | KVM_PGTABLE_S2_IDMAP)
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struct host_mmu host_mmu;
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···
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params->vttbr = kvm_get_vttbr(mmu);
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params->vtcr = mmu->vtcr;
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params->hcr_el2 |= HCR_VM;
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if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
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params->hcr_el2 |= HCR_FWB;
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/*
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* The CMO below not only cleans the updated params to the
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-12
arch/arm64/kvm/hyp/pgtable.c
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arch/arm64/kvm/hyp/pgtable.c
···
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return vtcr;
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}
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-
static bool stage2_has_fwb(struct kvm_pgtable *pgt)
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{
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if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
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return false;
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return !(pgt->flags & KVM_PGTABLE_S2_NOFWB);
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}
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void kvm_tlb_flush_vmid_range(struct kvm_s2_mmu *mmu,
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phys_addr_t addr, size_t size)
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{
···
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}
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}
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-
#define KVM_S2_MEMATTR(pgt, attr) PAGE_S2_MEMATTR(attr, stage2_has_fwb(pgt))
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#define KVM_S2_MEMATTR(pgt, attr) \
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({ \
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kvm_pte_t __attr; \
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\
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if ((pgt)->flags & KVM_PGTABLE_S2_AS_S1) \
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__attr = PAGE_S2_MEMATTR(AS_S1); \
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else \
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__attr = PAGE_S2_MEMATTR(attr); \
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\
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__attr; \
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})
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static int stage2_set_xn_attr(enum kvm_pgtable_prot prot, kvm_pte_t *attr)
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{
···
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* system supporting FWB as the optimization is entirely
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* pointless when the unmap walker needs to perform CMOs.
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*/
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return system_supports_tlb_range() && stage2_has_fwb(pgt);
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return system_supports_tlb_range() && cpus_have_final_cap(ARM64_HAS_STAGE2_FWB);
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}
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static void stage2_unmap_put_pte(const struct kvm_pgtable_visit_ctx *ctx,
···
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if (mm_ops->page_count(childp) != 1)
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return 0;
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} else if (stage2_pte_cacheable(pgt, ctx->old)) {
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need_flush = !stage2_has_fwb(pgt);
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need_flush = !cpus_have_final_cap(ARM64_HAS_STAGE2_FWB);
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}
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/*
···
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.arg = pgt,
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};
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if (stage2_has_fwb(pgt))
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if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
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return 0;
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return kvm_pgtable_walk(pgt, addr, size, &walker);