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dt-bindings: PCI: Add binding for Toshiba TC9563 PCIe switch

Add a device tree binding for the Toshiba TC9563 PCIe switch, which
provides an Ethernet MAC integrated to the 3rd downstream port and
two downstream PCIe ports.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20251101-tc9563-v9-1-de3429f7787a@oss.qualcomm.com

authored by

Krishna Chaitanya Chundru and committed by
Bjorn Helgaas
26f3ac88 3a866087

+179
+179
Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pci/toshiba,tc9563.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Toshiba TC9563 PCIe switch 8 + 9 + maintainers: 10 + - Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> 11 + 12 + description: | 13 + Toshiba TC9563 PCIe switch has one upstream and three downstream ports. 14 + The 3rd downstream port has integrated endpoint device of Ethernet MAC. 15 + Other two downstream ports are supposed to connect to external device. 16 + 17 + The TC9563 PCIe switch can be configured through I2C interface before 18 + PCIe link is established to change FTS, ASPM related entry delays, 19 + tx amplitude etc for better power efficiency and functionality. 20 + 21 + properties: 22 + compatible: 23 + enum: 24 + - pci1179,0623 25 + 26 + reg: 27 + maxItems: 1 28 + 29 + resx-gpios: 30 + maxItems: 1 31 + description: 32 + GPIO controlling the RESX# pin. 33 + 34 + vdd18-supply: true 35 + 36 + vdd09-supply: true 37 + 38 + vddc-supply: true 39 + 40 + vddio1-supply: true 41 + 42 + vddio2-supply: true 43 + 44 + vddio18-supply: true 45 + 46 + i2c-parent: 47 + $ref: /schemas/types.yaml#/definitions/phandle-array 48 + description: 49 + A phandle to the parent I2C node and the slave address of the device 50 + used to configure tc9563 to change FTS, tx amplitude etc. 51 + items: 52 + - description: Phandle to the I2C controller node 53 + - description: I2C slave address 54 + 55 + patternProperties: 56 + "^pcie@[1-3],0$": 57 + description: 58 + child nodes describing the internal downstream ports of 59 + the tc9563 switch. 60 + type: object 61 + allOf: 62 + - $ref: "#/$defs/tc9563-node" 63 + - $ref: /schemas/pci/pci-pci-bridge.yaml# 64 + unevaluatedProperties: false 65 + 66 + $defs: 67 + tc9563-node: 68 + type: object 69 + 70 + properties: 71 + toshiba,tx-amplitude-microvolt: 72 + description: 73 + Change Tx Margin setting for low power consumption. 74 + 75 + toshiba,no-dfe-support: 76 + type: boolean 77 + description: 78 + Disable DFE (Decision Feedback Equalizer), which mitigates 79 + intersymbol interference and some reflections caused by 80 + impedance mismatches. 81 + 82 + required: 83 + - resx-gpios 84 + - vdd18-supply 85 + - vdd09-supply 86 + - vddc-supply 87 + - vddio1-supply 88 + - vddio2-supply 89 + - vddio18-supply 90 + - i2c-parent 91 + 92 + allOf: 93 + - $ref: "#/$defs/tc9563-node" 94 + - $ref: /schemas/pci/pci-bus-common.yaml# 95 + 96 + unevaluatedProperties: false 97 + 98 + examples: 99 + - | 100 + #include <dt-bindings/gpio/gpio.h> 101 + 102 + pcie { 103 + #address-cells = <3>; 104 + #size-cells = <2>; 105 + 106 + pcie@0 { 107 + device_type = "pci"; 108 + reg = <0x0 0x0 0x0 0x0 0x0>; 109 + 110 + #address-cells = <3>; 111 + #size-cells = <2>; 112 + ranges; 113 + bus-range = <0x01 0xff>; 114 + 115 + pcie@0,0 { 116 + compatible = "pci1179,0623"; 117 + 118 + reg = <0x10000 0x0 0x0 0x0 0x0>; 119 + device_type = "pci"; 120 + #address-cells = <3>; 121 + #size-cells = <2>; 122 + ranges; 123 + bus-range = <0x02 0xff>; 124 + 125 + i2c-parent = <&qup_i2c 0x77>; 126 + 127 + vdd18-supply = <&vdd>; 128 + vdd09-supply = <&vdd>; 129 + vddc-supply = <&vdd>; 130 + vddio1-supply = <&vdd>; 131 + vddio2-supply = <&vdd>; 132 + vddio18-supply = <&vdd>; 133 + 134 + resx-gpios = <&gpio 1 GPIO_ACTIVE_LOW>; 135 + 136 + pcie@1,0 { 137 + compatible = "pciclass,0604"; 138 + reg = <0x20800 0x0 0x0 0x0 0x0>; 139 + #address-cells = <3>; 140 + #size-cells = <2>; 141 + device_type = "pci"; 142 + ranges; 143 + bus-range = <0x03 0xff>; 144 + 145 + toshiba,no-dfe-support; 146 + }; 147 + 148 + pcie@2,0 { 149 + compatible = "pciclass,0604"; 150 + reg = <0x21000 0x0 0x0 0x0 0x0>; 151 + #address-cells = <3>; 152 + #size-cells = <2>; 153 + device_type = "pci"; 154 + ranges; 155 + bus-range = <0x04 0xff>; 156 + }; 157 + 158 + pcie@3,0 { 159 + compatible = "pciclass,0604"; 160 + reg = <0x21800 0x0 0x0 0x0 0x0>; 161 + #address-cells = <3>; 162 + #size-cells = <2>; 163 + device_type = "pci"; 164 + ranges; 165 + bus-range = <0x05 0xff>; 166 + 167 + toshiba,tx-amplitude-microvolt = <10>; 168 + 169 + ethernet@0,0 { 170 + reg = <0x50000 0x0 0x0 0x0 0x0>; 171 + }; 172 + 173 + ethernet@0,1 { 174 + reg = <0x50100 0x0 0x0 0x0 0x0>; 175 + }; 176 + }; 177 + }; 178 + }; 179 + };