Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
net: stmmac: provide common stmmac_axi_blen_to_mask()
Provide a common stmmac_axi_blen_to_mask() function to translate the
burst length array to the value for the AXI bus mode register, and use
it for dwmac, dwmac4 and dwxgmac2. Remove the now unnecessary
XGMAC_BLEN* definitions.
Note that stmmac_axi_blen_to_dma_mask() is coded to be more efficient
than the original three implementations, and verifies the contents of
the burst length array.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1vLfLR-0000000FMav-0VL6@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
authored by
Russell King (Oracle)
and committed by
Jakub Kicinski
2704af20
8c696659
+56
-93
+3
drivers/net/ethernet/stmicro/stmmac/common.h
+3
drivers/net/ethernet/stmicro/stmmac/common.h
···
557
557
#define DMA_AXI_BLEN16 BIT(3)
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#define DMA_AXI_BLEN8 BIT(2)
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#define DMA_AXI_BLEN4 BIT(1)
560
+
#define DMA_AXI_BLEN_MASK GENMASK(7, 1)
561
+
562
+
void stmmac_axi_blen_to_mask(u32 *regval, const u32 *blen, size_t len);
560
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#define STMMAC_CHAIN_MODE 0x1
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#define STMMAC_RING_MODE 0x2
+4
-27
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
+4
-27
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
···
19
19
static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
20
20
{
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u32 value = readl(ioaddr + DMA_AXI_BUS_MODE);
22
-
int i;
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pr_info("dwmac1000: Master AXI performs %s burst length\n",
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!(value & DMA_AXI_UNDEF) ? "fixed" : "any");
···
38
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/* Depending on the UNDEF bit the Master AXI will perform any burst
40
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* length according to the BLEN programmed (by default all BLEN are
41
-
* set).
42
+
* set). Note that the UNDEF bit is readonly, and is the inverse of
43
+
* Bus Mode bit 16.
42
44
*/
43
-
for (i = 0; i < AXI_BLEN; i++) {
44
-
switch (axi->axi_blen[i]) {
45
-
case 256:
46
-
value |= DMA_AXI_BLEN256;
47
-
break;
48
-
case 128:
49
-
value |= DMA_AXI_BLEN128;
50
-
break;
51
-
case 64:
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-
value |= DMA_AXI_BLEN64;
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-
break;
54
-
case 32:
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-
value |= DMA_AXI_BLEN32;
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-
break;
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-
case 16:
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-
value |= DMA_AXI_BLEN16;
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-
break;
60
-
case 8:
61
-
value |= DMA_AXI_BLEN8;
62
-
break;
63
-
case 4:
64
-
value |= DMA_AXI_BLEN4;
65
-
break;
66
-
}
67
-
}
45
+
stmmac_axi_blen_to_mask(&value, axi->axi_blen,
46
+
ARRAY_SIZE(axi->axi_blen));
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47
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writel(value, ioaddr + DMA_AXI_BUS_MODE);
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49
}
+4
-27
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
+4
-27
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
···
18
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static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
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{
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u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
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-
int i;
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pr_info("dwmac4: Master AXI performs %s burst length\n",
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(value & DMA_SYS_BUS_FB) ? "fixed" : "any");
···
37
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/* Depending on the UNDEF bit the Master AXI will perform any burst
39
40
* length according to the BLEN programmed (by default all BLEN are
40
-
* set).
41
+
* set). Note that the UNDEF bit is readonly, and is the inverse of
42
+
* Bus Mode bit 16.
41
43
*/
42
-
for (i = 0; i < AXI_BLEN; i++) {
43
-
switch (axi->axi_blen[i]) {
44
-
case 256:
45
-
value |= DMA_AXI_BLEN256;
46
-
break;
47
-
case 128:
48
-
value |= DMA_AXI_BLEN128;
49
-
break;
50
-
case 64:
51
-
value |= DMA_AXI_BLEN64;
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-
break;
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-
case 32:
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-
value |= DMA_AXI_BLEN32;
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-
break;
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-
case 16:
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-
value |= DMA_AXI_BLEN16;
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-
break;
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-
case 8:
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-
value |= DMA_AXI_BLEN8;
61
-
break;
62
-
case 4:
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-
value |= DMA_AXI_BLEN4;
64
-
break;
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-
}
66
-
}
44
+
stmmac_axi_blen_to_mask(&value, axi->axi_blen,
45
+
ARRAY_SIZE(axi->axi_blen));
67
46
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47
writel(value, ioaddr + DMA_SYS_BUS_MODE);
69
48
}
-2
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
-2
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
-2
drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
-2
drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
···
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#define DMA_AXI_UNDEF BIT(0)
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80
-
#define DMA_AXI_BURST_LEN_MASK 0x000000FE
81
-
82
80
#define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */
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#define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */
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#define DMA_HW_FEATURE 0x00001058 /* HW Feature Register */
+1
-8
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+1
-8
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
···
340
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#define XGMAC_LPI_XIT_PKT BIT(14)
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#define XGMAC_AAL DMA_AXI_AAL
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#define XGMAC_EAME BIT(11)
343
-
#define XGMAC_BLEN GENMASK(7, 1)
344
-
#define XGMAC_BLEN256 DMA_AXI_BLEN256
345
-
#define XGMAC_BLEN128 DMA_AXI_BLEN128
346
-
#define XGMAC_BLEN64 DMA_AXI_BLEN64
347
-
#define XGMAC_BLEN32 DMA_AXI_BLEN32
348
-
#define XGMAC_BLEN16 DMA_AXI_BLEN16
349
-
#define XGMAC_BLEN8 DMA_AXI_BLEN8
350
-
#define XGMAC_BLEN4 DMA_AXI_BLEN4
343
+
/* XGMAC_BLEN* are now defined as DMA_AXI_BLEN* in common.h */
351
344
#define XGMAC_UNDEF BIT(0)
352
345
#define XGMAC_TX_EDMA_CTRL 0x00003040
353
346
#define XGMAC_TDPS GENMASK(29, 0)
+7
-27
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
+7
-27
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
···
84
84
static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
85
85
{
86
86
u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
87
-
int i;
88
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if (axi->axi_lpi_en)
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value |= XGMAC_EN_LPI;
···
101
102
if (!axi->axi_fb)
102
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value |= XGMAC_UNDEF;
103
104
104
-
value &= ~XGMAC_BLEN;
105
-
for (i = 0; i < AXI_BLEN; i++) {
106
-
switch (axi->axi_blen[i]) {
107
-
case 256:
108
-
value |= XGMAC_BLEN256;
109
-
break;
110
-
case 128:
111
-
value |= XGMAC_BLEN128;
112
-
break;
113
-
case 64:
114
-
value |= XGMAC_BLEN64;
115
-
break;
116
-
case 32:
117
-
value |= XGMAC_BLEN32;
118
-
break;
119
-
case 16:
120
-
value |= XGMAC_BLEN16;
121
-
break;
122
-
case 8:
123
-
value |= XGMAC_BLEN8;
124
-
break;
125
-
case 4:
126
-
value |= XGMAC_BLEN4;
127
-
break;
128
-
}
129
-
}
105
+
/* Depending on the UNDEF bit the Master AXI will perform any burst
106
+
* length according to the BLEN programmed (by default all BLEN are
107
+
* set). Note that the UNDEF bit is readonly, and is the inverse of
108
+
* Bus Mode bit 16.
109
+
*/
110
+
stmmac_axi_blen_to_mask(&value, axi->axi_blen,
111
+
ARRAY_SIZE(axi->axi_blen));
130
112
131
113
writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
132
114
writel(XGMAC_TDPS, ioaddr + XGMAC_TX_EDMA_CTRL);
+37
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+37
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
···
190
190
EXPORT_SYMBOL_GPL(stmmac_set_clk_tx_rate);
191
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192
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/**
193
+
* stmmac_axi_blen_to_mask() - convert a burst length array to reg value
194
+
* @regval: pointer to a u32 for the resulting register value
195
+
* @blen: pointer to an array of u32 containing the burst length values in bytes
196
+
* @len: the number of entries in the @blen array
197
+
*/
198
+
void stmmac_axi_blen_to_mask(u32 *regval, const u32 *blen, size_t len)
199
+
{
200
+
size_t i;
201
+
u32 val;
202
+
203
+
for (val = i = 0; i < len; i++) {
204
+
u32 burst = blen[i];
205
+
206
+
/* Burst values of zero must be skipped. */
207
+
if (!burst)
208
+
continue;
209
+
210
+
/* The valid range for the burst length is 4 to 256 inclusive,
211
+
* and it must be a power of two.
212
+
*/
213
+
if (burst < 4 || burst > 256 || !is_power_of_2(burst)) {
214
+
pr_err("stmmac: invalid burst length %u at index %zu\n",
215
+
burst, i);
216
+
continue;
217
+
}
218
+
219
+
/* Since burst is a power of two, and the register field starts
220
+
* with burst = 4, shift right by two bits so bit 0 of the field
221
+
* corresponds with the minimum value.
222
+
*/
223
+
val |= burst >> 2;
224
+
}
225
+
226
+
u32p_replace_bits(regval, val, DMA_AXI_BLEN_MASK);
227
+
}
228
+
229
+
/**
193
230
* stmmac_verify_args - verify the driver parameters.
194
231
* Description: it checks the driver parameters and set a default in case of
195
232
* errors.