Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpio: aspeed-sgpio: Support G7 Aspeed sgpiom controller
In the 7th generation of the SoC from Aspeed, the control logic of the
SGPIO controller has been updated to support per-pin control. Each pin now
has its own 32-bit register, allowing for individual control of the pin's
value, interrupt type, and other settings.
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Link: https://lore.kernel.org/r/20260123-upstream_sgpio-v2-6-69cfd1631400@aspeedtech.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
authored by
Billy Tsai
and committed by
Bartosz Golaszewski
274ea0f1
14947001
+108
-2
+108
-2
drivers/gpio/gpio-aspeed-sgpio.c
+108
-2
drivers/gpio/gpio-aspeed-sgpio.c
···
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#define ASPEED_SGPIO_CTRL 0x54
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#define SGPIO_G7_IRQ_STS_BASE 0x40
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#define SGPIO_G7_IRQ_STS_OFFSET(x) (SGPIO_G7_IRQ_STS_BASE + (x) * 0x4)
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#define SGPIO_G7_CTRL_REG_BASE 0x80
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#define SGPIO_G7_CTRL_REG_OFFSET(x) (SGPIO_G7_CTRL_REG_BASE + (x) * 0x4)
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#define SGPIO_G7_OUT_DATA BIT(0)
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#define SGPIO_G7_PARALLEL_OUT_DATA BIT(1)
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#define SGPIO_G7_IRQ_EN BIT(2)
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#define SGPIO_G7_IRQ_TYPE0 BIT(3)
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#define SGPIO_G7_IRQ_TYPE1 BIT(4)
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#define SGPIO_G7_IRQ_TYPE2 BIT(5)
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#define SGPIO_G7_RST_TOLERANCE BIT(6)
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#define SGPIO_G7_INPUT_MASK BIT(9)
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#define SGPIO_G7_HW_BYPASS_EN BIT(10)
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#define SGPIO_G7_HW_IN_SEL BIT(11)
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#define SGPIO_G7_IRQ_STS BIT(12)
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#define SGPIO_G7_IN_DATA BIT(13)
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#define SGPIO_G7_PARALLEL_IN_DATA BIT(14)
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#define SGPIO_G7_SERIAL_OUT_SEL GENMASK(17, 16)
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#define SGPIO_G7_PARALLEL_OUT_SEL GENMASK(19, 18)
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#define SELECT_FROM_CSR 0
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#define SELECT_FROM_PARALLEL_IN 1
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#define SELECT_FROM_SERIAL_IN 2
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#define ASPEED_SGPIO_G4_CFG_OFFSET 0x54
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#define ASPEED_SGPIO_G7_CFG_OFFSET 0x0
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#define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16)
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#define ASPEED_SGPIO_ENABLE BIT(0)
···
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struct aspeed_sgpio_pdata {
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const u32 pin_mask;
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const struct aspeed_sgpio_llops *llops;
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const u32 cfg_offset;
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};
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struct aspeed_sgpio {
···
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default:
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/* acturally if code runs to here, it's an error case */
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BUG();
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}
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}
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static u32 aspeed_sgpio_g7_reg_mask(const enum aspeed_sgpio_reg reg)
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{
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switch (reg) {
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case reg_val:
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case reg_rdata:
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return SGPIO_G7_OUT_DATA;
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case reg_irq_enable:
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return SGPIO_G7_IRQ_EN;
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case reg_irq_type0:
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return SGPIO_G7_IRQ_TYPE0;
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case reg_irq_type1:
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return SGPIO_G7_IRQ_TYPE1;
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case reg_irq_type2:
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return SGPIO_G7_IRQ_TYPE2;
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case reg_irq_status:
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return SGPIO_G7_IRQ_STS;
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case reg_tolerance:
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return SGPIO_G7_RST_TOLERANCE;
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default:
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WARN_ON_ONCE(1);
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return 0;
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}
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}
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···
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static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
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.pin_mask = GENMASK(9, 6),
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.llops = &aspeed_sgpio_g4_llops,
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.cfg_offset = ASPEED_SGPIO_G4_CFG_OFFSET,
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};
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static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip,
···
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static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = {
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.pin_mask = GENMASK(10, 6),
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.llops = &aspeed_sgpio_g4_llops,
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.cfg_offset = ASPEED_SGPIO_G4_CFG_OFFSET,
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};
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static void aspeed_sgpio_g7_reg_bit_set(struct aspeed_sgpio *gpio, unsigned int offset,
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const enum aspeed_sgpio_reg reg, bool val)
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{
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u32 mask = aspeed_sgpio_g7_reg_mask(reg);
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void __iomem *addr = gpio->base + SGPIO_G7_CTRL_REG_OFFSET(offset >> 1);
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u32 write_val;
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if (mask) {
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write_val = (ioread32(addr) & ~(mask)) | field_prep(mask, val);
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iowrite32(write_val, addr);
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}
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}
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static bool aspeed_sgpio_g7_reg_bit_get(struct aspeed_sgpio *gpio, unsigned int offset,
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const enum aspeed_sgpio_reg reg)
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{
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u32 mask = aspeed_sgpio_g7_reg_mask(reg);
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void __iomem *addr;
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addr = gpio->base + SGPIO_G7_CTRL_REG_OFFSET(offset >> 1);
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if (reg == reg_val)
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mask = SGPIO_G7_IN_DATA;
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if (mask)
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return field_get(mask, ioread32(addr));
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else
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return 0;
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}
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static int aspeed_sgpio_g7_reg_bank_get(struct aspeed_sgpio *gpio, unsigned int offset,
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const enum aspeed_sgpio_reg reg)
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{
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void __iomem *addr;
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if (reg == reg_irq_status) {
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addr = gpio->base + SGPIO_G7_IRQ_STS_OFFSET(offset >> 6);
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return ioread32(addr);
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} else {
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return -EOPNOTSUPP;
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}
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}
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static const struct aspeed_sgpio_llops aspeed_sgpio_g7_llops = {
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.reg_bit_set = aspeed_sgpio_g7_reg_bit_set,
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.reg_bit_get = aspeed_sgpio_g7_reg_bit_get,
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.reg_bank_get = aspeed_sgpio_g7_reg_bank_get,
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};
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static const struct aspeed_sgpio_pdata ast2700_sgpiom_pdata = {
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.pin_mask = GENMASK(11, 6),
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.llops = &aspeed_sgpio_g7_llops,
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.cfg_offset = ASPEED_SGPIO_G7_CFG_OFFSET,
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};
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static const struct of_device_id aspeed_sgpio_of_table[] = {
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{ .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, },
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{ .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, },
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{ .compatible = "aspeed,ast2600-sgpiom", .data = &ast2600_sgpiom_pdata, },
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{ .compatible = "aspeed,ast2700-sgpiom", .data = &ast2700_sgpiom_pdata, },
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{}
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};
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···
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gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask;
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iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval |
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ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL);
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ASPEED_SGPIO_ENABLE, gpio->base + gpio->pdata->cfg_offset);
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raw_spin_lock_init(&gpio->lock);
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