Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'riscv-for-linus-6.5-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Palmer Dabbelt:
- fix a formatting error in the hwprobe documentation
- fix a spurious warning in the RISC-V PMU driver
- fix memory detection on rv32 (problem does not manifest on any known
system)
- avoid parsing legacy parsing of I in ACPI ISA strings
* tag 'riscv-for-linus-6.5-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
RISC-V: Don't include Zicsr or Zifencei in I from ACPI
riscv: mm: fix truncation warning on RV32
perf: RISC-V: Remove PERF_HES_STOPPED flag checking in riscv_pmu_start()
Documentation: RISC-V: hwprobe: Fix a formatting error
+4
-12
+1
-1
Documentation/riscv/hwprobe.rst
+1
-1
Documentation/riscv/hwprobe.rst
···
49
49
privileged ISA, with the following known exceptions (more exceptions may be
50
50
added, but only if it can be demonstrated that the user ABI is not broken):
51
51
52
-
* The :fence.i: instruction cannot be directly executed by userspace
52
+
* The ``fence.i`` instruction cannot be directly executed by userspace
53
53
programs (it may still be executed in userspace via a
54
54
kernel-controlled mechanism such as the vDSO).
55
55
+2
-7
arch/riscv/kernel/cpufeature.c
+2
-7
arch/riscv/kernel/cpufeature.c
···
318
318
}
319
319
320
320
/*
321
-
* Linux requires the following extensions, so we may as well
322
-
* always set them.
323
-
*/
324
-
set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
325
-
set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
326
-
327
-
/*
328
321
* These ones were as they were part of the base ISA when the
329
322
* port & dt-bindings were upstreamed, and so can be set
330
323
* unconditionally where `i` is in riscv,isa on DT systems.
331
324
*/
332
325
if (acpi_disabled) {
326
+
set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
327
+
set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
333
328
set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa);
334
329
set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa);
335
330
}
+1
-1
arch/riscv/mm/init.c
+1
-1
arch/riscv/mm/init.c
···
1346
1346
*/
1347
1347
crash_base = memblock_phys_alloc_range(crash_size, PMD_SIZE,
1348
1348
search_start,
1349
-
min(search_end, (unsigned long) SZ_4G));
1349
+
min(search_end, (unsigned long)(SZ_4G - 1)));
1350
1350
if (crash_base == 0) {
1351
1351
/* Try again without restricting region to 32bit addressible memory */
1352
1352
crash_base = memblock_phys_alloc_range(crash_size, PMD_SIZE,
-3
drivers/perf/riscv_pmu.c
-3
drivers/perf/riscv_pmu.c