tjh.dev / kernel
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drm/amdgpu: convert gfx.kiq to array type (v3)

v1: more kiq instances are a available in SOC (Le)
v2: squash commits to avoid breaking the build (Le)
v3: make the conversion for gfx/mec v11_0 (Hawking)

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Le Ma and committed by
Alex Deucher 277bd337 20c3dffd

+122 -122
+3 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
··· 288 288 uint32_t pipe_id, uint32_t queue_id, 289 289 uint32_t doorbell_off) 290 290 { 291 - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 291 + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 292 292 struct v10_compute_mqd *m; 293 293 uint32_t mec, pipe; 294 294 int r; ··· 303 303 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 304 304 mec, pipe, queue_id); 305 305 306 - spin_lock(&adev->gfx.kiq.ring_lock); 306 + spin_lock(&adev->gfx.kiq[0].ring_lock); 307 307 r = amdgpu_ring_alloc(kiq_ring, 7); 308 308 if (r) { 309 309 pr_err("Failed to alloc KIQ (%d).\n", r); ··· 330 330 amdgpu_ring_commit(kiq_ring); 331 331 332 332 out_unlock: 333 - spin_unlock(&adev->gfx.kiq.ring_lock); 333 + spin_unlock(&adev->gfx.kiq[0].ring_lock); 334 334 release_queue(adev); 335 335 336 336 return r;
+3 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
··· 275 275 uint32_t pipe_id, uint32_t queue_id, 276 276 uint32_t doorbell_off) 277 277 { 278 - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 278 + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 279 279 struct v10_compute_mqd *m; 280 280 uint32_t mec, pipe; 281 281 int r; ··· 290 290 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 291 291 mec, pipe, queue_id); 292 292 293 - spin_lock(&adev->gfx.kiq.ring_lock); 293 + spin_lock(&adev->gfx.kiq[0].ring_lock); 294 294 r = amdgpu_ring_alloc(kiq_ring, 7); 295 295 if (r) { 296 296 pr_err("Failed to alloc KIQ (%d).\n", r); ··· 317 317 amdgpu_ring_commit(kiq_ring); 318 318 319 319 out_unlock: 320 - spin_unlock(&adev->gfx.kiq.ring_lock); 320 + spin_unlock(&adev->gfx.kiq[0].ring_lock); 321 321 release_queue(adev); 322 322 323 323 return r;
+3 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
··· 260 260 uint32_t pipe_id, uint32_t queue_id, 261 261 uint32_t doorbell_off) 262 262 { 263 - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 263 + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 264 264 struct v11_compute_mqd *m; 265 265 uint32_t mec, pipe; 266 266 int r; ··· 275 275 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 276 276 mec, pipe, queue_id); 277 277 278 - spin_lock(&adev->gfx.kiq.ring_lock); 278 + spin_lock(&adev->gfx.kiq[0].ring_lock); 279 279 r = amdgpu_ring_alloc(kiq_ring, 7); 280 280 if (r) { 281 281 pr_err("Failed to alloc KIQ (%d).\n", r); ··· 302 302 amdgpu_ring_commit(kiq_ring); 303 303 304 304 out_unlock: 305 - spin_unlock(&adev->gfx.kiq.ring_lock); 305 + spin_unlock(&adev->gfx.kiq[0].ring_lock); 306 306 release_queue(adev); 307 307 308 308 return r;
+3 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
··· 300 300 uint32_t pipe_id, uint32_t queue_id, 301 301 uint32_t doorbell_off) 302 302 { 303 - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 303 + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 304 304 struct v9_mqd *m; 305 305 uint32_t mec, pipe; 306 306 int r; ··· 315 315 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 316 316 mec, pipe, queue_id); 317 317 318 - spin_lock(&adev->gfx.kiq.ring_lock); 318 + spin_lock(&adev->gfx.kiq[0].ring_lock); 319 319 r = amdgpu_ring_alloc(kiq_ring, 7); 320 320 if (r) { 321 321 pr_err("Failed to alloc KIQ (%d).\n", r); ··· 342 342 amdgpu_ring_commit(kiq_ring); 343 343 344 344 out_unlock: 345 - spin_unlock(&adev->gfx.kiq.ring_lock); 345 + spin_unlock(&adev->gfx.kiq[0].ring_lock); 346 346 release_queue(adev); 347 347 348 348 return r;
+17 -17
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
··· 296 296 struct amdgpu_ring *ring, 297 297 struct amdgpu_irq_src *irq) 298 298 { 299 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 299 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 300 300 int r = 0; 301 301 302 302 spin_lock_init(&kiq->ring_lock); ··· 329 329 330 330 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev) 331 331 { 332 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 332 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 333 333 334 334 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL); 335 335 } ··· 339 339 { 340 340 int r; 341 341 u32 *hpd; 342 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 342 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 343 343 344 344 r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE, 345 345 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, ··· 368 368 int r, i; 369 369 370 370 /* create MQD for KIQ */ 371 - ring = &adev->gfx.kiq.ring; 371 + ring = &adev->gfx.kiq[0].ring; 372 372 if (!adev->enable_mes_kiq && !ring->mqd_obj) { 373 373 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must 374 374 * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD ··· 458 458 &ring->mqd_ptr); 459 459 } 460 460 461 - ring = &adev->gfx.kiq.ring; 461 + ring = &adev->gfx.kiq[0].ring; 462 462 kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]); 463 463 amdgpu_bo_free_kernel(&ring->mqd_obj, 464 464 &ring->mqd_gpu_addr, ··· 467 467 468 468 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev) 469 469 { 470 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 470 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 471 471 struct amdgpu_ring *kiq_ring = &kiq->ring; 472 472 int i, r = 0; 473 473 474 474 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 475 475 return -EINVAL; 476 476 477 - spin_lock(&adev->gfx.kiq.ring_lock); 477 + spin_lock(&adev->gfx.kiq[0].ring_lock); 478 478 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 479 479 adev->gfx.num_compute_rings)) { 480 - spin_unlock(&adev->gfx.kiq.ring_lock); 480 + spin_unlock(&adev->gfx.kiq[0].ring_lock); 481 481 return -ENOMEM; 482 482 } 483 483 ··· 485 485 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i], 486 486 RESET_QUEUES, 0, 0); 487 487 488 - if (adev->gfx.kiq.ring.sched.ready && !adev->job_hang) 488 + if (adev->gfx.kiq[0].ring.sched.ready && !adev->job_hang) 489 489 r = amdgpu_ring_test_helper(kiq_ring); 490 - spin_unlock(&adev->gfx.kiq.ring_lock); 490 + spin_unlock(&adev->gfx.kiq[0].ring_lock); 491 491 492 492 return r; 493 493 } ··· 507 507 508 508 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev) 509 509 { 510 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 511 - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 510 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 511 + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 512 512 uint64_t queue_mask = 0; 513 513 int r, i; 514 514 ··· 532 532 533 533 DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe, 534 534 kiq_ring->queue); 535 - spin_lock(&adev->gfx.kiq.ring_lock); 535 + spin_lock(&adev->gfx.kiq[0].ring_lock); 536 536 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 537 537 adev->gfx.num_compute_rings + 538 538 kiq->pmf->set_resources_size); 539 539 if (r) { 540 540 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 541 - spin_unlock(&adev->gfx.kiq.ring_lock); 541 + spin_unlock(&adev->gfx.kiq[0].ring_lock); 542 542 return r; 543 543 } 544 544 ··· 550 550 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.compute_ring[i]); 551 551 552 552 r = amdgpu_ring_test_helper(kiq_ring); 553 - spin_unlock(&adev->gfx.kiq.ring_lock); 553 + spin_unlock(&adev->gfx.kiq[0].ring_lock); 554 554 if (r) 555 555 DRM_ERROR("KCQ enable failed\n"); 556 556 ··· 788 788 signed long r, cnt = 0; 789 789 unsigned long flags; 790 790 uint32_t seq, reg_val_offs = 0, value = 0; 791 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 791 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 792 792 struct amdgpu_ring *ring = &kiq->ring; 793 793 794 794 if (amdgpu_device_skip_hw_access(adev)) ··· 856 856 signed long r, cnt = 0; 857 857 unsigned long flags; 858 858 uint32_t seq; 859 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 859 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 860 860 struct amdgpu_ring *ring = &kiq->ring; 861 861 862 862 BUG_ON(!ring->funcs->emit_wreg);
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
··· 296 296 struct amdgpu_ce ce; 297 297 struct amdgpu_me me; 298 298 struct amdgpu_mec mec; 299 - struct amdgpu_kiq kiq; 299 + struct amdgpu_kiq kiq[AMDGPU_MAX_GC_INSTANCES]; 300 300 struct amdgpu_imu imu; 301 301 bool rs64_enable; /* firmware format */ 302 302 const struct firmware *me_fw; /* ME firmware */
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
··· 74 74 uint32_t reg0, uint32_t reg1, 75 75 uint32_t ref, uint32_t mask) 76 76 { 77 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 77 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 78 78 struct amdgpu_ring *ring = &kiq->ring; 79 79 signed long r, cnt = 0; 80 80 unsigned long flags;
+16 -16
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
··· 3568 3568 struct amdgpu_device *adev = kiq_ring->adev; 3569 3569 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3570 3570 3571 - if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) { 3571 + if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 3572 3572 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 3573 3573 return; 3574 3574 } ··· 3636 3636 3637 3637 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3638 3638 { 3639 - adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 3639 + adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; 3640 3640 } 3641 3641 3642 3642 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) ··· 4550 4550 /* KIQ event */ 4551 4551 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4552 4552 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4553 - &adev->gfx.kiq.irq); 4553 + &adev->gfx.kiq[0].irq); 4554 4554 if (r) 4555 4555 return r; 4556 4556 ··· 4635 4635 return r; 4636 4636 } 4637 4637 4638 - kiq = &adev->gfx.kiq; 4638 + kiq = &adev->gfx.kiq[0]; 4639 4639 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 4640 4640 if (r) 4641 4641 return r; ··· 4693 4693 amdgpu_gfx_mqd_sw_fini(adev); 4694 4694 4695 4695 if (!adev->enable_mes_kiq) { 4696 - amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 4696 + amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 4697 4697 amdgpu_gfx_kiq_fini(adev); 4698 4698 } 4699 4699 ··· 6214 6214 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6215 6215 break; 6216 6216 } 6217 - adev->gfx.kiq.ring.sched.ready = false; 6217 + adev->gfx.kiq[0].ring.sched.ready = false; 6218 6218 } 6219 6219 udelay(50); 6220 6220 } ··· 6524 6524 #ifndef BRING_UP_DEBUG 6525 6525 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 6526 6526 { 6527 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 6528 - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 6527 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 6528 + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 6529 6529 int r, i; 6530 6530 6531 6531 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) ··· 6885 6885 struct amdgpu_ring *ring; 6886 6886 int r; 6887 6887 6888 - ring = &adev->gfx.kiq.ring; 6888 + ring = &adev->gfx.kiq[0].ring; 6889 6889 6890 6890 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6891 6891 if (unlikely(r != 0)) ··· 7243 7243 #ifndef BRING_UP_DEBUG 7244 7244 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 7245 7245 { 7246 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 7246 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 7247 7247 struct amdgpu_ring *kiq_ring = &kiq->ring; 7248 7248 int i; 7249 7249 ··· 8640 8640 { 8641 8641 int i, r = 0; 8642 8642 struct amdgpu_device *adev = ring->adev; 8643 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 8643 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 8644 8644 struct amdgpu_ring *kiq_ring = &kiq->ring; 8645 8645 unsigned long flags; 8646 8646 ··· 9148 9148 enum amdgpu_interrupt_state state) 9149 9149 { 9150 9150 uint32_t tmp, target; 9151 - struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 9151 + struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9152 9152 9153 9153 if (ring->me == 1) 9154 9154 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); ··· 9192 9192 struct amdgpu_iv_entry *entry) 9193 9193 { 9194 9194 u8 me_id, pipe_id, queue_id; 9195 - struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 9195 + struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9196 9196 9197 9197 me_id = (entry->ring_id & 0x0c) >> 2; 9198 9198 pipe_id = (entry->ring_id & 0x03) >> 0; ··· 9369 9369 { 9370 9370 int i; 9371 9371 9372 - adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9372 + adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9373 9373 9374 9374 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9375 9375 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; ··· 9403 9403 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9404 9404 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9405 9405 9406 - adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9407 - adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9406 + adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9407 + adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9408 9408 9409 9409 adev->gfx.priv_reg_irq.num_types = 1; 9410 9410 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
+13 -13
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
··· 192 192 struct amdgpu_device *adev = kiq_ring->adev; 193 193 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 194 194 195 - if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) { 195 + if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 196 196 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 197 197 return; 198 198 } ··· 260 260 261 261 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 262 262 { 263 - adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs; 263 + adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; 264 264 } 265 265 266 266 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) ··· 1395 1395 return r; 1396 1396 } 1397 1397 1398 - kiq = &adev->gfx.kiq; 1398 + kiq = &adev->gfx.kiq[0]; 1399 1399 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1400 1400 if (r) 1401 1401 return r; ··· 1466 1466 amdgpu_gfx_mqd_sw_fini(adev); 1467 1467 1468 1468 if (!adev->enable_mes_kiq) { 1469 - amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 1469 + amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1470 1470 amdgpu_gfx_kiq_fini(adev); 1471 1471 } 1472 1472 ··· 3337 3337 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3338 3338 } 3339 3339 3340 - adev->gfx.kiq.ring.sched.ready = enable; 3340 + adev->gfx.kiq[0].ring.sched.ready = enable; 3341 3341 3342 3342 udelay(50); 3343 3343 } ··· 3732 3732 #ifndef BRING_UP_DEBUG 3733 3733 static int gfx_v11_0_kiq_enable_kgq(struct amdgpu_device *adev) 3734 3734 { 3735 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3736 - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3735 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 3736 + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 3737 3737 int r, i; 3738 3738 3739 3739 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) ··· 4108 4108 struct amdgpu_ring *ring; 4109 4109 int r; 4110 4110 4111 - ring = &adev->gfx.kiq.ring; 4111 + ring = &adev->gfx.kiq[0].ring; 4112 4112 4113 4113 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4114 4114 if (unlikely(r != 0)) ··· 4417 4417 #ifndef BRING_UP_DEBUG 4418 4418 static int gfx_v11_0_kiq_disable_kgq(struct amdgpu_device *adev) 4419 4419 { 4420 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4420 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4421 4421 struct amdgpu_ring *kiq_ring = &kiq->ring; 4422 4422 int i, r = 0; 4423 4423 ··· 4432 4432 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 4433 4433 PREEMPT_QUEUES, 0, 0); 4434 4434 4435 - if (adev->gfx.kiq.ring.sched.ready) 4435 + if (adev->gfx.kiq[0].ring.sched.ready) 4436 4436 r = amdgpu_ring_test_helper(kiq_ring); 4437 4437 4438 4438 return r; ··· 5622 5622 { 5623 5623 int i, r = 0; 5624 5624 struct amdgpu_device *adev = ring->adev; 5625 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 5625 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 5626 5626 struct amdgpu_ring *kiq_ring = &kiq->ring; 5627 5627 unsigned long flags; 5628 5628 ··· 6120 6120 enum amdgpu_interrupt_state state) 6121 6121 { 6122 6122 uint32_t tmp, target; 6123 - struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 6123 + struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 6124 6124 6125 6125 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6126 6126 target += ring->pipe; ··· 6317 6317 { 6318 6318 int i; 6319 6319 6320 - adev->gfx.kiq.ring.funcs = &gfx_v11_0_ring_funcs_kiq; 6320 + adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; 6321 6321 6322 6322 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6323 6323 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx;
+8 -8
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
··· 2021 2021 return r; 2022 2022 } 2023 2023 2024 - kiq = &adev->gfx.kiq; 2024 + kiq = &adev->gfx.kiq[0]; 2025 2025 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 2026 2026 if (r) 2027 2027 return r; ··· 2051 2051 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 2052 2052 2053 2053 amdgpu_gfx_mqd_sw_fini(adev); 2054 - amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 2054 + amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 2055 2055 amdgpu_gfx_kiq_fini(adev); 2056 2056 2057 2057 gfx_v8_0_mec_fini(adev); ··· 4292 4292 WREG32(mmCP_MEC_CNTL, 0); 4293 4293 } else { 4294 4294 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 4295 - adev->gfx.kiq.ring.sched.ready = false; 4295 + adev->gfx.kiq[0].ring.sched.ready = false; 4296 4296 } 4297 4297 udelay(50); 4298 4298 } ··· 4314 4314 4315 4315 static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev) 4316 4316 { 4317 - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 4317 + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 4318 4318 uint64_t queue_mask = 0; 4319 4319 int r, i; 4320 4320 ··· 4678 4678 struct amdgpu_ring *ring; 4679 4679 int r; 4680 4680 4681 - ring = &adev->gfx.kiq.ring; 4681 + ring = &adev->gfx.kiq[0].ring; 4682 4682 4683 4683 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4684 4684 if (unlikely(r != 0)) ··· 4741 4741 if (r) 4742 4742 return r; 4743 4743 4744 - ring = &adev->gfx.kiq.ring; 4744 + ring = &adev->gfx.kiq[0].ring; 4745 4745 r = amdgpu_ring_test_helper(ring); 4746 4746 if (r) 4747 4747 return r; ··· 4808 4808 static int gfx_v8_0_kcq_disable(struct amdgpu_device *adev) 4809 4809 { 4810 4810 int r, i; 4811 - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 4811 + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 4812 4812 4813 4813 r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings); 4814 4814 if (r) ··· 7001 7001 { 7002 7002 int i; 7003 7003 7004 - adev->gfx.kiq.ring.funcs = &gfx_v8_0_ring_funcs_kiq; 7004 + adev->gfx.kiq[0].ring.funcs = &gfx_v8_0_ring_funcs_kiq; 7005 7005 7006 7006 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7007 7007 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
+12 -12
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 898 898 899 899 static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 900 900 { 901 - adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; 901 + adev->gfx.kiq[0].pmf = &gfx_v9_0_kiq_pm4_funcs; 902 902 } 903 903 904 904 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) ··· 2174 2174 return r; 2175 2175 } 2176 2176 2177 - kiq = &adev->gfx.kiq; 2177 + kiq = &adev->gfx.kiq[0]; 2178 2178 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 2179 2179 if (r) 2180 2180 return r; ··· 2216 2216 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 2217 2217 2218 2218 amdgpu_gfx_mqd_sw_fini(adev); 2219 - amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 2219 + amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 2220 2220 amdgpu_gfx_kiq_fini(adev); 2221 2221 2222 2222 gfx_v9_0_mec_fini(adev); ··· 3155 3155 } else { 3156 3156 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 3157 3157 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 3158 - adev->gfx.kiq.ring.sched.ready = false; 3158 + adev->gfx.kiq[0].ring.sched.ready = false; 3159 3159 } 3160 3160 udelay(50); 3161 3161 } ··· 3610 3610 struct amdgpu_ring *ring; 3611 3611 int r; 3612 3612 3613 - ring = &adev->gfx.kiq.ring; 3613 + ring = &adev->gfx.kiq[0].ring; 3614 3614 3615 3615 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3616 3616 if (unlikely(r != 0)) ··· 3789 3789 */ 3790 3790 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3791 3791 mutex_lock(&adev->srbm_mutex); 3792 - soc15_grbm_select(adev, adev->gfx.kiq.ring.me, 3793 - adev->gfx.kiq.ring.pipe, 3794 - adev->gfx.kiq.ring.queue, 0); 3795 - gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring); 3792 + soc15_grbm_select(adev, adev->gfx.kiq[0].ring.me, 3793 + adev->gfx.kiq[0].ring.pipe, 3794 + adev->gfx.kiq[0].ring.queue, 0); 3795 + gfx_v9_0_kiq_fini_register(&adev->gfx.kiq[0].ring); 3796 3796 soc15_grbm_select(adev, 0, 0, 0, 0); 3797 3797 mutex_unlock(&adev->srbm_mutex); 3798 3798 } ··· 3913 3913 unsigned long flags; 3914 3914 uint32_t seq, reg_val_offs = 0; 3915 3915 uint64_t value = 0; 3916 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3916 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 3917 3917 struct amdgpu_ring *ring = &kiq->ring; 3918 3918 3919 3919 BUG_ON(!ring->funcs->emit_rreg); ··· 5385 5385 { 5386 5386 int i, r = 0; 5387 5387 struct amdgpu_device *adev = ring->adev; 5388 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 5388 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 5389 5389 struct amdgpu_ring *kiq_ring = &kiq->ring; 5390 5390 unsigned long flags; 5391 5391 ··· 6964 6964 { 6965 6965 int i; 6966 6966 6967 - adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; 6967 + adev->gfx.kiq[0].ring.funcs = &gfx_v9_0_ring_funcs_kiq; 6968 6968 6969 6969 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6970 6970 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
+6 -6
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
··· 343 343 /* For SRIOV run time, driver shouldn't access the register through MMIO 344 344 * Directly use kiq to do the vm invalidation instead 345 345 */ 346 - if (adev->gfx.kiq.ring.sched.ready && !adev->enable_mes && 346 + if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes && 347 347 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 348 348 down_read_trylock(&adev->reset_domain->sem)) { 349 349 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; ··· 428 428 uint16_t queried_pasid; 429 429 bool ret; 430 430 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout; 431 - struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 432 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 431 + struct amdgpu_ring *ring = &adev->gfx.kiq[0].ring; 432 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 433 433 434 434 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 435 - spin_lock(&adev->gfx.kiq.ring_lock); 435 + spin_lock(&adev->gfx.kiq[0].ring_lock); 436 436 /* 2 dwords flush + 8 dwords fence */ 437 437 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 438 438 kiq->pmf->kiq_invalidate_tlbs(ring, ··· 440 440 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 441 441 if (r) { 442 442 amdgpu_ring_undo(ring); 443 - spin_unlock(&adev->gfx.kiq.ring_lock); 443 + spin_unlock(&adev->gfx.kiq[0].ring_lock); 444 444 return -ETIME; 445 445 } 446 446 447 447 amdgpu_ring_commit(ring); 448 - spin_unlock(&adev->gfx.kiq.ring_lock); 448 + spin_unlock(&adev->gfx.kiq[0].ring_lock); 449 449 r = amdgpu_fence_wait_polling(ring, seq, usec_timeout); 450 450 if (r < 1) { 451 451 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
+6 -6
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
··· 291 291 /* For SRIOV run time, driver shouldn't access the register through MMIO 292 292 * Directly use kiq to do the vm invalidation instead 293 293 */ 294 - if ((adev->gfx.kiq.ring.sched.ready || adev->mes.ring.sched.ready) && 294 + if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) && 295 295 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 296 296 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 297 297 const unsigned eng = 17; ··· 329 329 uint32_t seq; 330 330 uint16_t queried_pasid; 331 331 bool ret; 332 - struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 333 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 332 + struct amdgpu_ring *ring = &adev->gfx.kiq[0].ring; 333 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 334 334 335 335 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 336 - spin_lock(&adev->gfx.kiq.ring_lock); 336 + spin_lock(&adev->gfx.kiq[0].ring_lock); 337 337 /* 2 dwords flush + 8 dwords fence */ 338 338 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 339 339 kiq->pmf->kiq_invalidate_tlbs(ring, ··· 341 341 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 342 342 if (r) { 343 343 amdgpu_ring_undo(ring); 344 - spin_unlock(&adev->gfx.kiq.ring_lock); 344 + spin_unlock(&adev->gfx.kiq[0].ring_lock); 345 345 return -ETIME; 346 346 } 347 347 348 348 amdgpu_ring_commit(ring); 349 - spin_unlock(&adev->gfx.kiq.ring_lock); 349 + spin_unlock(&adev->gfx.kiq[0].ring_lock); 350 350 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 351 351 if (r < 1) { 352 352 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
+6 -6
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
··· 824 824 /* This is necessary for a HW workaround under SRIOV as well 825 825 * as GFXOFF under bare metal 826 826 */ 827 - if (adev->gfx.kiq.ring.sched.ready && 827 + if (adev->gfx.kiq[0].ring.sched.ready && 828 828 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 829 829 down_read_trylock(&adev->reset_domain->sem)) { 830 830 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; ··· 934 934 uint16_t queried_pasid; 935 935 bool ret; 936 936 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout; 937 - struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 938 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 937 + struct amdgpu_ring *ring = &adev->gfx.kiq[0].ring; 938 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 939 939 940 940 if (amdgpu_in_reset(adev)) 941 941 return -EIO; ··· 955 955 if (vega20_xgmi_wa) 956 956 ndw += kiq->pmf->invalidate_tlbs_size; 957 957 958 - spin_lock(&adev->gfx.kiq.ring_lock); 958 + spin_lock(&adev->gfx.kiq[0].ring_lock); 959 959 /* 2 dwords flush + 8 dwords fence */ 960 960 amdgpu_ring_alloc(ring, ndw); 961 961 if (vega20_xgmi_wa) ··· 966 966 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 967 967 if (r) { 968 968 amdgpu_ring_undo(ring); 969 - spin_unlock(&adev->gfx.kiq.ring_lock); 969 + spin_unlock(&adev->gfx.kiq[0].ring_lock); 970 970 up_read(&adev->reset_domain->sem); 971 971 return -ETIME; 972 972 } 973 973 974 974 amdgpu_ring_commit(ring); 975 - spin_unlock(&adev->gfx.kiq.ring_lock); 975 + spin_unlock(&adev->gfx.kiq[0].ring_lock); 976 976 r = amdgpu_fence_wait_polling(ring, seq, usec_timeout); 977 977 if (r < 1) { 978 978 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
+11 -11
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
··· 797 797 798 798 static int mes_v10_1_kiq_enable_queue(struct amdgpu_device *adev) 799 799 { 800 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 801 - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 800 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 801 + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 802 802 int r; 803 803 804 804 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) ··· 863 863 { 864 864 struct amdgpu_ring *ring; 865 865 866 - spin_lock_init(&adev->gfx.kiq.ring_lock); 866 + spin_lock_init(&adev->gfx.kiq[0].ring_lock); 867 867 868 - ring = &adev->gfx.kiq.ring; 868 + ring = &adev->gfx.kiq[0].ring; 869 869 870 870 ring->me = 3; 871 871 ring->pipe = 1; ··· 891 891 struct amdgpu_ring *ring; 892 892 893 893 if (pipe == AMDGPU_MES_KIQ_PIPE) 894 - ring = &adev->gfx.kiq.ring; 894 + ring = &adev->gfx.kiq[0].ring; 895 895 else if (pipe == AMDGPU_MES_SCHED_PIPE) 896 896 ring = &adev->mes.ring; 897 897 else ··· 974 974 amdgpu_ucode_release(&adev->mes.fw[pipe]); 975 975 } 976 976 977 - amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, 978 - &adev->gfx.kiq.ring.mqd_gpu_addr, 979 - &adev->gfx.kiq.ring.mqd_ptr); 977 + amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 978 + &adev->gfx.kiq[0].ring.mqd_gpu_addr, 979 + &adev->gfx.kiq[0].ring.mqd_ptr); 980 980 981 981 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 982 982 &adev->mes.ring.mqd_gpu_addr, 983 983 &adev->mes.ring.mqd_ptr); 984 984 985 - amdgpu_ring_fini(&adev->gfx.kiq.ring); 985 + amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 986 986 amdgpu_ring_fini(&adev->mes.ring); 987 987 988 988 amdgpu_mes_fini(adev); ··· 1038 1038 1039 1039 mes_v10_1_enable(adev, true); 1040 1040 1041 - mes_v10_1_kiq_setting(&adev->gfx.kiq.ring); 1041 + mes_v10_1_kiq_setting(&adev->gfx.kiq[0].ring); 1042 1042 1043 1043 r = mes_v10_1_queue_init(adev); 1044 1044 if (r) ··· 1090 1090 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1091 1091 * with MES enabled. 1092 1092 */ 1093 - adev->gfx.kiq.ring.sched.ready = false; 1093 + adev->gfx.kiq[0].ring.sched.ready = false; 1094 1094 adev->mes.ring.sched.ready = true; 1095 1095 1096 1096 return 0;
+13 -13
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
··· 864 864 865 865 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 866 866 { 867 - struct amdgpu_kiq *kiq = &adev->gfx.kiq; 868 - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 867 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 868 + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 869 869 int r; 870 870 871 871 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) ··· 894 894 int r; 895 895 896 896 if (pipe == AMDGPU_MES_KIQ_PIPE) 897 - ring = &adev->gfx.kiq.ring; 897 + ring = &adev->gfx.kiq[0].ring; 898 898 else if (pipe == AMDGPU_MES_SCHED_PIPE) 899 899 ring = &adev->mes.ring; 900 900 else ··· 961 961 { 962 962 struct amdgpu_ring *ring; 963 963 964 - spin_lock_init(&adev->gfx.kiq.ring_lock); 964 + spin_lock_init(&adev->gfx.kiq[0].ring_lock); 965 965 966 - ring = &adev->gfx.kiq.ring; 966 + ring = &adev->gfx.kiq[0].ring; 967 967 968 968 ring->me = 3; 969 969 ring->pipe = 1; ··· 989 989 struct amdgpu_ring *ring; 990 990 991 991 if (pipe == AMDGPU_MES_KIQ_PIPE) 992 - ring = &adev->gfx.kiq.ring; 992 + ring = &adev->gfx.kiq[0].ring; 993 993 else if (pipe == AMDGPU_MES_SCHED_PIPE) 994 994 ring = &adev->mes.ring; 995 995 else ··· 1074 1074 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1075 1075 } 1076 1076 1077 - amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, 1078 - &adev->gfx.kiq.ring.mqd_gpu_addr, 1079 - &adev->gfx.kiq.ring.mqd_ptr); 1077 + amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1078 + &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1079 + &adev->gfx.kiq[0].ring.mqd_ptr); 1080 1080 1081 1081 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1082 1082 &adev->mes.ring.mqd_gpu_addr, 1083 1083 &adev->mes.ring.mqd_ptr); 1084 1084 1085 - amdgpu_ring_fini(&adev->gfx.kiq.ring); 1085 + amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1086 1086 amdgpu_ring_fini(&adev->mes.ring); 1087 1087 1088 1088 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { ··· 1175 1175 1176 1176 mes_v11_0_enable(adev, true); 1177 1177 1178 - mes_v11_0_kiq_setting(&adev->gfx.kiq.ring); 1178 + mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1179 1179 1180 1180 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1181 1181 if (r) ··· 1196 1196 } 1197 1197 1198 1198 if (amdgpu_sriov_vf(adev)) { 1199 - mes_v11_0_kiq_dequeue(&adev->gfx.kiq.ring); 1199 + mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1200 1200 mes_v11_0_kiq_clear(adev); 1201 1201 } 1202 1202 ··· 1244 1244 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1245 1245 * with MES enabled. 1246 1246 */ 1247 - adev->gfx.kiq.ring.sched.ready = false; 1247 + adev->gfx.kiq[0].ring.sched.ready = false; 1248 1248 adev->mes.ring.sched.ready = true; 1249 1249 1250 1250 return 0;