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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge branch 'add-gmac-support-for-renesas-rz-t2h-n2h-socs'
Lad Prabhakar says:
====================
Add GMAC support for Renesas RZ/{T2H, N2H} SoCs
This series adds support for the Ethernet MAC (GMAC) IP present on
the Renesas RZ/T2H and RZ/N2H SoCs.
While these SoCs use the same Synopsys DesignWare MAC IP (version 5.20) as
the existing RZ/V2H(P), the hardware is synthesized with different options
that require driver and binding updates:
- 8 RX/TX queue pairs instead of 4 (requiring 19 interrupts vs 11)
- Different clock requirements (3 clocks vs 7)
- Different reset handling (2 named resets vs 1 unnamed)
- Split header feature enabled
- GMAC connected through a MIIC PCS on RZ/T2H
The series first updates the generic dwmac binding to accommodate the
higher interrupt count, then extends the Renesas-specific binding with
a to document both SoCs.
The driver changes prepare for multi-SoC support by introducing OF match
data for per-SoC configuration, then add RZ/T2H support including PCS
integration through the existing RZN1 MIIC driver.
Note this patch series is dependent on the PCS driver [0]
(not a build dependency).
[0] https://lore.kernel.org/all/20250904114204.4148520-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
====================
Link: https://patch.msgid.link/20250908105901.3198975-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+248
-59
+138
-40
Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml
+138
-40
Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml
···
17
17
- renesas,r9a09g047-gbeth
18
18
- renesas,r9a09g056-gbeth
19
19
- renesas,r9a09g057-gbeth
20
+
- renesas,r9a09g077-gbeth
21
+
- renesas,r9a09g087-gbeth
20
22
- renesas,rzv2h-gbeth
21
23
required:
22
24
- compatible
23
25
24
26
properties:
25
27
compatible:
26
-
items:
27
-
- enum:
28
-
- renesas,r9a09g047-gbeth # RZ/G3E
29
-
- renesas,r9a09g056-gbeth # RZ/V2N
30
-
- renesas,r9a09g057-gbeth # RZ/V2H(P)
31
-
- const: renesas,rzv2h-gbeth
32
-
- const: snps,dwmac-5.20
28
+
oneOf:
29
+
- items:
30
+
- enum:
31
+
- renesas,r9a09g047-gbeth # RZ/G3E
32
+
- renesas,r9a09g056-gbeth # RZ/V2N
33
+
- renesas,r9a09g057-gbeth # RZ/V2H(P)
34
+
- const: renesas,rzv2h-gbeth
35
+
- const: snps,dwmac-5.20
36
+
- items:
37
+
- const: renesas,r9a09g077-gbeth # RZ/T2H
38
+
- const: snps,dwmac-5.20
39
+
- items:
40
+
- const: renesas,r9a09g087-gbeth # RZ/N2H
41
+
- const: renesas,r9a09g077-gbeth
42
+
- const: snps,dwmac-5.20
33
43
34
44
reg:
35
45
maxItems: 1
36
46
37
47
clocks:
38
-
items:
39
-
- description: CSR clock
40
-
- description: AXI system clock
41
-
- description: PTP clock
42
-
- description: TX clock
43
-
- description: RX clock
44
-
- description: TX clock phase-shifted by 180 degrees
45
-
- description: RX clock phase-shifted by 180 degrees
48
+
oneOf:
49
+
- items:
50
+
- description: CSR clock
51
+
- description: AXI system clock
52
+
- description: PTP clock
53
+
- description: TX clock
54
+
- description: RX clock
55
+
- description: TX clock phase-shifted by 180 degrees
56
+
- description: RX clock phase-shifted by 180 degrees
57
+
- items:
58
+
- description: CSR clock
59
+
- description: AXI system clock
60
+
- description: TX clock
46
61
47
62
clock-names:
48
-
items:
49
-
- const: stmmaceth
50
-
- const: pclk
51
-
- const: ptp_ref
52
-
- const: tx
53
-
- const: rx
54
-
- const: tx-180
55
-
- const: rx-180
56
-
57
-
interrupts:
58
-
minItems: 11
63
+
oneOf:
64
+
- items:
65
+
- const: stmmaceth
66
+
- const: pclk
67
+
- const: ptp_ref
68
+
- const: tx
69
+
- const: rx
70
+
- const: tx-180
71
+
- const: rx-180
72
+
- items:
73
+
- const: stmmaceth
74
+
- const: pclk
75
+
- const: tx
59
76
60
77
interrupt-names:
61
-
items:
62
-
- const: macirq
63
-
- const: eth_wake_irq
64
-
- const: eth_lpi
65
-
- const: rx-queue-0
66
-
- const: rx-queue-1
67
-
- const: rx-queue-2
68
-
- const: rx-queue-3
69
-
- const: tx-queue-0
70
-
- const: tx-queue-1
71
-
- const: tx-queue-2
72
-
- const: tx-queue-3
78
+
oneOf:
79
+
- items:
80
+
- const: macirq
81
+
- const: eth_wake_irq
82
+
- const: eth_lpi
83
+
- const: rx-queue-0
84
+
- const: rx-queue-1
85
+
- const: rx-queue-2
86
+
- const: rx-queue-3
87
+
- const: tx-queue-0
88
+
- const: tx-queue-1
89
+
- const: tx-queue-2
90
+
- const: tx-queue-3
91
+
- items:
92
+
- const: macirq
93
+
- const: eth_wake_irq
94
+
- const: eth_lpi
95
+
- const: rx-queue-0
96
+
- const: rx-queue-1
97
+
- const: rx-queue-2
98
+
- const: rx-queue-3
99
+
- const: rx-queue-4
100
+
- const: rx-queue-5
101
+
- const: rx-queue-6
102
+
- const: rx-queue-7
103
+
- const: tx-queue-0
104
+
- const: tx-queue-1
105
+
- const: tx-queue-2
106
+
- const: tx-queue-3
107
+
- const: tx-queue-4
108
+
- const: tx-queue-5
109
+
- const: tx-queue-6
110
+
- const: tx-queue-7
73
111
74
112
resets:
75
-
items:
76
-
- description: AXI power-on system reset
113
+
oneOf:
114
+
- items:
115
+
- description: AXI power-on system reset
116
+
- items:
117
+
- description: AXI power-on system reset
118
+
- description: AHB reset
119
+
120
+
pcs-handle:
121
+
description:
122
+
phandle pointing to a PCS sub-node compatible with
123
+
Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml#
124
+
(Refer RZ/T2H portion in the DT-binding file)
77
125
78
126
required:
79
127
- compatible
···
134
86
135
87
allOf:
136
88
- $ref: snps,dwmac.yaml#
89
+
90
+
- if:
91
+
properties:
92
+
compatible:
93
+
contains:
94
+
const: renesas,r9a09g077-gbeth
95
+
then:
96
+
properties:
97
+
clocks:
98
+
maxItems: 3
99
+
100
+
clock-names:
101
+
maxItems: 3
102
+
103
+
interrupts:
104
+
minItems: 19
105
+
106
+
interrupt-names:
107
+
minItems: 19
108
+
109
+
resets:
110
+
minItems: 2
111
+
112
+
reset-names:
113
+
minItems: 2
114
+
115
+
required:
116
+
- reset-names
117
+
else:
118
+
properties:
119
+
clocks:
120
+
minItems: 7
121
+
122
+
clock-names:
123
+
minItems: 7
124
+
125
+
interrupts:
126
+
minItems: 11
127
+
maxItems: 11
128
+
129
+
interrupt-names:
130
+
minItems: 11
131
+
maxItems: 11
132
+
133
+
resets:
134
+
maxItems: 1
135
+
136
+
pcs-handle: false
137
+
138
+
reset-names: false
137
139
138
140
unevaluatedProperties: false
139
141
+5
-4
Documentation/devicetree/bindings/net/snps,dwmac.yaml
+5
-4
Documentation/devicetree/bindings/net/snps,dwmac.yaml
···
75
75
- qcom,sc8280xp-ethqos
76
76
- qcom,sm8150-ethqos
77
77
- renesas,r9a06g032-gmac
78
+
- renesas,r9a09g077-gbeth
78
79
- renesas,rzn1-gmac
79
80
- renesas,rzv2h-gbeth
80
81
- rockchip,px30-gmac
···
119
118
120
119
interrupts:
121
120
minItems: 1
122
-
maxItems: 11
121
+
maxItems: 19
123
122
124
123
interrupt-names:
125
124
minItems: 1
126
-
maxItems: 11
125
+
maxItems: 19
127
126
items:
128
127
oneOf:
129
128
- description: Combined signal for various interrupt events
···
135
134
- description: The interrupt that occurs when HW safety error triggered
136
135
const: sfty
137
136
- description: Per channel receive completion interrupt
138
-
pattern: '^rx-queue-[0-3]$'
137
+
pattern: '^rx-queue-[0-7]$'
139
138
- description: Per channel transmit completion interrupt
140
-
pattern: '^tx-queue-[0-3]$'
139
+
pattern: '^tx-queue-[0-7]$'
141
140
142
141
clocks:
143
142
minItems: 1
+7
-5
drivers/net/ethernet/stmicro/stmmac/Kconfig
+7
-5
drivers/net/ethernet/stmicro/stmmac/Kconfig
···
133
133
stmmac device driver.
134
134
135
135
config DWMAC_RENESAS_GBETH
136
-
tristate "Renesas RZ/V2H(P) GBETH support"
136
+
tristate "Renesas RZ/V2H(P) GBETH and RZ/T2H, RZ/N2H GMAC support"
137
137
default ARCH_RENESAS
138
138
depends on OF && (ARCH_RENESAS || COMPILE_TEST)
139
+
select PCS_RZN1_MIIC
139
140
help
140
-
Support for Gigabit Ethernet Interface (GBETH) on Renesas
141
-
RZ/V2H(P) SoCs.
141
+
Support for Gigabit Ethernet Interface (GBETH)/ Ethernet MAC (GMAC)
142
+
on Renesas SoCs.
142
143
143
-
This selects the Renesas RZ/V2H(P) Soc specific glue layer support
144
-
for the stmmac device driver.
144
+
This selects Renesas SoC glue layer support for the stmmac device
145
+
driver. This driver is used for the RZ/V2H(P) family, RZ/T2H and
146
+
RZ/N2H SoCs.
145
147
146
148
config DWMAC_ROCKCHIP
147
149
tristate "Rockchip dwmac support"
+98
-10
drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c
+98
-10
drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c
···
16
16
#include <linux/clk.h>
17
17
#include <linux/device.h>
18
18
#include <linux/module.h>
19
+
#include <linux/of.h>
20
+
#include <linux/pcs-rzn1-miic.h>
19
21
#include <linux/platform_device.h>
20
22
#include <linux/reset.h>
23
+
#include <linux/types.h>
21
24
22
25
#include "stmmac_platform.h"
23
26
27
+
/**
28
+
* struct renesas_gbeth_of_data - OF data for Renesas GBETH
29
+
*
30
+
* @clks: Array of clock names
31
+
* @num_clks: Number of clocks
32
+
* @stmmac_flags: Flags for the stmmac driver
33
+
* @handle_reset: Flag to indicate if reset control is
34
+
* handled by the glue driver or core driver.
35
+
* @set_clk_tx_rate: Flag to indicate if Tx clock is fixed or
36
+
* set_clk_tx_rate is needed.
37
+
* @has_pcs: Flag to indicate if the MAC has a PCS
38
+
*/
39
+
struct renesas_gbeth_of_data {
40
+
const char * const *clks;
41
+
u8 num_clks;
42
+
u32 stmmac_flags;
43
+
bool handle_reset;
44
+
bool set_clk_tx_rate;
45
+
bool has_pcs;
46
+
};
47
+
24
48
struct renesas_gbeth {
49
+
const struct renesas_gbeth_of_data *of_data;
25
50
struct plat_stmmacenet_data *plat_dat;
26
51
struct reset_control *rstc;
27
52
struct device *dev;
···
55
30
static const char *const renesas_gbeth_clks[] = {
56
31
"tx", "tx-180", "rx", "rx-180",
57
32
};
33
+
34
+
static const char *const renesas_gmac_clks[] = {
35
+
"tx",
36
+
};
37
+
38
+
static int renesas_gmac_pcs_init(struct stmmac_priv *priv)
39
+
{
40
+
struct device_node *np = priv->device->of_node;
41
+
struct device_node *pcs_node;
42
+
struct phylink_pcs *pcs;
43
+
44
+
pcs_node = of_parse_phandle(np, "pcs-handle", 0);
45
+
if (pcs_node) {
46
+
pcs = miic_create(priv->device, pcs_node);
47
+
of_node_put(pcs_node);
48
+
if (IS_ERR(pcs))
49
+
return PTR_ERR(pcs);
50
+
51
+
priv->hw->phylink_pcs = pcs;
52
+
}
53
+
54
+
return 0;
55
+
}
56
+
57
+
static void renesas_gmac_pcs_exit(struct stmmac_priv *priv)
58
+
{
59
+
if (priv->hw->phylink_pcs)
60
+
miic_destroy(priv->hw->phylink_pcs);
61
+
}
62
+
63
+
static struct phylink_pcs *renesas_gmac_select_pcs(struct stmmac_priv *priv,
64
+
phy_interface_t interface)
65
+
{
66
+
return priv->hw->phylink_pcs;
67
+
}
58
68
59
69
static int renesas_gbeth_init(struct platform_device *pdev, void *priv)
60
70
{
···
130
70
131
71
static int renesas_gbeth_probe(struct platform_device *pdev)
132
72
{
73
+
const struct renesas_gbeth_of_data *of_data;
133
74
struct plat_stmmacenet_data *plat_dat;
134
75
struct stmmac_resources stmmac_res;
135
76
struct device *dev = &pdev->dev;
···
152
91
if (!gbeth)
153
92
return -ENOMEM;
154
93
155
-
plat_dat->num_clks = ARRAY_SIZE(renesas_gbeth_clks);
94
+
of_data = of_device_get_match_data(&pdev->dev);
95
+
gbeth->of_data = of_data;
96
+
97
+
plat_dat->num_clks = of_data->num_clks;
156
98
plat_dat->clks = devm_kcalloc(dev, plat_dat->num_clks,
157
99
sizeof(*plat_dat->clks), GFP_KERNEL);
158
100
if (!plat_dat->clks)
159
101
return -ENOMEM;
160
102
161
103
for (i = 0; i < plat_dat->num_clks; i++)
162
-
plat_dat->clks[i].id = renesas_gbeth_clks[i];
104
+
plat_dat->clks[i].id = of_data->clks[i];
163
105
164
106
err = devm_clk_bulk_get(dev, plat_dat->num_clks, plat_dat->clks);
165
107
if (err < 0)
···
173
109
return dev_err_probe(dev, -EINVAL,
174
110
"error finding tx clock\n");
175
111
176
-
gbeth->rstc = devm_reset_control_get_exclusive(dev, NULL);
177
-
if (IS_ERR(gbeth->rstc))
178
-
return PTR_ERR(gbeth->rstc);
112
+
if (of_data->handle_reset) {
113
+
gbeth->rstc = devm_reset_control_get_exclusive(dev, NULL);
114
+
if (IS_ERR(gbeth->rstc))
115
+
return PTR_ERR(gbeth->rstc);
116
+
}
179
117
180
118
gbeth->dev = dev;
181
119
gbeth->plat_dat = plat_dat;
182
120
plat_dat->bsp_priv = gbeth;
183
-
plat_dat->set_clk_tx_rate = stmmac_set_clk_tx_rate;
121
+
if (of_data->set_clk_tx_rate)
122
+
plat_dat->set_clk_tx_rate = stmmac_set_clk_tx_rate;
184
123
plat_dat->init = renesas_gbeth_init;
185
124
plat_dat->exit = renesas_gbeth_exit;
186
-
plat_dat->flags |= STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY |
187
-
STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP |
188
-
STMMAC_FLAG_SPH_DISABLE;
125
+
plat_dat->flags |= STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP |
126
+
gbeth->of_data->stmmac_flags;
127
+
if (of_data->has_pcs) {
128
+
plat_dat->pcs_init = renesas_gmac_pcs_init;
129
+
plat_dat->pcs_exit = renesas_gmac_pcs_exit;
130
+
plat_dat->select_pcs = renesas_gmac_select_pcs;
131
+
}
189
132
190
133
return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
191
134
}
192
135
136
+
static const struct renesas_gbeth_of_data renesas_gbeth_of_data = {
137
+
.clks = renesas_gbeth_clks,
138
+
.num_clks = ARRAY_SIZE(renesas_gbeth_clks),
139
+
.handle_reset = true,
140
+
.set_clk_tx_rate = true,
141
+
.stmmac_flags = STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY |
142
+
STMMAC_FLAG_SPH_DISABLE,
143
+
};
144
+
145
+
static const struct renesas_gbeth_of_data renesas_gmac_of_data = {
146
+
.clks = renesas_gmac_clks,
147
+
.num_clks = ARRAY_SIZE(renesas_gmac_clks),
148
+
.stmmac_flags = STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY,
149
+
.has_pcs = true,
150
+
};
151
+
193
152
static const struct of_device_id renesas_gbeth_match[] = {
194
-
{ .compatible = "renesas,rzv2h-gbeth", },
153
+
{ .compatible = "renesas,r9a09g077-gbeth", .data = &renesas_gmac_of_data },
154
+
{ .compatible = "renesas,rzv2h-gbeth", .data = &renesas_gbeth_of_data },
195
155
{ /* Sentinel */ }
196
156
};
197
157
MODULE_DEVICE_TABLE(of, renesas_gbeth_match);