Merge branch 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

+30

Documentation/devicetree/bindings/i2c/i2c-axxia.txt

··· 1 + LSI Axxia I2C 2 + 3 + Required properties : 4 + - compatible : Must be "lsi,api2c" 5 + - reg : Offset and length of the register set for the device 6 + - interrupts : the interrupt specifier 7 + - #address-cells : Must be <1>; 8 + - #size-cells : Must be <0>; 9 + - clock-names : Must contain "i2c". 10 + - clocks: Must contain an entry for each name in clock-names. See the common 11 + clock bindings. 12 + 13 + Optional properties : 14 + - clock-frequency : Desired I2C bus clock frequency in Hz. If not specified, 15 + the default 100 kHz frequency will be used. As only Normal and Fast modes 16 + are supported, possible values are 100000 and 400000. 17 + 18 + Example : 19 + 20 + i2c@02010084000 { 21 + compatible = "lsi,api2c"; 22 + device_type = "i2c"; 23 + #address-cells = <1>; 24 + #size-cells = <0>; 25 + reg = <0x20 0x10084000 0x00 0x1000>; 26 + interrupts = <0 19 4>; 27 + clocks = <&clk_per>; 28 + clock-names = "i2c"; 29 + clock-frequency = <400000>; 30 + };

+2

Documentation/devicetree/bindings/i2c/i2c-exynos5.txt

··· 12 12 on Exynos5250 and Exynos5420 SoCs. 13 13 -> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available 14 14 on Exynos5260 SoCs. 15 + -> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available 16 + on Exynos7 SoCs. 15 17 16 18 - reg: physical base address of the controller and length of memory mapped 17 19 region.

+24

Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt

··· 1 + I2C for Hisilicon hix5hd2 chipset platform 2 + 3 + Required properties: 4 + - compatible: Must be "hisilicon,hix5hd2-i2c" 5 + - reg: physical base address of the controller and length of memory mapped 6 + region. 7 + - interrupts: interrupt number to the cpu. 8 + - #address-cells = <1>; 9 + - #size-cells = <0>; 10 + - clocks: phandles to input clocks. 11 + 12 + Optional properties: 13 + - clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000 14 + - Child nodes conforming to i2c bus binding 15 + 16 + Examples: 17 + I2C0@f8b10000 { 18 + compatible = "hisilicon,hix5hd2-i2c"; 19 + reg = <0xf8b10000 0x1000>; 20 + interrupts = <0 38 4>; 21 + clocks = <&clock HIX5HD2_I2C0_RST>; 22 + #address-cells = <1>; 23 + #size-cells = <0>; 24 + }

+1

Documentation/i2c/busses/i2c-i801

··· 28 28 * Intel Wildcat Point (PCH) 29 29 * Intel Wildcat Point-LP (PCH) 30 30 * Intel BayTrail (SOC) 31 + * Intel Sunrise Point-H (PCH) 31 32 Datasheets: Publicly available at the Intel website 32 33 33 34 On Intel Patsburg and later chipsets, both the normal host SMBus controller

+24 -1

drivers/i2c/busses/Kconfig

··· 77 77 This driver can also be built as a module. If so, the module 78 78 will be called i2c-amd8111. 79 79 80 + config I2C_HIX5HD2 81 + tristate "Hix5hd2 high-speed I2C driver" 82 + depends on ARCH_HIX5HD2 83 + help 84 + Say Y here to include support for high-speed I2C controller in the 85 + Hisilicon based hix5hd2 SoCs. 86 + 87 + This driver can also be built as a module. If so, the module 88 + will be called i2c-hix5hd2. 89 + 80 90 config I2C_I801 81 91 tristate "Intel 82801 (ICH/PCH)" 82 92 depends on PCI ··· 122 112 Wildcat Point (PCH) 123 113 Wildcat Point-LP (PCH) 124 114 BayTrail (SOC) 115 + Sunrise Point-H (PCH) 125 116 126 117 This driver can also be built as a module. If so, the module 127 118 will be called i2c-i801. ··· 348 337 This driver can also be built as a module. If so, the module 349 338 will be called i2c-au1550. 350 339 340 + config I2C_AXXIA 341 + tristate "Axxia I2C controller" 342 + depends on ARCH_AXXIA || COMPILE_TEST 343 + default ARCH_AXXIA 344 + help 345 + Say yes if you want to support the I2C bus on Axxia platforms. 346 + 347 + Please note that this controller is limited to transfers of maximum 348 + 255 bytes in length. Any attempt to to a larger transfer will return 349 + an error. 350 + 351 351 config I2C_BCM2835 352 352 tristate "Broadcom BCM2835 I2C controller" 353 353 depends on ARCH_BCM2835 ··· 445 423 config I2C_DESIGNWARE_PLATFORM 446 424 tristate "Synopsys DesignWare Platform" 447 425 select I2C_DESIGNWARE_CORE 426 + depends on (ACPI && COMMON_CLK) || !ACPI 448 427 help 449 428 If you say yes to this option, support will be included for the 450 429 Synopsys DesignWare I2C adapter. Only master mode is supported. ··· 488 465 489 466 config I2C_EXYNOS5 490 467 tristate "Exynos5 high-speed I2C driver" 491 - depends on ARCH_EXYNOS5 && OF 468 + depends on ARCH_EXYNOS && OF 492 469 default y 493 470 help 494 471 High-speed I2C controller on Exynos5 based Samsung SoCs.

+2

drivers/i2c/busses/Makefile

··· 31 31 # Embedded system I2C/SMBus host controller drivers 32 32 obj-$(CONFIG_I2C_AT91) += i2c-at91.o 33 33 obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o 34 + obj-$(CONFIG_I2C_AXXIA) += i2c-axxia.o 34 35 obj-$(CONFIG_I2C_BCM2835) += i2c-bcm2835.o 35 36 obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o 36 37 obj-$(CONFIG_I2C_CADENCE) += i2c-cadence.o ··· 48 47 obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o 49 48 obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o 50 49 obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o 50 + obj-$(CONFIG_I2C_HIX5HD2) += i2c-hix5hd2.o 51 51 obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o 52 52 obj-$(CONFIG_I2C_IMX) += i2c-imx.o 53 53 obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o

+559

drivers/i2c/busses/i2c-axxia.c

··· 1 + /* 2 + * This driver implements I2C master functionality using the LSI API2C 3 + * controller. 4 + * 5 + * NOTE: The controller has a limitation in that it can only do transfers of 6 + * maximum 255 bytes at a time. If a larger transfer is attempted, error code 7 + * (-EINVAL) is returned. 8 + * 9 + * This software is licensed under the terms of the GNU General Public 10 + * License version 2, as published by the Free Software Foundation, and 11 + * may be copied, distributed, and modified under those terms. 12 + */ 13 + #include <linux/clk.h> 14 + #include <linux/clkdev.h> 15 + #include <linux/err.h> 16 + #include <linux/i2c.h> 17 + #include <linux/init.h> 18 + #include <linux/interrupt.h> 19 + #include <linux/module.h> 20 + #include <linux/io.h> 21 + #include <linux/kernel.h> 22 + #include <linux/platform_device.h> 23 + 24 + #define SCL_WAIT_TIMEOUT_NS 25000000 25 + #define I2C_XFER_TIMEOUT (msecs_to_jiffies(250)) 26 + #define I2C_STOP_TIMEOUT (msecs_to_jiffies(100)) 27 + #define FIFO_SIZE 8 28 + 29 + #define GLOBAL_CONTROL 0x00 30 + #define GLOBAL_MST_EN BIT(0) 31 + #define GLOBAL_SLV_EN BIT(1) 32 + #define GLOBAL_IBML_EN BIT(2) 33 + #define INTERRUPT_STATUS 0x04 34 + #define INTERRUPT_ENABLE 0x08 35 + #define INT_SLV BIT(1) 36 + #define INT_MST BIT(0) 37 + #define WAIT_TIMER_CONTROL 0x0c 38 + #define WT_EN BIT(15) 39 + #define WT_VALUE(_x) ((_x) & 0x7fff) 40 + #define IBML_TIMEOUT 0x10 41 + #define IBML_LOW_MEXT 0x14 42 + #define IBML_LOW_SEXT 0x18 43 + #define TIMER_CLOCK_DIV 0x1c 44 + #define I2C_BUS_MONITOR 0x20 45 + #define SOFT_RESET 0x24 46 + #define MST_COMMAND 0x28 47 + #define CMD_BUSY (1<<3) 48 + #define CMD_MANUAL (0x00 | CMD_BUSY) 49 + #define CMD_AUTO (0x01 | CMD_BUSY) 50 + #define MST_RX_XFER 0x2c 51 + #define MST_TX_XFER 0x30 52 + #define MST_ADDR_1 0x34 53 + #define MST_ADDR_2 0x38 54 + #define MST_DATA 0x3c 55 + #define MST_TX_FIFO 0x40 56 + #define MST_RX_FIFO 0x44 57 + #define MST_INT_ENABLE 0x48 58 + #define MST_INT_STATUS 0x4c 59 + #define MST_STATUS_RFL (1 << 13) /* RX FIFO serivce */ 60 + #define MST_STATUS_TFL (1 << 12) /* TX FIFO service */ 61 + #define MST_STATUS_SNS (1 << 11) /* Manual mode done */ 62 + #define MST_STATUS_SS (1 << 10) /* Automatic mode done */ 63 + #define MST_STATUS_SCC (1 << 9) /* Stop complete */ 64 + #define MST_STATUS_IP (1 << 8) /* Invalid parameter */ 65 + #define MST_STATUS_TSS (1 << 7) /* Timeout */ 66 + #define MST_STATUS_AL (1 << 6) /* Arbitration lost */ 67 + #define MST_STATUS_ND (1 << 5) /* NAK on data phase */ 68 + #define MST_STATUS_NA (1 << 4) /* NAK on address phase */ 69 + #define MST_STATUS_NAK (MST_STATUS_NA | \ 70 + MST_STATUS_ND) 71 + #define MST_STATUS_ERR (MST_STATUS_NAK | \ 72 + MST_STATUS_AL | \ 73 + MST_STATUS_IP | \ 74 + MST_STATUS_TSS) 75 + #define MST_TX_BYTES_XFRD 0x50 76 + #define MST_RX_BYTES_XFRD 0x54 77 + #define SCL_HIGH_PERIOD 0x80 78 + #define SCL_LOW_PERIOD 0x84 79 + #define SPIKE_FLTR_LEN 0x88 80 + #define SDA_SETUP_TIME 0x8c 81 + #define SDA_HOLD_TIME 0x90 82 + 83 + /** 84 + * axxia_i2c_dev - I2C device context 85 + * @base: pointer to register struct 86 + * @msg: pointer to current message 87 + * @msg_xfrd: number of bytes transferred in msg 88 + * @msg_err: error code for completed message 89 + * @msg_complete: xfer completion object 90 + * @dev: device reference 91 + * @adapter: core i2c abstraction 92 + * @i2c_clk: clock reference for i2c input clock 93 + * @bus_clk_rate: current i2c bus clock rate 94 + */ 95 + struct axxia_i2c_dev { 96 + void __iomem *base; 97 + struct i2c_msg *msg; 98 + size_t msg_xfrd; 99 + int msg_err; 100 + struct completion msg_complete; 101 + struct device *dev; 102 + struct i2c_adapter adapter; 103 + struct clk *i2c_clk; 104 + u32 bus_clk_rate; 105 + }; 106 + 107 + static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask) 108 + { 109 + u32 int_en; 110 + 111 + int_en = readl(idev->base + MST_INT_ENABLE); 112 + writel(int_en & ~mask, idev->base + MST_INT_ENABLE); 113 + } 114 + 115 + static void i2c_int_enable(struct axxia_i2c_dev *idev, u32 mask) 116 + { 117 + u32 int_en; 118 + 119 + int_en = readl(idev->base + MST_INT_ENABLE); 120 + writel(int_en | mask, idev->base + MST_INT_ENABLE); 121 + } 122 + 123 + /** 124 + * ns_to_clk - Convert time (ns) to clock cycles for the given clock frequency. 125 + */ 126 + static u32 ns_to_clk(u64 ns, u32 clk_mhz) 127 + { 128 + return div_u64(ns * clk_mhz, 1000); 129 + } 130 + 131 + static int axxia_i2c_init(struct axxia_i2c_dev *idev) 132 + { 133 + u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate; 134 + u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000; 135 + u32 t_setup; 136 + u32 t_high, t_low; 137 + u32 tmo_clk; 138 + u32 prescale; 139 + unsigned long timeout; 140 + 141 + dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n", 142 + idev->bus_clk_rate, clk_mhz, divisor); 143 + 144 + /* Reset controller */ 145 + writel(0x01, idev->base + SOFT_RESET); 146 + timeout = jiffies + msecs_to_jiffies(100); 147 + while (readl(idev->base + SOFT_RESET) & 1) { 148 + if (time_after(jiffies, timeout)) { 149 + dev_warn(idev->dev, "Soft reset failed\n"); 150 + break; 151 + } 152 + } 153 + 154 + /* Enable Master Mode */ 155 + writel(0x1, idev->base + GLOBAL_CONTROL); 156 + 157 + if (idev->bus_clk_rate <= 100000) { 158 + /* Standard mode SCL 50/50, tSU:DAT = 250 ns */ 159 + t_high = divisor * 1 / 2; 160 + t_low = divisor * 1 / 2; 161 + t_setup = ns_to_clk(250, clk_mhz); 162 + } else { 163 + /* Fast mode SCL 33/66, tSU:DAT = 100 ns */ 164 + t_high = divisor * 1 / 3; 165 + t_low = divisor * 2 / 3; 166 + t_setup = ns_to_clk(100, clk_mhz); 167 + } 168 + 169 + /* SCL High Time */ 170 + writel(t_high, idev->base + SCL_HIGH_PERIOD); 171 + /* SCL Low Time */ 172 + writel(t_low, idev->base + SCL_LOW_PERIOD); 173 + /* SDA Setup Time */ 174 + writel(t_setup, idev->base + SDA_SETUP_TIME); 175 + /* SDA Hold Time, 300ns */ 176 + writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME); 177 + /* Filter <50ns spikes */ 178 + writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN); 179 + 180 + /* Configure Time-Out Registers */ 181 + tmo_clk = ns_to_clk(SCL_WAIT_TIMEOUT_NS, clk_mhz); 182 + 183 + /* Find prescaler value that makes tmo_clk fit in 15-bits counter. */ 184 + for (prescale = 0; prescale < 15; ++prescale) { 185 + if (tmo_clk <= 0x7fff) 186 + break; 187 + tmo_clk >>= 1; 188 + } 189 + if (tmo_clk > 0x7fff) 190 + tmo_clk = 0x7fff; 191 + 192 + /* Prescale divider (log2) */ 193 + writel(prescale, idev->base + TIMER_CLOCK_DIV); 194 + /* Timeout in divided clocks */ 195 + writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL); 196 + 197 + /* Mask all master interrupt bits */ 198 + i2c_int_disable(idev, ~0); 199 + 200 + /* Interrupt enable */ 201 + writel(0x01, idev->base + INTERRUPT_ENABLE); 202 + 203 + return 0; 204 + } 205 + 206 + static int i2c_m_rd(const struct i2c_msg *msg) 207 + { 208 + return (msg->flags & I2C_M_RD) != 0; 209 + } 210 + 211 + static int i2c_m_ten(const struct i2c_msg *msg) 212 + { 213 + return (msg->flags & I2C_M_TEN) != 0; 214 + } 215 + 216 + static int i2c_m_recv_len(const struct i2c_msg *msg) 217 + { 218 + return (msg->flags & I2C_M_RECV_LEN) != 0; 219 + } 220 + 221 + /** 222 + * axxia_i2c_empty_rx_fifo - Fetch data from RX FIFO and update SMBus block 223 + * transfer length if this is the first byte of such a transfer. 224 + */ 225 + static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev) 226 + { 227 + struct i2c_msg *msg = idev->msg; 228 + size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO); 229 + int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd); 230 + 231 + while (bytes_to_transfer-- > 0) { 232 + int c = readl(idev->base + MST_DATA); 233 + 234 + if (idev->msg_xfrd == 0 && i2c_m_recv_len(msg)) { 235 + /* 236 + * Check length byte for SMBus block read 237 + */ 238 + if (c <= 0 || c > I2C_SMBUS_BLOCK_MAX) { 239 + idev->msg_err = -EPROTO; 240 + i2c_int_disable(idev, ~0); 241 + complete(&idev->msg_complete); 242 + break; 243 + } 244 + msg->len = 1 + c; 245 + writel(msg->len, idev->base + MST_RX_XFER); 246 + } 247 + msg->buf[idev->msg_xfrd++] = c; 248 + } 249 + 250 + return 0; 251 + } 252 + 253 + /** 254 + * axxia_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer. 255 + * @return: Number of bytes left to transfer. 256 + */ 257 + static int axxia_i2c_fill_tx_fifo(struct axxia_i2c_dev *idev) 258 + { 259 + struct i2c_msg *msg = idev->msg; 260 + size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO); 261 + int bytes_to_transfer = min(tx_fifo_avail, msg->len - idev->msg_xfrd); 262 + int ret = msg->len - idev->msg_xfrd - bytes_to_transfer; 263 + 264 + while (bytes_to_transfer-- > 0) 265 + writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA); 266 + 267 + return ret; 268 + } 269 + 270 + static irqreturn_t axxia_i2c_isr(int irq, void *_dev) 271 + { 272 + struct axxia_i2c_dev *idev = _dev; 273 + u32 status; 274 + 275 + if (!(readl(idev->base + INTERRUPT_STATUS) & INT_MST)) 276 + return IRQ_NONE; 277 + 278 + /* Read interrupt status bits */ 279 + status = readl(idev->base + MST_INT_STATUS); 280 + 281 + if (!idev->msg) { 282 + dev_warn(idev->dev, "unexpected interrupt\n"); 283 + goto out; 284 + } 285 + 286 + /* RX FIFO needs service? */ 287 + if (i2c_m_rd(idev->msg) && (status & MST_STATUS_RFL)) 288 + axxia_i2c_empty_rx_fifo(idev); 289 + 290 + /* TX FIFO needs service? */ 291 + if (!i2c_m_rd(idev->msg) && (status & MST_STATUS_TFL)) { 292 + if (axxia_i2c_fill_tx_fifo(idev) == 0) 293 + i2c_int_disable(idev, MST_STATUS_TFL); 294 + } 295 + 296 + if (status & MST_STATUS_SCC) { 297 + /* Stop completed */ 298 + i2c_int_disable(idev, ~0); 299 + complete(&idev->msg_complete); 300 + } else if (status & MST_STATUS_SNS) { 301 + /* Transfer done */ 302 + i2c_int_disable(idev, ~0); 303 + if (i2c_m_rd(idev->msg) && idev->msg_xfrd < idev->msg->len) 304 + axxia_i2c_empty_rx_fifo(idev); 305 + complete(&idev->msg_complete); 306 + } else if (unlikely(status & MST_STATUS_ERR)) { 307 + /* Transfer error */ 308 + i2c_int_disable(idev, ~0); 309 + if (status & MST_STATUS_AL) 310 + idev->msg_err = -EAGAIN; 311 + else if (status & MST_STATUS_NAK) 312 + idev->msg_err = -ENXIO; 313 + else 314 + idev->msg_err = -EIO; 315 + dev_dbg(idev->dev, "error %#x, addr=%#x rx=%u/%u tx=%u/%u\n", 316 + status, 317 + idev->msg->addr, 318 + readl(idev->base + MST_RX_BYTES_XFRD), 319 + readl(idev->base + MST_RX_XFER), 320 + readl(idev->base + MST_TX_BYTES_XFRD), 321 + readl(idev->base + MST_TX_XFER)); 322 + complete(&idev->msg_complete); 323 + } 324 + 325 + out: 326 + /* Clear interrupt */ 327 + writel(INT_MST, idev->base + INTERRUPT_STATUS); 328 + 329 + return IRQ_HANDLED; 330 + } 331 + 332 + static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg) 333 + { 334 + u32 int_mask = MST_STATUS_ERR | MST_STATUS_SNS; 335 + u32 rx_xfer, tx_xfer; 336 + u32 addr_1, addr_2; 337 + int ret; 338 + 339 + if (msg->len > 255) { 340 + dev_warn(idev->dev, "unsupported length %u\n", msg->len); 341 + return -EINVAL; 342 + } 343 + 344 + idev->msg = msg; 345 + idev->msg_xfrd = 0; 346 + idev->msg_err = 0; 347 + reinit_completion(&idev->msg_complete); 348 + 349 + if (i2c_m_ten(msg)) { 350 + /* 10-bit address 351 + * addr_1: 5'b11110 | addr[9:8] | (R/nW) 352 + * addr_2: addr[7:0] 353 + */ 354 + addr_1 = 0xF0 | ((msg->addr >> 7) & 0x06); 355 + addr_2 = msg->addr & 0xFF; 356 + } else { 357 + /* 7-bit address 358 + * addr_1: addr[6:0] | (R/nW) 359 + * addr_2: dont care 360 + */ 361 + addr_1 = (msg->addr << 1) & 0xFF; 362 + addr_2 = 0; 363 + } 364 + 365 + if (i2c_m_rd(msg)) { 366 + /* I2C read transfer */ 367 + rx_xfer = i2c_m_recv_len(msg) ? I2C_SMBUS_BLOCK_MAX : msg->len; 368 + tx_xfer = 0; 369 + addr_1 |= 1; /* Set the R/nW bit of the address */ 370 + } else { 371 + /* I2C write transfer */ 372 + rx_xfer = 0; 373 + tx_xfer = msg->len; 374 + } 375 + 376 + writel(rx_xfer, idev->base + MST_RX_XFER); 377 + writel(tx_xfer, idev->base + MST_TX_XFER); 378 + writel(addr_1, idev->base + MST_ADDR_1); 379 + writel(addr_2, idev->base + MST_ADDR_2); 380 + 381 + if (i2c_m_rd(msg)) 382 + int_mask |= MST_STATUS_RFL; 383 + else if (axxia_i2c_fill_tx_fifo(idev) != 0) 384 + int_mask |= MST_STATUS_TFL; 385 + 386 + /* Start manual mode */ 387 + writel(CMD_MANUAL, idev->base + MST_COMMAND); 388 + 389 + i2c_int_enable(idev, int_mask); 390 + 391 + ret = wait_for_completion_timeout(&idev->msg_complete, 392 + I2C_XFER_TIMEOUT); 393 + 394 + i2c_int_disable(idev, int_mask); 395 + 396 + if (readl(idev->base + MST_COMMAND) & CMD_BUSY) 397 + dev_warn(idev->dev, "busy after xfer\n"); 398 + 399 + if (ret == 0) 400 + idev->msg_err = -ETIMEDOUT; 401 + 402 + if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO) 403 + axxia_i2c_init(idev); 404 + 405 + return idev->msg_err; 406 + } 407 + 408 + static int axxia_i2c_stop(struct axxia_i2c_dev *idev) 409 + { 410 + u32 int_mask = MST_STATUS_ERR | MST_STATUS_SCC; 411 + int ret; 412 + 413 + reinit_completion(&idev->msg_complete); 414 + 415 + /* Issue stop */ 416 + writel(0xb, idev->base + MST_COMMAND); 417 + i2c_int_enable(idev, int_mask); 418 + ret = wait_for_completion_timeout(&idev->msg_complete, 419 + I2C_STOP_TIMEOUT); 420 + i2c_int_disable(idev, int_mask); 421 + if (ret == 0) 422 + return -ETIMEDOUT; 423 + 424 + if (readl(idev->base + MST_COMMAND) & CMD_BUSY) 425 + dev_warn(idev->dev, "busy after stop\n"); 426 + 427 + return 0; 428 + } 429 + 430 + static int 431 + axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 432 + { 433 + struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); 434 + int i; 435 + int ret = 0; 436 + 437 + for (i = 0; ret == 0 && i < num; ++i) 438 + ret = axxia_i2c_xfer_msg(idev, &msgs[i]); 439 + 440 + axxia_i2c_stop(idev); 441 + 442 + return ret ? : i; 443 + } 444 + 445 + static u32 axxia_i2c_func(struct i2c_adapter *adap) 446 + { 447 + u32 caps = (I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | 448 + I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA); 449 + return caps; 450 + } 451 + 452 + static const struct i2c_algorithm axxia_i2c_algo = { 453 + .master_xfer = axxia_i2c_xfer, 454 + .functionality = axxia_i2c_func, 455 + }; 456 + 457 + static int axxia_i2c_probe(struct platform_device *pdev) 458 + { 459 + struct device_node *np = pdev->dev.of_node; 460 + struct axxia_i2c_dev *idev = NULL; 461 + struct resource *res; 462 + void __iomem *base; 463 + int irq; 464 + int ret = 0; 465 + 466 + idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL); 467 + if (!idev) 468 + return -ENOMEM; 469 + 470 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 471 + base = devm_ioremap_resource(&pdev->dev, res); 472 + if (IS_ERR(base)) 473 + return PTR_ERR(base); 474 + 475 + irq = platform_get_irq(pdev, 0); 476 + if (irq < 0) { 477 + dev_err(&pdev->dev, "missing interrupt resource\n"); 478 + return irq; 479 + } 480 + 481 + idev->i2c_clk = devm_clk_get(&pdev->dev, "i2c"); 482 + if (IS_ERR(idev->i2c_clk)) { 483 + dev_err(&pdev->dev, "missing clock\n"); 484 + return PTR_ERR(idev->i2c_clk); 485 + } 486 + 487 + idev->base = base; 488 + idev->dev = &pdev->dev; 489 + init_completion(&idev->msg_complete); 490 + 491 + of_property_read_u32(np, "clock-frequency", &idev->bus_clk_rate); 492 + if (idev->bus_clk_rate == 0) 493 + idev->bus_clk_rate = 100000; /* default clock rate */ 494 + 495 + ret = axxia_i2c_init(idev); 496 + if (ret) { 497 + dev_err(&pdev->dev, "failed to initialize\n"); 498 + return ret; 499 + } 500 + 501 + ret = devm_request_irq(&pdev->dev, irq, axxia_i2c_isr, 0, 502 + pdev->name, idev); 503 + if (ret) { 504 + dev_err(&pdev->dev, "failed to claim IRQ%d\n", irq); 505 + return ret; 506 + } 507 + 508 + clk_prepare_enable(idev->i2c_clk); 509 + 510 + i2c_set_adapdata(&idev->adapter, idev); 511 + strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); 512 + idev->adapter.owner = THIS_MODULE; 513 + idev->adapter.algo = &axxia_i2c_algo; 514 + idev->adapter.dev.parent = &pdev->dev; 515 + idev->adapter.dev.of_node = pdev->dev.of_node; 516 + 517 + platform_set_drvdata(pdev, idev); 518 + 519 + ret = i2c_add_adapter(&idev->adapter); 520 + if (ret) { 521 + dev_err(&pdev->dev, "failed to add adapter\n"); 522 + return ret; 523 + } 524 + 525 + return 0; 526 + } 527 + 528 + static int axxia_i2c_remove(struct platform_device *pdev) 529 + { 530 + struct axxia_i2c_dev *idev = platform_get_drvdata(pdev); 531 + 532 + clk_disable_unprepare(idev->i2c_clk); 533 + i2c_del_adapter(&idev->adapter); 534 + 535 + return 0; 536 + } 537 + 538 + /* Match table for of_platform binding */ 539 + static const struct of_device_id axxia_i2c_of_match[] = { 540 + { .compatible = "lsi,api2c", }, 541 + {}, 542 + }; 543 + 544 + MODULE_DEVICE_TABLE(of, axxia_i2c_of_match); 545 + 546 + static struct platform_driver axxia_i2c_driver = { 547 + .probe = axxia_i2c_probe, 548 + .remove = axxia_i2c_remove, 549 + .driver = { 550 + .name = "axxia-i2c", 551 + .of_match_table = axxia_i2c_of_match, 552 + }, 553 + }; 554 + 555 + module_platform_driver(axxia_i2c_driver); 556 + 557 + MODULE_DESCRIPTION("Axxia I2C Bus driver"); 558 + MODULE_AUTHOR("Anders Berg <anders.berg@lsi.com>"); 559 + MODULE_LICENSE("GPL v2");

+13 -2

drivers/i2c/busses/i2c-cros-ec-tunnel.c

··· 96 96 msg->addr_flags = i2c_msg->addr; 97 97 98 98 if (i2c_msg->flags & I2C_M_TEN) 99 - msg->addr_flags |= EC_I2C_FLAG_10BIT; 99 + return -EINVAL; 100 100 101 101 if (i2c_msg->flags & I2C_M_RD) { 102 102 msg->addr_flags |= EC_I2C_FLAG_READ; ··· 220 220 } 221 221 } 222 222 223 - ec_i2c_construct_message(request, i2c_msgs, num, bus_num); 223 + result = ec_i2c_construct_message(request, i2c_msgs, num, bus_num); 224 + if (result) 225 + goto exit; 224 226 225 227 msg.version = 0; 226 228 msg.command = EC_CMD_I2C_PASSTHRU; ··· 315 313 return 0; 316 314 } 317 315 316 + #ifdef CONFIG_OF 317 + static const struct of_device_id cros_ec_i2c_of_match[] = { 318 + { .compatible = "google,cros-ec-i2c-tunnel" }, 319 + {}, 320 + }; 321 + MODULE_DEVICE_TABLE(of, cros_ec_i2c_of_match); 322 + #endif 323 + 318 324 static struct platform_driver ec_i2c_tunnel_driver = { 319 325 .probe = ec_i2c_probe, 320 326 .remove = ec_i2c_remove, 321 327 .driver = { 322 328 .name = "cros-ec-i2c-tunnel", 329 + .of_match_table = of_match_ptr(cros_ec_i2c_of_match), 323 330 }, 324 331 }; 325 332

+72 -24

drivers/i2c/busses/i2c-designware-platdrv.c

··· 30 30 #include <linux/delay.h> 31 31 #include <linux/i2c.h> 32 32 #include <linux/clk.h> 33 + #include <linux/clk-provider.h> 33 34 #include <linux/errno.h> 34 35 #include <linux/sched.h> 35 36 #include <linux/err.h> ··· 42 41 #include <linux/io.h> 43 42 #include <linux/slab.h> 44 43 #include <linux/acpi.h> 44 + #include <linux/platform_data/i2c-designware.h> 45 45 #include "i2c-designware-core.h" 46 46 47 47 static struct i2c_algorithm i2c_dw_algo = { ··· 81 79 static int dw_i2c_acpi_configure(struct platform_device *pdev) 82 80 { 83 81 struct dw_i2c_dev *dev = platform_get_drvdata(pdev); 84 - bool fs_mode = dev->master_cfg & DW_IC_CON_SPEED_FAST; 85 - 86 - if (!ACPI_HANDLE(&pdev->dev)) 87 - return -ENODEV; 82 + const struct acpi_device_id *id; 88 83 89 84 dev->adapter.nr = -1; 90 85 dev->tx_fifo_depth = 32; ··· 91 92 * Try to get SDA hold time and *CNT values from an ACPI method if 92 93 * it exists for both supported speed modes. 93 94 */ 94 - dw_i2c_acpi_params(pdev, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, 95 - fs_mode ? NULL : &dev->sda_hold_time); 95 + dw_i2c_acpi_params(pdev, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, NULL); 96 96 dw_i2c_acpi_params(pdev, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, 97 - fs_mode ? &dev->sda_hold_time : NULL); 97 + &dev->sda_hold_time); 98 + 99 + /* 100 + * Provide a way for Designware I2C host controllers that are not 101 + * based on Intel LPSS to specify their input clock frequency via 102 + * id->driver_data. 103 + */ 104 + id = acpi_match_device(pdev->dev.driver->acpi_match_table, &pdev->dev); 105 + if (id && id->driver_data) 106 + clk_register_fixed_rate(&pdev->dev, dev_name(&pdev->dev), NULL, 107 + CLK_IS_ROOT, id->driver_data); 98 108 99 109 return 0; 110 + } 111 + 112 + static void dw_i2c_acpi_unconfigure(struct platform_device *pdev) 113 + { 114 + struct dw_i2c_dev *dev = platform_get_drvdata(pdev); 115 + const struct acpi_device_id *id; 116 + 117 + id = acpi_match_device(pdev->dev.driver->acpi_match_table, &pdev->dev); 118 + if (id && id->driver_data) 119 + clk_unregister(dev->clk); 100 120 } 101 121 102 122 static const struct acpi_device_id dw_i2c_acpi_match[] = { ··· 125 107 { "INT3433", 0 }, 126 108 { "80860F41", 0 }, 127 109 { "808622C1", 0 }, 110 + { "AMD0010", 133 * 1000 * 1000 }, 128 111 { } 129 112 }; 130 113 MODULE_DEVICE_TABLE(acpi, dw_i2c_acpi_match); ··· 134 115 { 135 116 return -ENODEV; 136 117 } 118 + static inline void dw_i2c_acpi_unconfigure(struct platform_device *pdev) { } 137 119 #endif 138 120 139 121 static int dw_i2c_probe(struct platform_device *pdev) ··· 142 122 struct dw_i2c_dev *dev; 143 123 struct i2c_adapter *adap; 144 124 struct resource *mem; 125 + struct dw_i2c_platform_data *pdata; 145 126 int irq, r; 127 + u32 clk_freq, ht = 0; 146 128 147 129 irq = platform_get_irq(pdev, 0); 148 130 if (irq < 0) { ··· 167 145 dev->irq = irq; 168 146 platform_set_drvdata(pdev, dev); 169 147 170 - dev->clk = devm_clk_get(&pdev->dev, NULL); 171 - dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz; 148 + /* fast mode by default because of legacy reasons */ 149 + clk_freq = 400000; 172 150 173 - if (IS_ERR(dev->clk)) 174 - return PTR_ERR(dev->clk); 175 - clk_prepare_enable(dev->clk); 176 - 177 - if (pdev->dev.of_node) { 178 - u32 ht = 0; 179 - u32 ic_clk = dev->get_clk_rate_khz(dev); 180 - 151 + if (ACPI_COMPANION(&pdev->dev)) { 152 + dw_i2c_acpi_configure(pdev); 153 + } else if (pdev->dev.of_node) { 181 154 of_property_read_u32(pdev->dev.of_node, 182 155 "i2c-sda-hold-time-ns", &ht); 183 - dev->sda_hold_time = div_u64((u64)ic_clk * ht + 500000, 184 - 1000000); 185 156 186 157 of_property_read_u32(pdev->dev.of_node, 187 158 "i2c-sda-falling-time-ns", ··· 182 167 of_property_read_u32(pdev->dev.of_node, 183 168 "i2c-scl-falling-time-ns", 184 169 &dev->scl_falling_time); 170 + 171 + of_property_read_u32(pdev->dev.of_node, "clock-frequency", 172 + &clk_freq); 173 + 174 + /* Only standard mode at 100kHz and fast mode at 400kHz 175 + * are supported. 176 + */ 177 + if (clk_freq != 100000 && clk_freq != 400000) { 178 + dev_err(&pdev->dev, "Only 100kHz and 400kHz supported"); 179 + return -EINVAL; 180 + } 181 + } else { 182 + pdata = dev_get_platdata(&pdev->dev); 183 + if (pdata) 184 + clk_freq = pdata->i2c_scl_freq; 185 185 } 186 186 187 187 dev->functionality = ··· 206 176 I2C_FUNC_SMBUS_BYTE_DATA | 207 177 I2C_FUNC_SMBUS_WORD_DATA | 208 178 I2C_FUNC_SMBUS_I2C_BLOCK; 209 - dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | 210 - DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST; 179 + if (clk_freq == 100000) 180 + dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | 181 + DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_STD; 182 + else 183 + dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | 184 + DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST; 211 185 212 - /* Try first if we can configure the device from ACPI */ 213 - r = dw_i2c_acpi_configure(pdev); 214 - if (r) { 186 + dev->clk = devm_clk_get(&pdev->dev, NULL); 187 + dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz; 188 + if (IS_ERR(dev->clk)) 189 + return PTR_ERR(dev->clk); 190 + clk_prepare_enable(dev->clk); 191 + 192 + if (!dev->sda_hold_time && ht) { 193 + u32 ic_clk = dev->get_clk_rate_khz(dev); 194 + 195 + dev->sda_hold_time = div_u64((u64)ic_clk * ht + 500000, 196 + 1000000); 197 + } 198 + 199 + if (!dev->tx_fifo_depth) { 215 200 u32 param1 = i2c_dw_read_comp_param(dev); 216 201 217 202 dev->tx_fifo_depth = ((param1 >> 16) & 0xff) + 1; ··· 281 236 282 237 pm_runtime_put(&pdev->dev); 283 238 pm_runtime_disable(&pdev->dev); 239 + 240 + if (ACPI_COMPANION(&pdev->dev)) 241 + dw_i2c_acpi_unconfigure(pdev); 284 242 285 243 return 0; 286 244 }

+65 -6

drivers/i2c/busses/i2c-exynos5.c

··· 83 83 #define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0) 84 84 #define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1) 85 85 #define HSI2C_INT_TRAILING_EN (1u << 6) 86 - #define HSI2C_INT_I2C_EN (1u << 9) 87 86 88 87 /* I2C_INT_STAT Register bits */ 89 88 #define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0) ··· 93 94 #define HSI2C_INT_RX_OVERRUN (1u << 5) 94 95 #define HSI2C_INT_TRAILING (1u << 6) 95 96 #define HSI2C_INT_I2C (1u << 9) 97 + 98 + #define HSI2C_INT_TRANS_DONE (1u << 7) 99 + #define HSI2C_INT_TRANS_ABORT (1u << 8) 100 + #define HSI2C_INT_NO_DEV_ACK (1u << 9) 101 + #define HSI2C_INT_NO_DEV (1u << 10) 102 + #define HSI2C_INT_TIMEOUT (1u << 11) 103 + #define HSI2C_INT_I2C_TRANS (HSI2C_INT_TRANS_DONE | \ 104 + HSI2C_INT_TRANS_ABORT | \ 105 + HSI2C_INT_NO_DEV_ACK | \ 106 + HSI2C_INT_NO_DEV | \ 107 + HSI2C_INT_TIMEOUT) 96 108 97 109 /* I2C_FIFO_STAT Register bits */ 98 110 #define HSI2C_RX_FIFO_EMPTY (1u << 24) ··· 152 142 #define HSI2C_FAST_SPD 0 153 143 154 144 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000)) 145 + 146 + #define HSI2C_EXYNOS7 BIT(0) 155 147 156 148 struct exynos5_i2c { 157 149 struct i2c_adapter adap; ··· 204 192 */ 205 193 struct exynos_hsi2c_variant { 206 194 unsigned int fifo_depth; 195 + unsigned int hw; 207 196 }; 208 197 209 198 static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = { ··· 213 200 214 201 static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = { 215 202 .fifo_depth = 16, 203 + }; 204 + 205 + static const struct exynos_hsi2c_variant exynos7_hsi2c_data = { 206 + .fifo_depth = 16, 207 + .hw = HSI2C_EXYNOS7, 216 208 }; 217 209 218 210 static const struct of_device_id exynos5_i2c_match[] = { ··· 230 212 }, { 231 213 .compatible = "samsung,exynos5260-hsi2c", 232 214 .data = &exynos5260_hsi2c_data 215 + }, { 216 + .compatible = "samsung,exynos7-hsi2c", 217 + .data = &exynos7_hsi2c_data 233 218 }, {}, 234 219 }; 235 220 MODULE_DEVICE_TABLE(of, exynos5_i2c_match); ··· 277 256 i2c->hs_clock : i2c->fs_clock; 278 257 279 258 /* 259 + * In case of HSI2C controller in Exynos5 series 280 260 * FPCLK / FI2C = 281 261 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE 262 + * 263 + * In case of HSI2C controllers in Exynos7 series 264 + * FPCLK / FI2C = 265 + * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE 266 + * 282 267 * utemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) 283 268 * utemp1 = (TSCLK_L + TSCLK_H + 2) 284 269 */ 285 270 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7; 286 - utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; 271 + utemp0 = (clkin / op_clk) - 8; 272 + 273 + if (i2c->variant->hw == HSI2C_EXYNOS7) 274 + utemp0 -= t_ftl_cycle; 275 + else 276 + utemp0 -= 2 * t_ftl_cycle; 287 277 288 278 /* CLK_DIV max is 256 */ 289 279 for (div = 0; div < 256; div++) { ··· 439 407 writel(int_status, i2c->regs + HSI2C_INT_STATUS); 440 408 441 409 /* handle interrupt related to the transfer status */ 442 - if (int_status & HSI2C_INT_I2C) { 410 + if (i2c->variant->hw == HSI2C_EXYNOS7) { 411 + if (int_status & HSI2C_INT_TRANS_DONE) { 412 + i2c->trans_done = 1; 413 + i2c->state = 0; 414 + } else if (int_status & HSI2C_INT_TRANS_ABORT) { 415 + dev_dbg(i2c->dev, "Deal with arbitration lose\n"); 416 + i2c->state = -EAGAIN; 417 + goto stop; 418 + } else if (int_status & HSI2C_INT_NO_DEV_ACK) { 419 + dev_dbg(i2c->dev, "No ACK from device\n"); 420 + i2c->state = -ENXIO; 421 + goto stop; 422 + } else if (int_status & HSI2C_INT_NO_DEV) { 423 + dev_dbg(i2c->dev, "No device\n"); 424 + i2c->state = -ENXIO; 425 + goto stop; 426 + } else if (int_status & HSI2C_INT_TIMEOUT) { 427 + dev_dbg(i2c->dev, "Accessing device timed out\n"); 428 + i2c->state = -EAGAIN; 429 + goto stop; 430 + } 431 + } else if (int_status & HSI2C_INT_I2C) { 443 432 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); 444 433 if (trans_status & HSI2C_NO_DEV_ACK) { 445 434 dev_dbg(i2c->dev, "No ACK from device\n"); ··· 565 512 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop) 566 513 { 567 514 u32 i2c_ctl; 568 - u32 int_en = HSI2C_INT_I2C_EN; 515 + u32 int_en = 0; 569 516 u32 i2c_auto_conf = 0; 570 517 u32 fifo_ctl; 571 518 unsigned long flags; 572 519 unsigned short trig_lvl; 520 + 521 + if (i2c->variant->hw == HSI2C_EXYNOS7) 522 + int_en |= HSI2C_INT_I2C_TRANS; 523 + else 524 + int_en |= HSI2C_INT_I2C; 573 525 574 526 i2c_ctl = readl(i2c->regs + HSI2C_CTL); 575 527 i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON); ··· 782 724 goto err_clk; 783 725 } 784 726 727 + /* Need to check the variant before setting up. */ 728 + i2c->variant = exynos5_i2c_get_variant(pdev); 729 + 785 730 ret = exynos5_hsi2c_clock_setup(i2c); 786 731 if (ret) 787 732 goto err_clk; 788 - 789 - i2c->variant = exynos5_i2c_get_variant(pdev); 790 733 791 734 exynos5_i2c_reset(i2c); 792 735

+557

drivers/i2c/busses/i2c-hix5hd2.c

··· 1 + /* 2 + * Copyright (c) 2014 Linaro Ltd. 3 + * Copyright (c) 2014 Hisilicon Limited. 4 + * 5 + * This program is free software; you can redistribute it and/or modify 6 + * it under the terms of the GNU General Public License as published by 7 + * the Free Software Foundation; either version 2 of the License, or 8 + * (at your option) any later version. 9 + * 10 + * Now only support 7 bit address. 11 + */ 12 + 13 + #include <linux/clk.h> 14 + #include <linux/delay.h> 15 + #include <linux/i2c.h> 16 + #include <linux/io.h> 17 + #include <linux/interrupt.h> 18 + #include <linux/module.h> 19 + #include <linux/of.h> 20 + #include <linux/platform_device.h> 21 + #include <linux/pm_runtime.h> 22 + 23 + /* Register Map */ 24 + #define HIX5I2C_CTRL 0x00 25 + #define HIX5I2C_COM 0x04 26 + #define HIX5I2C_ICR 0x08 27 + #define HIX5I2C_SR 0x0c 28 + #define HIX5I2C_SCL_H 0x10 29 + #define HIX5I2C_SCL_L 0x14 30 + #define HIX5I2C_TXR 0x18 31 + #define HIX5I2C_RXR 0x1c 32 + 33 + /* I2C_CTRL_REG */ 34 + #define I2C_ENABLE BIT(8) 35 + #define I2C_UNMASK_TOTAL BIT(7) 36 + #define I2C_UNMASK_START BIT(6) 37 + #define I2C_UNMASK_END BIT(5) 38 + #define I2C_UNMASK_SEND BIT(4) 39 + #define I2C_UNMASK_RECEIVE BIT(3) 40 + #define I2C_UNMASK_ACK BIT(2) 41 + #define I2C_UNMASK_ARBITRATE BIT(1) 42 + #define I2C_UNMASK_OVER BIT(0) 43 + #define I2C_UNMASK_ALL (I2C_UNMASK_ACK | I2C_UNMASK_OVER) 44 + 45 + /* I2C_COM_REG */ 46 + #define I2C_NO_ACK BIT(4) 47 + #define I2C_START BIT(3) 48 + #define I2C_READ BIT(2) 49 + #define I2C_WRITE BIT(1) 50 + #define I2C_STOP BIT(0) 51 + 52 + /* I2C_ICR_REG */ 53 + #define I2C_CLEAR_START BIT(6) 54 + #define I2C_CLEAR_END BIT(5) 55 + #define I2C_CLEAR_SEND BIT(4) 56 + #define I2C_CLEAR_RECEIVE BIT(3) 57 + #define I2C_CLEAR_ACK BIT(2) 58 + #define I2C_CLEAR_ARBITRATE BIT(1) 59 + #define I2C_CLEAR_OVER BIT(0) 60 + #define I2C_CLEAR_ALL (I2C_CLEAR_START | I2C_CLEAR_END | \ 61 + I2C_CLEAR_SEND | I2C_CLEAR_RECEIVE | \ 62 + I2C_CLEAR_ACK | I2C_CLEAR_ARBITRATE | \ 63 + I2C_CLEAR_OVER) 64 + 65 + /* I2C_SR_REG */ 66 + #define I2C_BUSY BIT(7) 67 + #define I2C_START_INTR BIT(6) 68 + #define I2C_END_INTR BIT(5) 69 + #define I2C_SEND_INTR BIT(4) 70 + #define I2C_RECEIVE_INTR BIT(3) 71 + #define I2C_ACK_INTR BIT(2) 72 + #define I2C_ARBITRATE_INTR BIT(1) 73 + #define I2C_OVER_INTR BIT(0) 74 + 75 + #define HIX5I2C_MAX_FREQ 400000 /* 400k */ 76 + #define HIX5I2C_READ_OPERATION 0x01 77 + 78 + enum hix5hd2_i2c_state { 79 + HIX5I2C_STAT_RW_ERR = -1, 80 + HIX5I2C_STAT_INIT, 81 + HIX5I2C_STAT_RW, 82 + HIX5I2C_STAT_SND_STOP, 83 + HIX5I2C_STAT_RW_SUCCESS, 84 + }; 85 + 86 + struct hix5hd2_i2c_priv { 87 + struct i2c_adapter adap; 88 + struct i2c_msg *msg; 89 + struct completion msg_complete; 90 + unsigned int msg_idx; 91 + unsigned int msg_len; 92 + int stop; 93 + void __iomem *regs; 94 + struct clk *clk; 95 + struct device *dev; 96 + spinlock_t lock; /* IRQ synchronization */ 97 + int err; 98 + unsigned int freq; 99 + enum hix5hd2_i2c_state state; 100 + }; 101 + 102 + static u32 hix5hd2_i2c_clr_pend_irq(struct hix5hd2_i2c_priv *priv) 103 + { 104 + u32 val = readl_relaxed(priv->regs + HIX5I2C_SR); 105 + 106 + writel_relaxed(val, priv->regs + HIX5I2C_ICR); 107 + 108 + return val; 109 + } 110 + 111 + static void hix5hd2_i2c_clr_all_irq(struct hix5hd2_i2c_priv *priv) 112 + { 113 + writel_relaxed(I2C_CLEAR_ALL, priv->regs + HIX5I2C_ICR); 114 + } 115 + 116 + static void hix5hd2_i2c_disable_irq(struct hix5hd2_i2c_priv *priv) 117 + { 118 + writel_relaxed(0, priv->regs + HIX5I2C_CTRL); 119 + } 120 + 121 + static void hix5hd2_i2c_enable_irq(struct hix5hd2_i2c_priv *priv) 122 + { 123 + writel_relaxed(I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL, 124 + priv->regs + HIX5I2C_CTRL); 125 + } 126 + 127 + static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c_priv *priv) 128 + { 129 + u32 rate, val; 130 + u32 scl, sysclock; 131 + 132 + /* close all i2c interrupt */ 133 + val = readl_relaxed(priv->regs + HIX5I2C_CTRL); 134 + writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL); 135 + 136 + rate = priv->freq; 137 + sysclock = clk_get_rate(priv->clk); 138 + scl = (sysclock / (rate * 2)) / 2 - 1; 139 + writel_relaxed(scl, priv->regs + HIX5I2C_SCL_H); 140 + writel_relaxed(scl, priv->regs + HIX5I2C_SCL_L); 141 + 142 + /* restore original interrupt*/ 143 + writel_relaxed(val, priv->regs + HIX5I2C_CTRL); 144 + 145 + dev_dbg(priv->dev, "%s: sysclock=%d, rate=%d, scl=%d\n", 146 + __func__, sysclock, rate, scl); 147 + } 148 + 149 + static void hix5hd2_i2c_init(struct hix5hd2_i2c_priv *priv) 150 + { 151 + hix5hd2_i2c_disable_irq(priv); 152 + hix5hd2_i2c_drv_setrate(priv); 153 + hix5hd2_i2c_clr_all_irq(priv); 154 + hix5hd2_i2c_enable_irq(priv); 155 + } 156 + 157 + static void hix5hd2_i2c_reset(struct hix5hd2_i2c_priv *priv) 158 + { 159 + clk_disable_unprepare(priv->clk); 160 + msleep(20); 161 + clk_prepare_enable(priv->clk); 162 + hix5hd2_i2c_init(priv); 163 + } 164 + 165 + static int hix5hd2_i2c_wait_bus_idle(struct hix5hd2_i2c_priv *priv) 166 + { 167 + unsigned long stop_time; 168 + u32 int_status; 169 + 170 + /* wait for 100 milli seconds for the bus to be idle */ 171 + stop_time = jiffies + msecs_to_jiffies(100); 172 + do { 173 + int_status = hix5hd2_i2c_clr_pend_irq(priv); 174 + if (!(int_status & I2C_BUSY)) 175 + return 0; 176 + 177 + usleep_range(50, 200); 178 + } while (time_before(jiffies, stop_time)); 179 + 180 + return -EBUSY; 181 + } 182 + 183 + static void hix5hd2_rw_over(struct hix5hd2_i2c_priv *priv) 184 + { 185 + if (priv->state == HIX5I2C_STAT_SND_STOP) 186 + dev_dbg(priv->dev, "%s: rw and send stop over\n", __func__); 187 + else 188 + dev_dbg(priv->dev, "%s: have not data to send\n", __func__); 189 + 190 + priv->state = HIX5I2C_STAT_RW_SUCCESS; 191 + priv->err = 0; 192 + } 193 + 194 + static void hix5hd2_rw_handle_stop(struct hix5hd2_i2c_priv *priv) 195 + { 196 + if (priv->stop) { 197 + priv->state = HIX5I2C_STAT_SND_STOP; 198 + writel_relaxed(I2C_STOP, priv->regs + HIX5I2C_COM); 199 + } else { 200 + hix5hd2_rw_over(priv); 201 + } 202 + } 203 + 204 + static void hix5hd2_read_handle(struct hix5hd2_i2c_priv *priv) 205 + { 206 + if (priv->msg_len == 1) { 207 + /* the last byte don't need send ACK */ 208 + writel_relaxed(I2C_READ | I2C_NO_ACK, priv->regs + HIX5I2C_COM); 209 + } else if (priv->msg_len > 1) { 210 + /* if i2c master receive data will send ACK */ 211 + writel_relaxed(I2C_READ, priv->regs + HIX5I2C_COM); 212 + } else { 213 + hix5hd2_rw_handle_stop(priv); 214 + } 215 + } 216 + 217 + static void hix5hd2_write_handle(struct hix5hd2_i2c_priv *priv) 218 + { 219 + u8 data; 220 + 221 + if (priv->msg_len > 0) { 222 + data = priv->msg->buf[priv->msg_idx++]; 223 + writel_relaxed(data, priv->regs + HIX5I2C_TXR); 224 + writel_relaxed(I2C_WRITE, priv->regs + HIX5I2C_COM); 225 + } else { 226 + hix5hd2_rw_handle_stop(priv); 227 + } 228 + } 229 + 230 + static int hix5hd2_rw_preprocess(struct hix5hd2_i2c_priv *priv) 231 + { 232 + u8 data; 233 + 234 + if (priv->state == HIX5I2C_STAT_INIT) { 235 + priv->state = HIX5I2C_STAT_RW; 236 + } else if (priv->state == HIX5I2C_STAT_RW) { 237 + if (priv->msg->flags & I2C_M_RD) { 238 + data = readl_relaxed(priv->regs + HIX5I2C_RXR); 239 + priv->msg->buf[priv->msg_idx++] = data; 240 + } 241 + priv->msg_len--; 242 + } else { 243 + dev_dbg(priv->dev, "%s: error: priv->state = %d, msg_len = %d\n", 244 + __func__, priv->state, priv->msg_len); 245 + return -EAGAIN; 246 + } 247 + return 0; 248 + } 249 + 250 + static irqreturn_t hix5hd2_i2c_irq(int irqno, void *dev_id) 251 + { 252 + struct hix5hd2_i2c_priv *priv = dev_id; 253 + u32 int_status; 254 + int ret; 255 + 256 + spin_lock(&priv->lock); 257 + 258 + int_status = hix5hd2_i2c_clr_pend_irq(priv); 259 + 260 + /* handle error */ 261 + if (int_status & I2C_ARBITRATE_INTR) { 262 + /* bus error */ 263 + dev_dbg(priv->dev, "ARB bus loss\n"); 264 + priv->err = -EAGAIN; 265 + priv->state = HIX5I2C_STAT_RW_ERR; 266 + goto stop; 267 + } else if (int_status & I2C_ACK_INTR) { 268 + /* ack error */ 269 + dev_dbg(priv->dev, "No ACK from device\n"); 270 + priv->err = -ENXIO; 271 + priv->state = HIX5I2C_STAT_RW_ERR; 272 + goto stop; 273 + } 274 + 275 + if (int_status & I2C_OVER_INTR) { 276 + if (priv->msg_len > 0) { 277 + ret = hix5hd2_rw_preprocess(priv); 278 + if (ret) { 279 + priv->err = ret; 280 + priv->state = HIX5I2C_STAT_RW_ERR; 281 + goto stop; 282 + } 283 + if (priv->msg->flags & I2C_M_RD) 284 + hix5hd2_read_handle(priv); 285 + else 286 + hix5hd2_write_handle(priv); 287 + } else { 288 + hix5hd2_rw_over(priv); 289 + } 290 + } 291 + 292 + stop: 293 + if ((priv->state == HIX5I2C_STAT_RW_SUCCESS && 294 + priv->msg->len == priv->msg_idx) || 295 + (priv->state == HIX5I2C_STAT_RW_ERR)) { 296 + hix5hd2_i2c_disable_irq(priv); 297 + hix5hd2_i2c_clr_pend_irq(priv); 298 + complete(&priv->msg_complete); 299 + } 300 + 301 + spin_unlock(&priv->lock); 302 + 303 + return IRQ_HANDLED; 304 + } 305 + 306 + static void hix5hd2_i2c_message_start(struct hix5hd2_i2c_priv *priv, int stop) 307 + { 308 + unsigned long flags; 309 + 310 + spin_lock_irqsave(&priv->lock, flags); 311 + hix5hd2_i2c_clr_all_irq(priv); 312 + hix5hd2_i2c_enable_irq(priv); 313 + 314 + if (priv->msg->flags & I2C_M_RD) 315 + writel_relaxed((priv->msg->addr << 1) | HIX5I2C_READ_OPERATION, 316 + priv->regs + HIX5I2C_TXR); 317 + else 318 + writel_relaxed(priv->msg->addr << 1, 319 + priv->regs + HIX5I2C_TXR); 320 + 321 + writel_relaxed(I2C_WRITE | I2C_START, priv->regs + HIX5I2C_COM); 322 + spin_unlock_irqrestore(&priv->lock, flags); 323 + } 324 + 325 + static int hix5hd2_i2c_xfer_msg(struct hix5hd2_i2c_priv *priv, 326 + struct i2c_msg *msgs, int stop) 327 + { 328 + unsigned long timeout; 329 + int ret; 330 + 331 + priv->msg = msgs; 332 + priv->msg_idx = 0; 333 + priv->msg_len = priv->msg->len; 334 + priv->stop = stop; 335 + priv->err = 0; 336 + priv->state = HIX5I2C_STAT_INIT; 337 + 338 + reinit_completion(&priv->msg_complete); 339 + hix5hd2_i2c_message_start(priv, stop); 340 + 341 + timeout = wait_for_completion_timeout(&priv->msg_complete, 342 + priv->adap.timeout); 343 + if (timeout == 0) { 344 + priv->state = HIX5I2C_STAT_RW_ERR; 345 + priv->err = -ETIMEDOUT; 346 + dev_warn(priv->dev, "%s timeout=%d\n", 347 + msgs->flags & I2C_M_RD ? "rx" : "tx", 348 + priv->adap.timeout); 349 + } 350 + ret = priv->state; 351 + 352 + /* 353 + * If this is the last message to be transfered (stop == 1) 354 + * Then check if the bus can be brought back to idle. 355 + */ 356 + if (priv->state == HIX5I2C_STAT_RW_SUCCESS && stop) 357 + ret = hix5hd2_i2c_wait_bus_idle(priv); 358 + 359 + if (ret < 0) 360 + hix5hd2_i2c_reset(priv); 361 + 362 + return priv->err; 363 + } 364 + 365 + static int hix5hd2_i2c_xfer(struct i2c_adapter *adap, 366 + struct i2c_msg *msgs, int num) 367 + { 368 + struct hix5hd2_i2c_priv *priv = i2c_get_adapdata(adap); 369 + int i, ret, stop; 370 + 371 + pm_runtime_get_sync(priv->dev); 372 + 373 + for (i = 0; i < num; i++, msgs++) { 374 + stop = (i == num - 1); 375 + ret = hix5hd2_i2c_xfer_msg(priv, msgs, stop); 376 + if (ret < 0) 377 + goto out; 378 + } 379 + 380 + if (i == num) { 381 + ret = num; 382 + } else { 383 + /* Only one message, cannot access the device */ 384 + if (i == 1) 385 + ret = -EREMOTEIO; 386 + else 387 + ret = i; 388 + 389 + dev_warn(priv->dev, "xfer message failed\n"); 390 + } 391 + 392 + out: 393 + pm_runtime_mark_last_busy(priv->dev); 394 + pm_runtime_put_autosuspend(priv->dev); 395 + return ret; 396 + } 397 + 398 + static u32 hix5hd2_i2c_func(struct i2c_adapter *adap) 399 + { 400 + return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 401 + } 402 + 403 + static const struct i2c_algorithm hix5hd2_i2c_algorithm = { 404 + .master_xfer = hix5hd2_i2c_xfer, 405 + .functionality = hix5hd2_i2c_func, 406 + }; 407 + 408 + static int hix5hd2_i2c_probe(struct platform_device *pdev) 409 + { 410 + struct device_node *np = pdev->dev.of_node; 411 + struct hix5hd2_i2c_priv *priv; 412 + struct resource *mem; 413 + unsigned int freq; 414 + int irq, ret; 415 + 416 + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 417 + if (!priv) 418 + return -ENOMEM; 419 + 420 + if (of_property_read_u32(np, "clock-frequency", &freq)) { 421 + /* use 100k as default value */ 422 + priv->freq = 100000; 423 + } else { 424 + if (freq > HIX5I2C_MAX_FREQ) { 425 + priv->freq = HIX5I2C_MAX_FREQ; 426 + dev_warn(priv->dev, "use max freq %d instead\n", 427 + HIX5I2C_MAX_FREQ); 428 + } else { 429 + priv->freq = freq; 430 + } 431 + } 432 + 433 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 434 + priv->regs = devm_ioremap_resource(&pdev->dev, mem); 435 + if (IS_ERR(priv->regs)) 436 + return PTR_ERR(priv->regs); 437 + 438 + irq = platform_get_irq(pdev, 0); 439 + if (irq <= 0) { 440 + dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n"); 441 + return irq; 442 + } 443 + 444 + priv->clk = devm_clk_get(&pdev->dev, NULL); 445 + if (IS_ERR(priv->clk)) { 446 + dev_err(&pdev->dev, "cannot get clock\n"); 447 + return PTR_ERR(priv->clk); 448 + } 449 + clk_prepare_enable(priv->clk); 450 + 451 + strlcpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name)); 452 + priv->dev = &pdev->dev; 453 + priv->adap.owner = THIS_MODULE; 454 + priv->adap.algo = &hix5hd2_i2c_algorithm; 455 + priv->adap.retries = 3; 456 + priv->adap.dev.of_node = np; 457 + priv->adap.algo_data = priv; 458 + priv->adap.dev.parent = &pdev->dev; 459 + i2c_set_adapdata(&priv->adap, priv); 460 + platform_set_drvdata(pdev, priv); 461 + spin_lock_init(&priv->lock); 462 + init_completion(&priv->msg_complete); 463 + 464 + hix5hd2_i2c_init(priv); 465 + 466 + ret = devm_request_irq(&pdev->dev, irq, hix5hd2_i2c_irq, 467 + IRQF_NO_SUSPEND | IRQF_ONESHOT, 468 + dev_name(&pdev->dev), priv); 469 + if (ret != 0) { 470 + dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", irq); 471 + goto err_clk; 472 + } 473 + 474 + pm_suspend_ignore_children(&pdev->dev, true); 475 + pm_runtime_set_autosuspend_delay(priv->dev, MSEC_PER_SEC); 476 + pm_runtime_use_autosuspend(priv->dev); 477 + pm_runtime_set_active(priv->dev); 478 + pm_runtime_enable(priv->dev); 479 + 480 + ret = i2c_add_adapter(&priv->adap); 481 + if (ret < 0) { 482 + dev_err(&pdev->dev, "failed to add bus to i2c core\n"); 483 + goto err_runtime; 484 + } 485 + 486 + return ret; 487 + 488 + err_runtime: 489 + pm_runtime_disable(priv->dev); 490 + pm_runtime_set_suspended(priv->dev); 491 + err_clk: 492 + clk_disable_unprepare(priv->clk); 493 + return ret; 494 + } 495 + 496 + static int hix5hd2_i2c_remove(struct platform_device *pdev) 497 + { 498 + struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev); 499 + 500 + i2c_del_adapter(&priv->adap); 501 + pm_runtime_disable(priv->dev); 502 + pm_runtime_set_suspended(priv->dev); 503 + 504 + return 0; 505 + } 506 + 507 + #ifdef CONFIG_PM 508 + static int hix5hd2_i2c_runtime_suspend(struct device *dev) 509 + { 510 + struct platform_device *pdev = to_platform_device(dev); 511 + struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev); 512 + 513 + clk_disable_unprepare(priv->clk); 514 + 515 + return 0; 516 + } 517 + 518 + static int hix5hd2_i2c_runtime_resume(struct device *dev) 519 + { 520 + struct platform_device *pdev = to_platform_device(dev); 521 + struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev); 522 + 523 + clk_prepare_enable(priv->clk); 524 + hix5hd2_i2c_init(priv); 525 + 526 + return 0; 527 + } 528 + #endif 529 + 530 + static const struct dev_pm_ops hix5hd2_i2c_pm_ops = { 531 + SET_PM_RUNTIME_PM_OPS(hix5hd2_i2c_runtime_suspend, 532 + hix5hd2_i2c_runtime_resume, 533 + NULL) 534 + }; 535 + 536 + static const struct of_device_id hix5hd2_i2c_match[] = { 537 + { .compatible = "hisilicon,hix5hd2-i2c" }, 538 + {}, 539 + }; 540 + MODULE_DEVICE_TABLE(of, hix5hd2_i2c_match); 541 + 542 + static struct platform_driver hix5hd2_i2c_driver = { 543 + .probe = hix5hd2_i2c_probe, 544 + .remove = hix5hd2_i2c_remove, 545 + .driver = { 546 + .name = "hix5hd2-i2c", 547 + .pm = &hix5hd2_i2c_pm_ops, 548 + .of_match_table = hix5hd2_i2c_match, 549 + }, 550 + }; 551 + 552 + module_platform_driver(hix5hd2_i2c_driver); 553 + 554 + MODULE_DESCRIPTION("Hix5hd2 I2C Bus driver"); 555 + MODULE_AUTHOR("Wei Yan <sledge.yanwei@huawei.com>"); 556 + MODULE_LICENSE("GPL"); 557 + MODULE_ALIAS("platform:i2c-hix5hd2");

+3

drivers/i2c/busses/i2c-i801.c

··· 62 62 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 63 63 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 64 64 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 65 + * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 65 66 * 66 67 * Features supported by this driver: 67 68 * Software PEC no ··· 185 184 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 186 185 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 187 186 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 187 + #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 188 188 189 189 struct i801_mux_config { 190 190 char *gpio_chip; ··· 832 830 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 833 831 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 834 832 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 833 + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 835 834 { 0, } 836 835 }; 837 836

+14 -2

drivers/i2c/busses/i2c-imx.c

··· 268 268 269 269 while (1) { 270 270 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 271 + 272 + /* check for arbitration lost */ 273 + if (temp & I2SR_IAL) { 274 + temp &= ~I2SR_IAL; 275 + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 276 + return -EAGAIN; 277 + } 278 + 271 279 if (for_busy && (temp & I2SR_IBB)) 272 280 break; 273 281 if (!for_busy && !(temp & I2SR_IBB)) ··· 710 702 pdev->name, i2c_imx); 711 703 if (ret) { 712 704 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 713 - return ret; 705 + goto clk_disable; 714 706 } 715 707 716 708 /* Init queue */ ··· 735 727 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 736 728 if (ret < 0) { 737 729 dev_err(&pdev->dev, "registration failed\n"); 738 - return ret; 730 + goto clk_disable; 739 731 } 740 732 741 733 /* Set up platform driver data */ ··· 749 741 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 750 742 751 743 return 0; /* Return OK */ 744 + 745 + clk_disable: 746 + clk_disable_unprepare(i2c_imx->clk); 747 + return ret; 752 748 } 753 749 754 750 static int i2c_imx_remove(struct platform_device *pdev)

+1 -1

drivers/i2c/busses/i2c-ismt.c

··· 81 81 #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a 82 82 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15 83 83 84 - #define ISMT_DESC_ENTRIES 32 /* number of descriptor entries */ 84 + #define ISMT_DESC_ENTRIES 2 /* number of descriptor entries */ 85 85 #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */ 86 86 87 87 /* Hardware Descriptor Constants - Control Field */

+3

drivers/i2c/busses/i2c-mxs.c

··· 307 307 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 308 308 309 309 while (readl(i2c->regs + MXS_I2C_CTRL0) & MXS_I2C_CTRL0_RUN) { 310 + if (readl(i2c->regs + MXS_I2C_CTRL1) & 311 + MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ) 312 + return -ENXIO; 310 313 if (time_after(jiffies, timeout)) 311 314 return -ETIMEDOUT; 312 315 cond_resched();

+11 -10

drivers/i2c/busses/i2c-rcar.c

··· 195 195 */ 196 196 rate = clk_get_rate(priv->clk); 197 197 cdf = rate / 20000000; 198 - if (cdf >= 1 << cdf_width) { 198 + if (cdf >= 1U << cdf_width) { 199 199 dev_err(dev, "Input clock %lu too high\n", rate); 200 200 return -EIO; 201 201 } ··· 245 245 return 0; 246 246 } 247 247 248 - static int rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 248 + static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 249 249 { 250 250 int read = !!rcar_i2c_is_recv(priv); 251 251 ··· 253 253 rcar_i2c_write(priv, ICMSR, 0); 254 254 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 255 255 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 256 - 257 - return 0; 258 256 } 259 257 260 258 /* ··· 363 365 static irqreturn_t rcar_i2c_irq(int irq, void *ptr) 364 366 { 365 367 struct rcar_i2c_priv *priv = ptr; 368 + irqreturn_t result = IRQ_HANDLED; 366 369 u32 msr; 367 370 368 371 /*-------------- spin lock -----------------*/ ··· 373 374 374 375 /* Only handle interrupts that are currently enabled */ 375 376 msr &= rcar_i2c_read(priv, ICMIER); 377 + if (!msr) { 378 + result = IRQ_NONE; 379 + goto exit; 380 + } 376 381 377 382 /* Arbitration lost */ 378 383 if (msr & MAL) { ··· 411 408 wake_up(&priv->wait); 412 409 } 413 410 411 + exit: 414 412 spin_unlock(&priv->lock); 415 413 /*-------------- spin unlock -----------------*/ 416 414 417 - return IRQ_HANDLED; 415 + return result; 418 416 } 419 417 420 418 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, ··· 457 453 priv->msg = &msgs[i]; 458 454 priv->pos = 0; 459 455 priv->flags = 0; 460 - if (priv->msg == &msgs[num - 1]) 456 + if (i == num - 1) 461 457 rcar_i2c_flags_set(priv, ID_LAST_MSG); 462 458 463 - ret = rcar_i2c_prepare_msg(priv); 459 + rcar_i2c_prepare_msg(priv); 464 460 465 461 spin_unlock_irqrestore(&priv->lock, flags); 466 462 /*-------------- spin unlock -----------------*/ 467 - 468 - if (ret < 0) 469 - break; 470 463 471 464 timeout = wait_event_timeout(priv->wait, 472 465 rcar_i2c_flags_has(priv, ID_DONE),

+2 -2

drivers/i2c/busses/i2c-rk3x.c

··· 208 208 * The hw can read up to 32 bytes at a time. If we need more than one 209 209 * chunk, send an ACK after the last byte of the current chunk. 210 210 */ 211 - if (unlikely(len > 32)) { 211 + if (len > 32) { 212 212 len = 32; 213 213 con &= ~REG_CON_LASTACK; 214 214 } else { ··· 403 403 } 404 404 405 405 /* is there anything left to handle? */ 406 - if (unlikely((ipd & REG_INT_ALL) == 0)) 406 + if ((ipd & REG_INT_ALL) == 0) 407 407 goto out; 408 408 409 409 switch (i2c->state) {

-3

include/linux/mfd/cros_ec_commands.h

··· 1928 1928 1929 1929 #define EC_CMD_I2C_PASSTHRU 0x9e 1930 1930 1931 - /* Slave address is 10 (not 7) bit */ 1932 - #define EC_I2C_FLAG_10BIT (1 << 16) 1933 - 1934 1931 /* Read data; if not present, message is a write */ 1935 1932 #define EC_I2C_FLAG_READ (1 << 15) 1936 1933

+21

include/linux/platform_data/i2c-designware.h

··· 1 + /* 2 + * Copyright(c) 2014 Intel Corporation. 3 + * 4 + * This program is free software; you can redistribute it and/or modify it 5 + * under the terms and conditions of the GNU General Public License, 6 + * version 2, as published by the Free Software Foundation. 7 + * 8 + * This program is distributed in the hope it will be useful, but WITHOUT 9 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 + * more details. 12 + */ 13 + 14 + #ifndef I2C_DESIGNWARE_H 15 + #define I2C_DESIGNWARE_H 16 + 17 + struct dw_i2c_platform_data { 18 + unsigned int i2c_scl_freq; 19 + }; 20 + 21 + #endif

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