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drm/nouveau: Fetch zcull info from device

This information will be exposed to userspace in the following commit.

Add struct nvkm_gr_zcull_info, which serves as abstraction layer between
the corresponding uAPI (added in a subsequent patch) and the firmware
structure.

Extend the existing get_ctxbufs callback to also fill in zcull info.
ctxsw_size and ctxsw_align come from
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO, which is
already called by r570_gr_get_ctxbufs, while the rest of the zcull
info comes from
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL.
Adding a separate callback for zcull info would require us to either:

1) Call GET_CONTEXT_BUFFERS_INFO twice, once for each callback. This
is a little slower and more verbose than calling it once.
or
2) Fill out zcull_info partially in r570_gr_get_ctxbufs and partially
in the new callback. Since we fill out only some of the info in each
we now need to handle edge cases where one function is called but not
the other as well as them being called in an arbitrary order.

Because of this, it's simplest to combine them in a single call
(get_ctxbufs_and_zcull_info), which avoids repeated rpc calls
to the gpu without the complexity of handling partially complete states.

Signed-off-by: Mel Henning <mhenning@darkrefraction.com>
Link: https://patch.msgid.link/20260219-zcull3-v3-1-dbe6a716f104@darkrefraction.com
Signed-off-by: Danilo Krummrich <dakr@kernel.org>

authored by

Mel Henning and committed by
Danilo Krummrich 27e125e5 61c0f69a

+77 -6
+19
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
··· 3 3 #define __NVKM_GR_H__ 4 4 #include <core/engine.h> 5 5 6 + struct nvkm_gr_zcull_info { 7 + __u32 width_align_pixels; 8 + __u32 height_align_pixels; 9 + __u32 pixel_squares_by_aliquots; 10 + __u32 aliquot_total; 11 + __u32 zcull_region_byte_multiplier; 12 + __u32 zcull_region_header_size; 13 + __u32 zcull_subregion_header_size; 14 + __u32 subregion_count; 15 + __u32 subregion_width_align_pixels; 16 + __u32 subregion_height_align_pixels; 17 + 18 + __u32 ctxsw_size; 19 + __u32 ctxsw_align; 20 + }; 21 + 6 22 struct nvkm_gr { 7 23 const struct nvkm_gr_func *func; 8 24 struct nvkm_engine engine; 25 + 26 + struct nvkm_gr_zcull_info zcull_info; 27 + bool has_zcull_info; 9 28 }; 10 29 11 30 u64 nvkm_gr_units(struct nvkm_gr *);
+6 -3
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c
··· 249 249 } 250 250 251 251 static int 252 - r535_gr_get_ctxbufs_info(struct r535_gr *gr) 252 + r535_gr_get_ctxbufs_and_zcull_info(struct r535_gr *gr) 253 253 { 254 254 NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS *info; 255 255 struct nvkm_subdev *subdev = &gr->base.engine.subdev; ··· 265 265 r535_gr_get_ctxbuf_info(gr, i, &info->engineContextBuffersInfo[0].engine[i]); 266 266 267 267 nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, info); 268 + 269 + gr->base.has_zcull_info = false; 270 + 268 271 return 0; 269 272 } 270 273 ··· 315 312 * 316 313 * Also build the information that'll be used to create channel contexts. 317 314 */ 318 - ret = rm->api->gr->get_ctxbufs_info(gr); 315 + ret = rm->api->gr->get_ctxbufs_and_zcull_info(gr); 319 316 if (ret) 320 317 goto done; 321 318 ··· 355 352 356 353 const struct nvkm_rm_api_gr 357 354 r535_gr = { 358 - .get_ctxbufs_info = r535_gr_get_ctxbufs_info, 355 + .get_ctxbufs_and_zcull_info = r535_gr_get_ctxbufs_and_zcull_info, 359 356 };
+32 -2
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gr.c
··· 164 164 } 165 165 166 166 static int 167 - r570_gr_get_ctxbufs_info(struct r535_gr *gr) 167 + r570_gr_get_ctxbufs_and_zcull_info(struct r535_gr *gr) 168 168 { 169 169 NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS *info; 170 + NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS *zcull_info; 170 171 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 171 172 struct nvkm_gsp *gsp = subdev->device->gsp; 172 173 ··· 180 179 for (int i = 0; i < ARRAY_SIZE(info->engineContextBuffersInfo[0].engine); i++) 181 180 r535_gr_get_ctxbuf_info(gr, i, &info->engineContextBuffersInfo[0].engine[i]); 182 181 182 + NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO zcull = info->engineContextBuffersInfo[0] 183 + .engine[NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL]; 184 + gr->base.zcull_info.ctxsw_size = zcull.size; 185 + gr->base.zcull_info.ctxsw_align = zcull.alignment; 186 + 183 187 nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, info); 188 + 189 + zcull_info = nvkm_gsp_rm_ctrl_rd(&gsp->internal.device.subdevice, 190 + NV2080_CTRL_CMD_GR_GET_ZCULL_INFO, 191 + sizeof(*zcull_info)); 192 + if (IS_ERR(zcull_info)) { 193 + nvdev_error(gr->base.engine.subdev.device, "could not fetch zcull info\n"); 194 + return PTR_ERR(zcull_info); 195 + } 196 + 197 + gr->base.zcull_info.width_align_pixels = zcull_info->widthAlignPixels; 198 + gr->base.zcull_info.height_align_pixels = zcull_info->heightAlignPixels; 199 + gr->base.zcull_info.pixel_squares_by_aliquots = zcull_info->pixelSquaresByAliquots; 200 + gr->base.zcull_info.aliquot_total = zcull_info->aliquotTotal; 201 + gr->base.zcull_info.zcull_region_byte_multiplier = zcull_info->zcullRegionByteMultiplier; 202 + gr->base.zcull_info.zcull_region_header_size = zcull_info->zcullRegionHeaderSize; 203 + gr->base.zcull_info.zcull_subregion_header_size = zcull_info->zcullSubregionHeaderSize; 204 + gr->base.zcull_info.subregion_count = zcull_info->subregionCount; 205 + gr->base.zcull_info.subregion_width_align_pixels = zcull_info->subregionWidthAlignPixels; 206 + gr->base.zcull_info.subregion_height_align_pixels = zcull_info->subregionHeightAlignPixels; 207 + 208 + nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, zcull_info); 209 + 210 + gr->base.has_zcull_info = true; 211 + 184 212 return 0; 185 213 } 186 214 187 215 const struct nvkm_rm_api_gr 188 216 r570_gr = { 189 - .get_ctxbufs_info = r570_gr_get_ctxbufs_info, 217 + .get_ctxbufs_and_zcull_info = r570_gr_get_ctxbufs_and_zcull_info, 190 218 .scrubber.init = r570_gr_scrubber_init, 191 219 .scrubber.fini = r570_gr_scrubber_fini, 192 220 };
+19
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/gr.h
··· 76 76 } NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS; 77 77 78 78 #define NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR (0x20800a46) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID" */ 79 + 80 + #define NV2080_CTRL_CMD_GR_GET_ZCULL_INFO (0x20801206U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */ 81 + 82 + #define NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_SUBREGION_SUPPORTED 83 + #define NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x6U) 84 + 85 + typedef struct NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS { 86 + NvU32 widthAlignPixels; 87 + NvU32 heightAlignPixels; 88 + NvU32 pixelSquaresByAliquots; 89 + NvU32 aliquotTotal; 90 + NvU32 zcullRegionByteMultiplier; 91 + NvU32 zcullRegionHeaderSize; 92 + NvU32 zcullSubregionHeaderSize; 93 + NvU32 subregionCount; 94 + NvU32 subregionWidthAlignPixels; 95 + NvU32 subregionHeightAlignPixels; 96 + } NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS; 97 + 79 98 #endif
+1 -1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h
··· 124 124 } *ce, *nvdec, *nvenc, *nvjpg, *ofa; 125 125 126 126 const struct nvkm_rm_api_gr { 127 - int (*get_ctxbufs_info)(struct r535_gr *); 127 + int (*get_ctxbufs_and_zcull_info)(struct r535_gr *); 128 128 struct { 129 129 int (*init)(struct r535_gr *); 130 130 void (*fini)(struct r535_gr *);